JP5170939B2 - Test apparatus and test method - Google Patents

Description

  The present invention relates to a test apparatus and a test method for testing an electronic device. In particular, the present invention relates to a test apparatus and a test method for supplying and testing an input signal to which jitter has been applied to an electronic device.

  The jitter test is an important test item for serial communication devices and serial I / O devices. For example, recommendations from the International Telecommunication Union, Bellcore, etc. stipulate measurement of jitter tolerance, jitter generation, and jitter transfer function. In particular, the jitter tolerance test is important because it can evaluate the operation limit of the device against the jitter added in the transmission medium. Here, the measurement of the jitter tolerance is to measure the threshold value of the magnitude of applied jitter at which the device starts to cause a bit error by changing the magnitude of the applied jitter applied to the input signal.

  FIG. 1 is a diagram for explaining conventional measurement of jitter tolerance. In the conventional jitter tolerance measurement, random jitter is applied to an input signal by superimposing white noise as shown in FIG. 1B on the input signal as shown in FIG. 1A. FIG. 1C shows an input signal to which random jitter is applied. Then, an input signal to which random jitter is applied is supplied to the electronic device to measure whether a bit error occurs in the electronic device.

  FIG. 2 shows a configuration of a conventional jitter injection apparatus 200 for applying jitter to an input signal. The clock source 204 supplies a clock for operating the pattern generator 202. In addition, sine wave jitter is applied to the input signal generated by the pattern generator 202 by the sine wave jitter source 206, and deterministic jitter is further applied by the deterministic jitter source 208. In addition, random jitter generated by the random jitter source 212 is applied in the adder 210. At this time, the amount of jitter applied to the input signal is adjusted by the magnitude of random jitter and the magnitude of sine wave jitter. Then, the limiting amplifier 214 amplifies the input signal, clips an amplitude component that is greater than a certain value and less than a certain value, and outputs it.

  FIG. 3 is a diagram for explaining the operation of the limiting amplifier 214. The limiting amplifier 214 is given an input signal as shown in FIG. Since random jitter is applied to the input signal, the input signal has an amplitude modulation component.

  Prior art documents include the following documents.
  US Patent Application Publication No. 2002/0174159

  As shown in FIG. 3B, the limiting amplifier 214 removes an amplitude component equal to or higher than the first threshold and equal to or lower than the second threshold from the amplitude component of the input signal to reduce the amplitude modulation component. The amplitude modulation component in the range below the first threshold and above the second threshold cannot be removed. In order to measure the jitter tolerance of an electronic device, an input signal having no amplitude modulation component is supplied to the electronic device, as in the input signal shown in FIG. 3C, and a bit error due to only the jitter component in the phase direction. However, in the conventional jitter injection apparatus 200, since the amplitude modulation component remains in the input signal as shown in FIG. 3B, the bit error due to the amplitude modulation component is also detected. End up. For this reason, the jitter tolerance of the electronic device is underestimated. In addition, since the conventional jitter injection apparatus 200 includes three jitter sources, that is, a sine wave jitter source 206, a deterministic jitter source 208, and a random jitter source 212, the apparatus cost increases.

  Therefore, an object of the present invention is to provide a test apparatus and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above-described problem, in a first embodiment of the present invention, a test apparatus for testing an electronic device, which applies deterministic jitter without generating an amplitude modulation component in a given input signal, The electronic device based on the output signal output from the electronic device in response to the input signal, the deterministic jitter applying means to be supplied to the electronic device, the jitter amount control means for controlling the magnitude of the deterministic jitter applied by the deterministic jitter applying means, There is provided a test apparatus comprising determination means for determining

  The deterministic jitter applying means may include a primary filter that passes the input signal and applies deterministic jitter. Further, the deterministic jitter applying means may include a cable that passes the input signal and applies deterministic jitter. The deterministic jitter applying means may further include a limiting amplifier that removes the amplitude modulation component of the input signal. The jitter amount control means determines the magnitude of the deterministic jitter based on a threshold value of a peak-to-peak value of alignment jitter between the input signal and a recovered clock signal regenerated from the input signal by the electronic device. Also good.

  The test apparatus may further include sine wave jitter applying means for applying sine wave jitter to the input signal, and the jitter amount control means may further control the magnitude of the sine wave jitter applied by the sine wave jitter applying means. The jitter amount control means is based on the threshold value of the peak-to-peak value of alignment jitter between the input signal and the recovered clock signal regenerated from the input signal by the electronic device, and the jitter transfer function in the non-defective electronic device, The magnitude of the sine wave jitter may be determined.

  Further, the jitter amount control means is configured to determine a sine wave jitter based on a sine wave jitter threshold obtained by multiplying a threshold of a peak-to-peak value of alignment jitter by a predetermined sine wave jitter ratio and a jitter transfer function. And determine the magnitude of the deterministic jitter based on the deterministic jitter threshold obtained by subtracting the sine wave jitter threshold from the alignment jitter peak-to-peak threshold and the jitter transfer function. May be. Further, the jitter amount control means includes a jitter transfer function estimator for deriving a jitter transfer function based on the timing jitter sequence of the input signal and the timing jitter sequence of the recovered clock signal reproduced from the input signal by a non-defective electronic device. You may have.

  The sine wave jitter applying means applies sine wave jitter having a plurality of frequency components to the input signal, and the jitter amount control means is based on the threshold value of the alignment jitter peak-to-peak value and the jitter transfer function. You may determine each magnitude | size of the several frequency component which a sine wave jitter has.

  For each of the plurality of frequency components, the jitter amount control means includes a frequency component threshold value obtained by multiplying a threshold value of a peak-to-peak value of alignment jitter by a frequency component ratio predetermined for the frequency component, and a jitter transfer function. Based on the deterministic jitter threshold obtained by subtracting the sum of the frequency component thresholds from the threshold value of the alignment jitter peak-to-peak value. Thus, the magnitude of the deterministic jitter may be determined.

  The electronic device inputs an input signal and a reference clock signal, samples the input signal based on the reference clock signal, and the test apparatus further includes a phase shifter that shifts the phase of the reference clock signal. Also good.

  In a second aspect of the present invention, a test apparatus for testing an electronic device, which applies sine wave jitter to a given input signal and supplies the sine wave jitter to the electronic device, and sine wave jitter application means Jitter amount control means for controlling the magnitude of the sine wave jitter applied by the device, and determination means for judging the quality of the electronic device based on the output signal output from the electronic device according to the input signal. The means is based on the threshold of the peak-to-peak value of the alignment jitter between the input signal and the recovered clock signal regenerated from the input signal by the electronic device, and the jitter transfer function in a good electronic device. A test apparatus for determining the size of the apparatus is provided.

  In a third aspect of the present invention, there is provided a test method for testing an electronic device, which includes applying a deterministic jitter without generating an amplitude modulation component to a given input signal and supplying the deterministic jitter to the electronic device. A jitter amount control stage for controlling the magnitude of the deterministic jitter to be applied in the deterministic jitter application stage, and a judgment stage for judging the quality of the electronic device based on the output signal output from the electronic device in accordance with the input signal. Provide test methods.

  In the deterministic jitter application step, deterministic jitter may be applied using a primary filter that passes the input signal. In the deterministic jitter application step, deterministic jitter may be applied using a cable that passes the input signal. The test method may further include a sine wave jitter application step of applying sine wave jitter to the input signal. In the sine wave jitter application step, sine wave jitter having a plurality of frequency components may be applied to the input signal.

  According to a fourth aspect of the present invention, there is provided a test method for testing an electronic device, which includes applying a sine wave jitter to a given input signal and supplying the sine wave jitter to the electronic device, and applying a sine wave jitter A jitter amount control stage for controlling the magnitude of the sine wave jitter applied in the step, and a judgment stage for judging the quality of the electronic device based on the output signal output from the electronic device according to the input signal. The stage determines the sine wave jitter based on the peak-to-peak threshold value of the alignment jitter between the input signal and the recovered clock signal recovered from the input signal by the electronic device and the jitter transfer function in a good electronic device. Provide a test method for determining the size of

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

First, the principle of the test apparatus and test method according to this embodiment will be described.
(1) Device Under Test
FIG. 4 is a diagram showing an example of the configuration of the electronic device 10 according to the embodiment of the present invention. FIG. 4A shows a first example of the configuration of the electronic device 10. The electronic device 10 according to the present embodiment is a deserializer as an example, and includes a clock recovery circuit 41 (Clock Recovery), a bit sampler 42 (Bit Sampler), a clock divider circuit 43 (Clock Divider), and a demultiplexer 44 ( DEMUX). The clock recovery circuit 41 recovers a clock signal from an input signal of a serial bit stream (Serial Data Stream) and outputs it as a recovered clock signal (Recovered Clock). The bit sampler 42 samples the input signal of the serial bit string based on the recovered clock signal. The clock divider circuit 43 divides the recovered clock signal. The demultiplexer 44 performs serial / parallel conversion on the bit string sampled by the bit sampler 42 by using the reproduction clock signal divided by the clock frequency dividing circuit 43, and outputs it as, for example, 16-bit reproduction data.

  When the rising edge in the bit string of the input signal fluctuates due to the influence of the jitter or the sampling timing fluctuates due to the jitter of the reproduced clock signal, the timing of the adjacent rising edge in the input signal crosses the sampling timing. As a result, since the bit sampler 42 samples the preceding bit and the next bit, a bit error occurs in the reproduction data output from the demultiplexer 44.

  FIG. 4B shows a second example of the configuration of the electronic device 10. In FIG. 4B, components having the same reference numerals as those in FIG. 4A have the same configurations and functions as those described in relation to FIG. 4A except for the points described below. Have. The electronic device 10 according to this example includes a PLL 45, a phase alignment means 46 (Phase Alignment), a bit sampler 42, a clock frequency divider circuit 43, and a demultiplexer 44, and includes a data signal (input signal) and a reference clock. The (Reference Clock) signal is input, and the data signal is sampled based on the reference clock signal.

  The PLL 45 receives the reference clock signal and generates a sampling clock used for sampling the input signal. In this example, the sampling clock generated by the PLL 45 has a frequency N times that of the input signal. The phase alignment means 46 adjusts the phase of the sampling clock with respect to the input signal. The bit sampler 42 samples the input signal at the N sampling timings per cycle using the phase-adjusted sampling clock, and uses the data sampled at the timing with the lowest error rate among these sampling timings to obtain the bit string. Reproduce.

  When the rising edge in the bit string of the input signal fluctuates due to the influence of jitter or the sampling timing fluctuates due to the jitter of the sampling clock, the timing of adjacent rising edges in the input signal cross the sampling timing. As a result, since the bit sampler 42 samples the preceding bit and the next bit, a bit error occurs in the reproduction data output from the demultiplexer 44.

  In the electronic device 10 shown in the second example, a maximum phase difference of 1 / N UI (Unit Interval) is generated between the input signal and the sampling clock due to the static phase difference between the input signal and the reference clock signal. . When a phase difference occurs between the input signal and the sampling clock, an offset is given to the alignment jitter shown below, and the timing margin in the bit string reproduction by the bit sampler 42 is reduced, so that a bit error is likely to occur.

電子デバイス１０は、入力データ列と再生クロックのタイミング・アラインメント誤差、すなわち、アラインメントジッタがしきい値より大きくなると、ビット誤りを生じる。 (2) Alignment jitter
The alignment jitter is an alignment error between the timing jitter Δθ [nT] of the input data string that is the input signal and the timing jitter Δφ [nT] of the recovered clock signal (see “Patrick R. Trischitta and Eve L. Varma, Jitter in Digital Transmission Systems, Artech House, p. 86, 1989 "). The alignment jitter can be obtained by the following equation (1).

The electronic device 10 generates a bit error when the timing alignment error between the input data string and the recovered clock, that is, the alignment jitter exceeds a threshold value.

FIG. 5 is a diagram schematically showing the worst-case alignment jitter in a range where no bit error occurs. In the worst case, alignment jitter causes the playback bit boundary to swing between 0 UI and 0.5 UI. When the amplitude of alignment jitter exceeds 0.5 UI _PP, for example, the electronic device 10 generates a bit error.

(3) Jitter transfer function
Next, a procedure for obtaining a jitter transfer function from timing jitter will be described. The sampling period T _S by the test apparatus is made equal to the clock period T of the clock recovery circuit 41 to be tested, and the instantaneous phase noise Δθ (t) or Δφ (t) near zero crossing (rising edge or falling edge) is resampled Then, input timing jitter Δθ [nT] and output timing jitter Δφ [nT] can be obtained. Then, if Δθ [nT] and Δφ [nT] are converted to the frequency domain by Fourier transformation, an input timing jitter spectrum (timing jitter spectrum) shown in the following equation (2) and an output timing shown in equation (3) Jitter spectrum can be obtained ("Takahiro J. Yamaguchi, Mani Soma, Louis Malarsie, Masahiro Ishida, Hirobumi Musha," Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division, "Proc. IEEE VLSI Test Symposium, Monterey, USA, April 28-May 2, 2002.)).

すなわち、勧告（「ITU-T, Recommendation G.958: Digital Line Systems Based on the Synchronous Digital Hierarchy for Use on Optical Fibre Cables, November 1994.」、「ITU-T, Recommendation O.172: Jitter and Wander Measuring Equipment for Digital Systems Which are Based on the Synchronous Digital Hierarchy (SDH), March 1999.」、及び、「Bellcore, Generic Requirements GR-1377-Core: SONET OC-192 Transport System Genetic Criteria, December 1998.」参照）のように狭帯域のフィルタをもちいると、ゼロ交叉におけるサンプリング（弱義周期定常信号にともなう処理）を避けることもできる。 Since the timing jitter is a wide-sense cyclostationary with a period T, using the timing jitter spectrum is more effective for analyzing the modulation noise source than using the phase noise spectrum. However, the following equations (4) and (5) are established by passing a narrow-band filter and converting a weakly defined periodic signal into a stationary signal.

That is, the recommendations ("ITU-T, Recommendation G.958: Digital Line Systems Based on the Synchronous Digital Hierarchy for Use on Optical Fiber Cables, November 1994.", "ITU-T, Recommendation O.172: Jitter and Wander Measuring Equipment for Digital Systems Which are Based on the Synchronous Digital Hierarchy (SDH), March 1999. "and" Bellcore, Generic Requirements GR-1377-Core: SONET OC-192 Transport System Genetic Criteria, December 1998. ") If a narrow band filter is used, sampling at zero crossing (processing with a weakly periodic signal) can be avoided.

The jitter transfer function H _J (f _J ) is calculated from the timing jitter spectrum shown in the above (2) and (3) (or (4) and (5)) by the following equations (6), (7), and It can be estimated using (8).

The jitter transfer function can also be obtained using a cross spectrum between input timing jitter and output timing jitter and a power spectrum of input timing jitter.

なお、H_J(f_J)は複素数である。 FIG. 6 shows an example of the jitter transfer function of the electronic device 10.
Furthermore, from the linearity of the equation (7) and Fourier transform, the input timing jitter Δθ [nT] and the output timing jitter Δφ [nT] have the relationship shown in the following equation (10).

H _J (f _J ) is a complex number.

ここで、Aはサイン波ジッタの振幅、φはサイン波ジッタの初期位相である。 (4) Determination of Jitter Size (4-1) When Sine Wave Jitter is Applied Next, for the input data string to the electronic device 10, the jitter frequency f _J shown in the following equation (11) A method of determining the magnitude of jitter when sine wave jitter is applied will be described.

Here, A is the amplitude of sine wave jitter, and φ is the initial phase of sine wave jitter.

式（１１）及び（１２）を式（１）に代入すると、以下の式（１３）に示すアラインメントジッタを得ることができる。

When the jitter transfer function of the electronic device 10 at the jitter frequency f is H _J (f), the timing jitter generated in the recovered clock by the clock recovery circuit 41 is expressed by the following equation (12).

When Expressions (11) and (12) are substituted into Expression (1), alignment jitter shown in Expression (13) below can be obtained.

When the peak-to-peak value Δalign _{PP of the} alignment jitter exceeds a threshold value Δ _{th, PP} (for example, 0.5 UI _PP ), the electronic device 10 generates a bit error. Therefore, a condition for preventing the electronic device 10 from causing a bit error is given by the following equation (14).

In the test apparatus and test method according to the present embodiment, the magnitude of the sine wave jitter to be applied to the electronic device 10 is determined by calculating the amplitude A that satisfies Equation (13). Then, by applying the sine wave jitter shown in the equation (11) to the input data string using the calculated amplitude A, it is determined whether or not the electronic device 10 causes a bit error, whereby the jitter at the jitter frequency f _J is determined. A defective device having a deteriorated proof stress can be identified.

ここで、A_kはジッタ周波数f_kのサイン波ジッタの振幅、φ_kはジッタ周波数f_kのサイン波ジッタの初期位相である。 (4-2) When Multitone Sine Wave Jitter is Applied Next, when multitone sine wave jitter represented by the following formula (15) is applied to the input data string to the electronic device 10, A method for determining the magnitude of jitter will be described. Here, the multitone sine wave jitter is a sine wave jitter obtained by synthesizing sine wave jitter corresponding to each of a plurality of frequency components (jitter frequencies) f _k (k = 1, 2,..., N).

Here, A _k is the amplitude of the sinusoidal jitter of the jitter frequency f _k, φ _k is the initial phase of the sinusoidal jitter of the jitter frequency f _k.

式（１５）及び（１６）を式（１）に代入すると、以下の式（１７）に示すアラインメントジッタを得ることができる。

When multitone sine wave jitter is applied, timing jitter generated in the recovered clock by the clock recovery circuit 41 is expressed by the following equation (16).

By substituting Equations (15) and (16) into Equation (1), the alignment jitter shown in Equation (17) below can be obtained.

When the peak-to-peak value Δalign _{PP of the} alignment jitter exceeds a threshold value Δ _{th, PP} (for example, 0.5 UI _PP ), the electronic device 10 causes a bit error. Therefore, a condition for preventing the electronic device 10 from causing a bit error is given by the following equation (18).

In the test apparatus and test method according to the present embodiment, the magnitude of the sine wave jitter to be applied to the electronic device 10 is determined by calculating the amplitude _Ak satisfying the equation (13). Then, by applying the sine wave jitter shown in Expression (15) to the input data string using the calculated amplitude A _k and determining whether or not the electronic device 10 causes a bit error, the jitter frequency f _k ( It is possible to discriminate a defective device whose jitter tolerance has deteriorated in any of k = 1, 2,..., N).

In the above, the jitter amplitude A _k of the plurality sinusoidal jitter applied to the input data sequence is set to satisfy the equation (18), set the jitter amplitude A _k of the jitter frequency f _k to the same value Alternatively, the weight may be set according to the importance of the jitter frequency f _k to be tested.

(4-3) When Deterministic Jitter is Applied Next, a method for determining the magnitude of jitter when applying deterministic jitter represented by the following equation (19) to the input data string to the electronic device 10 is described. Show.

ここで、A(f)はジッタ周波数fにおけるジッタ振幅、φ(f)はジッタ周波数fにおけるジッタの初期位相である。 When the jitter transfer function of the electronic device 10 at the jitter frequency f is H _J (f), the timing jitter generated in the recovered clock by the clock recovery circuit 41 is expressed by the following equation (20).

Here, A (f) is the jitter amplitude at the jitter frequency f, and φ (f) is the initial phase of jitter at the jitter frequency f.

By substituting Equation (19) and Equation (20) into Equation (1), the alignment jitter shown in Equation (21) below can be obtained.

When the peak-to-peak value Δalign _{PP of the} alignment jitter exceeds a threshold value Δ _{th, PP} (for example, 0.5 UI _PP ), the electronic device 10 causes a bit error. That is, the condition for preventing the electronic device 10 from causing a bit error is given by the following equation (22).

FIG. 7 shows an example of a spectrum of an input signal transmitted through a cable. In this example, the carrier frequency of the input signal is 2.5 Gbps and the cable length is 20 m. As shown in FIG. 7, by transmitting the cable, a wide sideband of about 200 MHz on one side is generated in the vicinity of the carrier frequency in the spectrum of the input signal. That is, the deterministic jitter applied to the input signal has a frequency component of about 200 MHz, and has a frequency component sufficiently higher than the cut-off frequency of the loop filter. Thus, the deterministic jitter has energy in a wide frequency band (several hundred MHz to several GHz) compared to the electronic device 10, for example, a loop band f _bound (usually about 1 MHz) of a deserializer, a clock regenerator, or a PLL. . Further, the jitter transfer function outside the loop band of the electronic device 10 is almost zero as shown in FIG. Therefore, the alignment jitter due to the jitter within the loop band is sufficiently small to be negligible compared to the alignment jitter due to the jitter outside the loop band, and Equation (23) is established.

ここで、｜Ｈ_Ｊ（ｆ＞ｆ_{ｂｏｕｎｄ}）｜≒０を用いた。 Therefore, the alignment jitter shown by the equation (21) can be modified as shown by the following equation (24).

Here, | H _J (f> f _bound ) | ≈0 was used.

ここで、Δθ_PPは入力データ列に印加された確定ジッタのピークツゥピーク値を表す。 And the condition shown by Formula (22) is also represented by the following Formula (25) using Formula (24).

Here, Δθ _PP represents the peak-to-peak value of the deterministic jitter applied to the input data string.

  In the test apparatus and test method according to the present embodiment, the amplitude of the deterministic jitter is determined so as to satisfy Expression (22) or Expression (25). Then, by applying the determined deterministic jitter to the input data string and determining whether or not the electronic device 10 causes a bit error, a defective device whose jitter tolerance has deteriorated mainly outside the loop band of the electronic device 10 is mainly determined. Can be determined.

(4-4) When Multitone Sine Wave Jitter and Deterministic Jitter are Applied Next, the jitter frequency f _k (k = 1) shown in the following equation (26) is applied to the input data string to the electronic device 10. , 2,..., N) and a deterministic jitter represented by the following equation (27) are applied.

When the jitter transfer function of the device under test at the jitter frequency f is H _J (f), the timing jitter generated in the recovered clock by the clock recovery circuit 41 is expressed by the following equation (28).

Therefore, the alignment jitter is given by the following equation (29).

ここで、確定ジッタにおいて、ループ帯域内のジッタによるアライメントジッタは、ループ帯域外のジッタによるアライメント・ジッタに比べ無視できる程度に十分小さい（式（２３））と仮定した。 When the peak-to-peak value Δalign _{PP of} alignment jitter exceeds a threshold value Δ _{th, PP} (for example, 0.5 UI _PP ), the electronic device 10 causes a bit error. Therefore, a condition for preventing the electronic device 10 from causing a bit error is given by the following equation (30).

Here, in the deterministic jitter, it is assumed that the alignment jitter due to the jitter within the loop band is sufficiently small (equation (23)) to be negligible compared to the alignment jitter due to the jitter outside the loop band.

In the test apparatus and test method according to the present embodiment, the amplitude of the sine wave and the amplitude of the deterministic jitter of each of the plurality of frequency components in the sine wave jitter are determined so as to satisfy Expression (29). Then, the determined sine wave jitter and deterministic jitter are applied to the input data sequence to determine whether or not the electronic device 10 causes a bit error. Thereby, according to the test apparatus and the test method according to the present embodiment, the jitter tolerance at any of the jitter frequencies f _k (k = 1, 2,..., N) or the jitter outside the loop band of the electronic device 10 A defective device having a deteriorated proof stress can be identified.

  In the above, the deterministic jitter amount applied to the input data string and each jitter amplitude of the multiple sine wave jitter are set so as to satisfy the equation (30), but the deterministic jitter amplitude and the multitone sine wave jitter amplitude are the same. The value may be set, or may be set with a weight corresponding to the importance of the jitter frequency region to be tested (within the loop band or outside the loop band).

(5) Method for Determining Threshold of Alignment Jitter The threshold value Δ _{th, PP} used as a criterion for determining whether or not the electronic device 10 is good may be set to 0.5 UI _PP from the worst case alignment jitter. You may obtain | require from the lower limit of the jitter tolerance of the electronic device 10. FIG. Further, it may be obtained from a typical value of jitter tolerance of the electronic device 10, and is obtained from a specification value of jitter tolerance defined in a test specification of the electronic device 10, for example, an ITU-T G.958 test specification for an SDH device. It may be set by the person who performs the test.

(6) Random Jitter Random jitter outside the loop band of the electronic device 10 can be treated as deterministic jitter as in the equation (19). Further, the random jitter in the loop band of the electronic device 10 can be treated as a multitone sine wave jitter, similarly to the equation (15).

  FIG. 8 is a diagram illustrating an example of the configuration of the test apparatus 100 according to the embodiment of the present invention. The test apparatus 100 is an apparatus for testing the jitter tolerance of the electronic device 10, and includes a pattern generator 102, a deterministic jitter applying unit 104, a jitter amount control unit 106, and a determination unit 108. The electronic device 10 is, for example, a serial communication device or a serial I / O device. The electronic device 10 is not limited to these devices. For example, in addition to these devices, an electronic circuit or a system including an electronic circuit may be used.

  The pattern generator 102 generates an input signal (input data string) to be supplied to the electronic device 10. The deterministic jitter applying unit 104 receives the input signal generated by the pattern generator 102, applies deterministic jitter without generating an amplitude modulation component in the input signal, and supplies the deterministic jitter to the electronic device 10. The deterministic jitter is, for example, jitter that depends on the signal pattern of the input signal.

  For example, the deterministic jitter applying unit 104 may be a primary filter that applies deterministic jitter to the input signal by passing the input signal. The primary filter is, for example, an RC filter. In this case, it is preferable that the resistance component and the capacitance component in the primary filter are variable.

  Further, the deterministic jitter applying means 104 may have a cable for applying deterministic jitter by passing an input signal. In this case, the deterministic jitter applying means 104 is preferably provided in parallel and has a plurality of cables having different lengths. Further, the deterministic jitter applying unit 104 may include a limiting amplifier that removes the amplitude modulation component of the input signal. The limiting amplifier may have the same function and configuration as the limiting amplifier 214 described in FIG. The amplitude limit value in the limiting amplifier is preferably determined in advance based on the magnitude of deterministic jitter to be applied.

The jitter amount control means 106 controls the magnitude of the deterministic jitter generated by the deterministic jitter applying means 104 and applied to the input signal. For example, when the deterministic jitter applying unit 104 generates deterministic jitter using a primary filter, the jitter amount control unit 106 controls the deterministic applied by controlling the magnitude of the resistance component and the capacitance component of the primary filter. Control the magnitude of jitter.
When the deterministic jitter applying means 104 has a plurality of cables, the jitter amount control means 106 controls the magnitude of the deterministic jitter generated by the cable by selecting which cable the input signal is allowed to pass through. To do.

  Then, the determination unit 108 determines the quality of the electronic device 10 by detecting a bit error in the output signal by the electronic device 10 in accordance with the input signal. At this time, the determination means 108 receives an expected value signal to be compared with the output signal from the pattern generator 102, and detects a bit error by comparing the bits of the output signal and the expected value signal.

  By performing such bit error detection for each magnitude of deterministic jitter to be applied, the jitter tolerance of the electronic device 10 can be measured. That is, the jitter amount control means 106 gradually changes the magnitude of the deterministic jitter, and the determination means 108 detects a bit error in the output signal for each definite jitter magnitude changed by the jitter amount control means 106. . And the quality of the electronic device 10 is determined by comparing the specification value of the jitter tolerance of the electronic device 10 and the measured jitter tolerance. Further, the test apparatus 100 may measure only the vicinity of the specification value of the jitter tolerance of the electronic device 10.

  FIG. 9 is a diagram illustrating an example of a step response of a filter. FIG. 9A shows the step response of the primary filter, and FIG. 9B shows the step response of the secondary filter. When the deterministic jitter applying means 104 generates deterministic jitter using a primary filter, the step response of the primary filter is as shown in FIG. As shown in FIG. 9A, the step response of the primary filter is a characteristic that increases smoothly, and therefore amplitude modulation as described in FIG. 3 does not occur. For this reason, when deterministic jitter is generated by the primary filter, bit errors due to amplitude modulation are not detected, and bit errors due only to jitter can be detected.

  On the other hand, when deterministic jitter is applied to the input signal by the secondary filter, the step response of the secondary filter is as shown in FIG. 9B, and therefore amplitude modulation as described in FIG. 3 occurs. End up. For this reason, a bit error due to amplitude modulation is detected, and the jitter tolerance of the electronic device 10 may not be detected accurately. Since the test apparatus 100 in this example generates deterministic jitter using a primary filter, it can accurately detect the jitter tolerance of the electronic device 10.

  When testing the jitter tolerance outside the loop band of a clock recovery circuit such as a PLL included in the electronic device 10, it is necessary to apply a jitter having a frequency component higher than the cutoff frequency of the loop filter of the clock recovery circuit to the input signal. There is. For example, the cut-off frequency of a loop filter used in a clock recovery circuit of a 2.5 Gbps communication device is in the frequency range of 1 MHz or more, but it is sufficiently higher than the cut-off frequency by generating jitter using a cable. Jitter having a high frequency component can be generated.

  FIG. 10 is a flowchart illustrating an example of a test method for testing the electronic device 10. The test method may be performed using the test apparatus 100 described with reference to FIG. First, in the deterministic jitter application step S302, deterministic jitter is applied to the input signal. In S302, the deterministic jitter is applied by using the deterministic jitter applying means 104 without generating an amplitude modulation component in the input signal. At this time, the magnitude of the deterministic jitter generated by the deterministic jitter applying unit 104 is controlled by the jitter amount control unit 106 in the jitter amount control step S304. In the determination step S306, the quality of the electronic device 10 is determined based on the output signal output from the electronic device 10 according to the input signal.

  In the above, the jitter amount control means 106 determines the magnitude of the deterministic jitter based on the threshold value of the peak-to-peak value of the alignment jitter between the input signal and the recovered clock signal regenerated from the input signal by the electronic device 10. To decide. More specifically, the jitter amount control means 106 determines the peak-to-peak value of the deterministic jitter so as to satisfy the equation (22) or (25). Then, in the jitter amount control step S304, the jitter amount control unit 106 adjusts the deterministic jitter applying unit 104 so as to apply deterministic jitter whose amplitude is the value determined as described above to the input signal.

Here, the threshold value _{Δth, PP} of the peak-to-peak value of alignment jitter may be set by the method shown in the principle (5) of the test apparatus and test method according to the present embodiment. Further, the jitter amount control means 106 calculates the peak-to-peak value of the alignment jitter measured by the test apparatus 100 for the non-defective electronic device 10 or the minimum value of the alignment jitter measured by the test apparatus 100 for the plurality of non-defective electronic devices 10. Alternatively _{, the} threshold value Δ _{th, PP} may be used. Instead, based on the statistical values of the alignment jitter measured by the test apparatus 100 for the plurality of electronic devices 10, that is, based on, for example, the average value and variance of the alignment jitter, The threshold value Δ _{th, PP} may be determined.

  FIG. 11 is a diagram illustrating another example of the configuration of the test apparatus 100. The test apparatus 100 in this example further includes sine wave jitter applying means 110 in addition to the configuration of the test apparatus 100 described in FIG. 11, components having the same reference numerals as those in FIG. 8 have the same configurations and functions as the components described in relation to FIG. 8 except for the points described below.

  The sine wave jitter applying unit 110 applies sine wave jitter to the input signal generated by the pattern generator 102. For example, the sine wave jitter applying means 110 generates sine wave jitter by modulating the phase of a clock used by the pattern generator 102 to generate an input signal using a sine wave. At this time, the sine wave jitter applying unit 110 may generate a sine wave jitter having a single frequency component, or may generate a sine wave jitter having a plurality of frequency components.

  The jitter amount control unit 106 further controls the magnitude of the sine wave jitter applied to the input signal by the sine wave jitter application unit 110 in addition to the magnitude of the deterministic jitter applied to the input signal by the deterministic jitter application unit 104. According to the test apparatus 100 in this example, it is possible to apply a predetermined magnitude of jitter having deterministic jitter and sine wave jitter to an input signal.

  FIG. 12 is a flowchart illustrating another example of a test method for testing the electronic device 10. The test method in this example further includes a sine wave jitter application step S308 in addition to the test method described in FIG. In the sine wave jitter applying step S308, the sine wave jitter is applied to the input signal using the sine wave jitter applying means 110 described in FIG. And the quality of the electronic device 10 is determined by performing the process of S302-S306.

  In the above, the jitter amount control means 106 is configured to detect the threshold of the peak-to-peak value of the alignment jitter between the input signal and the recovered clock signal regenerated from the input signal by the electronic device 10, and the jitter transmission in the good electronic device 10. Based on the function, the magnitude of the sine wave jitter is further determined. A method for determining the magnitudes of deterministic jitter and sine wave jitter will be described below.

(1) Determination method 1 of deterministic jitter and sine wave jitter
When the sine wave jitter shown in the principle (4-1) of the test apparatus and test method according to the present embodiment and the deterministic jitter shown in (4-3) are generated, the jitter amount control means 106 has these sizes. Is determined by the method exemplified below.

  First, the jitter amount control means 106 is preset with a sine wave jitter ratio indicating the ratio of sine wave jitter and a deterministic jitter ratio indicating the ratio of deterministic jitter among the magnitudes of jitter to be generated in the input signal. .

Then, the jitter amount control means 106 includes a sine wave jitter threshold value obtained by multiplying the threshold value _{Δth, PP} of the alignment jitter peak-to-peak value by a sine wave jitter ratio, and a jitter transfer function in the non-defective electronic device 10. Based on the above, the magnitude of the sine wave jitter is determined. That is, for example, the jitter amount control means 106 replaces the threshold value _{Δth, PP} in the equation (14) with a sine wave jitter threshold value and calculates the amplitude A that satisfies the equation (14), thereby increasing the magnitude of the sine wave jitter. You may decide.

In addition, the jitter amount control means 106 determines based on a deterministic jitter threshold obtained by subtracting the sine wave jitter threshold from the peak-to-peak threshold value _{Δth, PP} of the alignment jitter and a jitter transfer function. Determine the magnitude of the jitter. That is, for example, the jitter amount control means 106 may determine the magnitude of the deterministic jitter by replacing the threshold value _{Δth, PP} in the equation (22) or (25) with the deterministic jitter threshold value. The deterministic jitter threshold value described above is a value obtained by multiplying the threshold value _{Δth, PP} of the peak-to-peak value of alignment jitter by the deterministic jitter ratio.

(2) Method 2 for determining deterministic jitter and sine wave jitter
When the sine wave jitter and the deterministic jitter shown in the principle (4-4) of the test apparatus and test method according to the present embodiment are generated, the jitter amount control means 106 sets the threshold of the peak-to-peak value of the alignment jitter, Based on the jitter transfer function, the size of each of the plurality of frequency components of the sine wave jitter is determined. That is, the jitter amount control means 106 determines these sizes by the method exemplified below.

  First, the jitter amount control means 106 is preset with a sine wave jitter ratio indicating the ratio of sine wave jitter and a deterministic jitter ratio indicating the ratio of deterministic jitter among the magnitudes of jitter to be applied to the input signal. . Here, the sine wave jitter ratio is set as a total value of predetermined frequency component ratios indicating the ratio of the frequency components for each of a plurality of frequency components that should have multitone sine wave jitter.

Then, the jitter amount control means 106 calculates, for each of the plurality of frequency components, a frequency component obtained by multiplying the threshold value _{Δth, PP} of the alignment jitter peak-to-peak value by a frequency component ratio predetermined for the frequency component. Based on the threshold value and the jitter transfer function in the non-defective electronic device 10, the magnitude of the frequency component of the sine wave jitter is determined. That is, for example, the jitter amount control means 106 calculates the amplitude _Ak for each of a plurality of frequency components so that the threshold _{Δth, PP} in the equation (18) becomes the sine wave jitter threshold. The magnitude of sine wave jitter having a plurality of frequency components may be determined.

Also, the jitter amount control means 106 is a deterministic jitter threshold value obtained by subtracting the total value of frequency component threshold values, that is, a sine wave jitter threshold value, from the threshold value _{Δth, PP} of the peak-to-peak value of alignment jitter. The magnitude of deterministic jitter is determined based on That is, for example, the jitter amount control means 106 may determine the magnitude of the deterministic jitter by replacing the threshold value _{Δth, PP} in the equation (22) or (25) with the deterministic jitter threshold value. The deterministic jitter threshold value described above is a value obtained by multiplying the threshold value _{Δth, PP} of the peak-to-peak value of alignment jitter by the deterministic jitter ratio.

  Through the above processing, the jitter amount control means 106 can obtain the magnitudes of the sine wave jitter and the deterministic jitter that satisfy the equation (30). In order to obtain a jitter transfer function used to determine the magnitude of jitter in the above (1) and (2), the test apparatus 100 may include a jitter transfer function estimation unit. Based on the timing jitter sequence of the input signal and the timing jitter sequence of the regenerated clock signal regenerated from the input signal by the non-defective electronic device 10, the jitter transfer function estimator is represented by the equations (6), (7), (8), or The jitter transfer function in the non-defective electronic device 10 is derived by performing the calculation exemplified in Equation (9). Here, the jitter transfer function estimation unit may determine a jitter transfer function used by the jitter amount control means 106 based on a statistical value of the jitter transfer function measured for a plurality of non-defective electronic devices 10.

  8 to 12, the input and output of the electronic device 10 are described as one. However, when the electronic device 10 is a multi-input multi-output device, the test apparatus 100 supports a plurality of inputs / outputs. The pattern generator 102, the deterministic jitter applying means 104, the jitter amount controlling means 106, the sine wave jitter applying means 110, and the judging means 108 may be provided. 8 and 11, the pattern generator 102 may be provided outside the test apparatus 100.

  FIG. 13 is a diagram illustrating another example of the configuration of the test apparatus 100. 13 replaces the input signal generated by the pattern generator 102 shown in FIG. 8 with the signal generated by the transmitting electronic device 11 (Transmitter (DUT)) as the receiving electronic device 12 ( Used as input signal to Receiver (DUT). 13 having the same reference numerals as those in FIG. 8 have the same configurations and functions as the components described in relation to FIG. 8 except for the points described below.

  The test apparatus 100 according to the present embodiment includes a deterministic jitter applying unit 104, a jitter amount control unit 106, and a determination unit 108. The deterministic jitter applying means 104 uses the signal generated by the transmitting electronic device 11 and transmitted to the receiving electronic device 12 as an input signal, and applies deterministic jitter without causing an amplitude modulation component in the input signal. The jitter amount control unit 106 controls the magnitude of the deterministic jitter that the deterministic jitter applying unit 104 applies to the input signal in the same manner as the jitter amount control unit 106 shown in FIG. In the test method by the test apparatus 100 according to the present embodiment, the deterministic jitter applying unit 104 applies deterministic jitter to the input signal input from the transmitting electronic device 11 in S302, and the determining unit 108 in S306. However, it is the same as FIG. 10 except that the quality of the transmission side electronic device 11 and the reception side electronic device 12 is determined based on the output signal output from the reception side electronic device 12.

  The test apparatus 100 illustrated in FIG. 13 may further include sine wave jitter applying means 110 that applies sine wave jitter to an input signal input from the transmission-side electronic device 11. In this case, the test method using the test apparatus 100 is to transmit a plurality of signals from the transmitting-side electronic device 11 and apply jitter to each of these signals by the sine wave jitter applying means 110 and the deterministic jitter applying means 104. Except for the point of input to the reception-side electronic device 12 and the determination of pass / fail of the transmission-side electronic device 11 and the reception-side electronic device 12 based on a plurality of output signals corresponding to the plurality of signals. is there.

FIG. 14 is a diagram illustrating another example of the configuration of the test apparatus 100. The test apparatus 100 in this example tests the transmission-side electronic device 11 and the reception-side electronic device 12 that operate based on the reference clock signal generated by the reference clock generator 20. Here, the reception-side electronic device 12 receives the data signal (input signal) and the reference clock signal generated by the transmission-side electronic device 11, and samples the input signal based on the reference clock signal.
The test apparatus 100 includes a phase shifter 112 in addition to the configuration of the test apparatus 100 described in FIG. The phase shifter 112 shifts the phase of the reference clock signal generated by the reference clock generator 20, and is input to the reference electronic signal that is input to the transmission-side electronic device 11 and the reception-side electronic device 12. A predetermined static phase difference is given to the reference clock signal. By using this phase difference, the test apparatus 100 indicates the phase error of the reference clock signal within the range allowed by the specifications of the transmission-side electronic device 11 and the reception-side electronic device 12, for example, the transmission-side electronic device 11 and the reception-side electronic device. The test can be performed in the state given in FIG.

  FIG. 15 is a flowchart illustrating another example of a test method for testing the electronic device 10. The test method in this example further includes a phase shift step S310 in addition to the test method described in FIG. In the phase shift step S310, the phase of the reference clock signal generated by the reference clock generator 20 is shifted using the phase shifter 112 described in FIG. The test method using the test apparatus 100 according to the present embodiment is that the deterministic jitter applying unit 104 applies deterministic jitter to the input signal input from the transmission-side electronic device 11 in S302. Sampling the input signal based on the reference clock signal input from the phase shifter 112, and the determination means 108 in S306 based on the output signal output from the reception-side electronic device 12 and the transmission-side electronic device 11 and Except for determining whether the receiving electronic device 12 is good or bad, the processing is the same as FIG.

  The test apparatus 100 shown in FIG. 14 may further include sine wave jitter applying means 110 that applies sine wave jitter to the input signal input from the transmission-side electronic device 11. In this case, the test method by the test apparatus 100 shifts the phase of the reference clock signal supplied to the reception-side electronic device 12 in the phase shift step S310, and causes the transmission-side electronic device 11 to transmit a plurality of signals. Jitter is applied to each of the signals by the sine wave jitter applying means 110 and the deterministic jitter applying means 104 and input to the receiving-side electronic device 12, and the transmitting side based on a plurality of output signals corresponding to the plurality of signals. Except for determining whether the electronic device 11 and the reception-side electronic device 12 are good or bad, the process is the same as FIG.

ここで、アライメント・ジッタのピークツゥピーク値がしきい値Δ_th,PP（例えば0.5 UI_PP）を超えるとビット誤りが生じるので、ビット誤りを生じる最小の３トーンサイン波ジッタの振幅A_3-toneは次の式（３２）で与えられる。

FIG. 16 shows an example of a test result of the electronic device 10 by the test method according to the embodiment of the present invention. In this figure, the electronic device 10 is a 2.5 Gbps deserializer as an example, and applies a sine wave jitter and deterministic jitter of 90 kHz, 800 kHz, 7 MHz (3 tones) of the same amplitude to the input signal of the deserializer, The amplitude of the minimum three-tone sine wave jitter that causes bit errors was measured. Deterministic jitter was generated using a cable and a limiting amplifier, and the amount of deterministic jitter was changed by changing the cable length from 0.7 m to 20 m.
When the amplitude of sine wave jitter is constant and the amplitude of 3-tone sine wave jitter is A _3-tone , the amplitude A _k of each sine wave jitter in equation (15) is A _k = A _3-tone / 3 Appears. Therefore, the equation (30) can be transformed into the following equation (31).

Here, the threshold delta _th peak-to-peak value of the alignment _jitter, the bit error occurs exceeds _PP (e.g. 0.5 UI _PP), minimum 3 tone sinusoidal jitter causing bit error amplitude A _{3- tone} is given by the following equation (32).

  As shown in FIG. 16, when the deterministic jitter is changed, the value obtained by the equation (32) almost coincides with the result measured by the bit error rate test system (BERTS). According to the test apparatus and the test method according to the present embodiment, it is possible to determine the quality of the device under test using only a deterministic jitter source that can be configured with a cable, a filter, or the like, and to minimize the apparatus cost of the jitter source. Therefore, the test cost of the device can be greatly reduced.

  In addition, since the test apparatus and test method according to the present embodiment can determine whether or not a bit error occurs in the output of the device under test, it is not necessary to measure the bit error rate which is very time-consuming. High-speed device test can be realized.

  Further, according to the test apparatus and test method of the present embodiment, multitone sine wave jitter and deterministic jitter are given to the input data string of the device under test, and whether or not a bit error occurs in the output of the device under test is determined. By determining, it is possible to simultaneously test at least one parametric defect in either the jitter frequency of multiple sine waves or outside the loop band of the device under test, so that a very high-speed device test can be realized.

  Furthermore, since the test apparatus and test method according to the present embodiment can provide a test corresponding to the actual environment in which the device under test is used, not the test under the worst condition, the reliability of the device test, that is, the test result and It is possible to improve the correlation of defects in the actual operating environment.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, the test apparatus 100 shown in FIG. 11 does not have the deterministic jitter applying unit 104 and applies the input signal to which the sine wave jitter is applied by the sine wave jitter applying unit 110 from the pattern generator 102 to the electronic device 10. May be taken. In this case, the jitter amount control means 106 may determine the magnitude of the sine wave jitter by the method shown in the principle (4-1) or (4-2) of the test apparatus and test method according to this embodiment. .

  As is clear from the above, according to the present invention, it is possible to accurately test the jitter tolerance of an electronic device.

It is a figure explaining the measurement of the conventional jitter tolerance. It is a figure which shows the structure of the conventional jitter injection apparatus 200 for applying a jitter to an input signal. 6 is a diagram for explaining the operation of a limiting amplifier 214. FIG. 3A shows an input signal, FIG. 3B shows a signal output by the limiting amplifier 214, and FIG. 3C shows an input signal having no amplitude modulation component. It is a figure which shows an example of a structure of the electronic device 10 which concerns on embodiment of this invention. FIG. 4A shows a first example of the configuration of the electronic device 10. FIG. 4B shows a second example of the configuration of the electronic device 10. It is a figure which shows typically the alignment jitter of the worst case. 4 is a diagram illustrating an example of a jitter transfer function of the electronic device 10. FIG. It is a figure which shows an example of the spectrum of the input signal which transmitted the cable. It is a figure which shows an example of a structure of the test apparatus 100 which concerns on embodiment of this invention. It is a figure which shows an example of the step response of a filter. FIG. 9A shows the step response of the primary filter, and FIG. 9B shows the step response of the secondary filter. 4 is a flowchart illustrating an example of a test method for testing the electronic device 10. 3 is a diagram illustrating another example of the configuration of the test apparatus 100. FIG. 6 is a flowchart illustrating another example of a test method for testing the electronic device 10. 3 is a diagram illustrating another example of the configuration of the test apparatus 100. FIG. 3 is a diagram illustrating another example of the configuration of the test apparatus 100. FIG. 6 is a flowchart illustrating another example of a test method for testing the electronic device 10. It is a figure which shows an example of the test result of the electronic device 10 by the test method which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electronic device, 41 ... Clock reproduction circuit, 42 ... Bit sampler, 43 ... Clock dividing circuit, 44 ... Demultiplexer, 46 ... Phase alignment means, 100 ... Test apparatus, 102 ... Pattern generator, 104 ... Deterministic jitter applying means, 106 ... Jitter amount controlling means, 108 ... Judging means, 110 ... Sine wave jitter applying means, 112 ... Phase shifter, 200 ... Jitter applying device, 202 ... Pattern generator, 206 ... Sine wave jitter source, 208 ... Deterministic jitter source, 212 ... Random jitter source, 214 ... Limiting Amplifier

Claims (17)

A test apparatus for testing an electronic device,
Deterministic jitter applying means for receiving an input signal generated by a pattern generator, applying deterministic jitter according to the signal pattern of the input signal without generating an amplitude modulation component in the received input signal, and supplying the deterministic jitter to the electronic device; ,
A jitter amount control means for controlling the magnitude of the deterministic jitter generated by the deterministic jitter applying means;
A test apparatus comprising: a determination unit that determines whether the electronic device is good or not based on an output signal output from the electronic device according to the input signal. The test apparatus according to claim 1, wherein the deterministic jitter applying unit includes a primary filter that passes the input signal and generates the deterministic jitter. The test apparatus according to claim 1, wherein the deterministic jitter applying unit includes a cable that passes the input signal and generates the deterministic jitter. The test apparatus according to claim 2, wherein the deterministic jitter applying unit further includes a limiting amplifier that removes an amplitude modulation component of the input signal. A test apparatus for testing an electronic device,
Deterministic jitter applying means for receiving an input signal generated by the pattern generator, applying deterministic jitter without causing an amplitude modulation component in the received input signal, and supplying the deterministic jitter to the electronic device;
A jitter amount control means for controlling the magnitude of the deterministic jitter generated by the deterministic jitter applying means;
Determining means for determining the quality of the electronic device based on an output signal output from the electronic device in response to the input signal;
With
The jitter amount control means determines the magnitude of the deterministic jitter based on a threshold value of a peak-to-peak value of alignment jitter between the input signal and a recovered clock signal recovered from the input signal by the electronic device. A test device that determines the thickness. Further comprising sine wave jitter applying means for applying sine wave jitter to the input signal,
The test apparatus according to claim 1, wherein the jitter amount control unit further controls the magnitude of the sine wave jitter generated by the sine wave jitter application unit. The jitter amount control means includes a threshold value of a peak-to-peak value of alignment jitter between the input signal and a reproduction clock signal regenerated from the input signal by the electronic device, and a jitter transfer function in the non-defective electronic device. The test apparatus according to claim 6, wherein the magnitude of the sine wave jitter is determined based on: The jitter amount control means includes:
The magnitude of the sine wave jitter is determined based on a sine wave jitter threshold obtained by multiplying a threshold of a peak-to-peak value of the alignment jitter by a predetermined sine wave jitter ratio and the jitter transfer function. And
The magnitude of the deterministic jitter is determined based on a deterministic jitter threshold obtained by subtracting the sine wave jitter threshold from a threshold of a peak-to-peak value of the alignment jitter and the jitter transfer function. 8. The test apparatus according to 7. The jitter amount control means derives the jitter transfer function based on a timing jitter sequence of the input signal and a timing jitter sequence of a recovered clock signal regenerated from the input signal by a non-defective electronic device. The test apparatus according to claim 7, further comprising a function estimation unit. The sine wave jitter applying means applies the sine wave jitter having a plurality of frequency components to the input signal,
The jitter amount control means determines a size of each of the plurality of frequency components of the sine wave jitter based on a threshold of a peak-to-peak value of the alignment jitter and the jitter transfer function. Item 8. The test apparatus according to Item 7. The jitter amount control means includes:
For each of the plurality of frequency components, based on a frequency component threshold obtained by multiplying a threshold of a peak-to-peak value of the alignment jitter by a frequency component ratio predetermined for the frequency component, and the jitter transfer function Determining the magnitude of the frequency component of the sine wave jitter,
The test according to claim 10, wherein the magnitude of the deterministic jitter is determined based on a deterministic jitter threshold obtained by subtracting a total value of the frequency component thresholds from a threshold value of a peak-to-peak value of the alignment jitter. apparatus. The electronic device inputs the input signal and a reference clock signal, and samples the input signal based on the reference clock signal,
The test equipment
The test apparatus according to claim 1, further comprising a phase shifter that shifts a phase of the reference clock signal. A test method for testing an electronic device, comprising:
A deterministic jitter applying step of receiving an input signal generated by the pattern generator, applying deterministic jitter according to the signal pattern of the input signal without generating an amplitude modulation component in the received input signal, and supplying the deterministic jitter to the electronic device; ,
A jitter amount control step for controlling the magnitude of the deterministic jitter applied in the deterministic jitter application step;
A test method comprising: determining a quality of the electronic device based on an output signal output from the electronic device in response to the input signal. The test method according to claim 13, wherein in the deterministic jitter applying step, the deterministic jitter is generated using a primary filter that passes the input signal. The test method according to claim 13, wherein in the deterministic jitter applying step, the deterministic jitter is generated using a cable that passes the input signal. The test method according to claim 14, further comprising a sine wave jitter application step of applying a sine wave jitter to the input signal. The test method according to claim 16, wherein the sine wave jitter application step applies the sine wave jitter having a plurality of frequency components to the input signal.

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