JP5164400B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device that can be electrically written and erased.

  Conventionally, a flash memory is known as a semiconductor memory device that stores data in a nonvolatile manner. In this flash memory, a stacked gate structure transistor of a floating gate and a control gate is used as a memory cell transistor. The threshold voltage of the memory cell transistor is set according to the amount of charge (electrons) stored in the floating gate, and data is stored according to the threshold voltage of the memory cell.

  In the case of a memory cell structure using this floating gate, a high voltage is required for writing and erasing data. Since the write / erase voltage is high, it is difficult to miniaturize the memory cell transistor, and it is difficult to integrate it on the same semiconductor chip as other logic. Therefore, instead of such a floating gate type memory cell (stacked gate type memory cell transistor), a MONOS type memory cell that stores data by accumulating charges in an insulating film is used as a logic embedded memory. The structure of this MONOS type memory cell is shown, for example, in Patent Document 1 (Japanese Patent Laid-Open No. 2005-347679) and Patent Document 2 (Japanese Patent Laid-Open No. 2002-231830).

  As shown in these Patent Documents 1 and 2, the MONOS type memory cell includes a memory cell transistor and a selection transistor connected in series between a bit line and a source line. The selection transistor is composed of a normal MOS transistor (insulated gate field effect transistor), and one impurity diffusion region is connected to the bit line. The memory cell transistor includes a control gate (memory cell gate), a stacked insulating film, and one impurity diffusion layer (source / drain region). The laminated insulating film is composed of an ONO film (oxide film-nitride film-oxide film). Charges are accumulated in traps that are discretely distributed in the nitride film. The impurity diffusion layer forms a source line.

  In the MONOS type memory cell, charge traps are discretely distributed in the nitride film. Therefore, unlike the floating gate type memory cell, even when a local defect exists in the oxide film through which electrons pass, most of the charge is held in the trap. Thus, the oxide film can be made thinner than the floating gate type memory cell transistor, the write voltage can be lowered, and the element can be miniaturized accordingly. With these features, a nonvolatile memory having a MONOS type memory cell can share a logic and a process, and can be easily mixed.

  Further, since the selection transistor is used in the memory cell, the so-called “over-erasure” problem does not occur even if the memory cell transistor becomes a depletion type transistor. Therefore, a verify period for preventing over-erasing is not required, and writing can be speeded up (usually, erasing is performed before writing).

  Even in the case where a memory cell is constituted by such a selection transistor and a MONOS type memory cell transistor, a high electric field is applied between the gate and the source / drain for the half-selected memory cell. The half-selected memory cell refers to a memory cell in a selected row and a non-selected column or a selected column and a non-selected row. In this case, tunneling current or hot electrons / holes cause the movement of charges (electrons or holes) to the charge storage film, and data is lost or the stored charge amount changes and data is lost over time. Problem arises.

  A configuration for preventing such disturbance at the time of data writing / erasing is disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 2005-276347), Patent Document 4 (Japanese Patent Laid-Open No. 9-213090), and Patent Document 5 (Japanese Patent Laid-Open No. 2006-157050) discloses this.

  Patent Document 3 (Japanese Patent Laid-Open No. 2005-276347) shows a configuration for improving write disturb in a nonvolatile memory in which data is written by passing a constant current from a source line to a bit line. The memory cell is a split gate type memory cell having a selection transistor and a memory cell transistor. In the constant current writing method of Patent Document 3, when the threshold voltage of the selected memory cell is large, the bit line voltage is lowered and the voltage difference between the source line and the bit line is increased. In this state, in the memory cell in the half-selected state of the selected column and non-selected row, current may flow from the source line to the bit line, and erroneous writing may occur due to channel hot electrons. In order to avoid this write disturbance, Patent Document 3 maintains the voltage of the selected bit line at a voltage level equal to or higher than a predetermined value. The voltage having the predetermined value is a voltage level at which writing does not occur in the memory cells in the selected column and the non-selected row. By setting the voltage of the selected bit line to a predetermined value or higher for a memory cell that does not require writing and causes write disturbance in a non-selected memory cell, that is, a memory cell having a high threshold voltage, To prevent it. As the bit line voltage setting circuit, a source follower transistor is used to maintain the lower limit value of the bit line voltage at a predetermined value.

  When the threshold voltage of the selected memory cell is low, the voltage of the bit line becomes equal to or higher than a predetermined value by supplying current from the source line. The clamp transistor is turned off, and the clamping of the bit line voltage is stopped. In the non-selected memory cell, the voltage difference between the source line and the bit line is small, the generation of hot electrons due to the leakage current is avoided, and erroneous writing is prevented. A constant current flows through the selected memory cell, and writing is performed.

  When the threshold voltage of the selected memory cell is high, the voltage of the bit line becomes a predetermined value or less. In this case, the clamp transistor is turned on, and the bit line voltage is clamped to a predetermined value. In this state, a constant current is supplied to the bit line via the clamp transistor, and no constant current flows in the selected memory cell. Thereby, when the threshold voltage of the selected memory cell is high, writing to the selected memory cell is avoided. That is, in the selected column, the bit line is set to the level of the write inhibition voltage, and the source line is set to the write constant current supply voltage level. Thereby, the current flowing from the source line to the bit line in the half-selected memory cell is suppressed, and the write disturbance is suppressed.

  Japanese Patent Laid-Open No. 9-213090 discloses a configuration for avoiding drain disturbance in a floating gate type memory cell. In the drain disturbance, the following phenomenon occurs. In an unselected memory cell connected to the selected bit line, a high electric field between the drain (impurity region connected to the bit line) and the control gate generates electron / hole pairs by weak avalanche, and the holes float. Electrons are injected into the gate, and electrons are extracted from the floating gate to the drain by a tunnel current due to the high electric field of the drain. As a result, the threshold voltage of the unselected memory cell in the written state is lowered. Further, in the erased memory cell, the voltage of the floating gate rises as the bit line voltage rises due to capacitive coupling, a channel is formed, and electrons flow. Electron / hole pairs are generated by the avalanche effect due to the drain high electric field. Depending on the voltage level of the unselected word line, holes are injected into the floating gate and the threshold voltage is further lowered, or conversely, electrons are injected into the floating gate and the threshold voltage is increased.

  In Patent Document 4, in order to avoid such drain disturbance, a voltage VPP / 2 that is ½ times the write voltage Vpp is applied to an unselected word line and an unselected source line. Even in this case, in the memory cell in the erased state of the selected column and unselected row, a channel current flows as the bit line voltage increases. As the number of half-selected erased memory cells increases, the bit line voltage decreases. In order to prevent this, when the voltage of the unselected source line is simply set to the voltage VPP / 2, there arises a problem that writing is delayed. For this reason, Patent Document 4 further arranges the source lines in parallel with the word lines. The word line of the selected row is set to the write high voltage, and the source line is set to the ground voltage. For unselected rows, the word line is set to the intermediate voltage VPP / 2, and the source line is set to the open state. As for the bit lines, the bit lines of the selected column are set to a high voltage, and the unselected bit lines are set to an open state. In the memory cell in the selected column and in the non-selected row, the word line voltage is at an intermediate voltage level, and the drain high electric field is relaxed to suppress the injection of holes into the memory cell in the written state. Further, by setting the source line of the non-selected row to an open state, the channel current is limited in the erased memory cell, and the generation of electron / hole pairs is suppressed.

Japanese Patent Laid-Open No. 2006-157050 discloses a configuration for reducing write disturbance in a memory cell that uses an ONO film as charge storage means. In Patent Document 5, in an array configuration in which bit lines and source lines are arranged in parallel, a high voltage is applied to a word line in a selected row, and a channel region of a memory cell transistor is applied to a word line in a non-selected row. On the other hand, a voltage that is in a reverse bias state is applied, and a voltage that is reverse biased with respect to the channel region is applied to the bit line and the source line of the non-selected column. This patent document 5 aims to improve the write disturbance by increasing the upper limit of the write inhibition voltage of the bit line of the non-selected column by the voltage of the non-selected word line and the voltage of the non-selected source line. In the non-selected memory cell, the tunnel current due to the expansion of the depletion layer in the substrate region is suppressed, and the electric field in the vertical direction is relaxed to suppress the movement of charges with respect to the charge storage film.
JP 2005-347679 A JP 2002-231830 A JP 2005-276347 A Japanese Patent Laid-Open No. 9-213090 JP 2006-157050 A

  In the split gate MONOS cell having the MONOS type memory transistor and the selection transistor, there is a constant voltage bias type writing unlike the constant current writing method of Patent Document 3. In this constant voltage bias write method, a write voltage is transmitted to the source line and bit line of the selected column, and a channel current is caused to flow according to this voltage difference. Hot electrons of this channel current are injected into the charge storage film. The non-selected memory cell is prevented from being written by setting the voltage of the non-selected bit line to be equal to or higher than the voltage on the control gate line of the selection transistor of the memory cell. The control gate (word line) and source (bit line) of the selection transistor are set in a reverse bias state, and the selection transistor is set in a deep off state. For the non-selected memory cell, the memory gate line MG is written as a ground voltage in order to prevent hot hole injection due to the band-to-band tunnel current and to shorten the transition time from the non-selected state to the selected state. Is set to a voltage level between the first and second select voltages. This prevents a channel current from flowing through the selection transistor in the non-selected memory cell to cause hot electrons or hot holes.

  In applications such as portable devices, a large storage capacity is required for storing application programs and download data, and a low power consumption performance is required because a battery is used as a power source. Further, in order to perform high-speed reading, it is required to reduce the bit line load. In an array configuration in which source lines extend in the column direction, the source lines are constituted by impurity regions (diffusion layers), and when the resistance value increases, the source line voltage changes due to the resistance. It becomes difficult to set the source line voltage accurately for the memory cell. For these reasons, an increase in memory cells in the column direction is suppressed. Therefore, the storage capacity is usually increased by increasing the number of memory cells in one row. In this array configuration, when writing is performed by transmitting the write voltage in parallel to the source lines of all the memory cells, the power consumption of the circuit for generating the source line write voltage is increased, and the drive capability is increased. To increase the size, the area occupied by the circuit increases (to increase the size of the transistor). As described above, in the MONOS type memory cell, the source line is constituted by an impurity region, and the load is larger than the metal wiring such as the bit line due to its junction capacitance. In order to drive the source line at high speed, it is necessary to increase the current driving capability of the source line driving circuit, and as the number of memory cells increases, the problem of increase in current consumption and layout area of the source line driving circuit becomes remarkable. Become.

  In writing, if a write voltage is transmitted in parallel to all the bit lines, the write current increases, and the load on the bit line write voltage generation circuit and the source line drive circuit increases. In order to avoid this, the write voltage is sequentially transmitted to each bit line, and writing to the memory cell is executed. That is, data writing is executed according to a so-called “page mode”. Also in this case, if the number of memory cells connected to one word line increases, the writing time for the entire memory cell of one word line becomes longer. Accordingly, in the selected row, the time during which the memory cells in the non-selected columns are disturbed becomes longer, and there is a problem that the reliability of data is lowered.

  Therefore, when the memory capacity is increased, there is a problem that the time during which the memory cell is disturbed at the time of writing becomes longer and the data retention characteristic is deteriorated.

  In the above-mentioned Patent Document 1, the improvement of the manufacturing process of the silicon nitride film is merely considered in order to improve the charge retention characteristics by reducing the charge trap sites of the silicon nitride film of the charge storage film. Therefore, no consideration is given to the problem of disturbance at the time of data writing.

  Patent Document 2 only considers forming a contact to the memory cell gate line formed on the side wall in a self-aligned manner with respect to the control gate line accurately and stably. The memory cell disturbance is not taken into consideration.

  In the configuration shown in Patent Document 3, data is written by a constant current method. The bit line voltage is set to the write inhibition voltage level, and a constant current is selectively supplied to the selected memory cell according to the threshold voltage of the selected memory cell. In this case, write disturb is avoided in the memory cells in the selected column / non-selected row. However, the configuration of Patent Document 3 cannot be applied to a configuration in which current flows from the source line to the bit line with a constant voltage bias. Further, this Patent Document 3 does not consider the disturbance of the memory cells in the selected row / non-selected column. It also describes that all the source lines may be selected at the same time. However, no consideration is given to the problem of the current driving capability of the source line current driving circuit due to the source line load. Further, no consideration is given to high-speed and stable data writing in the page mode. Only writing data to a 1-bit memory cell is being considered.

  Patent Document 4 has a problem of disturbance of memory cells in selected columns and non-selected rows. No consideration is given to the disturbance of the memory cells in the selected row / non-selected column. In particular, in the split gate type memory cell, since the source line functions as the drain region of the memory cell transistor, the problem of drain disturbance of the selected row and the non-selected column becomes large. In Patent Document 4, in order to solve the problem of the conventional example, the source line is provided in parallel with the word line. It is necessary to set the potential / state for each source line, and it is necessary to arrange a source line switch circuit or a source line drive circuit for each source line. This increases the layout area in the row direction in the memory cell array. In particular, as a memory array structure, a plurality of memory blocks are provided, and word lines are separated between the memory blocks. Erasing is executed in units of word lines or blocks. Therefore, the layout area of the memory block increases, and it becomes difficult to realize a nonvolatile semiconductor memory device having a small occupation area.

  In the configuration of Patent Document 4, bit lines are set in a floating state for memory cells in a selected row and a non-selected column. Therefore, the bit line voltage may increase due to capacitive coupling between the word line and the bit line. In this state, the source line of the selected row is at the ground voltage level, channel current flows, electron / hole pairs are generated by a high electric field between the source line and the word line, and electrons are injected into the floating gate. Or disturb that holes flow to the source line. Patent Document 4 does not take into consideration such a disturbance problem of memory cells in selected rows and non-selected columns.

  Further, Patent Document 4 shows a configuration in which the source line potential is controlled for each block in units of word lines and the write prevention voltage is supplied to the source line voltage of the non-selected block in the conventional configuration. However, in this conventional example, since a high electric field is applied between the control gate and the source line in the memory cell in the selected row (word line) and the non-selected column in the selected block, the drain disturbance is suppressed. It is difficult. Further, since the source line of each memory cell in the memory block is driven in parallel, no consideration is given to the current consumption of the source line driver circuit when the source line is driven to the write voltage level. Further, this Patent Document 4 does not show a configuration for further suppressing drain disturbance in a memory cell array configuration in which source lines are arranged in parallel with bit lines.

  Patent Document 5 aims to improve the write disturbance by increasing the upper limit of the write inhibition voltage of the bit line of the unselected column by the unselected word line voltage and the unselected source line voltage. In the configuration of Patent Document 5, charge is injected from the substrate region to the floating gate. Due to the charge injection from the entire surface of the substrate region, a disturbance that causes weak writing to the memory cells in the selected row and the non-selected column occurs. In order to reliably suppress this disturbance, Patent Document 5 uses a junction bias in the channel region as a reverse bias, suppresses the tunnel current due to the spread of the depletion layer of the non-selected memory cell, and relaxes the electric field in the vertical direction. To do.

  In Patent Document 5, although writing is performed by setting a voltage for each selected column, that is, for each source line and bit line, a configuration for writing data in a so-called page mode is not considered. Further, in a configuration in which a plurality of columns of memory cells are commonly connected to one source line, no consideration is given to a configuration that reduces the write disturbance of memory cells in a selected row and a non-selected column. In addition, since a write voltage and a write protection voltage are applied to the source line of the selected column and the source line of the non-selected column at the time of writing, a source line driving circuit is required for each column, and the circuit occupation area increases. To do.

  Therefore, it is an object of the present invention to suppress writing disturbance and to write data accurately and stably even when the storage capacity is increased, and to suppress an increase in circuit occupation area and power consumption. It is an object of the present invention to provide a non-volatile semiconductor memory device that can be used.

  The nonvolatile semiconductor memory device according to the present invention can be summarized as a source line in an array configuration in which bit lines and source lines are arranged in parallel and a plurality of columns of memory cells are commonly coupled to one source line. Data is written in units of. In this case, the bit line may be selectively set to the write voltage level and the write inhibition voltage level according to the write data in parallel regardless of the selection / non-selection of the corresponding source line. Alternatively, the bit line may be written in accordance with the write data in parallel only to the bit line corresponding to the selected source line, and the bit line corresponding to the selected source line in turn. The line may be set to a write state according to the write data.

  Data is written in units of source lines. Unselected source lines are maintained at unselected voltage levels. That is, in one embodiment, in the selected row, with the control gate line and the memory gate line maintained in the selected state, the source lines are sequentially driven to the selected state, and the bit lines are written according to the write data. The voltage is transmitted in a predetermined sequence. The source line non-selection voltage and the bit line write inhibition voltage are at the same voltage level.

  Therefore, in the selected row and non-selected column, for example, if the source line is in a selected state and a write inhibition voltage is transmitted to the bit line, this write inhibition voltage is a voltage equal to or lower than the source line selection voltage. A leak current flows from the source line to the bit line. The select transistor is in a weak inversion state and a high resistance state according to the voltage of the control gate line. This disturbance voltage stress is applied only during a period in which the corresponding source line is selected. Therefore, the period during which the memory cells in the selected row and the non-selected column are subjected to disturbance can be shortened.

  In one embodiment, when a source line is selected, when a write voltage (write selection voltage) is sequentially transmitted to a bit line in units of bit lines, a bit line is used for a memory cell in a non-selected column in a selected row. The write block voltage and the source line non-select voltage are at the same voltage level. Therefore, no current flows between the source line and the bit line, and the occurrence of disturbance is suppressed. As a result, the number of memory cells that receive disturbance in the selected row can be reduced, and data retention characteristics can be guaranteed.

  In addition, since data is written in units of source lines, the current consumption of the circuit for driving the source lines can be sufficiently reduced as compared with the case where all the source lines are driven to the selected state in parallel. Therefore, it is not required to increase the layout area of the source line driver circuit even if the memory capacity increases. Data writing can be performed stably at high speed using a source line driver circuit having a small occupation area and low power consumption.

  One source line is provided for a plurality of columns of memory cells. Therefore, it is not necessary to arrange a source line driver circuit corresponding to each column, and an increase in layout area is suppressed.

[Embodiment 1]
FIG. 1 schematically shows a cross-sectional structure of a nonvolatile memory cell used in the present invention. In FIG. 1, memory cell MC includes impurity regions 2a and 2b (first and second conduction nodes) formed on the surface of semiconductor substrate region 1 and a substrate region between these impurity regions 2a and 2b. On the control gate electrode 4 formed on the gate insulating film 3, the charge storage film 5 formed in an L shape adjacent to the gate insulating film 3 and the control gate electrode 4, and on the charge storage film 5 A memory gate electrode 6 to be formed is included.

  The charge storage film 5 includes a bottom oxide film 5a formed on the substrate region 1, a nitride film 5b formed on the bottom oxide film 5a, and a top oxide film 5c formed on the nitride film 5b. A nitride film 5b is disposed between the bottom oxide film 5a and the top oxide film 5c, and charges are accumulated in the nitride film 5b. The top oxide film 5c suppresses charge leakage between the nitride film 5b and the memory gate electrode 6.

  The select transistor ST is formed by the impurity region 2a, the gate insulating film 3, and the control gate electrode 4. A memory cell transistor MT is formed by the charge storage film 5, the impurity region 2b, and the memory gate electrode 6. These selection transistor ST and memory cell transistor MT are connected in series. When memory cell MC is selected, a channel is selectively formed between impurity regions 2a and 2b in accordance with the threshold voltage of memory cell transistor MT.

  Usually, impurity region 2a is formed extending in the column direction, and is electrically connected to an upper bit line arranged in common in one column of memory cells. Impurity region 2b extends continuously in the column direction to form a source line common to one column of memory cells. Control gate electrode 4 is connected to a control gate line extending in the row direction. A control gate electrode of a selection transistor of memory cells arranged in a row is commonly connected to the control gate line. Similarly, the memory gate electrode 6 is connected to a memory gate line extending in the row direction. Memory gate electrodes of memory cells arranged in a row are commonly connected to the memory gate line.

  In the memory cell MC shown in FIG. 1, the control gate electrode 4 of the selection transistor is formed before the memory gate electrode 6. Therefore, the gate insulating film of the select gate transistor can be formed in the same process as the gate insulating film of the logic portion formed on the same semiconductor substrate with a good quality of the silicon substrate interface (semiconductor substrate region). Since the floating gate is not used in the memory cell transistor MT, the transistor manufacturing process can be shared with a logic transistor formed on the same semiconductor chip. In the following description, it is assumed that both the select transistor ST and the memory cell transistor MT are N-channel transistors.

  In the memory cell MC shown in FIG. 1, when data is written, a voltage of about 11 V is applied to the memory gate electrode 6 and a voltage of about 5 V is applied to the impurity region 2b. A voltage slightly higher than the threshold voltage of select transistor ST (for example, 1 V) is applied to control gate electrode 4. A voltage (0.8 V) slightly lower than the voltage of the control gate electrode 4 is applied to the impurity region 2a. In this state, a weak inversion layer is formed below the gate insulating film 3 in the selection transistor ST. The memory cell transistor MT is in a strong ON state, and a current flows from the impurity region 2b toward the impurity region 2a.

  In the channel region, the boundary between the select transistor ST and the memory cell transistor MT is in a high resistance state, and a high electric field is generated in this region. Due to this high electric field, electrons flowing from the impurity region 2 a to the impurity region 2 b become hot electrons, and are attracted by the high voltage of the memory gate electrode 6 to be injected and accumulated in the nitride film 5 b of the charge storage film 5. In the memory cell transistor MT, since electrons are injected from the source side, electrons are injected by the source side injection method, and electrons can be injected with higher efficiency than the configuration using the tunnel current. This write state corresponds to a state in which the threshold voltage of memory cell transistor MT is high.

  In the erase operation, a negative high voltage of, for example, −5V is applied to memory gate electrode 6, and a positive high voltage of about 7V is applied to impurity region 2b. Even during erasing, the selection transistor is set to a voltage level of, for example, 1 V for the control gate electrode 4 and 0.8 V for the impurity region 2a (bit line). A current flows from the impurity region 2b toward the impurity region 2a. A high electric field (drain high electric field) is generated at the end of the impurity region 2b, and hot holes are generated. Due to the negative voltage of the memory gate electrode 6, the band-to-band tunneling current flows to the nitride film 5b of the charge storage film 5 through the bottom oxide film 5a, and hot holes are injected and stored in the nitride film 5b. As a result, the electrons injected at the time of writing are neutralized to enter the erased state. This erased state corresponds to a state where the threshold voltage of the memory cell transistor MT is low.

  At the time of data reading, memory gate electrode 6 and select control gate electrode 4 are set to a read voltage level of 1.5V, for example, read voltage of about 1V is supplied to impurity region 2a, and impurity region 2b is set to the ground voltage level. Set to. The data stored in the memory cell MC is determined based on the magnitude of the current flowing from the impurity region 2a (bit line) to the impurity region 2b (source line).

  For example, the memory cell transistor MT may have a negative threshold voltage at the time of erasing. Therefore, even if the memory cell transistor MT is in an over-erased state in which the threshold voltage is negative, if the selection transistor ST is in the off state, no current flows, which affects the reading of other memory cells. Does not reach.

  Note that the threshold voltage of the memory cell transistor MT may be a positive voltage in both the erased state and the written state of the memory cell transistor MT. It is only necessary that a current for identifying the writing and erasing state flows in the bit line (impurity region 2a) during data reading, and this current difference can be detected by the reading circuit (sense amplifier).

  The applied voltage of the non-selected memory cell will be described later in detail in connection with the disturbance problem.

  FIG. 2 schematically shows a whole structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 2, the nonvolatile semiconductor memory device includes a memory cell array 10 in which memory cells MC are arranged in a matrix. In memory cell array 10, bit line BL and source line SL are arranged corresponding to each column of memory cells MC. The source lines SL are interconnected for each predetermined number of memory cell columns. A control gate line CG and a memory gate line MG are arranged corresponding to each row of memory cells MC.

  Memory cell MC has the configuration shown in FIG. 1, and includes a memory cell transistor and a selection transistor. Control gate line CG is connected to the control gate electrode of the select transistor of memory cell MC, and memory gate line MG is connected to the memory gate electrode of the memory cell transistor of memory cell MC. Bit line BL and source line SL are coupled to a select transistor and a memory cell transistor, respectively. The bit line BL is formed of an upper metal wiring and is electrically connected to the impurity layer 2a shown in FIG. The source line SL is a diffusion layer wiring formed by the impurity region 2b shown in FIG.

  The nonvolatile semiconductor memory device further includes a control gate line selection drive circuit 12 that selects the control gate line CG and a memory gate line selection drive circuit 14 that selects the memory gate line MG. Control gate line selection drive circuit 12 drives control gate line CG corresponding to the addressed row of memory cell array 10 to a selected state in accordance with X address signal ADX. Control gate voltage Vcg is applied to control gate line selection drive circuit 12. The control gate voltage Vcg indicates a voltage transmitted to the control gate line, and has a selection voltage level and a non-selection voltage level. At the time of writing and erasing, the selection voltage level of control gate voltage Vcg is a voltage level of about 1 V, which is slightly higher than the threshold voltage of the selection transistor of the memory cell. In reading, the selection voltage level of control gate voltage Vcg is set to a power supply voltage level sufficiently higher than the threshold voltage of the selection transistor of the memory cell or a voltage level of about 3.5V.

  When writing according to X address signal ADX, memory gate line selection drive circuit 14 sets memory gate line MG corresponding to the addressed row to a high voltage level (for example, 11 V), and sets memory gate line MG in the unselected row. Is maintained at a voltage level of, for example, 3.5V. At the time of reading, memory gate line selection drive circuit 14 maintains memory gate voltage Vmg at a voltage level between the threshold voltage in the erased state and the written state. The memory gate voltage Vmg also indicates a voltage transmitted to the memory gate line, and has a selection voltage level and a non-selection voltage level.

  In FIG. 2, in order to avoid complication of the drawing, the memory gate line selection drive circuit 14 and the control gate line selection drive circuit 12 are shown to face each other with respect to the memory cell array 10. However, these selective drive circuits 12 and 14 may be arranged adjacent to each other on one side of the memory cell array 10.

  The nonvolatile semiconductor memory device further selects the addressed column of the memory cell array 10 in accordance with the Y address signal ADY and the source line selection drive circuit 16 that sequentially drives the source lines SL to the selected state during data writing. A column selection circuit 18 is included. The source line selection drive circuit 16 receives the source line voltage Vs, and sequentially drives the source lines SL of the memory cell array 10 to the selected state at the time of data writing. Thereby, data writing is executed in units of source lines SL. Source line voltage Vs is also a voltage transmitted to the source line, and has a write selection voltage level and a write non-selection voltage level at the time of writing and erasing. At the time of reading, source line voltage Vs is set to the ground voltage level.

  The column selection circuit 18 couples the bit line BL of the selected column of the memory cell array 10 to the input / output circuit 22 in accordance with the Y address signal ADY. At the time of data writing, write data transmitted onto the bit line BL via the input / output circuit 22 and the column selection circuit 18 is latched by the data latch circuit 20. Data latch circuit 20 receives voltage Vd as an operating power supply voltage. Although the configuration of the data latch circuit 20 will be described in detail later, write data transmitted to the bit line BL of the memory cell array 10 is latched for each bit line BL at the time of data writing. Next, when data is written in source line units by the source line selection drive circuit 16, the data latch circuit 20 transmits the voltage Vd to the corresponding bit line BL according to the latch data. Voltage Vd is a voltage of the bit line, and indicates the voltage level of the write selection voltage and the write inhibition voltage at the time of writing. In the first embodiment, in parallel in memory cell array 10, bit line BL is set by data latch circuit 20 to a voltage level corresponding to the corresponding write data.

  The nonvolatile semiconductor memory device further includes a control circuit 24 that controls internal operations in accordance with an external command CMD, and internal voltages that generate various voltages Vmg, Vs, Vcg, and Vd under the control of the control circuit 24. Generating circuit 26. The internal voltage generation circuit 26 sets the level of each voltage according to the operation mode.

  FIG. 3 is a diagram more specifically showing the configuration of the main part of the nonvolatile semiconductor memory device shown in FIG. In FIG. 3, in the memory cell array 10, memory cells MC are arranged in a matrix. Memory cell MC includes a selection transistor ST and a memory cell transistor MT. In FIG. 3, the charge storage film of the memory cell transistor MT is indicated by a thick line.

  Corresponding to each row of memory cells MC, memory gate lines MG0-MGn and control gate lines CG0-CGn are provided. Memory gate lines MG0-MGn are connected to the gate (memory cell gate electrode 6) of memory cell transistor MT in the corresponding row. Control gate lines CG0 to CGn are respectively connected to the gates (control gate electrodes 4) of the select transistors ST of the memory cells MC in the corresponding row.

  Bit lines BL0 to BLm are provided corresponding to the memory cell columns. Source lines SL0 to SLk are arranged so as to be shared by adjacent column memory cells MC. Here, k = m / 2. Bit lines BL0 to BLm are respectively connected to the first conduction node (impurity region) of the select transistor of the memory cell in the corresponding column. Source lines SL0-SLk are connected to the second conduction node (impurity region) of memory cell transistor MT of memory cell MC in the corresponding column.

  In FIG. 3, the source lines are shown to be shared by adjacent columns of memory cells. However, a local source line may be provided corresponding to each column of memory cells, and the local source line may be connected to the common source line for each predetermined number of memory cell columns. In this source line arrangement, data is written in units of common source lines.

  Control gate line selection drive circuit 12 includes control gate line drivers CDR0 to CDRn provided corresponding to control gate lines CG0 to CGn, respectively. These control gate line drivers CDR0 to CDRn transmit selection / non-selection voltages to corresponding control gate lines in accordance with a row designation signal (decode signal) from a decode circuit (not shown) included in control gate line selection drive circuit 12. Control gate line drivers CDR0 to CDRn receive control gate line voltage Vcg as an operating power supply voltage.

  Memory gate line selection drive circuit 14 includes memory gate line drivers MDR0 to MDRn provided corresponding to memory gate lines MG0 to MGn, respectively. Memory gate line selection drive circuit 14 also transmits memory gate line voltage Vmg at the selected or non-selected voltage level to the corresponding memory gate line in accordance with a row designation signal (decode signal) from a decode circuit (not shown).

  Source line selection drive circuit 16 includes a shift register circuit SFR that performs a shift operation in accordance with a shift clock signal (not shown), and source line drivers SDR0 to SDRk provided corresponding to source lines SL0 to SLk, respectively. The shift register circuit SFR sequentially drives its output to a selected state in accordance with a shift clock signal (not shown) during data writing. Source line drivers SDR0 to SDRk sequentially drive corresponding source lines SL0 to SLk to a selected state in accordance with an output signal from a corresponding output node of shift register circuit SFR.

  Column selection circuit 18 includes column selection gates CG0-CGm provided corresponding to bit lines BL0-BLm, respectively. Each of these column selection gates CG0 to CGm is turned on in accordance with a column selection signal Y0 to Ym from a column decoder (not shown) (included in the column selection circuit 18). When turned on, corresponding bit lines BL (BL0 to BLm) are turned on. Are coupled to the internal data line IOL. Internal data line IOL is coupled to input / output circuit 22 shown in FIG.

  Data latch circuit 20 includes data latches DL0 to DLm provided corresponding to bit lines BL0 to BLm, respectively. These data latches DL0 to DLm latch data transmitted to the corresponding bit lines at the time of data writing. According to these latch data, data latches DL0-DLm receive bit line voltage Vd as an operating power supply voltage, and transmit a write voltage or a write inhibition voltage to the corresponding bit line at the time of writing.

  FIG. 4 is a diagram showing an example of the configuration of data latches DL0 to DLm shown in FIG. In FIG. 4, data latch DLi (I = 0-m) includes an inverter 30 and a tristate inverter 31. Tristate inverter 31 is selectively activated in accordance with an output signal of gate circuit 32 receiving write activation signal WEN and column selection signal Yi. The tri-state inverter 31 is inactivated when the output signal of the gate circuit 32 is at the H level, and is in an output high impedance state. When the tri-state inverter 31 is activated, the inverter 30 and the tri-state inverter 31 constitute an inverter latch.

  Data latch DLi further includes a transfer gate 33 for coupling the output of tri-state inverter 31 to corresponding bit line BLi in accordance with latch instruction signal LAT.

  At the time of data writing, write activation signal WEN is activated, and latch instruction signal LAT is also activated. Accordingly, transfer gate 33 is rendered conductive, and the input of inverter 30 is connected to corresponding bit line BLi. When write data is transmitted to corresponding bit line BLi via a column selection gate (CSGi), column selection signal Yi is at the H level in the selected state. Therefore, in this state, the output signal of gate circuit 32 is at the H level, and tristate inverter 31 is in the output high impedance state. When transmission of write data to bit line BLi is completed, column selection signal Yi is inactivated, and tristate inverter 31 is activated accordingly, and the write data transmitted via the bit line is latched. .

  At the time of data writing, first, column selection signals Y0-Ym shown in FIG. 3, for example, are sequentially driven to a selected state in accordance with the page mode, for example, and write data is latched in corresponding data latches DL0-DLm.

  FIG. 5 is a flowchart showing an operation at the time of data writing of the nonvolatile semiconductor memory device shown in FIGS. Hereinafter, with reference to the flowchart shown in FIG. 5, the operation at the time of data writing of the nonvolatile semiconductor memory device shown in FIGS. 3 and 4 will be described.

  First, in this nonvolatile semiconductor memory device, it is determined whether data writing is designated by an external command (step SP1). This write instruction is determined by decoding an external command CMD by the control circuit 24 shown in FIG. The write operation is waited until a data write instruction is given.

  When a data write instruction is given, a block or word line (control gate line and memory gate line) including a selected memory cell is first selected according to a write address. The memory cells in the selected block or selected row are erased (step SP2). Here, when erasing is in units of blocks, each memory cell row is sequentially erased in this selected block (step SP3). At the time of erasing, erase verify may be executed using the data latch of the data latch circuit 20. For a memory cell that has been erased, the corresponding data latch is set to a state that latches the data that has been erased (the erase inhibiting voltage is transmitted to the bit line during erasure).

  When the erasure of the memory cell to be erased is completed, the write data is transferred and the write data is latched in the data latch (DL) (step SP4). In this case, for example, the bit lines are sequentially selected in the page mode, and write data is transferred and write data is latched. Here, when page writing is described as an example, a head address and head write data are given. Next, the head address is decoded by the column selection circuit 18, the corresponding column selection gate CG (any one of CG0 to CGm) is turned on, and data is written. At this time, latch instruction signal LAT shown in FIG. 4 is in the active state of H level, and data latches DL (DL0 to DLm) are all set to a state for taking in data on the corresponding bit lines. When column selection signal Yi is driven to the selected state, the corresponding bit line data is taken in and latched. Next, from this head address, a count circuit (not shown) starts a count operation, sequentially updates the column selection signal, and successively applied data is sequentially written and latched.

  The write data is transferred and latched until transfer and latch of the write data to one row of memory cells (control gate line and memory cells connected to the memory gate line) are completed (step SP5). Thereby, the latch of the write data of one row (one page) is completed.

  When the writing of all the write data is completed, the latch instruction signal LAT is once inactivated, and the data latch DL and the corresponding bit line BL are separated. In this state, the voltage required for writing is then set by internal voltage generation circuit 26 shown in FIG. In this state, the data latch DL and the corresponding bit line BL are connected again by activating the latch instruction signal LAT (step SP6). Thereby, the write data is transmitted to each bit line BL0-BLm. In this case, when the memory cell is not written, the corresponding bit line is set to a voltage level of about 1.5V, and a voltage of 0.8V is transmitted to the bit line to be written.

  As an example, data “0” corresponds to a state in which the threshold voltage of the memory cell transistor is high, that is, a write state, and data “1” is a state in which the threshold voltage of the memory cell transistor is low, that is, an erase state. Suppose that The bit line to which data “1” is transmitted needs to be written, and is set to a write selection voltage of 0.8V. On the other hand, the bit line to which data “0” has been transmitted does not need to be written, and is set to a write inhibition voltage level of 1.5V.

  If data “0” and “1” correspond to the L level and the H level, respectively, the bit line voltage can be set according to the write data at the time of writing by using the following configuration. . That is, in the data latch DL, as the operation power supply voltage Vd of the inverter 30 and the tristate inverter 31, the high side voltage Vdh is set to 1.5V, and the low side power supply voltage Vdl is set to 0.8V. To the bit line to which data “0” has been transmitted, an L level voltage, that is, a low-side power supply voltage Vdl is transmitted by the data latch, and this bit line is set to the write selection voltage level. For the bit line to which data “1” is transmitted, the H level voltage, that is, the high-side power supply voltage Vdh is transmitted by the corresponding data latch, and this bit line is set to the write inhibition voltage level. As a result, the bit line voltage corresponding to the voltage level corresponding to the write data can be set and selectively written (memory cells not to be written are in the erased state, ie, data “1”. Is maintained in the memory state).

  Further, to the memory gate line selection drive circuit 14, as the memory gate voltage Vmg, a high side voltage (selection voltage level) of 11V and a low side voltage (non-selection voltage level) of 3.5V are transmitted as operation power supply voltages. The As a result, the memory gate line MG of the selected row is set to 11V, and the memory gate line MG of the non-selected row is set to 3.5V.

  The control gate line selection drive circuit 12 receives 1V as the high side voltage (selection voltage level) Vcgh of the voltage Vcg and the ground voltage as the low side voltage (non-selection voltage level) Vcgl. Therefore, in this state, a voltage corresponding to the write data is transmitted to the bit lines BL0 to BLm in parallel and is latched by the data latch.

  In this state, the output of the shift register circuit SFR shown in FIG. 3 is sequentially driven to the selected state. Accordingly, the write voltage (5 V) is sequentially transmitted to source lines SL0 to SLk through corresponding source line drivers. Thereby, data writing is executed in units of source lines (step SP7). Even if the write voltage is transmitted to the bit line, the unselected source line is at the write inhibit voltage level. Therefore, the flow of current from the source line to the bit line is suppressed, and the write disturbance of the memory cells in the selected row and non-selected column is suppressed.

  It is determined whether the data writing in units of source lines has been performed for all the source lines (step SP8). The determination as to whether or not the final source line has been driven to the selected state is made by determining whether or not the source line SLk has been driven to the selected state or determining whether or not the final output is set to the selected state in the shift register circuit SFR.

  When the driving of all the source lines to the selected state is completed, the writing of data in one row of memory cells is completed. Next, it is determined whether writing to all addresses is completed (step SP9). If the writing has not been completed, in order to write data to the next memory cell row of the same block, the process returns to step SP4 again, and data transfer and latch to the memory cell of the next row is performed. Is called. In the writing block, this operation is repeatedly executed until data writing is completed for all addresses. When the writing to the writing address of the writing block is completed, the data writing is completed. Note that writing / erasing may be performed not in units of blocks but in units of word lines.

  That is, in the first embodiment, not all source lines are set to a selected state and data is written for each bit line, but data is written in units of source lines. In the case of writing data using hot electrons, the current consumption is large, and in the case where data is written in parallel to one row of memory cells, the current consumption may increase. However, since data is written in units of source lines, an increase in current consumption during data writing is sufficiently suppressed. Further, the source line selection drive circuit need only supply the write current in units of source lines. Therefore, even when the load on the source line is large, the write voltage can be stably transmitted to the selected source line at high speed.

  The bit lines are driven to the write selection state in parallel. However, the bit line is composed of an upper layer metal wiring, and its load is smaller than that of the source line. Therefore, even if the bit lines BL0 to BLm are driven in parallel to the write selection voltage level according to the write data, the bit line write voltage can be stably supplied. Further, the bit line arranged corresponding to the unselected source line is merely required to be precharged to the write selection voltage or write inhibition voltage level according to the write data. Therefore, even if write data is transmitted in parallel to the bit line, an increase in current consumption is sufficiently suppressed.

  FIG. 6 is a diagram showing signal waveforms of the bit line, source line and latch instruction signal at the time of data writing in the nonvolatile semiconductor memory device shown in FIG. At the time of writing, control gate line CG and memory gate line MG in the selected row are maintained at the selected voltage level.

  Prior to the start of writing before time t0, bit lines BL0-BLm are precharged to the write inhibition voltage level. Prior to the start of writing, each bit line may be precharged to the ground voltage level or precharged to the write selection voltage level.

  At time t0, data writing is started (steps SP6 and SP7 in FIG. 5). Thus, data latch DL and corresponding bit line BL are connected, and write data is transmitted to each bit line. Here, FIG. 6 shows, as an example, a case where data to be written is transmitted to all bit lines BL0 to BLm for the sake of simplicity. Depending on the write data, the voltage level of each of bit lines BL0-BLm is set to either 0.8V or 1.5V.

  When the voltage level of the bit line is set according to the write data at time t1, source lines SL0 to SLk are successively maintained in an active state for a predetermined period from time t2. Thereby, in each source line, a current flows in accordance with the voltage between the source line SL and the bit line BL, and electrons are injected into the charge storage film by hot electrons.

  At time t3, data writing to the memory cell connected to the final source line SLk is completed. After completion of the writing, the latch instruction signal LAT is driven to an inactive state at time t4. In this case, for example, the bit lines BL0 to BLm are precharged to a predetermined voltage level by a precharge circuit (not shown). FIG. 6 shows, as an example, the case where the bit line precharge voltage after completion of writing is at the write inhibition voltage level. However, the bit line precharge voltage may be a ground voltage level or a write selection voltage level (set to a desired precharge voltage level by the bit line precharge circuit). This completes the writing to one row of memory cells.

  Even at the time of writing, the write data latched in the data latch circuit is compared with the data in the memory cell, and a verify operation is performed to determine whether the writing has been performed correctly. According to the verify result, the latch data for the memory cell for which writing has been completed is set to data corresponding to the write inhibition voltage.

  FIG. 7 shows a voltage applied to each memory cell during data writing. FIG. 7 representatively shows memory cells MC00-MC03 and MC10-MC13 arranged in 2 rows and 4 columns. The memory gate line MG0 in the selected row is set to the 11V selected state, and the memory gate line MG1 in the unselected row is set to the 3.5V unselected state. The control gate line CG0 of the selected row is set to the 1V selected state, and the control gate line CG1 of the unselected row is set to the 0V unselected state. Source line SL0 is set to 5V in the write selected state, and source line SL1 is set to 1.5V in the non-selected state. Bit lines BL0 to BL3 are set to a write selection state of 0.8 V in order to perform data writing.

  Under this condition, in memory cells MC00 and MC01, a current flows from impurity region 2b connected to source line SL0 to impurity region 2a connected to bit line BL0. Control gate line CG0 is 1V, a weak inversion layer is formed in the channel region of select transistor ST, and hot electrons are injected into the charge storage film of memory cell transistor MT. The same applies to the memory cell MC01.

  Assume that memory cells MC00 and MC01 are memory cells to be maintained in the erased state. In this case, bit lines BL0 and BL1 are set to the write inhibition voltage level. This disturbance is now called A mode. In this A mode disturbance, the voltage difference between the source line SL and the bit line BL is large, a leak current flows, and there is a possibility that weak writing by hot electrons is performed. However, the period during which the corresponding source line SL0 is maintained in the selected state is short, and is simply a period in which writing is performed in the memory cells in the corresponding column. Compared with the configuration in which all the source lines are maintained in the selected state and the write data is sequentially transferred to the bit lines when sequential writing is performed on the memory cells in one row, the A mode disturbance is achieved. The period during which the data is received can be greatly shortened, and the deterioration of the reliability of the write data and the data retention characteristics can be suppressed.

  In memory cells MC02 and MC03, source line SL1 is 1.5 V, and current flows from source line SL1 to bit lines BL2 and BL3 via select transistor ST. This disturbance mode is now called the I mode. In this I-mode disturbance, the memory cells MC02 and MC03 are in the on state where the select transistor ST is weak, and the amount of current flowing is small. Therefore, even if weak writing occurs due to generation of hot electrons, these memory cells MC02 and MC03 are memory cells to be written. Therefore, the problem of erroneous writing does not occur.

  When memory cells MC02 and MC03 are non-write target memory cells, a write inhibition voltage is transmitted to bit lines BL2 and BL3. This write inhibition voltage is at the same voltage level as the voltage of the unselected source line. Therefore, no current flows through the memory cell when the source line is not selected. Even when the source line SL1 is selected, the control gate and the bit line of the selection transistor ST are in the reverse bias state, and the selection transistor ST is in the off state. Accordingly, erroneous writing of the memory cell to be maintained in the erased state is avoided.

  In memory cells MC10 and MC11, impurity region 2a connected to bit lines BL0 and BL1 is 0.8 V in a selected state, and impurity region 2a connected to source line SL0 is 5V. This disturbance of the unselected memory cells MC10 and MC11 is referred to as a G mode. In this G mode disturbance, the selection transistor ST is in a deep off state in which the control gate and the source are in a reverse bias state. Therefore, in the memory cells MC10 and MC11, the current flowing from the source line SL0 to the bit lines BL0 and BL1 is a substantially negligible amount of current. In addition, since the memory cell gate line MG1 is 3.5 V, the possibility of erroneous writing disturbance due to the tunnel current from the impurity region 2b to the charge storage film can be almost ignored.

  In memory cells MC12 and MC13, impurity region 2a connected to bit lines BL2 and BL3 is 0.8V, and impurity region 2b connected to source line SL1 is 1.5V. The control gate line CG1 is 0V, and the selection transistor is in a deep off state. The disturbance in this state is referred to as D mode. Even in this D-mode disturbance, although there is a possibility that electron injection into the charge storage film is caused by a tunnel current between the memory cell gate and the impurity region 2b, this possibility is sufficiently small and should be almost ignored. Can do.

  As described above, according to the first embodiment of the present invention, the following effects can be obtained. It is possible to sufficiently suppress the disturbance of the A mode, which has the greatest influence of disturbance, and to guarantee the reliability of retained data. Further, data is written in units of source lines, and data is not written in units of bit lines while all source lines are kept in a selected state. Therefore, the source line selection drive circuit is only required to drive one source line. Therefore, even if the storage capacity increases and the number of memory cells in one row increases, the current driving force required for the source line selection driving circuit does not increase, and the increase in the area occupied by the circuit is suppressed. Can do. In addition, the write voltage can be stably transmitted to the source line at high speed, and data can be written stably at high speed.

  In addition, it is possible to shorten the time during which the non-selected memory cells are subjected to disturbance, and to prevent erroneous writing due to disturbance during writing. In addition, since a plurality of columns of memory cells are connected to the source line, data can be written in parallel to the plurality of columns of memory cells, and the time required for writing can be reduced for each bit line. Compared to the writing configuration, it can be shortened.

[Embodiment 2]
FIG. 8 is a timing diagram representing an operation at the time of data writing of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. The entire configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention is the same as that of the nonvolatile semiconductor memory device shown in FIG. Also, in FIG. 8, the operation of setting all the memory cells in the selected row to the write state is shown as an example.

  In the second embodiment, as shown in FIG. 8, source lines SL0 to SLk are sequentially driven to a selected state as in the first embodiment. In the second embodiment, at the time of writing, the bit lines provided corresponding to the source lines in each selected state are sequentially driven to the selected state according to the write data. The bit line is maintained at the write inhibit voltage level when not selected. Therefore, when source line SL0 is set to the selected state, bit lines BL0 and BL1 arranged correspondingly are sequentially driven to the selected state. Similarly, when source line SL1 is driven to a selected state, corresponding bit lines BL2 and BL3 are sequentially driven to a selected state according to write data. Therefore, even if the source lines are sequentially driven to the selected state in units of source lines, the write voltage is transmitted to each bit line according to the write data, and writing is performed in units of bit lines. Therefore, current consumption can be reduced during writing and hot electron injection, and the writing voltage and writing current can be stably transmitted to the source line SL.

  Further, it is not necessary to supply the write current in parallel to the two columns of memory cells, and only the write current is supplied to the one column of memory cells. Therefore, a large current can be supplied to the selected memory cell. Therefore, the generation efficiency of hot electrons due to the high source electric field can be increased, and the time required for writing can be shortened. The source line selection period in the second embodiment is appropriately determined according to the time required for writing the selected memory cell. In Embodiments 1 and 2, it is not particularly required that the period during which the source line is maintained in the selected state is the same.

  FIG. 9 shows a voltage applied to the memory cell at the time of data writing in the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 9 also representatively shows memory cells arranged in 2 rows and 4 columns. In FIG. 9, the memory gate line MG0 of the selected row is set to 11V, and the memory gate line MG1 of the non-selected row is set to 3.5V. The control gate line CG0 of the selected row is set to 1V, and the control gate line CG1 of the non-selected row is set to 0V. The bit line BL0 in the selected column is set to 0.8V in the write selected state, and the bit lines BL1 to BL3 in the unselected column are set to 1.5V in the non-selected state. The selected source line SL0 is set to 5V, and the unselected source line SL1 is set to 1.5V.

  Under this condition, data is written to the memory cell MC00. In the memory cell MC01, the memory gate of the memory cell transistor MT and the impurity region 2b are selected, and in the selection transistor ST, the control gate is at the selected voltage level and the impurity region 2a is in the non-selected state. Therefore, an A-mode disturbance occurs as a disturbance in the memory cell MC01. However, the period during which memory cell MC01 receives the A-mode disturbance is sufficiently shorter than the period during which corresponding source line SL0 is maintained in the selected state. Therefore, the time for which the memory cell MC01 receives the A-mode disturbance can be sufficiently shortened, and the influence can be sufficiently suppressed.

  In memory cells MC02 and MC03, the bit line and the source line are at the same voltage level, and no channel current flows. Therefore, disturbance can be sufficiently suppressed. In the selected row, although there are memory cells MC01 that receive the A mode as the disturbance mode, the number thereof can be reduced as compared with the case where all the source lines are driven to the selected state in parallel. The time for each memory cell to receive the A mode disturbance can be shortened.

  Although memory cell MC10 receives G-mode disturbance, the time for which the write voltage is transmitted to bit line BL0 can be shortened as described above, and the influence thereof can be sufficiently suppressed. Can do.

  Memory cell MC11 receives F-mode disturbance. In this F-mode disturbance, the control gate and source (bit line) of the selection transistor ST are in a reverse bias state, and are sufficiently deep off, and the leakage current from the source line SL0 to the bit line BL0 is sufficiently suppressed. can do. Further, the voltage of the memory gate of the memory cell transistor MT is at a low voltage level, and the influence of hot electrons / hot holes can be sufficiently reduced.

  In memory cells MC12 and MC13, the voltage levels of the bit line and the source line are the same voltage level. Therefore, no leak current flows and disturbance can be sufficiently suppressed.

  FIG. 10 schematically shows a structure of a main portion of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. In the configuration shown in FIG. 10, data latch / transfer operations of data latches DL0-DLm provided for bit lines BL0-BLm are controlled according to output signals Z0-Zm of bit line shift circuit 40. The bit line shift circuit 40 performs a shift operation in accordance with the divided clock signal DCLK output from the frequency dividing circuit 42 that divides the shift clock signal SCLK, and sequentially drives the output signals Z0 to Zm to a selected state.

  Shift clock signal CLK is generated at the time of data writing from control circuit 24 shown in FIG. 2, and shift register circuit SFR performs a shift operation in accordance with shift clock signal SCLK. The configuration of the source line selection drive circuit 16 is the same as the configuration of the source line selection drive circuit 16 shown in FIG. 3, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. However, when the period during which the source line is maintained in the selected state differs between the first and second embodiments, the cycle of the shift clock signal SCLK is changed.

  FIG. 11 shows an example of the configuration of data latches DL0 to DLm shown in FIG. FIG. 11 representatively shows a configuration of data latch DLi provided for bit line BLi. The configuration of the data latch DLi shown in FIG. 11 is different from that of the data latch DLi shown in FIG. 4 in the following points. That is, to the transfer gate 33 that controls the connection with the bit line BLi, the output signal of the OR circuit 34 that receives the output signal of the gate circuit 32 and the output signal Zi from the bit line shift circuit 40 is replaced with the latch instruction signal LAT. Given. The other configuration of the data latch DLi shown in FIG. 11 is the same as the configuration of the data latch shown in FIG. 4. Corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the case of data latch DLi shown in FIG. 11, write data transmitted to bit line BLi is latched by inverter 30 and tristate inverter 31 in accordance with column selection signal Yi. The latch operation is the same as in the first embodiment.

  At the time of data writing, column selection signal Yi is in a non-selected state, and the output signal of gate circuit 32 is at L level. In response, tristate inverter 31 operates as an inverter and maintains the state in which the write data is latched. In accordance with an output signal Zi from the bit line shift circuit 40 (see FIG. 10), the transfer gates 33 are sequentially driven to a conductive state. The frequency-divided clock signal DCLK supplied to the bit line shift circuit 40 is obtained by frequency-dividing the shift clock signal SCLK by 2, for example, by the frequency-dividing circuit 42, and the period thereof is ½ times the shift clock signal SCLK. . Therefore, the shift cycle of the bit line shift circuit 40 is ½ times the shift cycle of the shift register circuit SFR, and when the source line SL is selected, the corresponding bit lines can be sequentially driven to the selected state.

  In accordance with the output signal of OR circuit 34, the corresponding bit line is driven to the write inhibit voltage level via a bit line precharge circuit (not shown), thereby maintaining the bit line after the write is at the write inhibit voltage level. can do. As an example, this bit line precharge circuit can be configured by using a P-channel MOS transistor that receives the output signal of the OR circuit 34 at its gate. When transfer gate 33 is non-conductive, the precharge MOS transistor precharges the corresponding bit line to the write inhibit voltage level.

  As described above, in the second embodiment, in the configuration in which the source line is driven to the selected state in units of source lines, data is written in units of bit lines. Therefore, current consumption during writing can be reduced. In addition, current consumption during writing of the circuit for driving the source line can be reduced, and the circuit scale can be reduced accordingly. Further, the write source line current can be stably supplied, and data can be stably written.

[Example of change]
FIG. 12 schematically shows a structure of a main portion of a modification of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. FIG. 12 shows a configuration of a portion related to column selection and data writing / reading. The memory gate line selection drive circuit and the control gate line selection drive circuit are not shown in order to simplify the drawing. Also in the third embodiment, the entire configuration of the nonvolatile semiconductor memory device is the same as the entire configuration of the nonvolatile semiconductor memory device shown in FIG.

  12, the nonvolatile semiconductor memory device includes a write data register 50 that sequentially stores write data from input / output circuit 22. Write data register 50 sequentially captures and latches write data in accordance with a clock signal applied from gate circuit 51 when write activation signal WEN is activated, and sequentially outputs the latch data onto internal data line IOL. .

  Gate circuit 51 is formed of an OR circuit that receives frequency-divided clock signal DCLK and write clock signal WCLK, generates a write shift clock signal in accordance with clock signal DCLK or WCLK, and supplies it to write data register 50.

  This nonvolatile semiconductor memory device includes a column decoder 52, a shift register 54, a gate circuit 56, and a Y gate circuit 57 as the column selection drive circuit 18 shown in FIG. Column decoder 52 decodes a given column address signal (not shown) when write activation signal WEN is inactivated, and generates a column selection signal. Shift register 54 performs a shift operation in accordance with frequency-divided clock signal DCLK from frequency dividing circuit 58 when write activation signal WEN is activated. The frequency dividing circuit 58 divides the shift clock signal SCLK by 2 to generate a divided clock signal DCLK.

  Gate circuit 56 is formed of an OR circuit, and outputs a signal obtained by ORing the output signals of shift register 54 and column decoder 52. The gate circuit 56 calculates the logical sum of each output signal of the column decoder 52 and the shift register 54 to generate column selection signals Y0 to Ym for the column selection gates included in the Y gate circuit 57.

  In Y gate circuit 57, column select gates (CSG 0 to CSGm) are provided for each bit line included in memory cell array 10. These column select gates (CSG0 to CSGm) are selectively turned on in accordance with a column select signal applied from OR circuit 56 to each of the column select gates to couple internal data line IOL to the bit line of the selected column.

  Source line selection drive circuit 16 has the same configuration as that of the first or second embodiment, and performs a shift operation in accordance with shift clock signal SCLK to drive a source line (not shown) to a selected state during data writing.

  The internal data line IOL is further provided with a read data register 60 that latches read data when data is read. The output latch data of read data register 60 is output as external read data via input / output circuit 22 during data reading. The latch data of the read data register 60 may be used for comparing the coincidence / mismatch with the data stored in the write data register 50 during the write verify operation.

  In the nonvolatile semiconductor memory device shown in FIG. 12, at the time of data writing, write data register 50 receives write data supplied from input / output circuit 22 as a clock signal (write clock signal WCLK) from gate circuit 51. ) And sequentially latch. The write data register 50 may be configured, for example, first-in first-out.

  At the time of data writing, source line selection drive circuit 16 sequentially drives source lines SL0-SLk to a selected state in accordance with shift clock signal SCLK. At this time, the shift register 54 performs a shift operation according to the divided clock signal DCLK, the column selection gates (CSG0 to CSGm) of the Y gate circuit 57 are sequentially turned on, and the bit lines BL0 to BLm are sequentially connected to the internal data lines. Electrically connected to the IOL. At this time, the gate circuit 51 also generates a shift clock signal according to the divided clock signal DCLK. Data stored in write data register 50 is sequentially transmitted onto internal data line IOL in accordance with a clock signal output from gate circuit 51. Therefore, data stored in write data register 50 is sequentially transmitted onto bit lines BL0 to BLm via Y gate circuit 57.

  The frequency divider 58 divides the shift clock signal SCLK by 2, and the frequency of the frequency-divided clock signal DCLK is twice that of the shift clock signal SCLK. Therefore, also in the configuration shown in FIG. 12, when source lines SL0 to SLk are sequentially driven to the selected state, the bit lines corresponding to the selected source lines can be sequentially driven to the selected state. In this case, data is sequentially written using a write data register 50 provided for page mode operation. Therefore, it is not necessary to provide a data register for data writing for each bit line in the memory cell array 10, and the layout area of the memory cell array is reduced.

  The operation waveform at the time of data writing in this modified example is the same as the timing chart shown in FIG. A source line selection cycle is set in accordance with shift clock signal SCLK. The selection period of the Y gate, that is, the selection period of the bit line is set by the divided clock signal DCLK.

  At the time of data reading, column decoder 52 performs a decoding operation, Y gate circuit 57 selectively couples the bit line of the selected column to internal data line IOL, and read data is latched in read data register 60. .

  As described above, according to the second embodiment of the present invention, the source lines are sequentially driven to the selected state, and the bit lines corresponding to the selected source lines are sequentially driven to the selected state. Therefore, data writing is performed in units of bit lines, current consumption due to hot electron injection during data writing can be reduced, and data writing can be performed stably at high speed. Further, in the circuit for generating the internal voltage (write voltage), the source line is driven to the selected state in units of the source line, the current consumption of the portion generating the source line voltage is reduced, and the scale of the internal voltage generating circuit Can be reduced.

[Embodiment 3]
FIG. 13 is a timing diagram representing an operation at the time of data writing in the nonvolatile semiconductor memory device according to the third embodiment of the present invention. FIG. 13 also shows an example of the operation when writing is performed on the memory cell in the selected row. The voltage at the time of writing to the selected bit line is set according to the write data.

  In the third embodiment, as shown in FIG. 13, when source lines SL0 to SLk are sequentially activated, the corresponding bit lines are driven to the selected state (write state) in parallel according to the write data. To do. That is, when source line SL0 is driven to a selected state, write data is transmitted to corresponding bit lines BL0 and BL1 in parallel, and selective data writing is executed according to the write data. Similarly, when the source line SL1 is driven to the selected state, write data is transmitted in parallel to the corresponding bit lines BL2 and BL3, and data writing is executed. Thereafter, the same operation is repeated. At the end of one page, when source line SLk is selected, write data is transmitted in parallel to bit lines BLm-1 and BLm, and data writing according to the write data is executed.

  FIG. 14 shows an example of a voltage applied to the memory cell at the time of data writing in the third embodiment of the present invention. In FIG. 14, control gate line CG0 and memory gate line MG0 are driven to a selected state of 1V and 11V, respectively, and control gate line CG1 and memory gate line MG1 are maintained in a non-selected state of 0V and 3.5V, respectively. The The source line SL0 is set to the selected state (5V), and the source line SL1 is in the non-selected state (1.5V).

  In this state, a write voltage (0.8 V) is transmitted to bit lines BL0 and BL1 at the time of data writing. On the other hand, a 1.5V write inhibit voltage is transmitted to bit lines BL2 and BL3 corresponding to unselected source line SL1. Therefore, in memory cells MC02 and MC03 in the non-selected column on the selected row, since the source line and the bit line are at the same potential, current does not flow and occurrence of the previous I-mode disturbance is prevented. . At most, in the memory transistor MT of these memory cells, a tunnel current may only flow due to a high electric field between the memory cell gate and the impurity region (drain region) 2b. However, the disturbance that induces the tunnel current is extremely smaller than the influence of the A-mode disturbance that generates the hot electrons, and can be almost ignored.

  In memory cells MC12 and MC13, selection transistor ST is in a deep off state with its control gate and source being reverse-biased, and source line SL1 and bit lines BL2 and BL3 are at the same potential, and a leakage current flows. Absent. Also in the memory cell transistor MT, the voltage difference between the memory gate and the drain (impurity region 2b) is small, and no charge leakage of the charge storage film occurs. Therefore, no disturbance occurs in these memory cells MC12 and MC13.

  In the memory cells MC10 and MC11 in the non-selected row selection column, a G-mode disturbance occurs. However, the period in which this G mode disturbance occurs is only a period during which the corresponding source line SL0 is maintained in the selected state, and is a sufficiently short period. Therefore, it is possible to sufficiently shorten the time for which the memory cells in the non-selected rows are subjected to the G-mode disturbance, and the influence can be substantially suppressed.

  FIG. 15 schematically shows a structure of a main portion of the nonvolatile semiconductor memory device according to the third embodiment of the present invention. In the arrangement shown in FIG. 15, the configuration of source line selection drive circuit 16 is the same as in the first and second embodiments. Corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. .

  On the other hand, for data latches DL0 to DLm, a bit line shift circuit 70 for performing a shift operation in accordance with a shift clock signal SCLK supplied from control circuit 24 is provided. In this bit line shift circuit 70, two outputs (for example, Z0 and Z1) are short-circuited, and the data latch for the bit line corresponding to the selected source line is simultaneously set to a conductive state. The configuration of data latches DL0 to DLm is the same as that shown in FIG. Thereby, when the source line is selected, the write data can be transmitted to the corresponding bit line pair.

  In the third embodiment, data is simply written to two bit lines in units of source lines. Therefore, data is only written to the 2-bit memory cell, and current consumption during writing is suppressed (the driving capability of the circuit that drives the source line can be reduced).

  Note that as the configuration of the bit line precharge circuit, the same configuration as that described in the second embodiment can be used. A bit line precharge circuit (for example, a P channel MOS transistor) is selectively activated by the output signal of the OR circuit 34 shown in FIG. 11, whereby the voltage corresponding to the write data is applied to the bit line corresponding to the selected source line. , And the bit line after completion of writing can be maintained at the write inhibition voltage level.

  As described above, according to the third embodiment of the present invention, a source line is selected in units of source lines at the time of data writing, and writing is performed in parallel with respect to a bit line provided corresponding to the selected source line. Data is transmitted and data is written. Therefore, it is possible to eliminate memory cells that receive a disturbance such as A mode or I mode in a selected row, to realize stable data writing, and to suppress deterioration of data retention characteristics. it can. Further, as in the first and second embodiments, the write voltage can be stably supplied to the source line at high speed without increasing the layout area of the source line selection drive circuit.

  In the first to third embodiments described above, two columns of memory cells (two bit lines) are arranged in common with respect to one source line. However, more columns of memory cells may be commonly coupled to one source line. A local source line is provided in each column, and a predetermined number of local source lines are coupled to the common source line and are driven to a selected state in units of the common source line. Also in this case, the same effects as in the first to third embodiments can be obtained when memory cells in a smaller number of columns than all the memory cell columns in one row are coupled to a common source line.

  Further, as a memory cell structure, in addition to a memory cell using an ONO film as a charge storage film, the present invention can be applied to a memory cell structure that stores data by storing charges in a floating gate. it can. Further, the present invention can be applied even to a memory cell structure in which a selection transistor is not provided.

  The applied voltage level at the time of writing may be a voltage value different from the values shown in the first to third embodiments. The level of each voltage at the time of writing may be determined as appropriate according to the characteristics of the element.

  The present invention is applied to a non-volatile semiconductor memory device that accumulates electric charges in an insulating film, and is non-volatile that can be stably written with a low current consumption with little disturbance during data writing. A semiconductor memory device can be realized. This non-volatile semiconductor memory device may be integrated on the same semiconductor chip as other logic to constitute a system LSI, or may be used as a single non-volatile semiconductor memory device.

It is a figure which shows roughly the cross-sectional structure of the memory cell of the non-volatile semiconductor memory device to which this invention is applied. 1 schematically shows an entire configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. FIG. 3 is a diagram specifically showing a configuration of a main part of the nonvolatile semiconductor memory device shown in FIG. 2. FIG. 4 is a diagram illustrating an example of a configuration of a data latch illustrated in FIG. 3. FIG. 7 is a flowchart showing an operation at the time of data writing of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 6 is a timing chart representing an operation at the time of data writing of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. It is a figure which shows the applied voltage to the memory cell at the time of the data writing in Embodiment 1 of this invention. FIG. 11 is a timing chart representing an operation at the time of data writing of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. It is a figure which shows the applied voltage to the memory cell at the time of the data writing in Embodiment 2 of this invention. It is a figure which shows roughly the structure of the principal part of the non-volatile semiconductor memory device according to Embodiment 2 of this invention. It is a figure which shows an example of a structure of the data latch shown in FIG. It is a figure which shows schematically the structure of the example of a change of the non-volatile semiconductor memory device according to Embodiment 2 of this invention. FIG. 16 is a timing chart representing an operation at the time of data writing in the nonvolatile semiconductor memory device according to the third embodiment of the present invention. It is a figure which shows the applied voltage to the memory cell at the time of the data writing of the non-volatile semiconductor memory device according to Embodiment 3 of this invention. It is a figure which shows roughly the structure of the principal part of the non-volatile semiconductor memory device according to Embodiment 3 of this invention.

Explanation of symbols

  MC memory cell, MT memory cell transistor, ST selection transistor, 2a, 2b impurity region, 4 control gate electrode, 6 memory cell gate electrode, 5 charge storage film, 10 memory cell array, 12 control gate line selection drive circuit, 14 memory gate Line selection drive circuit, 16 source line selection drive circuit, 18 column selection circuit, DL0-DLm data latch, SFR shift register circuit, 40, 70 bit line shift circuit, 42, 58 frequency divider circuit, 50 write data register, 57 Y gate circuit, 54 shift register, 52 column decoder.

Claims (8)

A plurality of memory cells arranged in a matrix, each having a selection transistor and a memory transistor connected in series with the selection transistor and storing data according to the stored charge of the charge storage film;
A plurality of control gate lines arranged corresponding to each of the memory cell rows, each connected to a gate electrode of a select transistor of a memory cell in the corresponding row;
A plurality of memory gate lines arranged corresponding to each of the memory cell rows, each connected to a gate electrode of a memory transistor of a memory cell in the corresponding row;
A plurality of bit lines arranged corresponding to each of the memory cell columns, each connected to a first conduction node of a select transistor of a memory cell in the corresponding column;
A plurality of source lines arranged corresponding to the memory cell columns, each connected to a second conduction node of a memory transistor of a memory cell in the corresponding column ;
A control gate line driving circuit for driving a control gate line arranged corresponding to a selected row to a selected state at the time of data writing;
The data write operation, the memory gate line selection drive circuit for driving the memory gate line in the selected state arranged corresponding to the selected択行,
A source line that drives the plurality of source lines sequentially to a write selected state in a predetermined sequence in accordance with a clock signal within a period in which both the control gate line and the memory gate line are in a selected state during the data writing. selection drive circuit, and during the data writing, the write voltage level of the writing in accordance with at least one bit lines arranged corresponding to the memory cell column corresponding to the source line of the write selected state write data A non-volatile semiconductor memory device comprising a bit line selection drive circuit for driving to a select state. A plurality of nonvolatile memory cells arranged in a matrix, each having first and second conduction nodes and storing data in a nonvolatile manner;
A plurality of bit lines arranged corresponding to each of the non-volatile memory cell columns, each connected to a first conduction node of a non-volatile memory cell of the corresponding column;
Before SL are arranged corresponding to the nonvolatile memory cell columns, each of which second conduction node plurality of source lines coupled to the non-volatile memory cells in the corresponding column,
A row selection drive circuit for driving nonvolatile memory cells in a selected row to a selected state at the time of data writing;
During the data writing, a plurality of source lines source line select driver circuits is set to sequentially write select state in a predetermined sequence in response to the clock signal, and when the data writing, the source line of the write selected A non-volatile semiconductor memory device comprising a bit line selection drive circuit that sets at least one bit line arranged corresponding to a write selection state in accordance with write data.   The bit line selection drive circuit drives the plurality of bit lines in parallel to a write selection state according to write data, whereby a source line in a write selection state and a write selection state in a selected row 3. The nonvolatile semiconductor memory device according to claim 1, wherein data is written in accordance with write data to a memory cell connected between the bit line.   The bit line selection drive circuit sequentially drives a predetermined number of bit lines arranged corresponding to the source lines set in the write selection state by the source line selection drive circuit to the write selection state according to write data. The nonvolatile semiconductor memory device according to claim 1.   The bit line selection drive circuit selectively selects a predetermined number of bit lines arranged corresponding to the source lines in the write selection state by the source line selection drive circuit according to write data in parallel. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is driven to a state. And further comprising a plurality of common source lines to which the plurality of source lines are connected in common every predetermined number ,
The nonvolatile semiconductor memory device according to claim 1, wherein the predetermined sequence is sequentially set to a write state in units of the common source line . The source line selection drive circuit includes :
A register circuit that performs a shift operation according to the clock signal and sequentially drives the output to a selected state ;
The nonvolatile semiconductor memory device according to claim 6, further comprising a plurality of source line driver circuits provided corresponding to each of the plurality of common source lines and driving corresponding common source lines in accordance with an output of the register circuit . The nonvolatile semiconductor memory device according to claim 6, wherein the data writing is a page mode writing .

Images