JP5158764B2 - Phase shift method and circuit - Google Patents

Description

  The present invention relates to a phase shift method and circuit for obtaining a desired delay time by connecting a plurality of delay cells having a single delay time in series and enabling only an arbitrary number of stages, and in particular, is necessary. The present invention relates to a phase shift method and a circuit capable of greatly reducing the number of delay cell stages by connecting a small number of stages in a loop and repeatedly using them instead of connecting all the delay cells in series.

  With the spread of DDR SDRAM (DDR: Double Data Rate), a DLL (Delay Locked Loop) circuit has become indispensable. Although called a DLL circuit, a substantial purpose is a circuit that generates an absolute delay for performing a phase shift of 90 degrees or 270 degrees with respect to a reference clock.

  As one configuration method of the phase shift circuit, a desired delay time can be obtained by connecting a plurality of delay cells having a single delay time in series and enabling them by an arbitrary number of stages (for example, , See FIG. 9 of Patent Document 1). The configuration of the delay cell is not limited, but may be a CMOS gate circuit, for example. In order for the shift amount (delay time) in this phase shift circuit to be an absolute delay time of 90 degrees with respect to the reference clock (for example), it is only necessary to know the reference clock cycle Tref and the delay time Tdl per delay cell. , (Tref / Tdl) × (90/360) The number of delay cells may be enabled.

  However, since it is difficult to measure analog time in a semiconductor integrated circuit, a DLL circuit having the same delay cell as the phase shift circuit as an internal variable delay is locked in one cycle of the reference clock, and used when locked. The clock cycle is measured using a master DLL circuit that outputs the number of delay stages as “time for one clock cycle”. If the master DLL circuit is locked using, for example, 400 stages of delay cells, an absolute delay of 90 degrees of the reference clock can be obtained by enabling 100 stages of delay cells multiplied by 1/4 by the phase shift circuit. It is done.

Note that the master DLL circuit normally keeps track of delay time fluctuations of delay cells due to temperature fluctuations even after being locked, and updates the number of delay stages per clock cycle (for example, when the temperature rises and delay cell delays). If the delay time increases, the phase shift circuit updates from 400 stages → 399 stages → 398 stages), and the phase shift circuit can maintain the relationship of “validate the number of stages that is 1/4 of the number of stages for one clock cycle”. Thus, an absolute delay of 90 degrees can always be maintained.
Japanese Patent Laid-Open No. 11-298307

  One of the problems of the phase shift circuit using this DLL circuit is the cell area. Although the DDR SDRAM standard varies from generation to generation, since a data rate of 800 Mbps (using both edges of a 400 MHz clock) is also in the field of view, it is said that the resolution of delay adjustment needs several tens of ps. That is, several stages of delay cells are several tens of ps. On the other hand, not all high-speed data rates are required for all applications, and the application may be used at the lower limit of the DDR SDRAM frequency (about 80 MHz in the first generation).

  Therefore, if the phase shift circuit is intended to have general versatility in terms of frequency, it is necessary to provide a large number of delay cells on the order of 1000 stages in consideration of variations in delay time (especially, conditions under which the delay time is minimized). is there. In the above-mentioned Patent Document 1, it is described that the number of stages necessary for the paragraph 0068 is connected in series.

  An object of the present invention is to provide a phase shift method and circuit capable of greatly reducing the number of stages of delay cells by connecting a small number of delay cells in a loop and repeatedly using the same delay cells. It is.

To achieve the above object, the phase shift method of the invention according to claim 1, the unidirectional edge signal rising or falling edge of the input signal, the first delay and the first delay cell and a plurality of stages connected in series input to the first stage of the first delay cell of the cell group, the first of said first specific number-th of the first delay cell other than the delay cell in the final stage of the delay cell group reacts, and before the first delay cell of the final stage are reacted loop connected by connecting the output side of the first delay cell of the final stage on the input side of the first delay cell of the first stage The rising or falling reverse edge signal output from the first delay cell at the final stage is input to the first delay element at the first stage, and the one-way and reverse edge signals are input to the first delay element. Before the desired number of stages after the tour reaches the predetermined number And outputs an output signal from the first delay cell.
The invention according to claim 2, in the phase shift method according to claim 1, the output signal output from the first delay cell of said desired stage, and the second delay cells to a plurality of stages connected in series The output is performed after passing through one or more of the second delay cells in the two delay cell groups .
The invention according to claim 3, the rising edge signal of the input signal is delayed by the first route by a method according to claim 1, according to the edge signal falling of the input signal to the claim 1 It is delayed by a second route in a way, from the first root output signal and the output signal obtained in the second route obtained in, and generates a new output signal.
According to a fourth aspect of the present invention, in the phase shift method, the rising edge signal of the input signal is delayed in the first route by the method of claim 2 , and the falling edge signal of the input signal is the claim. 2 is delayed by a second route by the method described in, from an output signal obtained by said first output signal and the second route obtained by route, and characterized by generating a new output signal To do.
According to a fifth aspect of the present invention, a phase shift circuit includes a first edge detection circuit that detects a rising or falling edge of an input signal, and a first delay cell that delays an output signal of the first edge detection circuit. a first delay cell group in which a plurality stages connected in series, the output signal of the first delay cell of a particular number th other end-stage of the first delay cell group is changed, and the final stage Before the output signal of the first delay cell changes , the output side of the first delay cell at the final stage is connected to the input side of the first delay cell at the first stage to make a loop connection a control circuit, before SL when it counts a predetermined number set in advance the number of changes in the same direction of the output signal of a desired number-th of the first delay cell of the first delay cell group and a counter for outputting a pulse The pulse output from the counter is an output signal. And said that the content was.
The invention according to claim 6 is the phase shift circuit according to claim 5, a second delay cell group where the second delay cells to a plurality of stages connected in series, the pulse front Stories second outputs from said counter one or more of the foregoing second and a cell number setting circuit which via a delay cell, before Symbol one or more of said second delay cell of the second delay cell group among the delay cell group It is characterized in that the signal passed through is used as an output signal.
Phase shift circuit of the invention according to claim 7, comprising a second edge detection circuit, a phase shift circuit and a phase shift of the rising side of claim 5 for inputting the rising edge signal of the input signal, the 6. The phase shift circuit according to claim 5, wherein a falling edge signal of an input signal is inputted, and the second edge detection circuit is shifted by the rising phase shift unit. The output signal is raised by a signal, and the output signal is lowered by a signal shifted by the phase shift unit on the falling side.
Phase shift circuit of the invention according to claim 8, comprising a second edge detection circuit, a phase shift circuit and a phase shift of the rising side of claim 6 for inputting a rising edge signal of the input signal, the 7. The phase shift circuit according to claim 6, wherein a falling edge signal of an input signal is inputted, and the second edge detection circuit is shifted by the rising phase shift unit. The output signal is raised by a signal, and the output signal is lowered by a signal shifted by the phase shift unit on the falling side.

  According to the present invention, it is possible to significantly reduce the number of delay cells connected in series as compared with the prior art, and to significantly reduce the cell area. With this configuration, the minimum operating frequency is defined by the delay loop duty. It depends only on the maintenance characteristics and the scale of the number of times of patrol, and the increase of the delay cell area considering the lower limit of the corresponding frequency is also suppressed. Further, since the delay process is performed using only the rising edge, it becomes easy to perform the delay process while maintaining the duty of the pulse input to the input terminal and to output it to the output terminal.

  FIG. 1 shows the configuration of a phase shift circuit according to an embodiment of the present invention. A represents a phase shift unit on the rising edge side of the input clock, and B represents a phase shift unit on the falling edge side of the clock. 11 is an input terminal for inputting a clock, 12 is an output terminal for a delayed clock, 13A, 13B and 14 are D-type flip-flops, 15A and 15B are input selectors, and 16A and 16B are delays of a single delay time. Cells, 17A and 17B are loop switching control circuits, 18A and 18B are counters, 19A and 19B are delay cells having a single delay time, 20A and 20B are AND gates, 21A and 21B are output selectors, and 22 is a cell stage number setting circuit. , 23 is a loop cycle number setting circuit.

  The loop switching control circuit 17A detects when a rising edge appears at the output of a predetermined delay cell (four stages in FIG. 1) of the delay cells 16A connected in series in eight stages, and detects the rising edge. Is switched to the loop side, but when the value set by the counter 18A is counted, the input selector 15A is switched to the flip-flop 13A side, and at the same time, the flip-flop 13A is reset. The same applies to the loop switching control circuit 17B.

  The cell stage number setting circuit 22 includes one AND gate of the same number of stages among the eight AND gates 20A of the phase shift section A on the rising edge side and the eight AND gates 20B of the phase shift section B on the falling edge side. Is given an H signal, thereby opening only the AND gate. When any of the first and seventh stages of the AND gate 20A opens the gate, the output selector 21A selects the input side on the delay cell 19A side, and when only the final AND gate 20A opens the gate. The input side of the final AND gate 20A is selected. The same applies to the output selector 21B. As a result, the pulses output from the counters 18A and 18B do not pass through the AND gates 20A and 20B and one or more stages of delay cells 19A and 19B, or no delay cells, and are input to the clock terminal or reset terminal of the flip-flop 14. Is done.

  The loop circulation number setting circuit 23 gives the same preset value to the counters 18A and 18B. When the counters 18A and 18B are counted up to the preset value, the control signals are supplied to the loop switching control circuits 17A and 17B as described above, and at the same time, pulses are output to the AND gates 20A and 20B.

  This embodiment is characterized in that a plurality of stages of serially connected delay cells are connected in a loop, and a signal is circulated in the loop to generate a delay time. In FIG. 1, between the input selector 15A and the counter 18A and Between the input selector 15B and the counter 18B, a loop is constituted by eight stages of delay cells 16A and 16B, respectively. Further, delay cells 19A and 19B having a number of stages that is one stage less than the number of loop stages (seven stages in the figure) are connected between the counter 18A and the output selector 21A and between the counter 18B and the output selector 21B, respectively. Thus, a delay time as a phase shift circuit is generated. For example, when a delay time of 100 stages is required, in the shift section A on the rising edge side, after the input signal has made 12 rounds of the loop of the 8-stage delay cell 16A in the previous stage, the remaining 4-stage delay cells in the subsequent stage If output through 19A, there will be a total of 100 stages. The same applies to the shift part B on the falling edge side. Any number of stages can be specified in the same manner. This stage number designation is performed by the loop cycle number setting circuit 23 and the cell stage number setting circuit 22.

  Now, in the initial state, the flip-flop 13A receiving the clock from the input terminal 11 is in a state (Q = L) once reset and waiting for the rising edge of the clock. The input selector 15A at the subsequent stage is in a state where the output Q of the flip-flop 13A is selected. Since the delay cell 16A is a normal rotation type (not an inverting inverter), the outputs of all the delay cells 16A forming the loop are L.

  In this state, when the input terminal 11 receives the rising edge of the clock, the output Q of the flip-flop 13A changes to H, which is transmitted to the delay cell 16A through the selector 15A, and the output of the delay cell 16A sequentially changes to H. To go. However, since this loop does not have a self-oscillation function like a voltage-controlled oscillator, even if it is connected to the loop, all nodes are fixed at L or H as it is, and the counter 18A in the subsequent stage is counted up. Can not be made.

  Therefore, it is necessary to intentionally insert the falling edge as well as the rising edge. The H signal that has received the rising edge of the input terminal 11 travels through the delay cell 16A, but when it reaches the fourth half of the half, the loop switching control circuit 17A detects it and controls the input side of the input selector 15A. Switching from the flip-flop 13A side to the loop side, the flip-flop 13A is reset at the same time. When the input side of the input selector 15A is switched to the loop side, the output of the delay cell 16A at the eighth stage is still L, so this falling edge will be transmitted through the delay cell 16A. Since the edge is looped back, as a result, the rising edge and the falling edge circulate around this loop, and the counter 18A counts the number of circulations.

  When the counter 18A reaches the count value preset by the loop circulation number setting circuit 23, the counter 18A notifies the loop switching control circuit 17A to that effect, and the loop switching control circuit 17A flips the input side of the input selector 15A to the flip-flop. Switching to the 13A side and releasing the reset of the flip-flop 13A, the loop of the delay cell 16A and the flip-flop 13A are in the initial state, and wait for the rising edge of the next clock.

  At the same time, the counter 18A sends a rising edge (precisely, a pulse having a sufficient H width as a clock of the flip-flop 14 of the output stage) to the subsequent AND gate 20A, and passes through the AND gate 20A that opens the gate. The signal is input from the output selector 21A to the clock terminal of the flip-flop 14 via the predetermined number of delay cells 19A or not via the delay cell 19A. Thereby, the flip-flop 14 sets its output Q to H, and a series of phase shift operations based on the rising edge of the clock input to the input terminal 11 is completed.

  The falling edge of the clock input to the input terminal 11 is input to the flip-flop 13B, and is similarly subjected to a delay in the falling-side phase shift unit B in the same manner as the rising-edge-side phase shift unit A described above. , Input as a reset signal of the flip-flop 14 from the output selector 21B, and the output Q of the flip-flop 14 is set to L. As a result, a pulse having the same pulse width as the clock input to the input terminal 11 and receiving a predetermined delay is output from the output Q of the flip-flop 14 to the output terminal 12.

  The biggest difficulty in maintaining duty in a circuit that requires multistage connection of delay cells such as a phase shift circuit is that the difference between Tdlh (rising delay) and Tdhl (falling delay) for one delay cell is accumulated by the number of delay stages. It is how to solve the point that is done. In the conventional configuration in which the delay cells are arranged in a single row, the difference between Tdlh and Tdhl directly affects the maintenance of the duty, and the fluctuation due to use conditions increases. However, in the configuration of this embodiment, the input clock When both the rising edge and falling edge are passing through the delay cell, only Tdlh is related to the phase shift time, so there is no concern about the accumulation of duty collapse.

  Of course, even in the phase shift circuit of this embodiment, there is no loss of duty. In the flip-flop 14 on the output side, the rising edge of the output Q clock is a delay from the rising edge of the output signal of the output selector 21A to the rising edge of the Q output, and the falling edge is from the falling edge of the output signal of the output selector 21B. It is generated including the delay of the falling edge of the Q output, which may cause duty collapse. However, these portions are fixed duty fluctuations that do not depend on conditions such as the input frequency and the phase shift amount, and can be adjusted relatively easily by adjusting the delay time, and therefore do not cause much problem. As described above, the phase shift circuit of this embodiment has a feature that it is easy to output the output to the output terminal 12 while maintaining the duty of the clock input to the input terminal 11.

  In the phase shift circuit of this embodiment, the delay line is divided into the phase shift section A on the rising edge side and the phase shift section B on the falling edge side. This corresponds to a flexible (wide) shift amount. This is an inevitable configuration. For example, when the H / L width of the clock input to the input terminal 11 is 50/50 and a phase shift of 270 degrees is desired, the delay loop falls while the rising edge is being shifted. Since an edge is input, different delay lines are required on the rising side and the falling side. If the rising edge and the falling edge do not interfere with each other in the circuit, for example, if the phase shift circuit is limited to 90 ° shift, the delay cells 16A and 19A are shared with the delay cells 16B and 19B by devising the input / output unit. You can also

  Further, the number of delay cells 16A and 16B to be looped is not limited to eight. The number of stages is preferably set to the minimum number of stages at which the peripheral circuits of the delay loop, specifically, the counters 18A and 18B and the loop switching control circuits 17A and 17B can operate normally, and the number of stages must be an even number. Absent.

  Further, the timing of the falling edge input to the loop is triggered when the output of the fourth stage, which is exactly half the number of stages of the delay cells 16A and 16B, rises, but this is also not limited to “half”. The timing when the output of any delay cell other than the final stage rises may be used as a trigger. Usually, the time Tdlh through which the rising edge passes through the circuit and the time Tdhl through which the falling edge passes are not equal. Therefore, if the loop of the rising edge and the falling edge is left in the loop circuit of the delay cells 16A and 16B, the H width Or L width is gradually narrowed, and the pulse is finally lost. Therefore, the falling edge should be input at the optimum point so that the signal does not disappear even if the rising edge and the falling edge are turned as many times as the number of loops to be handled.

  The optimum points are the duty maintaining characteristics of the delay loop including the input selectors 15A and 15B (time difference between Tdlh and Tdhl), the H pulse width at which the counters 18A and 18B operate normally, and the loop switching control circuits 17A and 17B being the input selector 15A. , 15B is determined in consideration of the delay time required for switching, and there is no other constraint.

  Furthermore, in the current mainstream process, a delay cell that combines only unconventional logic gates (and forwards through at least two stages of inverters because of normal rotation) guarantees a delay time of several tens of ps under all conditions. Because it is difficult to do so, we have realized a time difference (resolution) that cannot be engraved only by switching the number of logic gate stages, for example, by switching the capacitance value hung on the inverter output. And so on.

  In this regard, the delay cell that is the subject of the present embodiment corresponds to a “coarse adjustment unit” and a “course adjustment unit” for engraving rough steps. The fine adjustment unit is usually provided separately from the coarse adjustment unit and is not included in the configuration of FIG. 1 because the area is not large, but if necessary, a delay cell 16A at a specific stage is shown in FIG. The delay cell 16A1 having a fine adjustment unit may be replaced. The same applies to the other delay cells 16B, 19A, 19B. In FIG. 2, INV1 and INV2 are inverters, SW11 to SW1N and SW21 to SW2N are switches, and C11 to C1N and C21 to C2N are capacitors. By selectively turning on one or more of the switches SW11 to SW1N and SW21 to SW2N, the delay time can be finely adjusted.

  Of course, there is a possibility that a resolution of several tens of ps can be achieved only by switching the number of stages of delay cells due to process evolution, and in this sense, the fine adjustment unit is not an essential configuration.

  FIG. 3 is a diagram showing the configuration of a phase shift circuit according to another embodiment of the present invention in which the delay cells 16A and 19A are shared with the delay cells 16B and 19B. 14 'is an output-side flip-flop, 24 is an OR circuit for inputting the outputs of the flip-flops 13A and 13B and inputting the input to the input selector 15A, and 25 is a reset control circuit for detecting a rising edge of the input clock and generating a reset signal. It is. Here, the falling-side phase shift part B (excluding the flip-flop 13B) in FIG. 1 is deleted.

  At the rising edge of the clock input to the input terminal 11, the output of the flip-flop 13A becomes H, and at the falling edge, the flip-flop 13B becomes H. In either case, the output of the OR circuit 24 becomes H, and the delay element The operation of the 16A loop starts and phase shift is performed. That is, if one of the rising edge and falling edge of the input clock arrives, delay processing is performed. However, if a reverse edge arrives at the input terminal 11 before the loop operation (specified number of loops) is completed, a malfunction occurs, and the amount of phase shift is limited. The output side flip-flop 14 'constitutes a simple divide-by-2 circuit (T-type flip-flop) in which the inverted Q output is connected to the D input. Note that the flip-flop 14 'needs to be reset so that the logic of the output signal DOUT matches the input signal DIN. Here, the input clock is monitored by the reset control circuit 25, and the circuit always detects the input clock. It starts to move from the rising edge. Others are the same as the phase shift circuit of FIG.

It is a block diagram which shows the structure of the phase shift circuit of the Example of this invention. It is a circuit diagram of a delay cell having a fine adjustment unit of the same embodiment. It is a block diagram which shows the structure of the phase shift circuit of another Example of this invention.

Explanation of symbols

11: Input terminal 12: Output terminal 13A, 13B, 14, 14 ': Flip-flop 15A, 15B: Input selector 16A, 16B: Delay cell 17A, 17B: Loop switching control circuit 18A, 18B: Counter 19A, 19B: Delay cell 20A, 20B: AND gates 21A, 21B: output selector 22: cell stage number setting circuit 23: loop cycle number setting circuit 24: OR circuit 25: reset control circuit

Claims (8)

A unidirectional edge signal rising or falling edge of the input signal, input to the first delay cell of the first stage of the first delay cell group where the first delay cell and a plurality of stages connected in series, said first delay before the first delay cell of a particular number th other than the first delay cell in the final stage of the cell group to react, and the first delay cell of the final stage are reacted in the final stage said output side of the first delay cell connected in a loop by connecting to the input side of the first delay cell of the first stage, the rising or falling output from the first delay cell of the final stage The edge signal in the reverse direction is input to the first delay element in the first stage, the edge signals in the one direction and the reverse direction are circulated, and the first number of the desired number of stages after the circulation reaches a predetermined number of times. A phase shift method characterized by outputting an output signal from a delay cell . The phase shifting method according to claim 1, wherein
Said output signal output from the first delay cell of said desired stage, one or more of the second delay cell of the second delay cell group where the second delay cells to a plurality of stages connected in series A phase shift method characterized by outputting after passing through. The rising edge signal of the input signal is delayed by the first route by a method according to claim 1, delayed by the second route by the method described edge signal falling of the input signal to the claim 1 is allowed, the phase shift method, characterized in that the output signal obtained in the output signal obtained by the first route and the second route, to generate a new output signal. The rising edge signal of the input signal is delayed by the first route by a method according to claim 2, delayed by a second route by the method described edge signal falling of the input signal to the claim 2 is allowed, the phase shift method, characterized in that the output signal obtained in the output signal obtained by the first route and the second route, to generate a new output signal. A first edge detection circuit for detecting a rising or falling edge of an input signal;
A first delay cell group in which a plurality of first delay cells for delaying an output signal of the first edge detection circuit are connected in series;
Before the output signal of the first delay cell of a particular number th other end-stage of the first delay cell group varies, and the output signal of the first delay cell of the final stage is changed in the loop switching control circuit to loop connection by connecting the output side of the first delay cell of the final stage on the input side of the first stage of the first delay cell,
And a counter for outputting a pulse when the count by a predetermined number set in advance the number of changes in the same direction before Symbol first output signal of a desired number-th of the first delay cell of the delay cell group,
A phase shift circuit characterized in that the pulse output from the counter is an output signal. The phase shift circuit according to claim 5, wherein
A second delay cell group in which a plurality of second delay cells are connected in series;
And a cell number setting circuit which via one or more of the second delay cell of the pulse of the previous SL second delay cell group outputted from said counter,
Before Symbol phase shift circuit, characterized in that a second output signal a signal obtained by way of one or more of the second delay cell of the delay cell group. A second edge detection circuit;
6. The phase shift circuit according to claim 5, wherein the rising edge signal is input to the rising edge phase signal, and the falling edge signal of the input signal is input. As the phase shift part on the falling side,
The second edge detection circuit raises an output signal with a signal shifted by the rising-side phase shift unit, and drops the output signal with a signal shifted by the falling-side phase shift unit. A characteristic phase shift circuit. A second edge detection circuit;
A phase shift circuit and a phase shift of the rising side of claim 6 for inputting a rising edge signal of the input signal, a phase shift circuit according to claim 6 for inputting an edge signal of a falling edge of the input signal As the phase shift part on the falling side,
The second edge detection circuit raises an output signal with a signal shifted by the rising-side phase shift unit, and drops the output signal with a signal shifted by the falling-side phase shift unit. A characteristic phase shift circuit.

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