JP5157242B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including a CMOS structure.

  Patent Document 1 discloses that in an output buffer circuit having a CMOS structure, a capacitor is provided between a source and a gate to ensure that an output terminal is in a high-impedance state when a power supply voltage is lower than a normal use condition range immediately after power-on. The technique which can be made is disclosed.

  The design of the semiconductor integrated circuit (also referred to as an IC) is not limited to the case immediately after the power is turned on, and must be assumed to be different from normal use conditions. This is because the power supply terminal and the external signal terminal are exposed to the outside of the IC, and there is a danger that a reverse voltage is applied due to a human operation error. For example, in the output buffer circuit having the CMOS structure shown in FIG. 1, unlike the normal operation, the power supply terminal VSS is set to 0 [V], the output terminal OUT is opened or opened, and the power supply terminal VDD is set to, for example, −16 [ Suppose that a negative potential of V] is applied. In this case, current flows through the parasitic bipolar transistor formed in the substrate that supports the pMOS transistor 3 and the nMOS transistor 4, leading to lead disconnection or thermal breakdown.

In particular, in an automobile using an IC for in-vehicle use, it is assumed that there is a high risk of erroneously connecting the battery in reverse during repair, inspection, or maintenance, and an IC that does not break down even in such a situation is required. Therefore, in a conventional IC for in-vehicle use, a diode is inserted in series between the power supply circuit of the power supply unit and the power supply terminal of the IC in order to cope with a case where a + 12V power supply is connected in reverse. To take measures against the abnormal current of the IC.
JP-A-5-175824

  However, the configuration using a diode has a drawback in that only a voltage lower than the power supply voltage to which the output voltage from the IC is supplied is output due to a forward voltage drop of the diode during normal operation. In particular, when a power supply voltage needs to be used as a reference voltage as in a linear Hall IC, there is a problem that such a voltage drop is undesirable.

  An object of the present invention is to provide a semiconductor integrated circuit capable of preventing destruction when an abnormal voltage is applied to a power supply terminal or an external signal terminal while minimizing adverse effects during normal operation.

A semiconductor integrated circuit according to the present invention includes at least a pair of MOS transistors each formed in a well provided in a semiconductor substrate and connected in series via output terminals to form a CMOS structure, and a source terminal of the MOS transistor or A semiconductor including a pair of power supply terminals each connected to a drain terminal, and at least one pair of guard contacts each connected to the pair of power supply terminals and respectively providing a power supply potential to the semiconductor substrate and the well A current limiting resistor provided in the substrate and inserted in one of a current path between the guard contact and the power supply terminal; and provided in the semiconductor substrate and connected to the output terminal. At least one other MOS transistor that conducts in accordance with the applied voltage of the transistor and shuts off one of the pair of MOS transistors. A drain terminal of the other MOS transistor is connected to a drain terminal of the one MOS transistor, a source terminal of the other MOS transistor is connected to a gate terminal of the one MOS transistor, and The gate terminals of the other MOS transistors are connected to one of the pair of power supply terminals .

  The semiconductor integrated circuit according to the present invention provides a configuration in which a power supply limiting resistor is inserted between a guard contact surrounding a pair of CMOS transistors having a CMOS structure and a power supply terminal. As a result, it is possible to prevent destruction when an abnormal voltage is applied to the power supply terminal or the external signal terminal while minimizing adverse effects during normal operation.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First embodiment>
FIG. 2 shows the first embodiment, and shows the entire circuit configuration including the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 according to the present invention includes an output enable circuit 80 including a plurality of logic operation circuits U1 to U7, and an output buffer circuit 90 including an nMOS transistor 30 and a pMOS transistor 40. With the configuration of the output enable circuit 80 and the output buffer circuit 90, the semiconductor integrated circuit 10 takes the input signal into the input terminal IN and outputs the output signal OUT to the outside in accordance with the enable signal supplied to the enable signal terminal OE. The function to output to. Since the connection relationship of the plurality of logic operation circuits U1 to U7 in the configuration of the output enable circuit 80 is a normal output enable circuit configuration, description thereof is omitted here.

  Referring to the output buffer circuit 90, the output enable circuit 80 is connected so that the signal C is supplied to the gate of the pMOS transistor 40, and the signal G from the output enable circuit 80 is supplied to the gate of the nMOS transistor 30. Normally, the power supply terminal VDD for supplying a positive potential is connected to the drain of the pMOS transistor 40, the source of the pMOS transistor 40 is connected to the output terminal OUT and the drain of the nMOS transistor 30, and the source of the nMOS transistor 30 is normally connected. Is connected to a power supply terminal VSS for supplying a negative potential. Further, a resistor R1 is inserted in the current path between the P-type substrate 11 that is a semiconductor substrate that supports the nMOS transistor 30 and the power supply terminal VSS. The potential J of the P-type substrate 11 provides a power supply potential to an nMOS transistor (not shown) formed inside the logic operation circuits U1 to U7.

  FIG. 3 shows an example of the upper surface arrangement of the circuit configuration shown in the drawing. As shown in the figure, the semiconductor integrated circuit 10 is formed as a 4000 μm square chip, for example. An output enable circuit 80 and an output buffer circuit 90 are arranged on the upper surface of the chip of the semiconductor integrated circuit 10, and an arbitrary circuit can be formed in the remaining area. In the output buffer circuit 90, a pMOS transistor 40 surrounded by an N-type contact 22 as a guard contact, an nMOS transistor 30 surrounded by a P-type contact 12 as a guard contact, and an output terminal OUT are arranged. .

  Further, the power supply terminal VDD and the power supply terminal VSS are arranged on the upper surface of the chip of the semiconductor integrated circuit 10, and the resistor R1 is arranged in the vicinity of the power supply terminal VSS. The resistor R1 functions as a current limiting resistor and is formed of a material such as a poly resistor. The poly resistor can be formed by implanting impurities such as phosphorus into polysilicon. The resistance value of R1 is typically selected to be 400Ω, and is selected to be about 480Ω at maximum. Specifically, when the junction potential difference between the P-type substrate and the N well is 0.5 V, 15.5 V / 50 mA = 310 Ω (min) is selected.

  FIG. 4 shows a partial cross section of the output buffer circuit shown in FIG. Here, the nMOS transistor 30 is formed on the P-type substrate 11, and the pMOS transistor 40 is formed in the N-well 21 formed on the P-type substrate 11 in the vicinity thereof.

  The nMOS transistor 30 includes a gate 31 to which a signal G (see FIG. 2) is supplied, and a source 32 and a drain 33 which are N-type regions. The source 32 is connected to the power supply terminal VSS, and the drain 33 is connected to the output terminal OUT. A P-type contact 12 and a P-type contact 13 are formed on the P-type substrate 11 on both sides of the nMOS transistor 30 to supply the power supply potential of the power supply terminal VSS via a current path. The P-type contact 12 and the P-type contact 13 are normally formed continuously so as to surround the nMOS transistor 30.

  Parasitic transistors Q4 and Q5 are formed parasitically inside the P-type substrate 11 below the nMOS transistor 30. The parasitic transistor Q4 forms an NPN transistor by using the source 32 as an N region, the P-type substrate 11 as a P region, and the drain 33 as an N region. The parasitic transistor Q5 forms an NPN transistor by using the source 32 as an N region, the P-type substrate 11 as a P region, and the N well 21 as an N region.

  The pMOS transistor 40 includes a gate 41 to which a signal C (see FIG. 2) is supplied, and a source 42 and a drain 43 which are P-type regions. The source 42 is connected to the output terminal OUT, and the drain 43 is connected to the power supply terminal VDD. On both sides of the pMOS transistor 40, an N-type contact 22 and an N-type contact 23 are formed on the N-well 21 to supply the power supply potential of the power supply terminal VDD via a current path. The N-type contact 22 and the N-type contact 23 are normally formed continuously so as to surround the pMOS transistor 40.

  A plurality of parasitic transistors Q1 to Q3 and a parasitic diode D1 are parasitically formed in the N well 21 below the pMOS transistor 40. The parasitic transistor Q1 is a PNP transistor by using the P-type substrate 11 as the P region, the N well 21 as the N region, and the drain 43 as the P region. The parasitic transistor Q2 is a PNP transistor by using the P-type substrate 11 as the P region, the N well 21 as the N region, and the source 42 as the P region. The parasitic transistor Q3 is a PNP transistor by using the source 42 as a P region, the N well 21 as an N region, and the drain 43 as a P region. Further, the parasitic diode D1 forms a PN type diode by using the drain 43 as a P region and the N type contact 23 as an N region.

  Further, the distance between the nMOS transistor 30 and the N well 21, preferably the distance between the drain 33 of the nMOS transistor 30 and the N-type contact 22 is increased to, for example, 10 μm or more.

  With reference to FIG. 4, the operation of the semiconductor integrated circuit in the first embodiment when the power supply is abnormal will be described. Here, it is assumed that the power supply terminal VSS is fixed to 0 [V] as a reference potential, the output terminal OUT is opened or opened, and a negative potential (for example, −16 [V]) is applied to the power supply terminal VDD as an assumed reverse voltage. .

  Although the base current of the parasitic transistor Q1 flows, the potential difference between the P-type contact 13 and the power supply terminal VDD decreases due to the voltage drop of the resistor R1, and the base current of the parasitic transistor Q1 is limited. As the base current of the parasitic transistor Q1 is limited, the collector currents of the parasitic transistors Q1 to Q5 also decrease.

  In the first embodiment described above, by applying the semiconductor integrated circuit according to the present invention, the base current and the collector current of the parasitic transistor Q1 are limited, and the collector current of the parasitic transistor Q2 is limited to prevent device destruction. The On the other hand, during normal operation, no current limiting resistor is inserted in series with the source and drain of the nMOS transistor 30, so that the circuit characteristics such as current capability are not affected.

  Further, a P-type contact 13 and an N-type contact 22 are inserted in a portion facing the nMOS transistor 30 and the N-well 21. As a result, the thyristor structure constituted by the parasitic transistor Q1 and the parasitic transistor Q5 is separated by the P-type contact 13, and a large current is prevented from flowing through the path from the source of the nMOS transistor 30 to the source of the pMOS transistor 40 by the thyristor. ing.

  Further, the distance between the drain of the nMOS transistor 30 and the N-type contact 22 is increased (for example, 10 μm or more). Thereby, the substrate resistance to the parasitic transistor Q1 is increased, and the collector current of the parasitic transistor Q1 is reduced. In general, when the base width is widened, the current amplification factor of the bipolar transistor is lowered. Therefore, by widening the base width of the parasitic transistor Q5, the current amplification factor of the parasitic transistor Q5 is also reduced to prevent a large current.

  Note that, instead of the form in which the resistor R1 is connected to the current path between the power supply terminal VSS and the P-type contact, a form in which the resistor R1 is connected to the current path between the power supply terminal VDD and the N-type contact is also possible. It is.

<Second embodiment>
FIG. 5 shows a second embodiment and shows the entire circuit configuration including the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 10 according to the present invention includes an output enable circuit composed of logic operation circuits U1 to U7 and an output buffer circuit composed of an nMOS transistor 30 and a pMOS transistor 40, in substantially the same manner as in the first embodiment.

  In the second embodiment, a resistor R2 is further connected to the current path between the output terminal OUT and the drain of the nMOS transistor 30, and the nMOS transistor 50 is connected between the drain of the nMOS transistor 30 and the gate of the nMOS transistor 30. An nMOS transistor 70 is connected between the drain of the nMOS transistor 30 and the input of the logic operation circuit U7 which is a logic inversion circuit (INV). The gates of both the nMOS transistor 50 and the nMOS transistor 70 are connected to the power supply terminal VSS.

  FIG. 6 shows an example of the top surface arrangement of the circuit configuration shown in FIG. As in the first embodiment, the semiconductor integrated circuit 10 is formed as, for example, a 4000 μm square chip, and an output buffer circuit 90 is disposed on the upper surface of the chip. In the output buffer circuit 90, a pMOS transistor 40 surrounded by the N-type contact 22, an nMOS transistor 30 surrounded by the P-type contact 12, and an output terminal OUT are arranged. Further, two nMOS transistors 50 and 70 are arranged adjacent to the nMOS transistor 30 surrounded by the P-type contact 12.

  A resistor R2 is disposed in the vicinity of the nMOS transistor 30. The resistor R2 functions as a current limiting resistor and is formed of a material such as a poly resistor. The poly resistor can be formed by implanting impurities such as phosphorus into polysilicon. The resistance value of R2 is typically 112Ω, and the maximum value is 134Ω. Specifically, when the potential difference between the source and drain of the nMOS transistor 30 is 0.5 V, 4.5 V / 50 mA = 90Ω needs to be selected as the minimum value.

  FIG. 7 shows a partial cross section of the output buffer circuit shown in FIG. Here, the nMOS transistor 30 is formed on the P-type substrate 11, and the pMOS transistor 40 is formed in the N-well 21 formed on the P-type substrate 11 in the vicinity thereof. The connection relationship between the nMOS transistor 30 and the pMOS transistor 40 and the power supply terminal VSS and the power supply terminal VDD is basically the same as in the first embodiment, but between the drain 33 of the nMOS transistor 30 and the output terminal OUT. A resistor R2 is inserted in the current path. Further, the parasitic transistors Q1 to Q5 and the parasitic diode D1 are formed parasitically as in the case of the first embodiment.

  With reference to FIG. 7, the operation of the semiconductor integrated circuit in the second embodiment when the power supply is abnormal will be described. Here, it is assumed that the power supply terminal VSS is fixed to 0 [V] as a reference potential, the power supply terminal VDD is opened or opened, and a negative potential (−5 [V] in the example) is applied to the output terminal OUT as an assumed reverse voltage. To do.

  Although the base current of the parasitic transistor Q4 flows, the potential difference between the P-type contact 13 and the output terminal OUT decreases due to the voltage drop of the resistor R1, and the base current of the parasitic transistor Q4 is limited. As the base current of the parasitic transistor Q4 is limited, the collector current of the parasitic transistor Q4 decreases. By adding the resistor R2, the potential difference between the drain of the nMOS transistor 30 and the power supply terminal VSS decreases, and the collector current of the parasitic transistor Q4 further decreases.

  When a negative potential is applied to the output terminal OUT, the source potential of the nMOS transistor 50 and the nMOS transistor 70 becomes lower than the gate potential, the nMOS transistor 50 and the nMOS transistor 70 are turned on, and the input signal F and the nMOS of the logic operation circuit U7. The gate input signal G of the transistor 30 and the drain of the nMOS transistor 30 are at the same potential, and the nMOS transistor 30 is reliably turned off. If the nMOS transistor in the logic operation circuit U7 is not turned off, the gate signal G of the nMOS transistor 30 is divided by the nMOS transistor 50, and the nMOS transistor 30 may not be turned off reliably. This avoids such a situation.

  In the second embodiment described above, by applying the semiconductor integrated circuit according to the present invention, the resistor R2 is inserted between the drain of the nMOS transistor 30 and the output terminal OUT. Thereby, the current of the nMOS transistor 30 and the parasitic transistor Q4 is limited, and the thermal destruction of the device is prevented.

  An nMOS transistor 50 is added between the gate and drain of the nMOS transistor 30. Thereby, even when an abnormal voltage is applied to the output terminal OUT, the nMOS transistor 50 is turned on, so that the gate potential and the drain potential of the nMOS transistor 30 are made the same, and the on-current of the nMOS transistor 30 is cut off. As a result, lead disconnection or thermal breakdown can be further prevented.

  Further, an nMOS transistor 70 is added between the input of the logic operation circuit U7 and the drain of the nMOS transistor 30. Thereby, even when an abnormal voltage is applied to the output terminal OUT, the nMOS transistor 70 is turned on, so that the nMOS transistor in the logic operation circuit U7 is turned off, and the gate potential and the drain potential of the nMOS transistor 30 are surely set. In the same manner, the on-current of the nMOS transistor 30 can be cut off.

  The semiconductor integrated circuit according to the present invention has been described by taking a digital output circuit as an example, but can also be applied to an analog output circuit such as a voltage follower amplifier.

It is explanatory drawing explaining the operation | movement at the time of abnormality in the general CMOS output circuit without negative voltage protection. 1 is a block diagram showing an entire circuit configuration including a semiconductor integrated circuit according to the present invention according to a first embodiment. FIG. FIG. 3 is a top view illustrating an example of a top surface arrangement of the circuit configuration illustrated in FIG. 2. FIG. 3 is a cross-sectional view showing a partial cross section of the output buffer circuit shown in FIG. 2. It is a block diagram which shows the 2nd Example and shows the whole circuit structure containing the semiconductor integrated circuit by this invention. FIG. 6 is a top view illustrating an example of a top surface arrangement of the circuit configuration illustrated in FIG. 5. FIG. 6 is a sectional view showing a partial section of the output buffer circuit shown in FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 11 P-type substrate 12, 13 P-type contact 22, 23 N-type contact 21 N well 31, 41 Gate 30, 50, 70 nMOS transistor 32, 42 Source 33, 43 Drain 40 pMOS transistor 80 Output enable circuit 90 Output buffer circuit D1 Parasitic diode OUT Output terminal Q1-Q5 Parasitic transistor R1, R2 Resistance U1-U7 Logic operation circuit VDD, VSS Power supply terminal

Claims (3)

At least a pair of MOS transistors each formed in a well provided in a semiconductor substrate and connected in series with each other via an output terminal to form a CMOS structure, and each source terminal or drain terminal of the MOS transistor are connected to each other. A pair of power supply terminals, and at least one pair of guard contacts respectively connected to the pair of power supply terminals and supplying a power potential to the semiconductor substrate and the well,
A current limiting resistor provided in the semiconductor substrate and inserted in one of the current paths between the guard contact and the power supply terminal ;
And at least one other MOS transistor provided in the semiconductor substrate and conducting in response to a voltage applied to the output terminal and blocking any one of the pair of MOS transistors,
The drain terminal of the other MOS transistor is connected to the drain terminal of the one MOS transistor, the source terminal of the other MOS transistor is connected to the gate terminal of the one MOS transistor, and the gate of the other MOS transistor. A terminal is connected to one of the pair of power supply terminals .   2. The semiconductor device according to claim 1, further comprising a second current limiting resistor provided in the semiconductor substrate and inserted in a current path between the output terminal and one of the pair of MOS transistors. The semiconductor integrated circuit as described. 2. The semiconductor integrated circuit according to claim 1, wherein the pair of guard contacts are provided so as to surround each of the pair of MOS transistors.

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