JP5157217B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device.

2. Description of the Related Art A semiconductor device having a trench gate electrode group that reaches a drift region through a body region from the surface of a semiconductor substrate, such as a trench gate type MOS-FET and a trench gate type IGBT, is known. In such a semiconductor device, a trench gate type channel structure including a trench gate electrode group and a body region may be formed in a plurality of regions of the semiconductor substrate that are spaced apart from each other. That is, adjacent body regions are separated by a drift region formed in a separation range therebetween. In this type of semiconductor device, the electric field tends to concentrate on the lower end of the trench gate electrode, the edge of the body region, and the like in the vicinity of the isolation range. Therefore, the breakdown voltage of the semiconductor device is lowered unless the electric field concentration near the separation range is suppressed.
In order to solve this problem, a semiconductor device in which a diffusion region is formed in a range covering the body region and the trench gate electrode in the vicinity of the isolation range is known. The diffusion region is a region where impurities having the same conductivity type as the body region are diffused. When the diffusion region is formed in this way, the concentration of the electric field on the lower end of the trench gate electrode near the isolation range, the edge of the body region, and the like can be suppressed.
Patent Document 1 discloses a technique for improving the breakdown voltage of a semiconductor device by forming an insulator region near the edge of a semiconductor substrate.

JP 2005-136099 A

  In the technique described above, the concentration of the electric field in the vicinity of the separation range can be suppressed by forming the diffusion layer in the vicinity of the separation range. Therefore, when manufacturing this semiconductor device, an impurity implantation step for forming a diffusion layer must be performed. In this impurity implantation step, it is necessary to distribute the impurities to a position deep enough to cover the trench gate electrode, which is very time consuming. Therefore, this semiconductor device has a problem that the manufacturing efficiency is very poor.

  The present invention has been made in view of the above-described circumstances, and provides a semiconductor device in which a trench gate type channel structure is formed in a plurality of areas separated from each other, has a high breakdown voltage, and can be easily manufactured. The purpose is to do.

The semiconductor device of the present invention includes a first body region, a second body region, a drift region, a first trench gate electrode group, a second trench gate electrode group, a first trench insulator group, and a second trench. An insulator group is provided. The first body region is formed in a first island-shaped range extending from the surface of the semiconductor substrate to the first depth in a first range when the semiconductor substrate is viewed in plan, and is of a first conductivity type. The second body region has a second island shape extending from the semiconductor substrate surface to a second depth in a second range adjacent to the first range with a separation range when the semiconductor substrate is viewed in plan. The first conductivity type is formed in the range. The drift region is formed from the isolation range to a lower portion of the first body region and a lower portion of the second body region, and is of a second conductivity type. The first trench gate electrode group penetrates the first body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval at least within the first range. It exists in the state covered with the insulating layer in 1 trench group. The second trench gate electrode group penetrates the second body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval at least in the second range. The two trench groups are covered with an insulating layer. When the semiconductor substrate is viewed in plan, the arrangement direction of the plurality of first trench gate electrodes constituting the first trench gate electrode group is determined by the plurality of second trench gates constituting the second trench gate electrode group. It coincides with the arrangement direction of the electrodes. In a cross section cut out in a range including the first range, the second range, and the separation range, the first range and the second range are adjacent to each other with the separation range along the arrangement direction. Yes. An insulating film is formed on the surface of the semiconductor substrate at the center of the separation range in the arrangement direction, and is connected to the first trench gate electrode group and the second trench gate electrode group on the insulating film. The gate wiring is formed. The first trench insulator group includes a first trench gate electrode between the first trench gate electrode closest to the isolation range among the plurality of first trench gate electrodes and the center of the gate wiring in the arrangement direction. Within the specific range, it is formed along the boundary between the first range and the isolation range on the surface of the semiconductor substrate, is shallower than the first trench gate electrode group, and at least the tip of the trench is the first region. Each of the plurality of first trench insulators extending to the outside of the body region and constituting the first trench insulator group has a relationship that the first trench insulator close to the second range is shallower. Satisfies. In the arrangement direction, the second trench insulator group includes a second trench gate electrode between a second trench gate electrode closest to the isolation range among the plurality of second trench gate electrodes and a center of the gate wiring. Within the specific range, it is formed along the boundary between the second range and the isolation range on the surface of the semiconductor substrate, is shallower than the second trench gate electrode group, and at least the tip of the trench is the second region. Each of the plurality of second trench insulators extending to the outside of the body region and constituting the second trench insulator group has a relationship that the second trench insulator closer to the first range is shallower. Satisfies.
Note that the trench insulator is a trench-shaped portion that is insulated from at least the semiconductor substrate, and a conductor may exist inside the trench insulator. For example, similarly to the trench gate electrode, the trench insulator may include an electrode inside, and the electrode may be electrically connected to the trench gate electrode.

In this semiconductor device, the first trench insulator group is formed along the boundary in the vicinity of the boundary between the first range and the isolation range, and the second trench insulator group is formed between the second range and the first range. It is formed along the boundary in the vicinity of the boundary with the separation range. Therefore, it is possible to suppress the concentration of the electric field at the lower end of the trench gate electrode and the edge of the body region near the isolation range. In addition, the first trench insulator group is shallower than the first trench gate electrode group, and the plurality of first trench insulators constituting the first trench insulator group is the first trench insulator closer to the second range. Satisfies the shallow relationship. Therefore, the concentration of the electric field near the lower end of the first trench insulator is also suppressed. Similarly, the concentration of the electric field near the lower end of the second trench insulator is also suppressed. Therefore, in this semiconductor device, the concentration of the electric field in the vicinity of the separation range is suppressed, and the breakdown voltage is high.
The trench insulator group can be formed together with the trench gate electrode group. Therefore, this semiconductor device can be manufactured very efficiently.

In the semiconductor device described above, an insulating film is formed on the surface of the semiconductor substrate in the center of the isolation range, and the first trench gate electrode group and the second trench gate electrode group are connected on the insulating film. It has been that gate wiring that are formed.
According to such a configuration, the gate wiring is not routed extremely long, and signal delay on the gate wiring can be suppressed.

In the above-described semiconductor device, the are first shallower than closer to the second body region in a certain range, the first trench insulator group protrudes into the drift region through said first body region It is preferable.
According to such a structure, it can suppress suitably that an electric field concentrates in the isolation | separation range vicinity.

In the semiconductor device described above, the first trench insulator group may be formed in the drift region located in the isolation range.
Even with such a configuration, it is possible to suitably suppress the concentration of the electric field in the vicinity of the separation range.

The semiconductor device described above preferably has a narrower width as the trench insulator is shallower.
According to such a configuration, each trench insulator can be easily formed in the semiconductor substrate.

The present invention also provides another form of semiconductor device that solves the above-described problems.
The semiconductor device includes a first body region, a second body region, a drift region, a first trench gate electrode group, and a second trench gate electrode group. The first body region is formed in a first island-shaped range extending from the surface of the semiconductor substrate to the first depth in a first range when the semiconductor substrate is viewed in plan, and is of a first conductivity type. The second body region has a second island shape extending from the semiconductor substrate surface to a second depth in a second range adjacent to the first range with a separation range when the semiconductor substrate is viewed in plan. The first conductivity type is formed in the range. The drift region is formed from the isolation range to a lower portion of the first body region and a lower portion of the second body region, and is of a second conductivity type. The first trench gate electrode group penetrates the first body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval in at least the first range. In the first trench group covered with an insulating layer, the first trench group extends toward the isolation range, and in the vicinity of the boundary between the first range and the isolation range. It terminates satisfying the relationship of becoming shallower as it approaches the second range. The second trench gate electrode group penetrates the second body region from the surface of the semiconductor substrate and reaches the drift region, and is regularly arranged at a predetermined interval at least in the second range. The second trench group is covered with an insulating layer .
When the semiconductor substrate is viewed in plan, the longitudinal direction of each first trench constituting the first trench group coincides with the longitudinal direction of each second trench constituting the second trench group. In a cross section cut out in a range including the first range, the second range, and the separation range, the first range and the second range are adjacent to each other with the separation range along the longitudinal direction. Yes. An insulating film is formed on the surface of the semiconductor substrate at the center of the separation range in the longitudinal direction, and is connected to the first trench gate electrode group and the second trench gate electrode group on the insulating film. The gate wiring is formed. The longitudinal direction is a direction orthogonal to the gate wiring. Each of the first trenches has an end portion in the longitudinal direction that overlaps with the separation range, extends toward the separation range, and the depth of the end portion in the longitudinal direction approaches the second range. It ends with the relationship of becoming shallower. As for each said 2nd trench, the longitudinal direction edge part has overlapped with the isolation | separation range, and while extending toward the said isolation | separation range, the depth of the said longitudinal direction edge part is so close to the said 1st range. It ends with the relationship of becoming shallower.
In this semiconductor device, the first trench gate electrode group terminates satisfying the relationship that the first trench gate electrode group becomes shallower toward the second range in the vicinity of the boundary between the first range and the separation range. Further, the second trench gate electrode group terminates satisfying the relationship that the second trench gate electrode group becomes shallower toward the first range in the vicinity of the boundary between the second range and the separation range. Therefore, the concentration of the electric field in the vicinity of the terminal portion on the separation range side of the first and second trench gate electrode groups is suppressed. This semiconductor device has a high breakdown voltage.

The semiconductor device described above, the depth of the longitudinal end of the first body region, and shallower than closer to the second body region, the first trench gate electrode group over the entire length first It is preferable to protrude through the one body region into the drift region.
According to such a structure, it can suppress that an electric field concentrates on the edge of the 1st body area | region of the isolation | separation range vicinity.

The semiconductor device described above, the width of the longitudinal ends of the first trench, it is preferable Chikazukuho etc. are narrower Kuna' the second body region.
According to such a configuration, the first trench group can be easily formed in the semiconductor substrate.

The present invention also provides a method for manufacturing the semiconductor device described above.
This manufacturing method includes an etching mask arrangement step and an etching step. In the etching mask arrangement step, the opening group for forming the first trench gate electrode group, the opening group for forming the second trench gate electrode group, the opening group for forming the first trench insulator group, and the second trench insulator A plurality of openings constituting the first trench insulator group forming opening group satisfy the relationship that the opening closer to the second range has a smaller width, An etching mask that satisfies the relationship that the opening close to the first range has a narrower width than the plurality of openings constituting the opening group for forming the two-trench insulator group is disposed on the semiconductor substrate. In the etching step, the surface of the semiconductor substrate is etched through the arranged etching mask to thereby form a trench group for the first trench gate electrode group, a trench group for the second trench gate electrode group, and a first trench. A trench group for the insulator group and a trench group for the second trench insulator group are formed.
The etching rate of the semiconductor substrate increases as the opening width of the etching mask increases. Therefore, according to this manufacturing method, the depths of the trench group for the first trench gate electrode group and the trench group for the second trench gate electrode group are set to the trench group for the first trench insulator group and the second trench insulator. It can be deeper than the group trench group. In addition, each of the trenches constituting the trench group for the first trench insulator group can be formed because the trench closer to the second range is shallower. Further, the trenches constituting the trench group for the second trench insulator group can be formed in a relationship that the trench closer to the first range is shallower. That is, each trench can be formed by one etching, and a semiconductor device can be manufactured efficiently.

The present invention also provides a method for manufacturing the semiconductor device according to another embodiment described above.
This manufacturing method includes an etching mask arrangement step and an etching step. In the etching step, a first aperture group for trench gate electrodes formed width closer to the second range is narrower formed in the longitudinal direction, a width closer to the first range in the longitudinal direction is more An etching mask having an opening group for forming a second trench gate electrode group formed narrowly is disposed on the semiconductor substrate. In the etching step, the surface of the semiconductor substrate is etched through the arranged etching mask to form a trench group for the first trench gate electrode group and a trench group for the second trench gate electrode group.
According to this manufacturing method, the portion near the isolation range of each trench constituting the trench group for the first trench gate electrode group can be formed shallower as it approaches the second range. In addition, the portion near the isolation range of each trench constituting the trench group for the second trench gate electrode group can be formed shallower as it approaches the first range. That is, the first trench group and the second trench group can be formed by one etching, and the semiconductor device can be manufactured efficiently.

(Feature 1) The IGBT includes a plurality of trench gate type channel structures.
(Feature 2) Each trench gate type channel structure has a body region and a trench gate electrode group penetrating the body region and reaching the drift region.
(Feature 3) All the trench gate electrodes are formed in parallel to each other.
(Feature 4) Each trench gate type channel structure is formed in a plurality of ranges separated from each other by a separation range when the semiconductor substrate is viewed in plan view.
(Feature 5) In the boundary region between the first range and the second range that is adjacent to the first range in the width direction of the trench gate electrode with the first separation range, the first range and the first separation range A first trench insulator group is formed in the vicinity of the boundary along the boundary, and a second trench insulator group is formed in the vicinity of the boundary between the second range and the first separation range along the boundary.
(Feature 6) The trench gate electrode group, the first trench insulator group, and the second trench insulator group are formed in parallel to each other.
(Feature 7) The first body region in the first range is shallower toward the second body region in the second range near the boundary between the first range and the first separation range.
(Characteristic 8) Of the plurality of first trench insulators constituting the first trench insulator group, one or more first trench insulators on the side far from the second range include the first body region. It penetrates and protrudes into the drift region.
(Feature 9) Among the plurality of first trench insulators constituting the first trench insulator group, one or more first trench insulators on the side close to the second range are drifts located in the isolation range. Formed in the region.
(Feature 10) In the boundary region between the first range and the third range that is adjacent to the first range in the length direction of the trench gate electrode with the second isolation range being separated, the second isolation range and the trench gate electrode The groups are orthogonal.

An IGBT according to an embodiment of the present invention will be described. The IGBT of this embodiment is composed of a silicon substrate, various electrodes, an insulating film, and the like. FIG. 1 shows an enlarged view of a part of the upper surface of the IGBT 10 of this embodiment (that is, the surface on the upper surface 12a side of the silicon substrate 12 shown in FIG. 2). As shown in FIG. 1, emitter electrodes 20 a to 20 c are formed on the upper surface 12 a of the silicon substrate 12. The emitter electrodes 20a to 20c are separated from each other.
As will be described in detail later, a trench gate type channel structure constituted by a plurality of gate electrodes 22, a body layer 26, and the like is formed below each emitter electrode 20 of the silicon substrate 12. Each trench gate channel structure is spaced from the other trench gate channel structures.

  As shown in FIGS. 3 and 4, a gate wiring 40 composed of a polysilicon wiring 40 a and an aluminum wiring 40 b is formed on the upper surface 12 a of the silicon substrate 12. The polysilicon wiring 40 a is formed on the interlayer insulating film 42 formed on the upper surface 12 a of the silicon substrate 12 and is not electrically connected to the silicon substrate 12. The polysilicon wiring 40a is covered with an insulating film 44 except for its upper surface. An aluminum wiring 40b is formed on the upper surface of the polysilicon wiring 40a. As shown in FIG. 1, the gate wiring 40, the interlayer insulating film 42, and the insulating film 44 are formed so as to pass between the emitter electrode 20a and the emitter electrode 20b.

  FIG. 2 shows a cross-sectional view of the IGBT 10 of FIG. 1 taken along the line II-II. As shown in the figure, a p-type body layer 26 is formed in the silicon substrate 12 below the emitter electrode 20a from the upper surface 12a to a predetermined depth range. Of the region facing the upper surface 12a of the silicon substrate 12, an n-type emitter region 25 is formed in a region in contact with a gate insulating film 23 described later. The emitter region 25 and the body layer 26 are electrically connected to the emitter electrode 20a. An n-type drift layer 28 is formed below the body layer 26. A p-type collector layer 30 is formed below the drift layer 28. The collector layer 30 is exposed on the lower surface 12 b of the silicon substrate 12. A collector electrode 32 is formed on the lower surface 12 b of the silicon substrate 12 and is electrically connected to the collector layer 30.

  A plurality of trenches 24 that penetrate through the body layer 26 and reach the drift layer 28 are formed on the upper surface 12 a of the silicon substrate 12. As shown in FIG. 1, the trenches 24 are formed in parallel to each other at equal intervals in the lower part of the emitter electrode 20a. A gate insulating film 23 is formed on the wall surface (side surface and bottom surface) of each trench 24. A gate electrode 22 made of poly-Si is formed inside each trench 24. The upper surface of each gate electrode 22 is covered with an interlayer insulating film 48. As will be described later, each gate electrode 22 is connected to a gate wiring 40. Therefore, a voltage can be applied to each gate electrode 22 by applying a voltage to the gate wiring 40.

  The trench gate type channel structure formed by the emitter region 25, the body layer 26, and the gate electrode 22 described above is formed below each emitter electrode 20, respectively. Further, the drift layer 28 and the collector layer 30 described above are formed over the entire planar direction of the silicon substrate 12. The collector electrode 32 described above is formed over substantially the entire lower surface 12 b of the silicon substrate 12.

  FIG. 3 shows a cross-sectional view of the IGBT 10 of FIG. 1 taken along the line III-III. That is, FIG. 3 shows a cross-sectional view of a boundary portion between the trench gate type channel structure on the emitter electrode 20a side and the trench gate type channel structure on the emitter electrode 20b side.

  As shown in the drawing, the drift layer 28 extends to the range where the drift layer 28 faces the upper surface 12a of the silicon substrate 12 in the range between the body layer 26 on the emitter electrode 20a side and the body layer 26 on the emitter electrode 20b side. Therefore, the body layer 26 on the emitter electrode 20 a side and the body layer 26 on the emitter electrode 20 b side are separated by the drift layer 28. Hereinafter, the range in which the drift layer 28 is formed between the two body layers 26 in FIG. In the cross section of FIG. 3, the gate wiring 40 described above is formed on the upper surface 12 a of the silicon substrate 12 in the isolation range 50.

As illustrated, trench insulators 52a to 52e are formed on the upper surface 12a of the silicon substrate 12 in the vicinity of the boundary between the isolation range 50 and the body layer 26 on the emitter electrode 20a side. The trench insulators 52a to 52e are parallel to the trench 24 in the range 100 of FIG. The trench insulators 52 a to 52 e are shallower than the trench 24. In the trench insulators 52a to 52e, the trench insulator 52a farthest from the emitter electrode 20b is deepest, and the trench insulator closer to the emitter electrode 20b is shallower. In addition, the trench insulators 52a to 52e have the widest trench insulator 52a farthest from the emitter electrode 20b and the narrower the trench insulator closer to the emitter electrode 20b. As shown in the drawing, in the vicinity of the boundary with the separation range 50, the body layer 26 on the emitter electrode 20a side becomes shallower as it approaches the emitter electrode 20b. The trench insulators 52a and 52b are formed so as to protrude from the body layer 26 near the boundary to the drift layer 28. The trench insulators 52c to 52e are formed in the isolation range 50.
The trench insulators 52a to 52e are composed of an insulating film formed on the wall surface (side surface and bottom surface) of the trench and a poly-Si conductor formed inside the trench. Therefore, each conductor is insulated from the semiconductor substrate 12 by the insulating film. The upper surface of each conductor is covered with an interlayer insulating film 55. Note that the conductor is connected to the gate wiring 40 in a portion not shown.

  Similar to the emitter electrode 20a side, trench insulators 52a to 52e are also formed near the boundary between the isolation range 50 and the body layer 26 on the emitter electrode 20b side.

  As described above, the separation structure for separating the two trench gate type channel structures is formed at the boundary between the trench gate type channel structure on the emitter electrode 20a side and the trench gate type channel structure on the emitter electrode 20b side. ing.

  FIG. 4 shows a cross-sectional view of the IGBT 10 of FIG. 1 taken along line IV-IV. That is, FIG. 4 shows a cross-sectional view of a boundary portion between the trench gate type channel structure on the emitter electrode 20a side and the trench gate type channel structure on the emitter electrode 20c side. Note that the body layer 26 indicated by a broken line in FIG. 4 indicates the position of the body layer 26 when the gate electrode 22 is seen through.

  As shown in the drawing, the drift layer 28 extends to the range between the body layer 26 on the emitter electrode 20a side and the body layer 26 on the emitter electrode 20c side so as to face the upper surface 12a of the silicon substrate 12. Therefore, the body layer 26 on the emitter electrode 20 a side and the body layer 26 on the emitter electrode 20 c side are separated by the drift layer 28. Hereinafter, the range in which the drift layer 28 is formed between the two body layers 26 in FIG. In the cross section of FIG. 4, the above-described gate wiring 40 is formed on the upper surface 12 a of the silicon substrate 12 in the isolation range 58.

As shown in the figure, the gate electrode 22 on the emitter electrode 20a side is shallower and terminates near the emitter electrode 20c in the vicinity of the separation range 58. Further, as shown in FIG. 1, the gate electrode 22 on the emitter electrode 20a side becomes narrower in the vicinity of the separation range 58 as it approaches the emitter electrode 20c. In the vicinity of the boundary with the isolation range 58, the body layer 26 on the emitter electrode 20a side becomes shallower as it approaches the emitter electrode 20c. Therefore, the gate electrode 22 protrudes below the body layer 26 in the vicinity of the boundary with the isolation range 58. That is, the gate electrode 22 penetrates the body layer 26 and protrudes to the drift layer 28 over the entire length.
In the isolation range 58, the gate electrode 22 is connected to the gate wiring 40 through a contact hole 46 formed in the interlayer insulating film 42 and the insulating film 44 around the gate wiring 40.

  The gate electrode 22 and the body layer 26 on the emitter electrode 20 c side are also formed in the vicinity of the boundary of the separation range 58 in the same manner as the gate electrode 22 and the body layer 26 on the emitter electrode 20 a side.

  As described above, the separation structure for separating the two trench gate type channel structures is formed at the boundary between the trench gate type channel structure on the emitter electrode 20a side and the trench gate type channel structure on the emitter electrode 20c side. ing. This isolation structure is also formed at the boundary between the trench gate type channel structure on the emitter electrode 20b side and the trench gate type channel structure on the emitter electrode 20c side in FIG.

  When a forward voltage is applied between the collector electrode 32 and the emitter electrode 20 of the IGBT 10 and an on-voltage is applied to the gate wiring 40 (that is, the gate electrode 22), a channel is formed in the body layer 26, and the IGBT 10 is turned on. When the voltage applied to the gate electrode 22 is turned off, the channel disappears and the IGBT 10 is turned off. When the IGBT 10 is off, carriers do not flow at the boundary between the body layer 26 and the drift layer 28, and an electric field from the drift layer 28 toward the body layer 26 is generated at the boundary. When the electric field is concentrated on a part of the boundary between the body layer 26 and the drift layer 28, an avalanche current is generated at the part, and the silicon substrate 12 may be damaged.

A broken line A1 in FIG. 3 indicates an equipotential line indicating a potential distribution near the boundary between the body layer 26 and the drift layer 28 in the cross section in FIG. 3 when the IGBT 10 is turned off. FIG. 5 shows, as a comparative example, a potential distribution in the vicinity of the boundary between the body layer 26 and the drift layer 28 in a cross section corresponding to the cross section of the conventional IGBT in FIG.
As shown in FIG. 5, in the conventional IGBT, equipotential lines are dense in the corner vicinity region 100 of the body layer 26 and the lower end vicinity region 102 of the gate electrode 22 closest to the isolation range 50. That is, the electric field is concentrated on the regions 100 and 102.
As shown in FIG. 3, in the IGBT 10 of this embodiment, trench insulators 52 a to 52 e are formed in the vicinity of the boundary between the isolation range 50 and the body layer 26. Accordingly, the equipotential lines extend greatly within the separation range 50 as shown in the figure. This suppresses the concentration of the electric field near the corners of the body layer 26 and near the lower end of the gate electrode 22. The trench insulators 52a to 52e are shallower than the gate electrode 22 and closer to the other emitter electrode 20 (for example, in the case of the trench insulators 52a to 52e on the emitter electrode 20a side, the trench closer to the emitter electrode 20b). It is shallower than the insulator). Therefore, the equipotential lines change smoothly as shown in the figure. That is, the electric field is dispersed in the trench insulators 52a to 52e. Therefore, the electric field is prevented from concentrating on the gate electrode 22 closest to the isolation region 50. Further, electric field concentration does not occur in the vicinity of the lower ends of the trench insulators 52a to 52e. That is, the occurrence of electric field concentration in the vicinity of the separation range 50 of the IGBT 10 is suppressed.

A broken line A2 in FIG. 4 indicates an equipotential line indicating a potential distribution near the boundary between the body layer 26 and the drift layer 28 in the cross section in FIG. 4 when the IGBT 10 is turned off. FIG. 6 shows, as a comparative example, a potential distribution in the vicinity of the boundary between the body layer 26 and the drift layer 28 in a cross section corresponding to the cross section in FIG. 4 of the conventional IGBT.
As shown in FIG. 6, in the conventional IGBT, equipotential lines are dense in the corner vicinity region 104 of the gate electrode 22. That is, the electric field concentrates in the corner vicinity region 104.
As shown in FIG. 4, in the IGBT 10 of the present embodiment, the gate electrode 22 becomes shallower as it approaches the other emitter electrode 20 (for example, the closer to the emitter electrode 20c in the case of the gate electrode 22 on the emitter electrode 20a side). Yes. Therefore, the electric field is suppressed from being concentrated in the vicinity of the gate electrode 22. Further, in the vicinity of the boundary with the separation range 58, the gate electrode 22 protrudes below the body layer 26 (that is, the gate electrode 22 protrudes below the body layer 26 over the entire length). Accordingly, the concentration of the electric field in the vicinity of the body layer 26 is also suppressed. That is, the occurrence of electric field concentration near the separation range 58 of the IGBT 10 is suppressed.

  As described above, in the IGBT 10 of this embodiment, the concentration of the electric field in the vicinity of the separation range 50 is suppressed by the trench insulators 52a to 52e. In the vicinity of the isolation range 58, the concentration of the electric field is suppressed by the gate electrode 22 becoming gradually shallower and circumferentially end. Therefore, the breakdown voltage of the IGBT 10 is very high.

  Further, in the IGBT 10 of this embodiment, the gate wiring 40 is formed on the surface of the semiconductor substrate 12 at the boundary portion of the trench gate type channel structure. Therefore, the maximum value of the distance from the end of the gate wiring 40 on the bonding pad side to the gate electrode 22 is shorter than when the gate wiring 40 is provided near the outer peripheral edge of the semiconductor substrate 12. Therefore, signal delay on the gate wiring is suppressed. In the case where a gate wiring is formed on a semiconductor substrate, the manufacturing efficiency of the IGBT may decrease if a structure such as a semiconductor region is formed under the gate wiring. However, the IGBT 10 of this embodiment does not require any structure to be formed under the gate wiring 40, and the IGBT 10 can be easily manufactured.

  In the IGBT 10 described above, the trench insulators 52 a and 52 b are formed so as to protrude from the body layer 26 in the vicinity of the boundary to the drift layer 28, and the trench insulators 52 c to 52 e are formed in the isolation range 50. However, all the trench insulators 52 may be formed in the isolation range 50 as shown in FIG. Further, as shown in FIG. 8, all the trench insulators 52 may be formed so as to protrude from the body layer 26 in the vicinity of the boundary to the drift layer 28. Even if the trench insulator is formed as shown in FIGS. 7 and 8, the concentration of the electric field in the vicinity of the isolation range 50 can be suppressed.

  Further, the above-described trench insulator group can be formed in the vicinity of the outer peripheral end of the silicon substrate 12. In this case, by forming the trench insulator closer to the outer periphery as shallow as possible, electric field concentration in the vicinity of the outer peripheral end can be suitably suppressed.

  Next, the manufacturing method of IGBT10 is demonstrated. The structure other than the gate electrode 22 and the trench insulators 52a to 52e can be formed by a conventionally known method. Therefore, a method for forming the gate electrode 22 and the trench insulators 52a to 52e will be described below.

First, the upper surface 12a of the silicon substrate 12 is etched by dry etching.
FIG. 9 shows the shape of the opening of the etching mask disposed on the upper surface 12a when the upper surface 12a of the silicon substrate 12 is etched. FIG. 9 shows only a part of the opening of the etching mask.
The opening 124 has a width substantially equal to that of the trench 24. The openings 152 a to 152 e are narrower than the opening 124. The openings 152a to 152e have substantially the same width as the trench insulators 52a to 52e. That is, the width of the opening 152a is the widest, and the width of the opening closer to the opening 152e is narrower. In addition, the openings 124 and 152a to 152e become narrower as the width near the end approaches the end.
After the etching mask is arranged, the upper surface 12a of the silicon substrate 12 is etched by dry etching through the arranged etching mask. Therefore, the silicon substrate 12 in each opening is etched. At this time, in the wide opening, the etching gas flows in a large amount, so that the etching rate is increased. In the opening having a narrow width, the amount of etching gas flowing is small, and the etching rate is slow. Therefore, after etching, trenches having different depths are formed in the silicon substrate 12 as shown in FIG. That is, the trenches 252 a to 252 e are shallower than the trench 24. The trenches 252a to 252e are deepest in the trench 252a and become shallower as the trench is farther from the trench 252a. Moreover, since the width | variety becomes narrow near the edge part near the edge part of opening 124,152a-152e, the edge part vicinity of trench 24,252a-252e becomes shallow, so that it approaches the edge part.

  After the trenches 24 and 252a to 252e are formed, an insulating film is formed on the wall surfaces of the trenches 24 and 252a to 252e by a conventionally known method, and poly-Si electrodes are formed in the trenches 24 and 252a to 252e. Interlayer insulating films 48 and 55 are formed on the upper surfaces of the electrodes. Thus, the poly-Si electrode in the trench 24 becomes the gate electrode 22, and the insulating film and the poly-Si electrode in the trenches 252a to 252e become the trench insulators 52a to 52e.

  As described above, according to this manufacturing method, trenches having different depths can be formed by a single etching. Therefore, trench insulators 52 a to 52 e can be formed simultaneously with gate electrode 22. Further, the vicinity of the end portion of the gate electrode 22 (that is, the vicinity of the separation region 58) can be formed shallower as the end portion is approached. Therefore, the IGBT 10 can be manufactured without reducing the manufacturing efficiency as compared with the case of manufacturing a normal IGBT.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

The top view of IGBT10. II-II sectional view taken on the line of FIG. III-III sectional view taken on the line of FIG. IV-IV sectional view taken on the line of FIG. Sectional drawing corresponding to FIG. 3 of IGBT of a comparative example. Sectional drawing corresponding to FIG. 4 of IGBT of a comparative example. Sectional drawing corresponding to FIG. 3 of IGBT of a 1st modification. Sectional drawing corresponding to FIG. 3 of IGBT of a 2nd modification. The partially enlarged view of the etching mask used when manufacturing IGBT10. FIG. 10 is a cross-sectional view of a trench formed by etching using the etching mask of FIG. 9.

Explanation of symbols

10: IGBT
12: silicon substrate 20: emitter electrode 22: gate electrode 23: gate insulating film 24: trench 25: emitter region 26: body layer 28: drift layer 30: collector layer 32: collector electrode 40: gate wiring 46: contact hole 50: Isolation range 52: Trench insulator 58: Isolation range

Claims (9)

A first body region, a second body region, a drift region, a first trench gate electrode group, a second trench gate electrode group, a first trench insulator group, and a second trench insulator group are provided. A semiconductor device,
The first body region is formed in a first island-shaped range extending from the surface of the semiconductor substrate to the first depth in the first range when the semiconductor substrate is viewed in plan, and is of the first conductivity type.
The second body region has a second island shape extending from the semiconductor substrate surface to a second depth in a second range adjacent to the first range with a separation range when the semiconductor substrate is viewed in plan. Is formed in a range and is of the first conductivity type,
The drift region is formed from the isolation range to a lower portion of the first body region and a lower portion of the second body region, and is of a second conductivity type.
The first trench gate electrode group penetrates the first body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval at least in the first range. It exists in a state covered with an insulating layer in the first trench group,
The second trench gate electrode group penetrates the second body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval at least in the second range. It exists in a state covered with an insulating layer in the second trench group,
When the semiconductor substrate is viewed in plan, the arrangement direction of the plurality of first trench gate electrodes constituting the first trench gate electrode group is determined by the plurality of second trench gates constituting the second trench gate electrode group. Match the electrode orientation,
In a cross section cut out in a range including the first range, the second range, and the separation range, the first range and the second range are adjacent to each other with the separation range along the arrangement direction. And
An insulating film is formed on the surface of the semiconductor substrate in the center of the separation range in the arrangement direction,
A gate wiring connected to the first trench gate electrode group and the second trench gate electrode group is formed on the insulating film,
The first trench insulator group includes a first trench gate electrode between the first trench gate electrode closest to the isolation range among the plurality of first trench gate electrodes and the center of the gate wiring in the arrangement direction. within a specific range, the are formed along boundary of the separation range between the first range in the semiconductor substrate surface, shallower than the first trench gate electrodes, and the tip portion of at least the trench is the first 1 extends to the outside of the body region, the first relationship each of the first trench insulator plurality of constituting the trench isolation unit is shallower toward the first trench insulator close to the second range Meets
In the arrangement direction, the second trench insulator group includes a second trench gate electrode between a second trench gate electrode closest to the isolation range among the plurality of second trench gate electrodes and a center of the gate wiring. within a specific range, the are formed along boundary of the separation range between the second range in the semiconductor substrate surface, shallower than the second trench gate electrodes, and the tip portion of at least the trench is the first 2 extends to the outside of the body region, the second relation that each of the second trench insulating a plurality of constituting the trench isolation unit is shallower toward the second trench insulator close to said first range Meets
A semiconductor device. The first body region is shallower than closer to the the first within a certain range the second body region,
The semiconductor device according to claim 1, wherein the first trench insulator group penetrates through the first body region and protrudes into the drift region.   The semiconductor device according to claim 1, wherein the first trench insulator group is formed in the drift region located in the isolation range. Each trench insulator, a semiconductor device according to any one of claims 1 to 3, the width as shallow trench insulator, characterized in that narrower. A semiconductor device comprising a first body region, a second body region, a drift region, a first trench gate electrode group, and a second trench gate electrode group,
The first body region is formed in a first island-shaped range extending from the surface of the semiconductor substrate to the first depth in the first range when the semiconductor substrate is viewed in plan, and is of the first conductivity type.
The second body region has a second island shape extending from the semiconductor substrate surface to a second depth in a second range adjacent to the first range with a separation range when the semiconductor substrate is viewed in plan. Is formed in a range and is of the first conductivity type,
The drift region is formed from the isolation range to a lower portion of the first body region and a lower portion of the second body region, and is of a second conductivity type.
The first trench gate electrode group penetrates the first body region from the surface of the semiconductor substrate to reach the drift region, and is regularly arranged at a predetermined interval in at least the first range. Existing in the first trench group covered with an insulating layer ,
The second trench gate electrode group penetrates the second body region from the surface of the semiconductor substrate and reaches the drift region, and is regularly arranged at a predetermined interval at least in the second range. Existing in the second trench group covered with an insulating layer ,
When the semiconductor substrate is viewed in plan, the longitudinal direction of each first trench constituting the first trench group coincides with the longitudinal direction of each second trench constituting the second trench group,
In a cross section cut out in a range including the first range, the second range, and the separation range, the first range and the second range are adjacent to each other with the separation range along the longitudinal direction. And
On the surface of the semiconductor substrate at the center of the separation range in the longitudinal direction, an insulating film is formed,
A gate wiring connected to the first trench gate electrode group and the second trench gate electrode group is formed on the insulating film,
The longitudinal direction is a direction orthogonal to the gate wiring,
Each of the first trenches has an end portion in the longitudinal direction that overlaps with the separation range, extends toward the separation range, and the depth of the end portion in the longitudinal direction approaches the second range. It is terminated with the relationship of becoming shallower,
As for each said 2nd trench, the longitudinal direction edge part has overlapped with the isolation | separation range, and while extending toward the said isolation | separation range, the depth of the said longitudinal direction edge part is so close to the said 1st range. It ends with the relationship of becoming shallower,
A semiconductor device. The first body region, the depth of the longitudinal ends, and shallower than closer to the second body region,
The semiconductor device according to claim 5 , wherein the first trench gate electrode group penetrates the first body region over the entire length and protrudes into the drift region. Before SL each first trench, the width of the longitudinal ends, the semiconductor device according to claim 5 or 6, characterized in that has a narrower Kuna' etc. Chikazukuho the second body region. A method of manufacturing a semiconductor device according to claim 4 ,
An opening group for forming a first trench gate electrode group, an opening group for forming a second trench gate electrode group, an opening group for forming a first trench insulator group, and an opening group for forming a second trench insulator group The plurality of openings constituting the opening group for forming the first trench insulator group satisfy the relationship that the opening closer to the second range has a narrower width, and the second trench insulator group is formed. An etching mask disposing step of disposing an etching mask on the semiconductor substrate that satisfies a relationship that the opening close to the first range is narrower than the plurality of openings constituting the opening group for
Etching the surface of the semiconductor substrate through the arranged etching mask, the trench group for the first trench gate electrode group, the trench group for the second trench gate electrode group, and the first trench insulator group The manufacturing method of the semiconductor device which has an etching process which forms the trench group for this, and the trench group for 2nd trench insulator groups. A method for manufacturing a semiconductor device according to claim 7 , comprising:
Oite in the longitudinal direction, the a first aperture group for trench gate electrodes formed width closer to the second range is narrower formed, Oite the longitudinal, width closer to the first range An etching mask disposing step of disposing an etching mask having a second trench gate electrode group forming opening group formed more narrowly on the semiconductor substrate;
A semiconductor device having an etching step of forming a trench group for the first trench gate electrode group and a trench group for the second trench gate electrode group by etching the surface of the semiconductor substrate through the arranged etching mask Manufacturing method.

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