JP5151532B2 - Manufacturing method of semiconductor optical integrated device - Google Patents

Description

  The present invention relates to a semiconductor optical integrated device in which a plurality of semiconductor optical devices are integrated on a single substrate.

  One method of integrating a plurality of semiconductor elements on a single semiconductor substrate is excellent in terms of loss and connection efficiency, and is a method of integrating by a butt joint (butt joint) that directly connects a plurality of semiconductor elements. is there.

Patent Document 1 discloses a method for bonding two semiconductor elements, a distributed feedback semiconductor laser (DFB laser) and an electroabsorption modulator (EA modulator). 8-10 is a figure which shows typically each process of the bonding | joining method of the semiconductor element currently disclosed in patent document 1. FIG. FIG. 8A to FIG. 10A are perspective views schematically showing the respective steps. FIG. 8B is a cross-sectional view taken along the line VIII-VIII in FIG. FIG. 9B is a cross-sectional view taken along the line IX-IX in FIG. FIG.10 (b) is sectional drawing along the XX line of Fig.10 (a). In a typical butt joint integration method disclosed in Patent Document 1, first, a diffraction grating 90 a is formed on a semiconductor substrate 90. Next, a semiconductor multilayer 91A including an active layer 93a for the DFB laser is grown on the diffraction grating 90a (FIGS. 8A to 8B). Next, an etching mask (SiN mask) 95 is formed on the uppermost layer of the semiconductor stack 91A. Thereafter, at least the portion where the SiN mask 95 does not exist is etched until the semiconductor substrate 90 is exposed (FIGS. 9A to 9B). Next, using the SiN mask 95 as a selective growth mask, the semiconductor layer 91B constituting the EA modulator including the active layer 93b in the etched portion is regrown (FIGS. 10A to 10B).
JP-A-62-194691

  However, during such regrowth, compositional variation and film thickness variation are likely to occur near the selective growth mask due to the influence of the selective growth mask. As a result, dislocations occur in the regrown active layer in the vicinity of the selective growth mask and the crystallinity deteriorates. In addition, the deterioration of the crystallinity of the active layer causes problems such as a decrease in device characteristics and a decrease in yield, and it is difficult to obtain a highly reliable device.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor optical integrated device capable of suppressing deterioration of crystallinity and improving reliability.

In order to solve the above-described problems, a method of manufacturing a semiconductor optical integrated device according to the present invention includes a first semiconductor element portion and a second semiconductor element portion that are disposed on the same semiconductor substrate and optically coupled to each other. In the method of manufacturing a semiconductor optical integrated device, the first semiconductor element portion has a first active layer, and the second semiconductor element portion has a second active layer having a composition different from that of the first active layer. A first active layer forming step of growing a first active layer on the semiconductor substrate; an etching mask forming step of forming an etching mask on the first active layer; and a first portion of the portion where no etching mask exists using the etching mask. An etching process for etching the active layer; a second active layer forming process for growing the second active layer after the etching process; and an etching mask removing process for removing the etching mask. The mask has a first part and a second part arranged at a predetermined interval along the optical waveguide direction of the first semiconductor element part and the second semiconductor element part, and the length of the second part in the optical waveguide direction is The first portion is shorter than the length in the optical waveguide direction.

In the method for manufacturing a semiconductor optical integrated device according to the present invention, the etching mask used when etching the first active layer in the etching step is predetermined along the optical waveguide direction of the first semiconductor element portion and the second semiconductor element portion. The first portion and the second portion are arranged at intervals of. This etching mask is also used as a selective growth mask when the second active layer is regrown in the second active layer forming step. Further, the length of the second portion in the optical waveguide direction is shorter than the length of the first portion in the optical waveguide direction. Therefore, when the second active layer is regrown, the influence of the second portion on the crystallinity of the second active layer is smaller than the influence of the first portion.

  As a result, in the vicinity of the second portion of the etching mask, composition variation and film thickness variation are suppressed, and dislocations and the like generated in the second active layer are suppressed. Further, the second portion blocks dislocations generated by the influence of the first portion during regrowth from propagating beyond the second portion. Accordingly, by forming the second semiconductor element portion in a region opposite to the first semiconductor element portion as viewed from the second portion of the regrown second active layer, the crystallinity of the second semiconductor element portion is deteriorated. Can be suppressed and reliability can be improved.

  The second active layer preferably has a strained quantum well structure. In the case where the second active layer to be regrown has a strained quantum well structure, the strain in the quantum well structure is relaxed due to composition variation, film thickness variation, etc. in the vicinity of the selective growth mask, and dislocations are easily generated, and the crystallinity is Especially worse. However, since the etching mask (selective growth mask) has the second portion, composition variation, film thickness variation, and the like in the vicinity of the selective growth mask are suppressed, so that deterioration of crystallinity can be suppressed.

  Preferably, one of the first semiconductor element portion and the second semiconductor element portion includes a semiconductor laser, and the other of the first semiconductor element portion and the second semiconductor element portion includes an electroabsorption modulator (EA modulator). It is. This method is particularly effective when the semiconductor optical integrated device to be manufactured includes a semiconductor laser and an electroabsorption modulator (EA modulator).

  According to the method for manufacturing a semiconductor optical integrated device of the present invention, there is provided a method for manufacturing a semiconductor optical integrated device capable of suppressing deterioration of crystallinity and improving reliability.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same reference numerals are used for the same or equivalent elements, and duplicate descriptions are omitted.

  FIG. 1A is a perspective view of a semiconductor optical integrated device 100 according to this embodiment, and FIG. 1B is a cross-sectional view of the semiconductor optical integrated device 100 taken along the line I-I.

  Referring to FIGS. 1A to 1B, a semiconductor optical integrated device 100 includes a DFB laser 100A (first semiconductor) provided on a semiconductor substrate 10 having a main surface including regions 10B, 10C, and 10D. Element portion), an EA modulator 100B (second semiconductor element portion), and an optical waveguide region 100C between the DFB laser and the EA modulator.

  The DFB laser 100A is provided on the main surface of the semiconductor substrate 10 corresponding to the region 10B and includes the semiconductor mesa portion 2A. The semiconductor mesa unit 2A has a diffraction grating 10a provided on the main surface of the semiconductor substrate 10, and a lower cladding layer 20a and an active layer 30a (first active layer) sequentially stacked on the diffraction grating 10a. And an upper cladding layer 40a. The period of the diffraction grating is, for example, 200 mm. The active layer 30a has a higher refractive index than the lower cladding layer 20a and the upper cladding layer 40a.

  The EA modulator 100B is provided on the main surface of the semiconductor substrate 10 corresponding to the region 10C and includes the semiconductor mesa portion 2B. The semiconductor mesa portion 2B includes a lower cladding layer 20b, an active layer 30b (second active layer), and an upper cladding layer 40b that are sequentially stacked on the semiconductor substrate 10.

  The active layer 30b is a layer having a strained multiple quantum well structure including well layers and barrier layers that are alternately stacked, for example. The well layer and the barrier layer are made of semiconductor materials having different compositions. The well layer of the active layer 30b has a higher band gap energy than the active layer 30a. Therefore, the well layer of the active layer 30b has a shorter photoluminescence (light emission) wavelength than the active layer 30a. The active layer 30b absorbs laser light emitted from the active layer 30a when a large reverse voltage is applied to the EA modulator 100B. The active layer 30b has a higher refractive index than the lower cladding layer 20b and the upper cladding layer 40b. Since the active layer 30b is a layer having a multiple quantum well structure, the EA modulator 100B can obtain a large extinction ratio. In addition, since strain is introduced into the well layer and the barrier layer, the modulation characteristics of the EA modulator 100B are improved.

  The optical waveguide region 100C is provided on the main surface of the semiconductor substrate 10 corresponding to the region 10D and includes the semiconductor mesa portion 2C. The semiconductor mesa unit 2C confines and guides laser light emitted from the active layer 30a of the DFB laser 100A and guides it to the active layer 30b of the EA modulator 100B. The semiconductor mesa unit 2C includes a semiconductor mesa unit 2q on the DFB laser 100A side and a semiconductor mesa unit 2p on the EA modulator 100B side. The semiconductor mesa unit 2q has the same configuration as the semiconductor mesa unit 2B and is shorter in the optical waveguide direction (x-axis direction) than the semiconductor mesa unit 2B. The semiconductor mesa unit 2p is optically coupled to the semiconductor mesa unit 2q, has the same configuration as the semiconductor mesa unit 2A, and is shorter in the x-axis direction than the semiconductor mesa unit 2A.

As shown in FIG. 1B, the semiconductor mesa portion 2C has both end faces extending along a reference plane (yz plane) intersecting the main surface of the semiconductor substrate 10, and the end faces The semiconductor mesa portion 2A is optically coupled to one side by a butt joint, and the semiconductor mesa portion 2B is optically coupled to the other side by a butt joint. Further, the end surface of the semiconductor mesa portion 2p optically coupled to the semiconductor mesa portion 2q by the butt joint extends in parallel with the direction in which both end surfaces of the semiconductor mesa portion 2C extend. Referring also to the figure, the semiconductor optical integrated device 100, and an interface 1d ₁ is formed by a semiconductor mesa portion 2A and the semiconductor mesa portion 2q of butt joint, butt joint of the semiconductor mesa portion 2B and the semiconductor mesa portion 2p Thus, an interface 1d ₂ is formed, and an interface 1d ₃ is formed by a butt joint of the semiconductor mesa portion 2q and the semiconductor mesa portion 2p.

  The semiconductor mesa portions 2A, 2B, and 2C constitute the semiconductor mesa portion 2 (see FIG. 1A). From the high resistance layer so as to embed the semiconductor mesa portion 2 on both side surfaces of the semiconductor mesa portion 2. A buried layer 50 is provided. A second upper cladding layer 60 is provided on the semiconductor mesa unit 2 and the buried layer 50. A contact layer 70 a is formed on the second upper cladding layer 60 corresponding to the region 10 B of the main surface of the semiconductor substrate 10, and the second upper cladding layer 60 corresponding to the region 10 C of the main surface of the semiconductor substrate 10. Is provided with a contact layer 70b.

  An electrode (anode) 80a for the DFB laser 100A is provided on the contact layer 70a, and an electrode (anode) 80b for the EA modulator 100B is provided on the contact layer 70b. On the back surface of the semiconductor substrate 10, an electrode (cathode) 80c commonly used for the DFB laser 100A and the EA modulator 100B is provided.

Hereinafter, if the constituent elements, dopant concentration, and thickness of each layer of the semiconductor optical integrated device 100 according to the present embodiment are exemplified,
Semiconductor substrate 10: n-type InP layer, 2 × 10 ¹⁸ cm ⁻³ , 350 μm
Lower clad layer 20a: Si-doped InGaAsP layer, 1 × 10 ¹⁸ cm ⁻³ , 200 nm
Lower clad layer 20b: Si-doped InGaAsP layer, 1 × 10 ¹⁸ cm ⁻³ , 175 nm
Active layer 30a: undoped InGaAsP layer, 250 nm
Active layer 30b: undoped InGaAsP layer, 300 nm
Well layer: InGaAsP layer with a band gap wavelength of 1.55 μm, 5 nm
Barrier layer: InGaAsP layer with a band gap wavelength of 1.2 μm, 10 nm
First upper clad layer 40a: Zn-doped InP layer, 1 × 10 ¹⁸ cm ⁻³ , 100 nm
First upper clad layer 40b: Zn-doped InP layer, 1 × 10 ¹⁸ cm ⁻³ , 75 nm
Embedding layer: Fe-doped InP layer, 5 × 10 ¹⁶ cm ⁻³ , 550 nm
Second upper clad layer 60: Zn-doped InP layer, 2 × 10 ¹⁸ cm ⁻³ , 2 μm
Contact layers 70a and 70b: Zn-doped InGaAs layer, 1 × 10 ¹⁹ cm ⁻³ , 200 nm
It is.

  The semiconductor optical integrated device 100 includes a lower optical confinement layer made of undoped InGaAsP between the lower cladding layer 20a and the active layer 30a and between the lower cladding layer 20b and the active layer 30b, and the upper cladding layer 40a and the active layer. An upper optical confinement layer made of undoped InGaAsP may be further provided between the upper cladding layer 40b and the active layer 30b. At this time, the thickness of the lower and upper light confinement layers is preferably about 50 nm.

  2-7 is a figure which shows typically each process of the manufacturing method of the semiconductor optical integrated device 100 concerning this embodiment. 2A to 5A and 6 to 7 are perspective views schematically showing each step of the method for manufacturing the semiconductor optical integrated device 100. FIG. FIG.2 (b) is sectional drawing along the II-II line of Fig.2 (a). FIG.3 (b) is sectional drawing along the III-III line of Fig.3 (a). FIG. 4B is a cross-sectional view taken along the line IV-IV in FIG. FIG. 5B is a cross-sectional view taken along the line V-V in FIG. The semiconductor optical integrated device 100 is manufactured, for example, through the following steps in order.

[Semiconductor layer forming step]
First, as illustrated in FIGS. 2A to 2B, the semiconductor layer 1 </ b> A is formed on the semiconductor substrate 10. In forming the semiconductor layer 1A, the diffraction grating 10a having a period of 200 mm is formed first. In order to form the diffraction grating 10a, a resist pattern having a period of 200 mm is transferred onto the semiconductor substrate 10 by interference exposure. Next, wet etching is performed using this resist pattern so that the depth becomes, for example, 10 nm. An etching solution used in this wet etching is, for example, a hydrochloric acid aqueous solution. Thereby, the diffraction grating 10a is formed. Thereafter, the resist is peeled off.

  Thereafter, the semiconductor layer 1A is formed on the diffraction grating 10a. First, the lower cladding layer 20a is grown, and the active layer 30a is grown on the lower cladding layer 20a (first active layer forming step). An upper cladding layer 40a is grown on the active layer 30a. Thereby, the semiconductor layer 1A is formed. A lower optical confinement layer may be further grown between the lower clad layer 20a and the active layer 30a, and an upper optical confinement layer may be further grown between the upper clad layer 40a and the active layer 30a. By further providing the lower light confinement layer and the lower light confinement layer in addition to the lower clad layer 20a and the upper clad layer 40a, the light generated from the active layer 30a can be more efficiently confined in the active layer 30a. For the growth of these layers, for example, metal organic vapor phase epitaxy (MOVPE) can be used.

[Etching mask formation process]
Next, as shown in FIGS. 3A to 3B, an etching mask 42 made of an insulating layer (for example, a silicon nitride (SiN _x ) layer) is formed on the upper cladding layer 40a. First, an SiN _X layer having a thickness of 100 nm is formed on the upper cladding layer 40a by using, for example, a chemical vapor deposition (CVD) method. Thereafter, a photosensitive resist is applied on the insulating layer to form a resist layer. Next, a resist pattern is formed using a normal photolithography technique. This resist pattern has a stripe-shaped first portion 42a having a width of 15 μm and a length of 300 μm in a portion corresponding to the region 10B, and has a width at a position 10 μm away from the first portion 42a in a portion corresponding to the region 10D. This is a pattern for an etching mask 42 described later having a rectangular second portion 42b having a length of 15 μm and a length of 5 μm. Further, the first portion 42a and the second portion 42b are arranged side by side along the x-axis direction, which will be the optical waveguide direction later.

Subsequently, by etching the SiN _X layer using this resist pattern as a mask, an etching mask 42 having a first portion 42a in the region 10B and a second portion 42b in the region 10D is formed. After the etching mask 42 is formed, the resist is removed.

[Etching process]
Subsequently, as shown in FIG. 4A to FIG. 4B, the portion of the semiconductor layer 1 </ b> A where the etching mask 42 does not exist is etched using the etching mask 42. This etching is performed to such a depth that the portion of the diffraction grating 10a where the etching mask 42 does not exist disappears. This etching is performed by dry etching, for example, and the etching depth is, for example, 450 nm. As a result, the diffraction grating 10a and the semiconductor layer 1A are removed from portions of the region 10C and the region 10D where the etching mask 42 does not exist.

[Re-growth process]
Next, as shown in FIGS. 5A to 5B, without removing the etching mask 42, the semiconductor layer 1B is regrown using the etching mask 42 as a selective growth mask. In this regrowth process, first, the lower clad layer 20b is grown on the semiconductor substrate 10 where the semiconductor layer 1A has been etched in the etching process. Next, the active layer 30b is grown on the lower cladding layer 20b (second active layer forming step). Thereafter, the upper clad layer 40b is grown on the active layer 30b. Thereby, the semiconductor layer 1B is regrown. The regrown total film thickness is preferably the same as the depth of the semiconductor layer 1A etched in the etching process.

  A lower optical confinement layer made of undoped InGaAsP may be further grown between the lower cladding layer 20b and the active layer 30b, and an upper optical confinement layer made of undoped InGaAsP may be further grown between the upper clad layer 40b and the active layer 30b. By further providing the lower light confinement layer and the lower light confinement layer in addition to the lower clad layer 20b and the upper clad layer 40b, the light generated from the active layer 30b can be confined more efficiently in the active layer 30b. For the growth of these layers, for example, the MOVPE method is used. After the above regrowth process, the etching mask 42 is removed using, for example, wet etching.

After this regrowth step, the interface 1d ₁ where the semiconductor layer 1A in the region 10B and the semiconductor layer 1B in the region 10D are optically coupled by a butt joint, and the semiconductor layer 1B in the region 10C and the semiconductor layer 1A in the region 10D The interface 1d ₂ that is optically coupled by the joint and the interface 1d ₃ that the semiconductor layer 1B in the region 10D and the semiconductor layer 1A in the region 10D are optically coupled by the butt joint are formed. The interfaces 1d ₁ , 1d _2, and 1d ₃ extend along a reference plane (yz plane in FIG. 5) that intersects the main surface of the semiconductor substrate 10.

[Semiconductor mesa formation process]
Next, as shown in FIG. 6, the semiconductor mesa portion 2 is formed on the semiconductor substrate 10. First, a striped insulating layer 44 is formed extending from the region 10B to the region 10C in a direction intersecting the interfaces 1d ₁ , 1d ₂ and 1d ₃ formed by regrowth (x-axis direction which is the optical waveguide direction). Thereafter, etching is performed using the insulating layer 44 as a mask until the semiconductor substrate 10 is exposed. Such etching is performed, for example, by wet etching using bromomethanol. By this etching, the semiconductor layers 1A and 1B where the stripe-shaped insulating layer 44 is not formed are removed.

  As a result, the semiconductor mesa unit 2 including the semiconductor mesa unit 2A in the region 10B, the semiconductor mesa unit 2B in the region 10C, and the semiconductor mesa unit 2C having the semiconductor mesa units 2q and 2p in the region 10D is formed. The semiconductor mesa unit 2 functions as an optical waveguide in the semiconductor optical integrated device 100.

[Built-in layer formation process]
Subsequently, as shown in FIG. 7, a buried layer 50 constituting a current confinement structure is formed. In the buried layer forming step, the buried layer 50 is grown so as to bury the semiconductor mesa portion 2 on both side surfaces of the semiconductor mesa portion 2 by using, for example, the MOVPE method without removing the stripe insulating layer 44. Thereafter, the insulating layer 44 is removed. Note that by forming the buried layer 50 on both side surfaces of the semiconductor mesa unit 2, the leakage current on the side surface of the semiconductor mesa unit 2 is effectively suppressed. Therefore, the semiconductor optical integrated device 100 according to the embodiment can achieve high light emission efficiency even when the drive current increases.

[Other processes]
After the insulating layer 44 is removed, a second upper cladding layer 60 is grown on the entire surface of the semiconductor mesa portion 2 and the buried layer 50. Subsequently, a contact layer 70a for the DFB laser 100A is formed on the upper cladding layer 60 in the region 10B, and a contact layer 70b for the EA modulator 100B is formed on the upper cladding layer 60 in the region 10C. The contact layers 70a and 70b are formed, for example, by growing a contact layer on the entire surface of the upper cladding layer 60 and removing the contact layer on the region 10D. Since the contact layer 70a and the contact layer 70b are separated from each other across the region 10D, one electrode for the DFB laser 100A can be electrically separated from the other electrode for the EA modulator 100B. . For the growth of these layers, for example, the MOVPE method is used.

  Subsequently, as shown in FIGS. 1A to 1B, a common electrode (cathode) 80 c for the DFB laser 100 </ b> A and the EA modulator 100 </ b> B is formed on the back surface of the semiconductor substrate 10. The semiconductor substrate 10 is preferably attached to a quartz substrate before the electrode 80c is formed, and the back surface of the semiconductor substrate 10 is polished so that the thickness of the semiconductor substrate 10 is about 100 μm.

  An electrode (anode) 80a for the DFB laser 100A is formed on the contact layer 70a, and an electrode (anode) 80b for the EA modulator 100B is formed on the contact layer 70b. Thereby, the DFB laser 100A is completed in the region 10B, and the EA modulator 100B is completed in the region 10C. Further, the optical waveguide region 100C is completed in the region 10D. The semiconductor optical integrated device 100 shown in FIGS. 1A to 1B is completed through the above steps.

  In the method for manufacturing a semiconductor optical integrated device according to the present invention, the etching mask 42 used as a selective growth mask when the semiconductor layer 1B is regrown is disposed 10 μm apart along the optical waveguide direction (x-axis direction). It has the 1st part 42a of the area | region 10B, and the 2nd part 42b of the area | region 10D. The first portion 42a has a stripe shape having a width of 15 μm and a length of 300 μm, and the second portion 42b has a rectangular shape having a width of 15 μm and a length of 5 μm.

  Thus, the length of the second portion 42b is shorter than the length of the first portion 42a in the optical waveguide direction. That is, the area of the second portion 42b of the etching mask 42 is sufficiently smaller than the area of the first portion 42a. Therefore, when the semiconductor layer 1B is regrown, the influence of the second portion 42b is sufficiently smaller than the influence of the first portion 42a. As a result, in the vicinity of the second portion 42b of the etching mask 42, composition variation and film thickness variation are suppressed, and the occurrence of dislocations and the like in the second active layer 30b is suppressed. Further, the second portion 42b can block the dislocation generated by the influence of the first portion 42a during the regrowth from propagating beyond the second portion 42b to the EA modulator 100B. Therefore, deterioration of the crystallinity of the semiconductor optical integrated device 100 can be suppressed and the reliability can be improved.

  Further, in the semiconductor optical integrated device 100 according to the present embodiment, the active layer 30b of the EA modulator 100B has a strained quantum well structure from the viewpoint of improving the extinction ratio and the modulation characteristic. When the regrowth active layer has a strained quantum well structure, the strain in the quantum well structure is alleviated due to composition variation, film thickness variation, etc. in the vicinity of the selective growth mask (etching mask 42), and dislocations are particularly likely to occur. . As a result, the crystallinity of the EA modulator 100B is deteriorated. However, according to the etching mask 42, composition variation, film thickness variation, and the like in the vicinity of the second portion 42b are suppressed, so that deterioration of crystallinity is effectively suppressed even in an EA modulator having a strained quantum well structure. be able to.

  The semiconductor optical integrated device 100 operates as follows when a forward bias voltage is applied to the DFB laser 100A and a reverse bias voltage is applied to the EA modulator 100B. In the DFB laser 100A to which a forward bias voltage is applied, holes are injected from the electrode 80a into the active layer 30a. The injected holes are efficiently confined in the active layer 30 a by the buried layer 50. The holes confined in the active layer 30a recombine in the active layer 30a, and light is emitted from the active layer 30a. Then, laser oscillation occurs, and this laser beam propagates in the active layer 30a. This laser light is guided by the optical waveguide region 100C and enters the EA modulator 100B.

  When a relatively low reverse bias voltage is applied to the EA modulator 100B, the effective photoluminescence wavelength of the active layer 30b is shorter than the oscillation wavelength, and thus the incident laser light is absorbed. Without being transmitted, the light propagates through the active layer 30 b and is output from the semiconductor optical integrated device 100. On the other hand, when a sufficiently high reverse bias voltage is applied to the EA modulator 100B, a quantum confined stark effect (QCSE) occurs in the active layer 30b, and the incident laser light is active. Absorbed by layer 30b. The wavelength of the laser light absorbed by the active layer 30 b is modulated according to the magnitude of the reverse bias voltage, and the modulated laser light is output from the semiconductor optical integrated device 100.

  As mentioned above, although preferred embodiment of this invention has been described, the said embodiment can be variously changed in the range which does not deviate from the summary of this invention. For example, the etching mask 42 has one second portion 42b in the region 10D, but may include two or more second portions 42b. Further, although the buried layer 50 is composed of one layer, the number of layers may be increased or decreased as necessary. The active layer 30a may have a single quantum well structure (SQW), or may have a multiple quantum well structure (MQW) like the active layer 30b. The active layer 30b is not limited to the strained multilayer quantum well structure, and may be a single quantum well structure (SQW) or a multiple quantum well structure (MQW) like the active layer 30b.

  In the above embodiment, the conductivity type of the semiconductor substrate 10 is n-type, but may be p-type. In this case, the conductivity type of the lower cladding layers 20a and 20b is changed to p-type. The conductivity types of the first upper cladding layers 40a and 40b, the second upper cladding layer 60, and the contact layers 70a and 70b are changed to n-type.

It is a figure which shows typically the semiconductor optical integrated element which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the manufacturing method of the semiconductor optical integrated device which concerns on this embodiment. It is a figure which shows typically 1 process of the conventional typical butt joint integration | stacking method. It is a figure which shows typically 1 process of the conventional typical butt joint integration | stacking method. It is a figure which shows typically 1 process of the conventional typical butt joint integration | stacking method.

Explanation of symbols

100 ... semiconductor optical integrated device, 100A ... DFB laser, 100B ... EA modulator, 100C ... optical waveguide _{region, 1d 1, 1d 2, 1d} 3 ... interface, 1A, 1B ... semiconductor layer, 2,2A, 2B, 2p, 2q, 2C ... semiconductor mesa portion, 10 ... semiconductor substrate, 10a ... diffraction grating, 20a, 20b ... lower cladding layer, 30a ... first active layer, 30b ... second active layer, 40a, 40b ... first upper cladding layer 42 ... Etching mask, 42a ... 1st part, 42b ... 2nd part, 44 ... Insulator layer, 50 ... Buried layer, 60 ... 2nd upper clad layer, 70a, 70b ... Contact layer, 80a, 80b, 80c …electrode.

Claims (3)

A first semiconductor element portion and a second semiconductor element portion which are disposed on the same semiconductor substrate and optically coupled to each other;
The first semiconductor element portion has a first active layer;
In the method of manufacturing a semiconductor optical integrated device, the second semiconductor element portion has a second active layer having a composition different from that of the first active layer.
A first active layer forming step of growing the first active layer on the semiconductor substrate;
An etching mask forming step of forming an etching mask on the first active layer;
An etching step of etching the first active layer in a portion where the etching mask does not exist using the etching mask;
A second active layer forming step of growing the second active layer using the etching mask as a selective growth mask after the etching step;
An etching mask removing step of removing the etching mask,
The semiconductor substrate has a main surface including a first region and a second region, and a third region between the first region and the second region, and the first semiconductor element portion is on the first region. The second semiconductor element unit is disposed on the second region, and the first semiconductor element unit and the second semiconductor element unit are optically coupled to each other via the optical waveguide region on the third region. Is connected to
The etching mask is disposed on the first region and the third region on the first region, which are arranged at predetermined intervals along the optical waveguide direction of the first semiconductor element unit and the second semiconductor element unit . A second part,
A method of manufacturing a semiconductor optical integrated device, wherein a length of the second portion in the optical waveguide direction is shorter than a length of the first portion in the optical waveguide direction.   The method of manufacturing a semiconductor optical integrated device according to claim 1, wherein the second active layer has a strained quantum well structure. One of the first semiconductor element portion and the second semiconductor element portion includes a semiconductor laser,
3. The method of manufacturing a semiconductor optical integrated device according to claim 1, wherein the other of the first semiconductor element portion and the second semiconductor element portion includes an electroabsorption modulator.

Images