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JP5150242B2 - Semiconductor memory device - Google Patents

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JP5150242B2
JP5150242B2 JP2007335665A JP2007335665A JP5150242B2 JP 5150242 B2 JP5150242 B2 JP 5150242B2 JP 2007335665 A JP2007335665 A JP 2007335665A JP 2007335665 A JP2007335665 A JP 2007335665A JP 5150242 B2 JP5150242 B2 JP 5150242B2
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pad
memory
wiring board
element group
metal wire
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JP2009158738A (en
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拓 西山
哲也 山本
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Toshiba Corp
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent contact of a metal wire between element groups in a semiconductor device where semiconductor elements are arranged in multistage on a wiring board. <P>SOLUTION: A plurality of semiconductor elements 9A-9D constituting a first element group 12 are stacked stepwise on a wiring board 2 while directing the pad arrangement sides toward the same direction. On the first element group 12, a plurality of semiconductor elements 9E-9H constituting a second element group 13 are stacked stepwise to expose electrode pads 11 while directing the pad arrangement sides toward the same direction as that of the first element group. The second element group 13 is arranged while being shifted from the first element group 12 in the arrangement direction of the electrode pads 11. Each semiconductor element 9 is electrically connected with the connection pad 7 of the wiring board 2 through a metal wire 14. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は半導体記憶装置に関する。 The present invention relates to semi-conductor memory device.

ＮＡＮＤ型フラッシュメモリ等を内蔵するメモリカード（半導体メモリカード）は、急速に小型化と高容量化が進められている。小型化されたメモリカードを実現するために、メモリ素子やコントローラ素子等の半導体素子は配線基板上に積層して搭載されている。さらに、メモリカードの高容量化を図るために、メモリ素子自体も配線基板上に多段に積層されるようになってきている。メモリ素子やコントローラ素子等の半導体素子の電極パッドはワイヤボンディングを適用して配線基板の接続パッドと電気的に接続される。   A memory card (semiconductor memory card) incorporating a NAND flash memory or the like has been rapidly reduced in size and capacity. In order to realize a miniaturized memory card, semiconductor elements such as a memory element and a controller element are stacked and mounted on a wiring board. Furthermore, in order to increase the capacity of memory cards, memory elements themselves are also stacked in multiple stages on a wiring board. Electrode pads of semiconductor elements such as memory elements and controller elements are electrically connected to connection pads of the wiring board by applying wire bonding.

メモリ素子の積層数は増加傾向にあり、メモリカードの記憶容量に応じて４段、さらには８段もしくはそれ以上に積層することが検討されている。多段に積層された半導体素子（メモリ素子）に対してワイヤボンディングを行うためには、例えば短辺片側パッド構造の半導体素子の電極パッドをそれぞれ露出させるように、複数の半導体素子を階段状に積層することが考えられる（例えば、特許文献１参照）。露出された電極パッドはボンディングワイヤ（金属ワイヤ等）を介して配線基板の接続パッドと電気的に接続される。   The number of stacked memory elements tends to increase, and it has been studied to stack four layers or even eight or more depending on the storage capacity of the memory card. In order to perform wire bonding on multi-layered semiconductor elements (memory elements), for example, a plurality of semiconductor elements are stacked stepwise so that the electrode pads of a semiconductor element having a short side pad structure are exposed. (For example, refer patent document 1). The exposed electrode pad is electrically connected to the connection pad of the wiring board via a bonding wire (metal wire or the like).

片側パッド構造の半導体素子を多段（例えば８段もしくはそれ以上）に階段積層する場合、半導体素子の積層数に応じて階段方向の長さが長くなる。このため、上段側に配置された半導体素子の電極パッドと配線基板の接続パッドとの距離は増大する傾向にある。多段に積層された半導体素子の電極パッドのうち、電気特性や信号特性等が等しい電極パッドについては金属ワイヤで順に接続することができる。しかし、チップセレクト用の電極パッドについては、制御信号に応じて配線基板の接続パッドと接続する必要がある。   When semiconductor elements having a single-sided pad structure are stacked in multiple steps (for example, eight or more steps), the length in the step direction becomes longer depending on the number of stacked semiconductor elements. For this reason, the distance between the electrode pad of the semiconductor element arranged on the upper side and the connection pad of the wiring board tends to increase. Of the electrode pads of the semiconductor elements stacked in multiple stages, electrode pads having the same electrical characteristics, signal characteristics, and the like can be sequentially connected with metal wires. However, the electrode pad for chip selection needs to be connected to the connection pad of the wiring board in accordance with the control signal.

例えば、多段に積層する半導体素子を第１の素子群と第２の素子群とに分け、これら素子群に応じてチップセレクトを行う制御信号用の金属ワイヤを、配線基板の接続パッドと接続する。このようなチップセレクト用の金属ワイヤに関しては、上段側の第２の素子群に接続された金属ワイヤを、下段側の第１の素子群に接続された金属ワイヤを避けてワイヤリングする必要がある。このため、第２の素子群はチップセレクト用の金属ワイヤに入線角度を付け、第１の素子群の金属ワイヤとの接触を抑制することが検討されている。   For example, the semiconductor elements stacked in multiple stages are divided into a first element group and a second element group, and a metal wire for a control signal for performing chip selection according to these element groups is connected to a connection pad of a wiring board. . With regard to such a metal wire for chip selection, it is necessary to wire the metal wire connected to the second element group on the upper stage side while avoiding the metal wire connected to the first element group on the lower stage side. . For this reason, it has been studied that the second element group provides an angle of entry to the chip select metal wire to suppress contact with the metal wire of the first element group.

しかしながら、半導体素子を例えば８段もしくはそれ以上というように多段化した場合、第２の素子群の金属ワイヤに入線角度を付けても、第１の素子群に接続された金属ワイヤとの接触が避けられないおそれがある。このため、金属ワイヤの接触を避けることが可能な半導体素子の積層構造や金属ワイヤの接続構造等が求められている。なお、特許文献１には２個のメモリ素子を階段状に積層するにあたって、２個のメモリ素子をパッド配列辺と直交する方向にもずらして積層することが記載されている。これは２個のメモリ素子の電極パッドを個々に配線基板の接続パッドと接続するにあたって、金属ワイヤの重なりを防止するものであり、半導体素子の多段積層については考慮されていない。
特開２００１−２１７３８３号公報 However, when the semiconductor element is multi-staged, for example, to have eight or more stages, contact with the metal wire connected to the first element group is not achieved even if the metal wire of the second element group is given an angle of entry. There is a risk that it cannot be avoided. For this reason, a laminated structure of semiconductor elements capable of avoiding contact of metal wires, a connection structure of metal wires, and the like are required. Patent Document 1 describes that when two memory elements are stacked stepwise, the two memory elements are stacked while being shifted in a direction orthogonal to the pad array side. This is to prevent the metal wires from overlapping when the electrode pads of the two memory elements are individually connected to the connection pads of the wiring board, and no consideration is given to multi-stage stacking of semiconductor elements.
JP 2001-217383 A

本発明の目的は、半導体素子を配線基板上に多段に積層するにあたって、金属ワイヤの接触を防止した半導体記憶装置を提供することにある。 An object of the present invention, when laminated in multiple stages a semiconductor element on a wiring substrate, is to provide a semi-conductor memory device which prevents contact of the metal wire.

本発明の態様に係る半導体記憶装置は、外部接続端子を備える第１の主面と、素子搭載部と接続パッドとを備え、前記第１の主面とは反対側の第２の主面とを有する配線基板と、外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように順に階段状に積層されている第１のメモリ素子群と、外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記第１のメモリ素子群上に前記第１のメモリ素子群とパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように順に階段状に積層されている第２のメモリ素子群と、前記第２のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、前記第１および第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第１の金属ワイヤと、前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第２の金属ワイヤと、前記第１および第２のメモリ素子群と前記コントローラ素子を前記第１および第２の金属ワイヤと共に封止するように、前記配線基板の前記第２の主面上に形成された封止樹脂層とを具備し、前記第２のメモリ素子群は、前記第１のメモリ素子群に対して前記電極パッドの配列方向にずらした状態で配置されていると共に、前記第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドが前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドの間に位置するように配置されており、前記第１の金属ワイヤは、前記第１および第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続するデータ信号用金属ワイヤと、前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第１の制御信号用金属ワイヤと、前記第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第２の制御信号用金属ワイヤとを備え、前記第２の制御信号用金属ワイヤは前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッド間にワイヤリングされていることを特徴としている。 A semiconductor memory device according to an aspect of the present invention includes a first main surface including an external connection terminal, an element mounting portion, and a connection pad, and a second main surface opposite to the first main surface; And a plurality of memory elements having electrode pads arranged along one side of the outer shape, wherein the plurality of memory elements have their pad arrangement sides directed in the same direction on the element mounting portion of the wiring board. A plurality of memory elements each having a first memory element group that is sequentially stacked in a stepped manner so that the electrode pads are exposed, and an electrode pad arranged along one side of the outer shape. second memory element devices are stacked in the first the first memory element group and the pad arrangement sides on the memory element group toward the same direction, and such that the electrode pads are exposed sequentially stepped A group and the second memory element A controller element having electrode pads stacked on at least one side of the outer shape, the electrode pads of the plurality of memory elements constituting the first and second memory element groups, and the wiring board A first metal wire that electrically connects the connection pad; a second metal wire that electrically connects the electrode pad of the controller element and the connection pad of the wiring board; and A sealing resin layer formed on the second main surface of the wiring board so as to seal the second memory element group and the controller element together with the first and second metal wires; , the second memory element group, the conjunction is arranged in a state shifted in the arrangement direction of the electrode pad with respect to the first memory element group, configure the second memory element group The electrode pads of the plurality of memory elements are disposed between the electrode pads of the plurality of memory elements constituting the first memory element group, and the first metal wire is Data signal metal wires for sequentially connecting the electrode pads of the plurality of memory elements constituting the first and second memory element groups and the connection pads of the wiring board, and the first memory element group A first control signal metal wire for sequentially connecting the electrode pads of the plurality of memory elements and the connection pads of the wiring board; and the plurality of memory elements constituting the second memory element group A second control signal metal wire for sequentially connecting the electrode pad and the connection pad of the wiring board; and the second control signal metal wire connects the first memory element group. It is characterized by being wired between the electrode pads of the plurality of memory elements constituting .

本発明の態様に係る半導体記憶装置においては、第２のメモリ素子群を第１のメモリ素子群に対して電極パッドの配列方向にずらした状態で配置している。従って、第２のメモリ素子群に接続された金属ワイヤを第１のメモリ素子群の電極パッド間にワイヤリングすることができるため、第１のメモリ素子群に接続された金属ワイヤと第２のメモリ素子群に接続された金属ワイヤとの接触を抑制することが可能となる。 In the semi-conductor memory device engaging Ru to an aspect of the present invention is arranged in a state of shifting the second memory element group in the direction of arrangement of the electrode pads to the first memory element group. Accordingly, the second for the connected metal wires in the memory element group can be wired between the first memory element group of the electrode pads, the first memory device connected to the metal wire group and the second memory It becomes possible to suppress contact with a metal wire connected to the element group.

以下、本発明を実施するための形態について、図面を参照して説明する。図１および図２は本発明の実施形態による半導体記憶装置（半導体装置）の構成を示す図であって、図１は半導体記憶装置（半導体装置）の平面図、図２はそのＡ−Ａ線に沿った断面図（長辺方向に切断した断面図）である。これらの図に示される半導体記憶装置１は半導体メモリカードを構成しており、例えば半導体記憶装置１のみでマイクロＳＤTM規格のメモリカードとして使用される。半導体記憶装置１はケースレスのメモリカードである。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. 1 and 2 are diagrams showing a configuration of a semiconductor memory device (semiconductor device) according to an embodiment of the present invention. FIG. 1 is a plan view of the semiconductor memory device (semiconductor device), and FIG. FIG. 6 is a cross-sectional view taken along the line (cross-sectional view cut in the long side direction). The semiconductor memory device 1 shown in these drawings constitutes a semiconductor memory card. For example, only the semiconductor memory device 1 is used as a memory card of the micro SD ™ standard. The semiconductor memory device 1 is a caseless memory card.

半導体記憶装置１は素子実装基板と端子形成基板とを兼ねる配線基板２を備えている。配線基板２は、例えば絶縁性樹脂基板の内部や表面に配線網を設けたものであり、具体的にはガラス−エポキシ樹脂やＢＴ樹脂（ビスマレイミド・トリアジン樹脂）等を使用したプリント配線板が適用される。配線基板２は、端子形成面となる第１の主面２ａと、素子実装面となる第２の主面２ｂとを備えている。配線基板２の第２の主面２ｂには、第１ないし第３のチップコンデンサＣ１〜Ｃ３が実装されている。   The semiconductor memory device 1 includes a wiring board 2 that serves as both an element mounting board and a terminal forming board. The wiring board 2 is, for example, a wiring network provided inside or on the surface of an insulating resin board. Specifically, a printed wiring board using glass-epoxy resin, BT resin (bismaleimide / triazine resin) or the like is used. Applied. The wiring board 2 includes a first main surface 2a serving as a terminal formation surface and a second main surface 2b serving as an element mounting surface. First to third chip capacitors C <b> 1 to C <b> 3 are mounted on the second main surface 2 b of the wiring board 2.

配線基板２は概略矩形状の外形を有している。配線基板２の一方の短辺３Ａはメモリカードをカードスロットに挿入する際の先端部に相当する。他方の短辺３Ｂはメモリカードの後方部に相当する。配線基板２の一方の長辺４Ａは直線形状であるのに対し、他方の長辺４Ｂはメモリカードの前後や表裏の向きを示す切り欠き部やくびれ部を有している。さらに、配線基板２の各角部は曲線状（Ｒ形状）とされている。   The wiring board 2 has a substantially rectangular outer shape. One short side 3 </ b> A of the wiring board 2 corresponds to a tip portion when the memory card is inserted into the card slot. The other short side 3B corresponds to the rear part of the memory card. One long side 4A of the wiring board 2 has a linear shape, while the other long side 4B has a notch portion or a constricted portion indicating the front and back direction of the memory card and the front and back sides. Further, each corner of the wiring board 2 is curved (R shape).

配線基板２の第１の主面２ａには、メモリカードの入出力端子となる外部接続端子５が形成されている。外部接続端子５は電解めっき等により形成された金属層で構成されている。なお、配線基板２の第１の主面２ａはメモリカードの表面に相当する。さらに、配線基板２の第１の主面２ａには、外部接続端子５の形成領域を除く領域に第１の配線網（図示せず）が設けられている。第１の配線網は例えばメモリカードのテストパッドを有している。第１の主面２ａに設けられた第１の配線網は、絶縁性の接着シールや接着テープ等を用いた絶縁層（図示せず）で覆われている。   On the first main surface 2 a of the wiring board 2, external connection terminals 5 that are input / output terminals of the memory card are formed. The external connection terminal 5 is composed of a metal layer formed by electrolytic plating or the like. The first main surface 2a of the wiring board 2 corresponds to the surface of the memory card. Furthermore, a first wiring network (not shown) is provided on the first main surface 2 a of the wiring board 2 in a region excluding the region where the external connection terminals 5 are formed. The first wiring network has, for example, a memory card test pad. The first wiring network provided on the first main surface 2a is covered with an insulating layer (not shown) using an insulating adhesive seal, adhesive tape, or the like.

配線基板２の第２の主面２ｂは、素子搭載部６と、ワイヤボンディング時のボンディング部となる接続パッド７を含む第２の配線網とを備えている。なお、配線基板２の第２の主面２ｂはメモリカードの裏面に対応するものである。接続パッド７を有する第２の配線網は、配線基板２の図示を省略した内部配線（スルーホール等）を介して、外部接続端子５や第１の配線網と電気的に接続されている。接続パッド７は短辺３Ｂに沿った第１のパッド領域８Ａと長辺４Ａに沿った第２のパッド領域８Ｂのそれぞれに配置されている。   The second main surface 2b of the wiring board 2 includes an element mounting portion 6 and a second wiring network including a connection pad 7 that becomes a bonding portion during wire bonding. The second main surface 2b of the wiring board 2 corresponds to the back surface of the memory card. The second wiring network having the connection pads 7 is electrically connected to the external connection terminals 5 and the first wiring network through internal wiring (such as through holes) (not shown) of the wiring board 2. The connection pad 7 is disposed in each of the first pad region 8A along the short side 3B and the second pad region 8B along the long side 4A.

配線基板２の素子搭載部６には、複数のメモリ素子（半導体素子）９が積層されて搭載されている。メモリ素子９としては、ＮＡＮＤ型フラッシュメモリ等の半導体メモリ素子が用いられる。メモリ素子９上にはコントローラ素子（半導体素子）１０が積層されている。コントローラ素子１０は、複数のメモリ素子９からデータの書き込みや読み出しを行うメモリ素子を選択（チップセレクト）し、選択したメモリ素子９へのデータを書き込み、また選択したメモリ素子９に記憶されたデータの読み出し等を行う。   A plurality of memory elements (semiconductor elements) 9 are stacked and mounted on the element mounting portion 6 of the wiring board 2. As the memory element 9, a semiconductor memory element such as a NAND flash memory is used. A controller element (semiconductor element) 10 is stacked on the memory element 9. The controller element 10 selects (chip selects) a memory element that writes and reads data from a plurality of memory elements 9, writes data to the selected memory element 9, and stores data stored in the selected memory element 9 Is read out.

配線基板２の第２の主面２ｂ上には、第１のメモリ素子９Ａ、第２のメモリ素子９Ｂ、第３のメモリ素子９Ｃ、第４のメモリ素子９Ｄ、第５のメモリ素子９Ｅ、第６のメモリ素子９Ｆ、第７のメモリ素子９Ｇおよび第８のメモリ素子９Ｈが順に積層されている。第１ないし第８のメモリ素子９Ａ〜９Ｈは矩形状の同一形状を有し、それぞれ電極パッド１１Ａ〜１１Ｈを備えている。第１ないし第８の電極パッド１１Ａ〜１１Ｈは、第１ないし第８のメモリ素子９Ａ〜９Ｈの外形の一辺、具体的には一方の短辺に沿って配列されている。第１ないし第８のメモリ素子９Ａ〜９Ｈは短辺片側パッド構造を有している。   On the second main surface 2b of the wiring board 2, the first memory element 9A, the second memory element 9B, the third memory element 9C, the fourth memory element 9D, the fifth memory element 9E, Six memory elements 9F, a seventh memory element 9G, and an eighth memory element 9H are sequentially stacked. The first to eighth memory elements 9A to 9H have the same rectangular shape and are provided with electrode pads 11A to 11H, respectively. The first to eighth electrode pads 11A to 11H are arranged along one side of the outer shape of the first to eighth memory elements 9A to 9H, specifically, one short side. The first to eighth memory elements 9A to 9H have a short side pad structure.

第１のメモリ素子９Ａは、第１の電極パッド１１Ａが形成された電極形成面を上方に向けて、配線基板２の素子搭載部６上に接着層を介して接着されている。接着層には一般的なポリイミド樹脂、エポキシ樹脂、アクリル樹脂等を主成分とするダイアタッチフィルム（接着剤フィルム）が用いられる。他のメモリ素子９の接着層も同様である。第１のメモリ素子９Ａはパッド配列辺（一方の短辺）を配線基板２の短辺３Ｂに向けて配置されている。すなわち、第１のメモリ素子９Ａは電極パッド１１Ａが配線基板２の第１のパッド領域８Ａの近傍に位置するように配置されている。   The first memory element 9A is bonded to the element mounting portion 6 of the wiring board 2 via an adhesive layer with the electrode formation surface on which the first electrode pad 11A is formed facing upward. A die attach film (adhesive film) mainly composed of a general polyimide resin, epoxy resin, acrylic resin or the like is used for the adhesive layer. The same applies to the adhesive layers of the other memory elements 9. The first memory element 9 </ b> A is arranged with the pad array side (one short side) facing the short side 3 </ b> B of the wiring board 2. That is, the first memory element 9 </ b> A is arranged such that the electrode pad 11 </ b> A is positioned in the vicinity of the first pad region 8 </ b> A of the wiring board 2.

第２のメモリ素子９Ｂは、第２の電極パッド１１Ｂが形成された電極形成面を上方に向けて、第１の電極パッド１１Ａを露出させつつ、第１のメモリ素子９Ａ上に接着層を介して接着されている。同様に、第３のメモリ素子９Ｃは第２のメモリ素子９Ｂ上に、また第４ないし第８のメモリ素子９Ｄ〜９Ｈはそれぞれ下段側のメモリ素子９Ｃ〜９Ｇ上にそれぞれ接着層を介して接着されている。第２ないし第８のメモリ素子９Ｂ〜９Ｈは、それぞれ第１のメモリ素子９Ａとパッド配列辺を同方向に向け、かつ下段側のメモリ素子９の電極パッド１１が露出するように階段状に積層されている。   The second memory element 9B has an electrode formation surface on which the second electrode pad 11B is formed facing upward, exposing the first electrode pad 11A, and an adhesive layer on the first memory element 9A. Are glued together. Similarly, the third memory element 9C is bonded to the second memory element 9B, and the fourth to eighth memory elements 9D to 9H are bonded to the lower memory elements 9C to 9G via adhesive layers, respectively. Has been. The second to eighth memory elements 9B to 9H are stacked in a stepped manner so that the first memory element 9A and the pad array side are directed in the same direction, and the electrode pads 11 of the lower memory element 9 are exposed. Has been.

このように、第１ないし第８のメモリ素子９Ａ〜９Ｈは、それらのパッド配列辺（一方の短辺）を同方向に向け、かつ下段側のメモリ素子９の電極パッド１１が露出するように、短辺（パッド配列辺）を長辺方向にずらして階段状に順に積層されている。第１ないし第８のメモリ素子９Ａ〜９Ｈの階段構造の積層状態に基づいて、第１ないし第８の電極パッド１１Ａ〜１１Ｈはいずれも上方に向けて露出されており、その状態で第１のパッド領域８Ａの近傍に位置している。   As described above, the first to eighth memory elements 9A to 9H have their pad arrangement sides (one short side) directed in the same direction, and the electrode pads 11 of the lower memory element 9 are exposed. The short sides (pad array sides) are shifted in the long side direction and stacked in order in a stepped manner. Based on the stacked state of the staircase structure of the first to eighth memory elements 9A to 9H, the first to eighth electrode pads 11A to 11H are all exposed upward, and in this state, the first It is located in the vicinity of the pad region 8A.

第１ないし第８のメモリ素子９Ａ〜９Ｈは、コントローラ素子１０による素子選択の制御信号に基づいて、第１のメモリ素子群１２と第２のメモリ素子群１３とに分けられている。第１のメモリ素子群１２は第１ないし第４のメモリ素子９Ａ〜９Ｄにより構成されており、第２のメモリ素子群１３は第５ないし第８のメモリ素子９Ｅ〜９Ｈにより構成されている。第１のメモリ素子群１２を構成する第１ないし第４のメモリ素子９Ａ〜９Ｄは、それらのパッド配列辺を同方向に向け、かつ長辺を揃えると共に、下段側のメモリ素子９の電極パッド１１が露出するように短辺を長辺方向にずらして階段状に積層されている。   The first to eighth memory elements 9A to 9H are divided into a first memory element group 12 and a second memory element group 13 based on an element selection control signal by the controller element 10. The first memory element group 12 is composed of first to fourth memory elements 9A to 9D, and the second memory element group 13 is composed of fifth to eighth memory elements 9E to 9H. The first to fourth memory elements 9A to 9D constituting the first memory element group 12 have their pad arrangement sides directed in the same direction and the long sides aligned, and the electrode pads of the memory element 9 on the lower stage side. 11 are stacked in a staircase pattern with the short side shifted in the long side direction so that 11 is exposed.

同様に、第２のメモリ素子群１３を構成する第５ないし第８のメモリ素子９Ｅ〜９Ｈは、それらのパッド配列辺を同方向に向け、かつ長辺を揃えると共に、下段側のメモリ素子９の電極パッド１１が露出するように短辺を長辺方向にずらして階段状に積層されている。ただし、第２のメモリ素子群１３は第１のメモリ素子群１２に対して電極パッド１１の配列方向にずらした状態で配置されている。すなわち、第２のメモリ素子群１３はそれを構成する第５ないし第８のメモリ素子９Ｅ〜９Ｈの電極パッド１１Ｅ〜１１Ｈが第１のメモリ素子群１１を構成する第１ないし第４のメモリ素子９Ａ〜９Ｄの電極パッド１１Ａ〜１１Ｄの間に位置するように配置されている。   Similarly, the fifth to eighth memory elements 9E to 9H constituting the second memory element group 13 have their pad array sides directed in the same direction and the long sides aligned, and the lower memory element 9 The electrode pads 11 are stacked stepwise with the short sides shifted in the long side direction so that the electrode pads 11 are exposed. However, the second memory element group 13 is arranged in a state shifted from the first memory element group 12 in the arrangement direction of the electrode pads 11. That is, the second memory element group 13 includes the first to fourth memory elements in which the electrode pads 11E to 11H of the fifth to eighth memory elements 9E to 9H constituting the second memory element group 13 constitute the first memory element group 11. It arrange | positions so that it may be located between the electrode pads 11A-11D of 9A-9D.

例えば、電極パッド１１の配置間隔が２２６μｍの場合、第２のメモリ素子群１３は第１のメモリ素子群１２に対して電極パッド１１の配列方向に、例えばパッド間隔（２２６μｍ）の半分の距離（１１３μｍ）だけオフセットされた状態で配置される。図１は第２のメモリ素子群１３を長辺４Ａに向けてオフセットさせて配置した状態を示している。第２のメモリ素子群１３を第１のメモリ素子群１２に対して電極パッド１１の配列方向にずらした状態で配置することによって、第５ないし第８の電極パッド１１Ｅ〜１１Ｈは第１ないし第４の電極パッド１１Ａ〜１１Ｄの間に位置することになる。   For example, when the arrangement interval of the electrode pads 11 is 226 μm, the second memory element group 13 is, for example, a distance half the pad interval (226 μm) in the arrangement direction of the electrode pads 11 with respect to the first memory element group 12 ( 113 μm) is offset. FIG. 1 shows a state in which the second memory element group 13 is arranged so as to be offset toward the long side 4A. By disposing the second memory element group 13 in a state in which the second memory element group 13 is shifted in the arrangement direction of the electrode pads 11 with respect to the first memory element group 12, the fifth to eighth electrode pads 11E to 11H are first to first. 4 electrode pads 11A to 11D.

このように、第１のメモリ素子群１２を構成する第１ないし第４のメモリ素子９Ａ〜９Ｄは、それらのパッド配列辺を同方向に向け、かつ長辺を揃えると共に、下段側のメモリ素子９の電極パッド１１が露出するように、素子搭載部６上に階段状に積層されている。第２のメモリ素子群１３を構成する第５ないし第８のメモリ素子９Ｅ〜９Ｈは、それらのパッド配列辺を第１のメモリ素子群１２と同方向に向け、かつ長辺を揃えると共に、下段側のメモリ素子９の電極パッド１１が露出するように、第１のメモリ素子群１２上に階段状に積層されている。第２のメモリ素子群１３は第１のメモリ素子群１２に対して電極パッド１１の配列方向にずらした状態で配置されている。   As described above, the first to fourth memory elements 9A to 9D constituting the first memory element group 12 have their pad arrangement sides directed in the same direction and the long sides aligned, and the lower-stage memory elements. The electrode pads 11 are stacked in a stepped manner on the element mounting portion 6 so that the nine electrode pads 11 are exposed. The fifth to eighth memory elements 9E to 9H constituting the second memory element group 13 have their pad array sides directed in the same direction as the first memory element group 12 and the long sides are aligned, On the first memory element group 12, the electrode pads 11 of the memory element 9 on the side are exposed stepwise. The second memory element group 13 is arranged in a state shifted from the first memory element group 12 in the arrangement direction of the electrode pads 11.

第１ないし第８のメモリ素子９Ａ〜９Ｈの電極パッド１１Ａ〜１１Ｈは、第１のパッド領域８Ａに配置された接続パッド７と第１の金属ワイヤ１４を介して電気的に接続されている。第１ないし第８のメモリ素子９Ａ〜９Ｈの電極パッド１１のうち、データ信号用端子（Ｉ／Ｏ）等に関しては図３および図４に示すように、第１ないし第８の電極パッド１１Ａ〜１１Ｈがデータ信号用金属ワイヤ１４ａで順に接続されている。このように、電極パッド１１の電気特性や信号特性等が等しい場合には、全てのメモリ素子９Ａ〜９Ｈの電極パッド１１Ａ〜１１Ｈを第１の金属ワイヤ１４で順に接続することができ、その上で配線基板２の接続パッド７と第１の金属ワイヤ１４を介して接続することができる。   The electrode pads 11A to 11H of the first to eighth memory elements 9A to 9H are electrically connected to the connection pads 7 arranged in the first pad region 8A via the first metal wires 14. Among the electrode pads 11 of the first to eighth memory elements 9A to 9H, the data signal terminals (I / O) and the like are shown in FIGS. 3 and 4 as shown in FIG. 3 and FIG. 11H are sequentially connected by a data signal metal wire 14a. As described above, when the electrical characteristics and signal characteristics of the electrode pads 11 are equal, the electrode pads 11A to 11H of all the memory elements 9A to 9H can be sequentially connected by the first metal wires 14, and further, Thus, it can be connected to the connection pads 7 of the wiring board 2 via the first metal wires 14.

一方、素子選択等の制御信号用の電極パッド（ＣＥ，ＲＢ，素子選択等）に関しては、第１のメモリ素子群１２と第２のメモリ素子群１３とに分けて、配線基板２の接続パッド７と電気的に接続する必要がある。図５に半導体記憶装置１の素子選択構造を示す。図５に示すように、素子選択は第１のメモリ素子群１２と第２のメモリ素子群１３とに分けて制御される。第１のメモリ素子群１２に関しては、第１ないし第４のメモリ素子９Ａ〜９Ｄの素子選択０端子および素子選択１端子の通電状態を確認して素子選択を行う。第２のメモリ素子群１３も同様であり、第５ないし第８のメモリ素子９Ｅ〜９Ｈの素子選択０端子および素子選択１端子の通電状態を確認して素子選択を行う。   On the other hand, electrode pads for control signals such as element selection (CE, RB, element selection, etc.) are divided into the first memory element group 12 and the second memory element group 13 and are connected to the connection pads of the wiring board 2. 7 need to be electrically connected. FIG. 5 shows an element selection structure of the semiconductor memory device 1. As shown in FIG. 5, element selection is controlled separately for the first memory element group 12 and the second memory element group 13. Regarding the first memory element group 12, element selection is performed by confirming the energization states of the element selection 0 terminal and the element selection 1 terminal of the first to fourth memory elements 9A to 9D. The same applies to the second memory element group 13, and element selection is performed by confirming the energization states of the element selection 0 terminal and the element selection 1 terminal of the fifth to eighth memory elements 9E to 9H.

第１のメモリ素子群１２を構成する第１ないし第４のメモリ素子９Ａ〜９Ｄの電極パッド１１のうち、ＣＥ（Ｃｈｉｐ ｅｎａｂｌｅ）端子やＲＢ（Ｒｅａｄｙ／Ｂｕｓｙ）端子は図３および図６に示すように、第１の制御信号用金属ワイヤ１４ｂで第１ないし第４の電極パッド１１Ａ〜１１Ｄが順に接続され、その上で第１の電極パッド１１Ａと接続パッド７とが第１の制御信号用金属ワイヤ１４ｂを介して接続されている。第２のメモリ素子群１３も同様であり、ＣＥ端子やＲＢ端子は第２の制御信号用金属ワイヤ１４ｃで第５ないし第８の電極パッド１１Ｅ〜１１Ｈが順に接続され、その上で第５の電極パッド１１Ａと接続パッド７とが第２の制御信号用金属ワイヤ１４ｃを介して接続されている。   Of the electrode pads 11 of the first to fourth memory elements 9A to 9D constituting the first memory element group 12, the CE (Chip enable) terminal and the RB (Ready / Busy) terminal are shown in FIG. 3 and FIG. As described above, the first to fourth electrode pads 11A to 11D are sequentially connected by the first control signal metal wire 14b, and then the first electrode pad 11A and the connection pad 7 are used for the first control signal. It is connected via a metal wire 14b. The same applies to the second memory element group 13. The CE terminal and the RB terminal are connected to the fifth to eighth electrode pads 11E to 11H in this order by the second control signal metal wire 14c, and then the fifth terminal 8B. The electrode pad 11A and the connection pad 7 are connected via the second control signal metal wire 14c.

第１の制御信号用金属ワイヤ１４ｂに関しては、接続パッド７とその近傍に位置する第１のメモリ素子９Ａの電極パッド１１Ａとを接続しているため、通常のワイヤボンディングで問題となることはない。一方、第２の制御信号用金属ワイヤ１４ｃに関しては、第１ないし第４の半導体素子９Ａ〜９Ｄの電極パッド１１Ａ〜１１Ｄを飛び越えて、接続パッド７と第５のメモリ素子９Ｅの電極パッド１１Ｅとの間を接続する必要がある。このため、半導体素子９の積層構造によっては、第２の制御信号用金属ワイヤ１４ｃがその下方に位置する第１の制御信号用金属ワイヤ１４ｂと接触するおそれがある。   With respect to the first control signal metal wire 14b, the connection pad 7 and the electrode pad 11A of the first memory element 9A located in the vicinity thereof are connected, so that there is no problem in normal wire bonding. . On the other hand, the second control signal metal wire 14c jumps over the electrode pads 11A to 11D of the first to fourth semiconductor elements 9A to 9D, and connects the connection pad 7 and the electrode pad 11E of the fifth memory element 9E. Need to connect between. Therefore, depending on the laminated structure of the semiconductor element 9, the second control signal metal wire 14c may come into contact with the first control signal metal wire 14b positioned therebelow.

例えば、単純に第１ないし第８の半導体素子９Ａ〜９Ｈの長辺を揃えて階段状に積層した場合、第２の制御信号用金属ワイヤ１４ｂは第１の制御信号用金属ワイヤ１４ｂ上をワイヤリングされるために接触しやすくなる。また、第２の制御信号用金属ワイヤ１４ｂに入線角度をつけたとしても、例えばメモリ素子９を８段もしくはそれ以上というように多段に積層した場合、入線角度に限界があることから、第２の制御信号用金属ワイヤ１４ｂの第１の制御信号用金属ワイヤ１４ｂとの接触が避けられないおそれがある。   For example, when the first to eighth semiconductor elements 9A to 9H are simply stacked stepwise with the long sides aligned, the second control signal metal wire 14b is wired on the first control signal metal wire 14b. To be easy to touch. Even when the second control signal metal wire 14b has an incoming angle, when the memory elements 9 are stacked in multiple stages such as eight or more, the incoming angle is limited. There is a possibility that the contact of the control signal metal wire 14b with the first control signal metal wire 14b cannot be avoided.

このような点に対して、この実施形態では第２のメモリ素子群１３を第１のメモリ素子群１２に対してずらして配置し、それによって第５ないし第８の電極パッド１１Ｅ〜１１Ｈを第１ないし第４の電極パッド１１Ａ〜１１Ｄの間に位置させている。このため、第２の制御信号用金属ワイヤ１４ｂは図３に示すように、入線角度をつけることなく、第１ないし第４の電極パッド１１Ａ〜１１Ｄの間にワイヤリングすることができる。従って、第２のメモリ素子群１３に第２の制御信号用金属ワイヤ１４ｂを接続する場合に、第１の制御信号用金属ワイヤ１４ｂとの接触を抑制することが可能となる。   In contrast to this, in this embodiment, the second memory element group 13 is shifted from the first memory element group 12, and thereby the fifth to eighth electrode pads 11E to 11H are arranged as the first. It is located between the first to fourth electrode pads 11A to 11D. For this reason, as shown in FIG. 3, the second control signal metal wire 14b can be wired between the first to fourth electrode pads 11A to 11D without making an entry angle. Therefore, when the second control signal metal wire 14b is connected to the second memory element group 13, contact with the first control signal metal wire 14b can be suppressed.

上述したように、この実施形態の半導体記憶装置１においては、第２のメモリ素子群１３を第１のメモリ素子群１２に対してずらして配置し、第５ないし第８の電極パッド１１Ｅ〜１１Ｈを第１ないし第４の電極パッド１１Ａ〜１１Ｄの間に位置させているため、第１のメモリ素子群１２に接続された第１の制御信号用金属ワイヤ１４ｂと第２のメモリ素子群１３に接続された第２の制御信号用金属ワイヤ１４ｂとの接触を防止することができる。従って、メモリ素子９を例えば８段もしくはそれ以上に積層する場合において、金属ワイヤ１４間の接触による不良発生を抑制することが可能となる。   As described above, in the semiconductor memory device 1 of this embodiment, the second memory element group 13 is arranged with being shifted with respect to the first memory element group 12, and the fifth to eighth electrode pads 11E to 11H are arranged. Is positioned between the first to fourth electrode pads 11A to 11D, the first control signal metal wire 14b connected to the first memory element group 12 and the second memory element group 13 are connected to each other. It is possible to prevent contact with the connected second control signal metal wire 14b. Therefore, when the memory elements 9 are stacked in, for example, eight stages or more, it is possible to suppress the occurrence of defects due to the contact between the metal wires 14.

第２のメモリ素子群１３（具体的には第８のメモリ素子９Ｈ）上には、コントローラ素子１０が接着層を介して接着されている。コントローラ素子１０はＬ型パッド構造を有しており、第１の外形辺とそれと直交する第２の外形辺のそれぞれに沿って配列された電極パッド１５Ａ、１５Ｂを備えている。これら電極パッド１５Ａ、１５Ｂのうち、第２のパッド領域８Ｂの近傍に位置する電極パッド１５Ａ（配線基板２の長辺４Ａと平行な第１の外形辺に沿って配列された電極パッド１５Ａ）は、第２のパッド領域８Ｂに配置された接続パッド７と第２の金属ワイヤ１６を介して電気的に接続されている。   On the second memory element group 13 (specifically, the eighth memory element 9H), the controller element 10 is bonded via an adhesive layer. The controller element 10 has an L-type pad structure, and includes electrode pads 15A and 15B arranged along a first outer shape side and a second outer shape side perpendicular thereto. Of these electrode pads 15A and 15B, an electrode pad 15A (electrode pad 15A arranged along the first outer side parallel to the long side 4A of the wiring board 2) located in the vicinity of the second pad region 8B is The connection pads 7 arranged in the second pad region 8B are electrically connected via the second metal wires 16.

ここで、第１ないし第８のメモリ素子９Ａ〜９Ｈは順に階段状に積層されているため、メモリ素子９の積層構造における階段方向の長さが長くなる。このため、配線基板２に対するメモリ素子９の占有面積（全素子の投影面積）が増加し、配線基板２の短辺に沿ったパッド配置領域が制約を受けることになる。半導体メモリカードは寸法が規定されているため、この実施形態では配線基板２の短辺３Ｂに沿った領域にコントローラ素子１０用のパッド領域を設定することができない。コントローラ素子１０はＬ型パッド構造を有するため、配線基板２の長辺４Ａに沿った第２のパッド領域８Ｂのみでは全ての電極パッド１５を接続パッド７と直接ワイヤボンディングすることができない。   Here, since the first to eighth memory elements 9A to 9H are sequentially stacked in a staircase pattern, the length in the staircase direction in the stacked structure of the memory elements 9 is increased. For this reason, the area occupied by the memory element 9 with respect to the wiring board 2 (projection area of all elements) increases, and the pad arrangement area along the short side of the wiring board 2 is restricted. Since the dimensions of the semiconductor memory card are defined, in this embodiment, the pad area for the controller element 10 cannot be set in the area along the short side 3B of the wiring board 2. Since the controller element 10 has an L-type pad structure, all the electrode pads 15 cannot be directly wire-bonded to the connection pads 7 only in the second pad region 8B along the long side 4A of the wiring board 2.

この実施形態による半導体記憶装置１においては、第２のメモリ素子群１３上にコントローラ素子１０と並列して中継素子１７を配置している。中継素子１７は他の素子と同様に接着層を介して第８のメモリ素子９Ｈ上に接着されている。中継素子１７は１つの外形辺とそれと直交する他の外形辺のそれぞれに沿って配列された電極パッド（中継パッド）１８Ａ、１８Ｂを有している。中継素子１７は電極パッド１８Ａがコントローラ素子１０の電極パッド１５Ｂと対向し、かつ電極パッド１８Ｂが第２のパッド領域８Ｂの近傍に位置するように配置されている。中継素子５０は通常の半導体素子と同様な構造を有する。   In the semiconductor memory device 1 according to this embodiment, the relay element 17 is arranged on the second memory element group 13 in parallel with the controller element 10. The relay element 17 is bonded onto the eighth memory element 9H through an adhesive layer in the same manner as other elements. The relay element 17 has electrode pads (relay pads) 18A and 18B arranged along one outer side and another outer side perpendicular thereto. The relay element 17 is arranged so that the electrode pad 18A faces the electrode pad 15B of the controller element 10 and the electrode pad 18B is positioned in the vicinity of the second pad region 8B. The relay element 50 has the same structure as a normal semiconductor element.

コントローラ素子１０の電極パッド１５Ｂ（配線基板２の長辺４Ａと直交する第２の外形辺に沿って配列された電極パッド）は、第３の金属ワイヤ（第１の中継用金属ワイヤ）１９Ａを介して中継素子１７の電極パッド１８Ａと電気的に接続されている。さらに、中継素子１７の電極パッド１８Ｂは、第３の金属ワイヤ（第２の中継用金属ワイヤ）１９Ｂを介して第２のパッド領域８Ｂに配置された接続パッド７と電気的に接続されている。中継素子１７は電極パッド１８Ａと電極パッド１８Ｂとを繋ぐ配線層を有している。コントローラ素子１０の電極パッド１５Ｂと第２のパッド領域８Ｂに配置された接続パッド７とは、中継素子１７を介して第３の金属ワイヤ１９により電気的に接続されている。   The electrode pad 15B of the controller element 10 (electrode pad arranged along the second outer side orthogonal to the long side 4A of the wiring board 2) is connected to the third metal wire (first relay metal wire) 19A. And is electrically connected to the electrode pad 18A of the relay element 17. Furthermore, the electrode pad 18B of the relay element 17 is electrically connected to the connection pad 7 disposed in the second pad region 8B via a third metal wire (second relay metal wire) 19B. . The relay element 17 has a wiring layer that connects the electrode pad 18A and the electrode pad 18B. The electrode pad 15B of the controller element 10 and the connection pad 7 arranged in the second pad region 8B are electrically connected by a third metal wire 19 via the relay element 17.

なお、ここでは中継素子１７を用いているが、コントローラ素子１０の電極パッド１５と配線基板２の接続パッド７との接続はこれに限られるものではない。例えば、配線基板２のパッド領域８Ａのスペースに余裕がある場合には、コントローラ素子１０の電極パッド１５Ｂ（この場合にはパッド領域８Ａ側の外形辺に沿って配列された電極パッド１５Ｂ）を接続パッド７と第２の金属ワイヤ１６を介して接続することができる。   Although the relay element 17 is used here, the connection between the electrode pad 15 of the controller element 10 and the connection pad 7 of the wiring board 2 is not limited to this. For example, when there is room in the pad area 8A of the wiring board 2, the electrode pad 15B of the controller element 10 (in this case, the electrode pad 15B arranged along the outer side of the pad area 8A) is connected. The pad 7 and the second metal wire 16 can be connected.

メモリ素子９やコントローラ素子１０が実装された配線基板２の第２の主面２ｂには、例えばエポキシ樹脂からなる封止樹脂層２０がモールド成形されている。メモリ素子９やコントローラ素子１０は、金属ワイヤ１４、１６、１９等と共に封止樹脂層２０で一体的に封止されている。封止樹脂層２０の先端には、メモリカードの前方を示す傾斜部２１が設けられている。封止樹脂層２０の後方には封止樹脂を一部盛り上げた取手部２２が設けられている。これらによって、半導体メモリカードとして用いられる半導体記憶装置１が構成されている。なお、図１では封止樹脂層２０の図示を省略している。   On the second main surface 2b of the wiring substrate 2 on which the memory element 9 and the controller element 10 are mounted, a sealing resin layer 20 made of, for example, an epoxy resin is molded. The memory element 9 and the controller element 10 are integrally sealed with a sealing resin layer 20 together with the metal wires 14, 16, 19 and the like. An inclined portion 21 indicating the front of the memory card is provided at the tip of the sealing resin layer 20. Behind the sealing resin layer 20 is provided a handle portion 22 in which the sealing resin is partially raised. These constitute a semiconductor memory device 1 used as a semiconductor memory card. In addition, illustration of the sealing resin layer 20 is abbreviate | omitted in FIG.

なお、第１および第２のメモリ素子群１２、１３を構成する第１ないし第８のメモリ素子９Ａ〜９Ｈは、電極パッド１１Ａ〜１１Ｈを露出させるように階段状に積層されているため、電極パッド１１が配列された一方の短辺と対向する他方の短辺側は順にひさし状に張り出している。メモリ素子９の積層体によるひさし部分は封止樹脂層２０の先端に設けられた傾斜部２１と同方向に傾斜している。メモリ素子９の積層体はひさし部分の一部が封止樹脂層２０の傾斜部２１と重なるように配置されている。これによって、封止樹脂層２０内に収容するメモリ素子数の増加に対応することが可能となる。   The first to eighth memory elements 9A to 9H constituting the first and second memory element groups 12 and 13 are stacked stepwise so as to expose the electrode pads 11A to 11H. The other short side opposite to the one short side on which the pads 11 are arranged projects in an eave-like shape in order. The eaves portion of the stacked body of the memory elements 9 is inclined in the same direction as the inclined portion 21 provided at the tip of the sealing resin layer 20. The stacked body of the memory elements 9 is arranged so that a part of the eaves portion overlaps the inclined portion 21 of the sealing resin layer 20. As a result, it is possible to cope with an increase in the number of memory elements accommodated in the sealing resin layer 20.

半導体記憶装置１は、ベースカードのような収納ケースを用いることなく、それ単体で半導体メモリカード（例えばマイクロＳＤTMカード）を構成するものである。従って、封止樹脂層２０等は直接外部に露出した状態とされる。すなわち、半導体記憶装置１は封止樹脂層２０等を外部に露出させたケースレスの半導体メモリカードである。このため、上述したメモリカードの前後や表裏の向き等を示す切り欠き部やくびれ部、また傾斜部２１は半導体記憶装置１自体に設けられている。 The semiconductor memory device 1 constitutes a semiconductor memory card (for example, a micro SD ™ card) by itself without using a storage case such as a base card. Accordingly, the sealing resin layer 20 and the like are directly exposed to the outside. That is, the semiconductor memory device 1 is a caseless semiconductor memory card in which the sealing resin layer 20 and the like are exposed to the outside. Therefore, the semiconductor memory device 1 itself is provided with the notches and the constricted portions 21 that indicate the front and back of the memory card, the front and back directions, and the inclined portion 21.

第１ないし第８のメモリ素子９Ａ〜９Ｈの厚さは、最下段に位置する第１のメモリ素子９Ａを除いて１０〜５０μｍの範囲とすることが好ましい。第１のメモリ素子９Ａの厚さは配線基板２の表面凹凸に起因する割れやクラック等の発生を抑制するために５０〜１５０μｍの範囲とすることが好ましい。例えば、配線基板２の厚さを１２５μｍ、第１のメモリ素子９Ａの厚さを６０μｍ、その接着層の厚さを２０μｍ、第２ないし第８の半導体素子９Ｂ〜９Ｈの各厚さを４０μｍ、それらの接着層の厚さを５μｍ、コントローラ素子１０の厚さを４０μｍ、その接着層の厚さを５μｍ、封止樹脂層２０の素子上樹脂厚を１３５μｍとしたとき、これらの合計厚は７００μｍとなり、例えばマイクロＳＤTMカードに求められるカード厚（７００〜７４０μｍの範囲）を満足させることが可能となる。 The thicknesses of the first to eighth memory elements 9A to 9H are preferably in the range of 10 to 50 μm except for the first memory element 9A located at the lowermost stage. The thickness of the first memory element 9 </ b> A is preferably in the range of 50 to 150 μm in order to suppress the occurrence of cracks and cracks due to the surface irregularities of the wiring substrate 2. For example, the thickness of the wiring board 2 is 125 μm, the thickness of the first memory element 9A is 60 μm, the thickness of the adhesive layer is 20 μm, the thickness of each of the second to eighth semiconductor elements 9B to 9H is 40 μm, When the thickness of the adhesive layer is 5 μm, the thickness of the controller element 10 is 40 μm, the thickness of the adhesive layer is 5 μm, and the resin thickness on the element of the sealing resin layer 20 is 135 μm, the total thickness is 700 μm. Thus, for example, it is possible to satisfy the card thickness (range of 700 to 740 μm) required for the Micro SD ™ card.

この実施形態の半導体記憶装置１において、メモリ素子９の搭載数（積層数）は８個に限られるものではなく、第１および第２のメモリ素子群１２、１３を構成するメモリ素子９の数がそれぞれ複数個であればよい。ただし、半導体記憶装置１の高容量化を図る上で、メモリ素子９の数は８個もしくはそれ以上であることが好ましい。例えば、記憶容量が１ＧＢのメモリ素子９を８個使用することで、８ＧＢのマイクロＳＤTMカードを半導体記憶装置４１で実現することが可能となる。また、メモリ素子９の積層構造は各素子群を構成するメモリ素子９を階段状に積層していればよく、各素子群は例えばスペーサを介した２段もしくはそれ以上の積層構造としてもよい。 In the semiconductor memory device 1 of this embodiment, the number of mounted memory elements 9 (the number of stacked layers) is not limited to eight, but the number of memory elements 9 constituting the first and second memory element groups 12 and 13. There may be a plurality of each. However, in order to increase the capacity of the semiconductor memory device 1, the number of memory elements 9 is preferably eight or more. For example, by using eight memory elements 9 having a storage capacity of 1 GB, an 8 GB micro SD ™ card can be realized by the semiconductor storage device 41. The memory element 9 may have a stacked structure in which the memory elements 9 constituting each element group are stacked stepwise, and each element group may have, for example, a stacked structure of two or more stages with a spacer interposed therebetween.

また、この実施形態の半導体記憶装置１はそれら単体で構成するケースレスの半導体メモリカードに対して有効であるが、必ずしもベースカードのようなケースを用いた半導体メモリカードを除外するものではない。さらに、半導体メモリカード以外の半導体記憶装置にも適用可能である。具体的には、実施形態の装置構造はＢＧＡパッケージ構造やＬＧＡパッケージ構造を有する半導体記憶装置に適用することができる。   In addition, the semiconductor memory device 1 of this embodiment is effective for a caseless semiconductor memory card configured as a single unit, but does not necessarily exclude a semiconductor memory card using a case such as a base card. Furthermore, the present invention can be applied to a semiconductor memory device other than the semiconductor memory card. Specifically, the device structure of the embodiment can be applied to a semiconductor memory device having a BGA package structure or an LGA package structure.

なお、本発明の半導体装置および半導体記憶装置は上記した実施形態に限定されるものではなく、配線基板上に複数のメモリ素子を積層して搭載した各種の半導体記憶装置等に適用可能である。本発明の半導体装置および半導体記憶装置の具体的な構造は、本発明の基本構成を満足するものであれば種々に変形が可能である。さらに、実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。   The semiconductor device and the semiconductor memory device of the present invention are not limited to the above-described embodiments, and can be applied to various semiconductor memory devices and the like in which a plurality of memory elements are stacked on a wiring board. The specific structures of the semiconductor device and the semiconductor memory device of the present invention can be variously modified as long as they satisfy the basic configuration of the present invention. Furthermore, the embodiments can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

本発明の実施形態による半導体記憶装置を示す平面図である。1 is a plan view showing a semiconductor memory device according to an embodiment of the present invention. 図１のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図１に示す半導体記憶装置を構成する第１および第２のメモリ素子群と配線基板との金属ワイヤによる接続状態を示す図である。FIG. 3 is a diagram showing a connection state of the first and second memory element groups constituting the semiconductor memory device shown in FIG. 1 and a wiring board by metal wires. 図１に示す半導体記憶装置の素子選択構造を示す図である。FIG. 2 is a diagram showing an element selection structure of the semiconductor memory device shown in FIG. 1. 図１に示す半導体記憶装置を構成する第１および第２のメモリ素子群と配線基板とのデータ信号用金属ワイヤによる接続状態を示す図である。FIG. 3 is a diagram showing a connection state of the first and second memory element groups constituting the semiconductor memory device shown in FIG. 1 and a wiring board by a data signal metal wire. 図１に示す半導体記憶装置を構成する第１および第２のメモリ素子群と配線基板との制御信号用金属ワイヤによる接続状態を示す図である。FIG. 3 is a diagram showing a connection state of the first and second memory element groups constituting the semiconductor memory device shown in FIG. 1 and a wiring board by a control signal metal wire.

符号の説明Explanation of symbols

１…半導体記憶装置、２…配線基板、５…外部接続端子、６…素子搭載部、７…接続パッド、８…パッド領域、９…メモリ素子、１０…コントローラ素子、１１，１５…電極パッド、１２…第１のメモリ素子群、１３…第２のメモリ素子群、１４…第１の金属ワイヤ、１４ａ…データ信号用金属ワイヤ、１４ｂ，１４ｃ…制御信号用金属ワイヤ、１６…第２の金属ワイヤ、２０…封止樹脂層。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 2 ... Wiring board, 5 ... External connection terminal, 6 ... Element mounting part, 7 ... Connection pad, 8 ... Pad area | region, 9 ... Memory element, 10 ... Controller element, 11, 15 ... Electrode pad, DESCRIPTION OF SYMBOLS 12 ... 1st memory element group, 13 ... 2nd memory element group, 14 ... 1st metal wire, 14a ... Metal wire for data signals, 14b, 14c ... Metal wire for control signals, 16 ... 2nd metal Wire, 20 ... sealing resin layer.

Claims (4)

外部接続端子を備える第１の主面と、素子搭載部と接続パッドとを備え、前記第１の主面とは反対側の第２の主面とを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記配線基板の前記素子搭載部上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように順に階段状に積層されている第１のメモリ素子群と、
外形の一辺に沿って配列された電極パッドを有する複数のメモリ素子を備え、前記複数のメモリ素子は前記第１のメモリ素子群上に前記第１のメモリ素子群とパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように順に階段状に積層されている第２のメモリ素子群と、
前記第２のメモリ素子群上に積層され、少なくとも外形の一辺に沿って配列された電極パッドを有するコントローラ素子と、
前記第１および第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第１の金属ワイヤと、
前記コントローラ素子の前記電極パッドと前記配線基板の前記接続パッドとを電気的に接続する第２の金属ワイヤと、
前記第１および第２のメモリ素子群と前記コントローラ素子を前記第１および第２の金属ワイヤと共に封止するように、前記配線基板の前記第２の主面上に形成された封止樹脂層とを具備し、
前記第２のメモリ素子群は、前記第１のメモリ素子群に対して前記電極パッドの配列方向にずらした状態で配置されていると共に、前記第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドが前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドの間に位置するように配置されており、
前記第１の金属ワイヤは、前記第１および第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続するデータ信号用金属ワイヤと、前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第１の制御信号用金属ワイヤと、前記第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドと前記配線基板の前記接続パッドとを順に接続する第２の制御信号用金属ワイヤとを備え、
前記第２の制御信号用金属ワイヤは前記第１のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッド間にワイヤリングされていることを特徴とする半導体記憶装置。 A wiring board having a first main surface including an external connection terminal, an element mounting portion and a connection pad, and having a second main surface opposite to the first main surface;
A plurality of memory elements having electrode pads arranged along one side of the outer shape, wherein the plurality of memory elements have their pad arrangement sides directed in the same direction on the element mounting portion of the wiring board; and A first memory element group that is sequentially stacked in a staircase pattern so as to be exposed;
A plurality of memory elements having electrode pads arranged along one side of the outer shape, wherein the plurality of memory elements are arranged on the first memory element group with the first memory element group and the pad array side in the same direction; And a second memory element group stacked stepwise in order so that the electrode pads are exposed,
A controller element having electrode pads stacked on the second memory element group and arranged along at least one side of the outer shape;
A first metal wire that electrically connects the electrode pads of the plurality of memory elements constituting the first and second memory element groups and the connection pads of the wiring board;
A second metal wire that electrically connects the electrode pad of the controller element and the connection pad of the wiring board;
A sealing resin layer formed on the second main surface of the wiring board so as to seal the first and second memory element groups and the controller element together with the first and second metal wires. And
The second memory element group is arranged in a state of being shifted in the arrangement direction of the electrode pads with respect to the first memory element group, and the plurality of memories constituting the second memory element group The electrode pads of the elements are disposed between the electrode pads of the plurality of memory elements constituting the first memory element group;
The first metal wire includes a data signal metal wire for sequentially connecting the electrode pads of the plurality of memory elements constituting the first and second memory element groups and the connection pads of the wiring board; A first control signal metal wire for sequentially connecting the electrode pads of the plurality of memory elements constituting the first memory element group and the connection pads of the wiring board; and the second memory element group. A second control signal metal wire for sequentially connecting the electrode pads of the plurality of memory elements to be configured and the connection pads of the wiring board;
2. The semiconductor memory device according to claim 1, wherein the second control signal metal wire is wired between the electrode pads of the plurality of memory elements constituting the first memory element group. 請求項１記載の半導体記憶装置において、
さらに、前記第２のメモリ素子群上に前記コントローラ素子と並列して配置され、第１の外形辺に沿って配列された第１の中継パッド、前記第１の外形辺と直交する第２の外形辺に沿って配列された第２の中継パッド、および前記第１の中継パッドと前記第２の中継パッドとを電気的に繋ぐ配線層を有する中継素子を具備し、
前記コントローラ素子の前記電極パッドは、第１の外形辺に沿って配列された第１の電極パッドと、前記第１の外形辺と直交する第２の外形辺に沿って配列された第２の電極パッドとを有し、
前記コントローラ素子の前記第１の電極パッドは、前記配線基板の前記接続パッドと前記第２の金属ワイヤを介して電気的に接続されており、
前記コントローラ素子の前記第２の電極パッドは、前記中継素子の前記第１の中継パッドと第１の中継用金属ワイヤを介して電気的に接続されており、
前記中継素子の前記第２の中継パッドは、前記配線基板の前記接続パッドと第２の中継用金属ワイヤを介して電気的に接続されていることを特徴とする半導体記憶装置。 The semiconductor memory device according to claim 1.
Further, a first relay pad arranged in parallel with the controller element on the second memory element group and arranged along the first outer edge, and a second relay pad orthogonal to the first outer edge. A relay element having a second relay pad arranged along an outer side and a wiring layer that electrically connects the first relay pad and the second relay pad;
The electrode pads of the controller element include a first electrode pad arranged along a first outer edge and a second outer edge arranged along a second outer edge orthogonal to the first outer edge. An electrode pad,
The first electrode pad of the controller element is electrically connected to the connection pad of the wiring board via the second metal wire,
The second electrode pad of the controller element is electrically connected to the first relay pad of the relay element via a first relay metal wire,
The semiconductor memory device, wherein the second relay pad of the relay element is electrically connected to the connection pad of the wiring board via a second metal wire for relay. 請求項２記載の半導体記憶装置において、
前記配線基板は略矩形状の外形を有し、前記外形は直線形状の第１の長辺、切り欠き部を有する第２の長辺、第１の短辺および第２の短辺を有し、
前記配線基板の前記第２の主面は、前記第１の短辺に沿って設けられた第１のパッド領域と、前記第１の長辺に沿って設けられた第２のパッド領域とを有し、
前記第１および第２のメモリ素子群を構成する前記複数のメモリ素子の前記電極パッドは、前記第１のパッド領域に配置された前記接続パッドと前記第１の金属ワイヤを介して電気的に接続されており、
前記コントローラ素子の前記第１の電極パッドは、前記第２のパッド領域に配置された前記接続パッドと前記第２の金属ワイヤを介して電気的に接続されており、
前記中継素子の前記第２の中継パッドは、前記第２のパッド領域に配置された前記接続パッドと前記第２の中継用金属ワイヤを介して電気的に接続されていることを特徴とする半導体記憶装置。 The semiconductor memory device according to claim 2.
The wiring board has a substantially rectangular outer shape, and the outer shape has a linear first long side, a second long side having a notch, a first short side, and a second short side. ,
The second main surface of the wiring board includes a first pad region provided along the first short side and a second pad region provided along the first long side. Have
The electrode pads of the plurality of memory elements constituting the first and second memory element groups are electrically connected to the connection pads disposed in the first pad region via the first metal wires. Connected,
The first electrode pad of the controller element is electrically connected to the connection pad disposed in the second pad region via the second metal wire;
The second relay pad of the relay element is electrically connected to the connection pad arranged in the second pad region through the second relay metal wire. Storage device. 請求項１ないし請求項３のいずれか１項記載の半導体記憶装置において、
前記半導体記憶装置は半導体メモリカードであることを特徴とする半導体記憶装置。 4. The semiconductor memory device according to claim 1, wherein
The semiconductor memory device is a semiconductor memory card.
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CN103098206A (en) * 2010-03-18 2013-05-08 莫塞德技术公司 Multi-chip package with offset die stacking and method of making same
JP2014513870A (en) * 2011-05-18 2014-06-05 サンディスク セミコンダクター （シャンハイ） カンパニー， リミテッド Waterfall wire bonding

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