JP5126959B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technique for initializing circuit control data in a register, for example, a technique effective when applied to a liquid crystal driving semiconductor device that generates a gradation voltage used for driving a liquid crystal display and outputs a driving signal. .

  In some cases, it is necessary to initially set control data corresponding to the type or characteristics of the controlled object in the internal circuit of the semiconductor device. For this purpose, for example, a nonvolatile memory such as an EEPROM storing control data is prepared on the system, and when the power is turned on or the system is reset, the control data is read from the EEPROM and initialized in the internal circuit of the semiconductor device. Patent Document 1 describes a technique for reading display control parameter data from an EEPROM at power-on or system reset, and initializing the data in a register. In Patent Document 2, a non-volatile memory circuit that stores parameter data such as driving conditions according to the specifications of a liquid crystal display device to be used is provided in a semiconductor device for driving a liquid crystal display. A technique for initializing parameter data is described.

JP 2003-263134 A JP 2006-330582 A

  When a nonvolatile memory such as an EEPROM is used to store control data to be initialized, an external EEPROM for control data is always required separately from the semiconductor device for driving the liquid crystal, and the semiconductor for driving the liquid crystal is used. Even when the apparatus includes an on-chip EEPROM, a large storage capacity for the control data is required. Therefore, the present inventor considers determining the initial value of the control data by changing the wiring mask pattern as in the aluminum master slice technology without using a rewritable nonvolatile memory such as an EEPROM for storing the control data. did. For example, an aluminum master cell that outputs a logical value 1 or a logical value 0 by changing a wiring mask pattern is used for each bit of control data. However, even in that case, a register capable of setting control data in a programmable manner is required in terms of control diversity or good usability, so the output of the register and the aluminum master cell column corresponding to the register are necessary. In other words, a selector that can alternatively select one of the outputs is required, and the number of gates is greatly increased.

  An object of the present invention is to provide a semiconductor device that does not require a nonvolatile memory for initial setting of control data for a register and does not require a selector or an aluminum master cell for selecting the output of the register in order to replace the nonvolatile memory. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a semiconductor device used for liquid crystal driving or the like initializes a register storing control data for adjusting circuit characteristics such as a gradation voltage generation circuit in accordance with the control data to be initialized. It is constituted by an arrangement of a first latch circuit that latches a logical value 1 and a second latch circuit that latches a logical value 0 in response to the first state of the control signal and the first state of the latch enable control signal. As a result, an EEPROM is not required for initial setting of control data for the register, and a selector that receives the output of the register and an aluminum master cell that can be selected by the selector are not required. If the first latch circuit and the second latch circuit are rewritten after the initial setting, the control data can be changed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, a nonvolatile memory is not required for initial setting of control data for the register, and a selector or an aluminum master cell for selecting the output of the register is not required to replace the nonvolatile memory.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (30) according to the present invention includes a circuit (20) and a register (40) in which control data for adjusting the circuit is stored. The register latches a logical value 1 in response to the first state of the initialization control signal (sd) and the first state of the latch enable control signal (e) corresponding to the control data to be initialized. The first latch circuit (SL) and the second latch circuit (RSL) that latches the logical value 0 are arranged. In the first latch circuit and the second latch circuit, the semiconductor region formed on the semiconductor substrate and the gate wiring pattern (AR1, AR2) are the same, and one wiring layer connected to the semiconductor region and the gate wiring The pattern (AR3) is different. As a result, an EEPROM is not required for initial setting of control data for the register, and a selector that receives the output of the register and an aluminum master cell that can be selected by the selector are not required. If the first latch circuit and the second latch circuit are rewritten after the initial setting, the control data can be changed. The initial value of the control data can be easily determined simply by changing the mask pattern of the one wiring layer.

  [2] In the semiconductor device of [1], the initialization control signal is set to a first state in response to a reset instruction level by a reset signal to the semiconductor device, and is set to a second state in response to reset release by the reset signal. . In response to a reset instruction by a reset signal, control data can be initialized in the register.

  [3] In the semiconductor device of [2], the first latch circuit and the second latch circuit are responsive to the initialization control signal being set to the second state and the latch enable control signal being set to the first state. The value corresponding to the logical value of the signal supplied to the data input terminal is latched. After the reset release by the reset signal, the control data can be rewritten in accordance with a latch enable control signal which is a different signal.

  [4] The semiconductor device of the present invention according to one specific aspect generates a gradation voltage, selects a voltage corresponding to display data from the generated gradation voltage, and outputs a display drive signal for the display. Each semiconductor device has a register in which control data for generating the gradation voltage in accordance with the characteristics of the display is stored. A first latch circuit for latching a logical value of 1 in response to a first state of an initialization control signal and a first state of a latch enable control signal corresponding to the control data to be initialized; It has an arrangement with a second latch circuit that latches a logical value 0. In the first latch circuit and the second latch circuit, the semiconductor region formed on the semiconductor substrate and the gate wiring pattern are the same, and one wiring layer connected to the semiconductor region and the gate wiring is different. As a result, an EEPROM is not required for initial setting of control data for the register, and a selector that receives the output of the register and an aluminum master cell that can be selected by the selector are not required. If the first latch circuit and the second latch circuit are rewritten after the initial setting, the control data can be changed. The initial value of the control data can be easily determined simply by changing the mask pattern of the one wiring layer.

  [5] In the semiconductor device of [4], the latch is connected to the outside of the register through a wiring of a wiring layer formed in an upper layer of the one wiring layer. Input wiring and output wiring connected to the outside of the register are not affected at all by the arrangement state of the first latch circuit and the second latch circuit.

  [6] In the semiconductor device of [4], the initialization control signal is set to a first state in response to a reset instruction level by a reset signal to the semiconductor device, and is set to a second state in response to reset release by the reset signal. . In response to a reset instruction by a reset signal, control data can be initialized in the register.

  [7] In the semiconductor device of [6], the first latch circuit and the second latch circuit are responsive to the initialization control signal being set to the second state and the latch enable control signal being set to the first state. The value corresponding to the logical value of the signal supplied to the data input terminal is latched. After the reset release by the reset signal, the control data can be rewritten in accordance with a latch enable control signal which is a different signal.

  [8] The semiconductor device according to [7], including a system interface that receives commands and data from the outside, and the system interface controls the latch enable control signal to a first state for a predetermined period in response to a write command to the register. . The initialized control data can be rewritten in response to a predetermined command.

  [9] In the semiconductor device of [7], either one of the first latch circuit and the second latch circuit has a data input terminal and a terminal to which the initialization control signal is input. A two-input NOR gate circuit activated by a first state of the control signal and inactivated by a second state; and the two-input NOR gate circuit connected to the output of the two-input NOR gate circuit and in the first state of the latch enable control signal And a static latch that latches the input signal in the second state of the latch enable control signal. The other latch circuit has a data input terminal and a terminal to which an inverted signal of the initialization control signal is input. The latch circuit is activated by the first state of the latch enable control signal and deactivated by the second state. An input NAND gate circuit is connected to the output of the two-input NAND gate circuit, and the output signal of the two-nand gate circuit is input in the first state of the latch enable control signal. The input signal is input in the second state of the latch enable control signal. It has a static latch to latch. Thereby, a rewritable configuration of the first latch circuit and the second latch circuit can be easily realized.

  [10] In the semiconductor device of [4], the correction data is γ adjustment data for generating a drive signal in accordance with the γ characteristic of the display. As a result, a semiconductor device in which the γ characteristic of the applied display is reflected in the gradation voltage can be obtained.

  [11] The semiconductor device according to [10] is used to generate a gradation voltage from a first resistance voltage dividing circuit that resistance-divides a reference voltage and a plurality of voltages divided by the first resistance voltage dividing circuit. A selection circuit that selects a voltage in units of a plurality of steps, a second resistance voltage dividing circuit that generates a gradation voltage based on the plurality of voltages selected by the selection circuit, the first resistance voltage dividing circuit, and the reference voltage And a second variable resistor positioned between the first resistance voltage dividing circuit and the ground. At this time, the control data initially set in the register adjusts the amplitude of the gradation voltage by determining the resistance values of the first variable resistor and the second variable resistor. A semiconductor device in which the γ characteristic is reflected in the amplitude of the gradation voltage can be obtained.

  [12] The semiconductor device according to [11] further includes a third variable resistor disposed in the middle of the first resistance voltage dividing circuit. At this time, the control data initially set in the register further adjusts the slope of the gradation number-gradation voltage characteristic near the center by determining the resistance value of the third variable resistance. A semiconductor device can be obtained in which the γ characteristic is reflected in the gradient near the center of the gradation number-gradation voltage characteristic.

  [13] In the semiconductor device of item 12, the control data initially set in the register further finely adjusts the gradation voltage by determining the selection voltage by the selection circuit. The reflection of the γ characteristic with respect to the gradation voltage can be finely adjusted.

2. Details of Embodiment << Liquid Crystal Display System >>
FIG. 2 illustrates a liquid crystal display system. In the liquid crystal display panel 1 shown in the figure, an active matrix type liquid crystal display (DISP) 2 including a liquid crystal and a switching transistor is formed on a glass panel substrate. In the liquid crystal display 2, a large number of signal electrodes and scanning electrodes are arranged so as to intersect with each other, and the switching transistor is formed at the intersection. The switching transistor has a gate electrode coupled to a corresponding scan line and a source electrode coupled to a corresponding signal line. Signal lines, scanning lines, and the like are drawn out to the edge portion of the panel substrate. Reference numeral 3 denotes a liquid crystal drive control device (LCDDRV) formed as a semiconductor integrated circuit, which is connected to the host device (HST) 4 through the host interface terminals Tacc and Tprc, and to the signal terminal (source) connected to the signal line. Terminals) S1 to Sn and scanning terminals (gate terminals) G1 to Gm connected to the scanning lines. The host device 4 includes a processor (PRCS) 5 that controls the entire device and an accelerator (ACCL) 6 that exclusively bears display control for the liquid crystal display panel 1. A RAM 7 is a volatile memory used for a work area or the like of the processor 5, and an IO 9 is an external input / output circuit, which are connected to the processor 5 and the accelerator 6 via the bus 8.

  The processor 5 performs an initialization operation for the liquid crystal drive control device 3 and the accelerator 6. The initial setting of control data such as parameter data represented by γ (gamma) adjustment data corresponding to the characteristics of the liquid crystal display 2 will be described later in detail, but the register in which it is initialized is set in accordance with the wiring mask pattern. A circuit configuration in which the initial value is determined is adopted. The accelerator 6 performs control to supply necessary display data to the liquid crystal drive control device 3 according to, for example, a high-speed serial interface protocol in accordance with a command given from the processor 5.

<Liquid crystal drive control device>
FIG. 1 shows an example of the liquid crystal drive control device 3. The liquid crystal drive control device 3 is formed on one semiconductor substrate by a complementary MOS integrated circuit manufacturing technique, for example, and has a host interface terminal Tacc connected to the accelerator 6 and a host interface terminal Tprc connected to the processor 5. . The host interface circuit (HIF) 11 connected to the host interface terminals Tacc and Tprc is not particularly limited, and a display interface circuit that inputs display data and commands according to a predetermined packet format via the host interface terminal Tacc, and a host A system control interface circuit for inputting commands and data and outputting internal data via the interface terminal Tprc. For example, when a high-speed serial interface is employed as the display interface circuit, commands and display data are received differentially. When a parallel interface is employed as the system control interface, input / output operations are performed in accordance with input strobe signals such as a chip select signal, a write signal, and a read signal. When the host interface circuit 11 receives a command from the host interface terminals Tacc and Tprc, the host interface circuit 11 predecodes the command and determines whether to perform a write operation or a read operation on the register of the control register circuit (CREG) 12. The command is latched by the index circuit (IDX) 13. The index circuit 13 decodes the latched command and selects the register of the control register circuit 12 according to the decoding result.

  When the host interface circuit 11 performs a read operation in accordance with the predecode result, the host interface circuit 11 outputs a value from the register of the selected control register circuit 12, and the internal operation such as a display operation and a read operation is controlled using the output as a control signal. The In the display operation, the start address of the display data is preset in the address counter (ACUNT) 15, the display data is set in the write data register (WDR) 16, and the set display data is in accordance with the memory address generated by the address counter 15. It is written in the display memory (GRAM) 17. Display data written in the display memory 17 is read out to a source driver (SOCDRV) 19 by a timing control circuit (TGNR) 18 in synchronization with the display timing. The source driver 19 is supplied with gradation voltages 26 for a plurality of gradations (for example, 64 gradations) generated by a gradation voltage generation circuit (TWVG) 20. The source driver 19 that receives the display data and the gradation voltage outputs a drive signal for driving the source line from the signal terminals S1 to Sn to the outside by the gradation voltage of the gradation specified by the display data. In short, the display data is DA-converted in a range of a plurality of gradation voltages to drive the signal terminals S1 to Sn. The timing control circuit 18 applies the gate signal line scanning timing to the gate driver (GTDRV) 22 in parallel with the driving of the source lines by the signal terminals S1 to Sn, and the gate driver 22 synchronizes with the scanning timing. A drive signal for the gate electrode is output from Gm. For driving the scanning terminals G1 to Gm, a driving voltage 27 generated by a liquid crystal driving level generating circuit (DRLG) 23 having a charge pump circuit is used. A plurality of external terminals Tc connected to the liquid crystal drive level generation circuit 23 are external terminals such as a capacitor for constituting a charge pump circuit. In the read operation, display data is read from the display memory 17 to the read data register (RDR) 24 based on the memory address preset in the address counter (ACUNT) 15, and the read display data is stored in the host interface circuit 11. To the host device 4.

  When the host interface circuit 11 performs the write operation according to the predecode result, the host interface circuit 11 performs control to write data to the register of the control register circuit 12 selected by the index register 13 through the signal path 25.

  The clock pulse generator (CPG) 30 receives the original oscillation clock from the terminals OSC1 and OSC2, generates an internal clock CLK, and supplies it to the timing generator 50 and the like as an operation reference clock. The power supply circuit (VSPL) 31 generates an internal power supply VDD and the like based on the reference voltage VREF and the external power supply voltage VCC.

  The control register circuit 12 has a large number of control registers 40, and the data read by the designation from the index circuit 13 as described above functions as an operation control signal for the internal circuit in the liquid crystal drive control device 3. Is done. The signal functions as a sequence control signal for defining an internal operation procedure, and further functions as parameter data for adjusting the characteristics of the internal circuit. The former is for power-on sequence control, display operation sequence control, readout operation sequence control, and the like. The latter includes gamma adjustment data for generating a drive signal in accordance with the gamma characteristics of the display, system definition data according to the display color of the display, start address definition data of the display memory according to the display size, etc. The Initial values are set in these control registers 40 at the time of power-on reset or system reset.

<Control register set latch and reset latch>
FIG. 3 illustrates one control register 40 provided in the control register circuit 12. One control register 40 representatively shown in the figure has an arrangement of latch circuits of a plurality of bits D0 to Dk, for example. The latch circuit for each bit of D0 to Dk latches the logical value 1 in response to the initialization instruction level (for example, high level: H) of the initialization control signal sd corresponding to the control data to be initialized. It is suitable for a combination of a set latch circuit (SL: Set Latch) and a reset latch circuit that latches a logical value 0. For example, in order to latch the values “101... 110” in Dk to D0 in response to the initialization instruction level of the initialization control signal sd, the bit Dk is set latch circuit SL, Dj is reset latch circuit RSL, Di is set latched The circuits SL,..., D2 may be configured by a set latch circuit SL, D1 may be configured by a set latch circuit SL, and D1 may be configured by a reset latch circuit RSL.

  The initialization control signal sd is set to a high level in response to a low level which is a reset instruction level by a reset signal RES (see FIG. 1) for the liquid crystal drive control device 3, and is set to a low level in response to a reset release by the reset signal. Is done. Control data can be initialized in the control register in response to a reset instruction by the reset signal RES. The reset signal RES may be considered as one terminal in the system interface terminal Tprc.

  Each of the latch circuits SL and RSL receives a signal supplied to the data input terminal in response to the latch enable control signal e being set to high level when the initialization control signal sd is set to low level. The latched signal is latched in response to the latching and latch enable control signal e being set to the low level. Therefore, after the reset is released by the reset signal RES, the control register 40 can rewrite the control data according to the latch enable control signal e which is a different signal. The initialization control signal sd, the latch enable control signal e, and the input data d are supplied from the host interface circuit 11 shown in FIG.

  FIG. 4 illustrates a logic circuit diagram of the reset latch circuit SL. The reset latch circuit SL includes a two-input NAND gate NAND, an inverter INV4 connected in antiparallel to the NAND gate NAND to form a static latch, an output inverter INV6, and logic matching inverters INV5A to INV5D. The inverter INV5D is activated by the high level of the latch enable control signal e and deactivated by the low level. When the inverter INV5D is activated, the NAND gate circuit NAND performs exclusive logic between the initialization control signal sd and the data d. Form product signal and output. The static latch composed of the NAND gate circuit NAND and the inverter INV4 inputs the output signal of the inverter INV5D at the high level of the latch enable control signal e, and latches the input signal at the low level of the latch enable control signal e. Therefore, in response to the reset instruction, the initialization control signal sd = H and the latch enable control signal e = H are set to initialize the logical value 0 in the static latch. Since the initialization control signal sd = L is fixed after the reset instruction is released, the static latch is set on condition that the write latch enable control signal e = H is set in response to the write command to the control register 40. Can be rewritten to a value corresponding to the logical value of the data d.

  FIG. 5 illustrates a logic circuit diagram of the set latch circuit SL. The set latch circuit SL includes a two-input NOR gate circuit NOR, an inverter INV1 connected in antiparallel to the NOR gate circuit NOR to form a static latch, an output inverter INV3, and logic matching inverters INV2A to INV2E. The inverter INV2E is activated by the high level of the latch enable control signal e (output operable state) and deactivated by the low level (output high impedance state), and when it is activated, the NOR gate circuit NOR is initialized. An exclusive OR signal of the control signal sd and the data d is formed and output. The static latch composed of the NOR gate circuit NOR and the inverter INV1 inputs the output of the inverter INV2E at the high level of the latch enable control signal e, and latches the input signal at the low level of the latch enable control signal e. Therefore, in response to the reset instruction, the initialization control signal sd = H and the latch enable control signal e = H are set to initialize the logical value 1 to the static latch. Since the initialization control signal sd = L is fixed after the reset instruction is released, the static latch is set on condition that the write latch enable control signal e = H is set in response to the write command to the control register 40. Can be rewritten to a value corresponding to the logical value of the data d.

  FIG. 6 illustrates a circuit for realizing the logic of FIG. 4 of the reset latch RSL. The reset latch RSL includes n-channel MOS transistors MN1 to MN9 and MN11 and p-channel MOS transistors MP1 to MP9 and MP11.

  FIG. 7 illustrates a circuit for realizing the logic of FIG. 5 of the set latch SL. The set latch SL includes n-channel MOS transistors MN1 to MN11 and p-channel MOS transistors MP1 to MP11. The n-channel MOS transistor MN10 used to configure the inverter INV2A in FIG. 7 is not used because its gate, source, and drain are commonly connected to the circuit ground terminal GND. Similarly, the p-channel MOS transistor MP10 used to configure the inverter INV2A in FIG. 7 is not used because its gate, source, and drain are commonly connected to the power supply terminal VDD.

《Set latch and reset latch layout pattern》
FIG. 8 illustrates a layout pattern of the reset latch RSL of FIG. Although not particularly limited, the n-channel MOS transistor is formed on a p-type semiconductor substrate, and the p-channel MOS transistor is formed in an n-type well region NWELL in the p-type semiconductor substrate. In FIG. 8, a region (pattern) surrounded by a thick broken line represented by AR1 is a semiconductor region such as a diffusion region for constituting a source / drain of a MOS transistor. A region (pattern) subjected to two types of hatching represented by AR2 is a gate wiring. A hatched region (pattern) represented by AR3 is a first-layer metal wiring. The second-layer metal wiring formed on the first-layer metal wiring and the third-layer metal wiring formed thereon are not shown. The intra-cell wiring in the reset latch circuit RSL is performed using the first layer metal wiring. The inter-cell wiring that connects the reset latch circuit RSL to the outside is performed using the second-layer metal wiring and the third-layer metal wiring. A rectangular region represented by AR4 means a through hole or a via for connecting the upper and lower conductive layers.

  FIG. 9 illustrates a layout pattern of the set latch SL of FIG. The only difference from FIG. 8 is the pattern of the metal wiring in the first layer that is hatched from the upper right to the lower left, represented by AR3, the semiconductor region surrounded by the thick broken line represented by AR1, and AR2 The hatched gate wiring pattern represented by (2) is the same as FIG. That is, the set latch SL and the reset latch RSL latch have the same wiring pattern (AR1, AR2) of the semiconductor region formed on the semiconductor substrate and one wiring layer connected to the semiconductor region and the gate wiring. The pattern (AR3) has a different relationship. FIG. 10 shows a common pattern of a semiconductor region represented by AR1 common to the set latch SL and the reset latch RSL and a gate wiring represented by AR2. FIG. 11 shows a first-layer metal wiring pattern represented by AR3 for the reset latch RSL. FIG. 12 shows a first-layer metal wiring pattern represented by AR3 for the set latch SL. As a result, the photomask pattern that defines the semiconductor region represented by AR1 and the photomask pattern that defines the gate wiring represented by AR2 used when manufacturing the liquid crystal drive control device are stored in the control register 40. It may be the same regardless of the initial value to be set. In short, in order to determine the arrangement of the set latch SL and the reset latch RSL in the register to determine the initial value of the control register 40, only the pattern of the photomask for manufacturing the pattern AR3 of the first metal wiring layer is required. It is enough to change.

  By adopting the set latch SL and the reset latch RSL, an EEPROM is not required for the initial setting of the control data for the control register 40, and a selector that receives the output of the register 40 and an aluminum that can be selected by the selector. No master cell is required. Although not specifically illustrated, if initial setting data of a plurality of control registers 40 are stored in the EEPROM, the host interface circuit 11 in the liquid crystal drive control device 3 of FIG. 1 must have an interface circuit connected to the EEPROM. Don't be. For specifications in which such initial setting must be performed by the liquid crystal drive control device 3 itself, the host interface circuit 11 itself must have a memory control function for the EEPROM. Even if the EEPROM is a serial memory, control logic and external terminals are required for this purpose, and not only the initial setting EEPROM must be mounted on the liquid crystal panel, but also the liquid crystal drive controller itself has a memory control function for the EEPROM. There must be. When the set latch SL and the reset latch RSL are not employed for the registers, as illustrated in FIG. 13, an array of selectors SLCT and an array of aluminum master cells AMCL must be arranged at the output of the register IREG. Aluminum master cell AMCL fixes one input of selector SLCT to ground voltage GND of logical value 0 or power supply voltage VDD of logical value 1 by a single layer of aluminum wiring. The selector SLCT selects the output of the aluminum master cell AMCL in response to the enable of the fixed selection signal FSEL. The selector SLCT requires 2.5 gates, the aluminum master cell AMCL requires 0.5 gates, and considering that the number of registers IREG corresponding to the register 40 reaches several thousand, a chip composed of the selector SLCT and the aluminum master cell AMCL. The increase in occupied area cannot be ignored. One gate means, for example, a CMOS basic gate. By adopting the set latch SL and the reset latch RSL in the large-scale register circuit 12 that requires initial setting, an increase in the chip occupation area can be significantly suppressed.

  In addition, by employing the set latch SL and the reset latch RSL, the initial value of the control data can be easily determined simply by changing the mask pattern of the one wiring layer forming the pattern AR3. For example, as illustrated in FIG. 14, when a sample LSI of the liquid crystal drive control device 3 is prototyped and submitted to a liquid crystal panel manufacturer (S1), the liquid crystal panel manufacturer incorporates the sample LSI into the liquid crystal panel. The panel is adjusted (S2), and γ adjustment data for the liquid crystal panel is generated (S3). During this period, the LSI manufacturer that provided the sample LSI manufactures a base wafer for the LSI that realizes the semiconductor drive control device, and forms the lowermost metal wiring layer as the one-layer wiring layer that forms the pattern AR3. A photomask for the wiring layer above M1 is manufactured in advance (S7). This is because it is only the pattern of the lowermost metal wiring layer M1 that determines whether each bit of the register 40 is the set latch SL or the reset latch RSL. When the LSI manufacturer receives the γ adjustment data, the photomask for the wiring pattern of the lowermost metal wiring layer M1 is revised accordingly (S5), and the revised photomask, Using the prepared photomask, LSI is mass-produced (S5), and the manufactured LSI is shipped (S6).

  Therefore, a nonvolatile memory for initial setting is not required, the chip area of the liquid crystal drive control device 3 is not significantly increased, and the time from the receipt of the γ adjustment data to the shipment of the liquid crystal drive control device. Can be kept short. The set latch SL and the reset latch RSL can be arbitrarily rewritten after the initial setting of a large number of control registers 40, and the control data can be changed after the initial setting.

《Gradation voltage generation circuit and γ adjustment》
Here, the gradation voltage generation function by the gradation voltage generation circuit 20 using γ adjustment data will be described as an example of use of the control data set in the control register 40.

  First, general gamma characteristics will be described with reference to FIG. FIG. 15A shows the applied voltage-luminance characteristics when the mode of the liquid crystal panel is a normally black mode. The luminance is low at a low applied voltage and high at a high applied voltage. A feature is that the luminance change with respect to the applied voltage becomes dull (saturated) in the low applied voltage region and the high applied voltage region. In addition to the normally black mode liquid crystal panel, there is a normally white mode liquid crystal panel. Hereinafter, a description will be given of a normally black mode liquid crystal panel. The present invention can be applied regardless of the mode of the liquid crystal panel.

FIG. 15B shows gradation number-luminance characteristics. Usually, this characteristic is called a gamma characteristic. Here, reference numeral 101 in FIG. 15B indicates a characteristic in which the luminance increases linearly as the gradation number increases, and this characteristic is referred to as a characteristic of γ = 1.0. Here, this γ value is expressed by the following equation (1) (tone number) ^γ = luminance [cd / m ² ] (1)
The following relational expression holds. The gradation number simply means an identification number assigned to a plurality of gradation voltages.

  From the above equation (1), 102 and 103 in FIG. 15B show the characteristics of γ = 2.2 and γ = 3.0, respectively. Here, conventionally, when display data is displayed on the liquid crystal panel, the characteristic that the displayed image feels the highest image quality to the human eye is generally when γ = 2.2 in 102 above.

  In the liquid crystal drive control device, the gamma characteristic is adjusted by adjusting the applied voltage for each gradation number. FIG. 15C is a relationship diagram of the gradation number-applied voltage described above, in which the number of gradations is 64 gradations. The applied voltage-luminance characteristics shown in FIG. 15 are different for each liquid crystal panel. For example, when the applied voltage is adjusted to γ = 2.2, the adjustment value of the applied voltage differs for each liquid crystal panel. Reference numeral 104 in FIG. 15C is a relationship diagram of gradation number-applied voltage when γ = 2.2. Reference numerals 105 and 106 are gradation number-applied voltage relationship diagrams when γ = 2.2 in a liquid crystal panel different from 104. The gradation voltage generation circuit 20 can adjust the gradation voltage to a desired gamma characteristic according to the characteristics of each liquid crystal panel.

  FIG. 16 shows a specific example of the gradation voltage generation circuit 20 that receives the γ adjustment data as an example of use of the control data set in the control register.

  FIG. 16 representatively shows three registers (REG_1 to REG_3) 40_1 to 40_3 that hold γ adjustment data for adjusting the gamma characteristic of the display as the control register 40 of the control register circuit 12. The register 40_1 is an amplitude adjustment register (AMPLTD), the register 40_2 is a slope adjustment register (GRDENT), and the register 40_3 is a fine adjustment register (FINTUN).

  The gradation voltage generation circuit 20 includes a ladder resistor circuit 50 that generates each gradation voltage from between the reference voltage VREF supplied from the outside and the ground voltage GND. The ladder resistor circuit 50 includes variable resistors 51 to 54 and resistor voltage dividing circuits 56 to 61 for further dividing the voltage divided by the variable resistors. A plurality of divided voltages generated by the resistor voltage dividing circuits 56 to 61 are selected by the corresponding selector circuits 66 to 71, respectively. The output voltage selected by each selector circuit, the voltage at the coupling node between the variable resistor 51 and the resistance voltage dividing circuit 56, and the voltage at the coupling node between the variable resistor 54 and the resistance voltage dividing circuit 61 are buffer amplifiers 75 to 82. Is input. An output ladder resistor circuit 90 is disposed at the voltage output terminals of the buffer amplifiers 75 to 82. The output ladder resistor circuit 90 forms, for example, gradation voltages for 64 gradations by a series circuit of resistors 91 and 92 and resistance voltage dividing circuits 93 to 97. The generated gradation voltage is supplied to the source driver 19. The source driver 19 selects a step voltage corresponding to the display data DAT_DISP supplied from the display memory 17 from the plurality of gradation voltages, and outputs drive signals S1 to Sn in units of pixels on the scanning line.

  Here, the lower variable resistor 54 installed on the lower side of the ladder resistor 50 is configured such that its resistance value can be set by the lower variable resistor setting value 110 of the amplitude adjustment register 40_1. The upper variable resistor 51 installed on the upper side of the ladder resistor 50 is configured such that its resistance value can be set by the upper variable resistor setting value 111 of the amplitude adjustment register 40_1. The voltage divided by the variable resistors 54 and 51 is used as the gradation voltage at both ends of the gradation number, and the amplitude of the gradation voltage can be adjusted according to the value of the amplitude adjustment register 40_1. FIG. 17A shows the gradation number-gradation voltage characteristics in each case where the variable resistance values at both ends of the ladder resistor 50 are set by the amplitude adjustment register 40_1. Here, 201 is a case where the voltage value on the lower side of the gradation voltage is not changed but the voltage value on the higher side is changed to adjust the amplitude voltage of the gradation voltage, and 202 is the higher side of the gradation voltage. FIG. 6 is a characteristic diagram when the amplitude value of the gradation voltage is adjusted by changing the voltage value on the lower side without changing the voltage value of. Reference numerals 201 and 202 denote cases where the variable resistance values at both ends of the ladder resistor are set only on one side (reference voltage side or GND side) by the amplitude adjustment register. Reference numeral 203 is a characteristic diagram when variable resistance values at both ends of the ladder resistor are simultaneously set by the amplitude adjustment register. In this case, the same effect as the offset adjustment performed in the amplifier circuit in the prior art can be obtained.

  The intermediate lower variable resistor 53 installed at the lower stage of the ladder resistor 50 is configured such that its resistance value can be set by the intermediate lower variable resistance setting value 120 of the inclination adjustment register 40_2. The middle part upper variable resistor 52 installed on the middle part upper side of the ladder resistor 50 is configured such that its resistance value can be set by the middle part upper variable resistance setting value 121 of the inclination adjustment register 40-2. The voltage divided by the two variable resistors 53 and 52 is used as the voltage of the gradation number that determines the gradient characteristic of the halftone portion, and the gradient characteristic of the voltage can be set according to the value of the gradient adjustment register 40_2. Reference numeral 204 in FIG. 17B is a characteristic diagram when the slope characteristic of the intermediate (halftone) portion of the gradation number of the gradation number-gradation voltage characteristic is adjusted. In the figure, reference numerals 205 and 206 denote voltages at portions where the slope is changed.

  The configuration of the ladder resistor 50 as described above is adopted, and the resistance division ratio is changed by setting the value of the variable resistor arranged in the ladder resistor 50 by the amplitude adjustment register 40_1 and the inclination adjustment register 40_2, and the voltage It becomes possible to adjust the amplitude voltage and the slope characteristic of the halftone portion. Thereby, it is possible to easily adjust a desired gamma characteristic in accordance with the characteristics of each liquid crystal panel, and to shorten the adjustment time.

  Further, the resistance dividing circuits 56 to 61 further finely divide the voltages generated by the variable resistance values respectively set by the amplitude adjustment register 40_1 and the inclination adjustment register 40_2, thereby finely adjusting the voltage. A fine adjustment voltage is generated. The fine adjustment voltage is selected by the selector circuits 66 to 71 according to the set value 130 of the fine adjustment register 40_3. Reference numeral 207 in FIG. 17C is a gradation number-gradation voltage characteristic diagram when each voltage is finely adjusted. With this configuration, even when one variable resistance value is changed, each voltage divided by this variable resistor is further divided into resistors, and a desired voltage value is selected from among them. Only a desired voltage can be adjusted without changing the voltage so much. In addition, by enabling fine adjustment of each voltage as described above, it is possible to improve the adjustment accuracy of the gamma characteristic and improve the degree of freedom of adjustment, and high image quality can be expected.

  Each voltage generated from the above is buffered by the buffer amplifiers 75 to 82 in the subsequent stage, and in order to generate a desired 64 gradation voltage, the output ladder resistor 90 makes the voltage relationship linear between the voltages. The resistance is divided so that gradation voltages for 64 gradations are generated. The gradation voltage of 64 gradations generated by the gradation voltage generation circuit 20 is supplied to the driver 19, and the gradation voltage according to the display data is output as an applied voltage from the terminals S1 to Sn to the liquid crystal panel.

  With the circuit configuration as described above, in the adjustment of the gamma characteristic, a ladder that can adjust rough gradation voltages such as the amplitude voltage of the gradation voltage and the inclination characteristic of the halftone part by setting the amplitude register 40_1 and the inclination register 40_2. Gamma characteristics can be easily adjusted and the adjustment time can be shortened by including a resistor 50 and making it possible to finely adjust each voltage from the voltage generated by the ladder resistor by setting the fine adjustment register 40_3. The accuracy and freedom of adjustment can be improved. As a result, it is possible to easily improve the image quality of the image display, to reduce the circuit scale of the gradation voltage generation circuit that can be expected to be versatile, and to realize the cost reduction of the liquid crystal drive control device formed as a semiconductor integrated circuit. Can do.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although all of the control registers 40 of the control register circuit 12 may be formed by the set latch SL and the reset latch RSL, data having a property that the initial setting value is not uniquely determined only by the system configuration is initialized. For the control register of this section, a simple static latch type circuit configuration in which an initial value is determined by data transfer may be employed. Even in such a case, the overall initial setting operation time can be shortened, and the host system can be burdened with the elbow and transfer control of the initial setting data. The use example of the control data set in the control register is not limited to the generation of the gradation voltage using the γ adjustment data. The set latch and the reset latch can be used for storing various initial setting data such as initial setting data corresponding to the panel size. The semiconductor device is not limited to the liquid crystal drive control device, but includes a semiconductor device including a circuit having an analog characteristic problem such as an A / D conversion circuit, a D / A conversion circuit, an amplifier, a filter, a mounted system, and another circuit. The present invention can be widely applied to semiconductor devices and the like in which initial setting data is determined according to the relationship.

FIG. 1 is a block diagram showing an example of a liquid crystal drive control device. FIG. 2 is a block diagram illustrating an example of a liquid crystal display system. FIG. 3 is a block diagram showing an example of a control register provided in the control register circuit. FIG. 4 is a logic circuit diagram showing an example of the reset latch circuit SL. FIG. 5 is a logic circuit diagram showing an example of the set latch circuit SL. FIG. 6 is an example circuit diagram for realizing the logic of FIG. 4 of the reset latch RSL. FIG. 7 is an example circuit diagram for realizing the logic of FIG. 5 of the set latch SL. FIG. 8 is a plan view illustrating a layout pattern of the reset latch RSL of FIG. FIG. 9 is a plan view illustrating a layout pattern of the set latch SL of FIG. FIG. 10 is a plan view illustrating a common pattern of a semiconductor region represented by AR1 common to the set latch SL and the reset latch RSL and a gate wiring represented by AR2. FIG. 11 is a plan view illustrating a first-layer metal wiring pattern R3 represented by AR3 for the reset latch RSL. FIG. 12 is a plan view illustrating a first-layer metal wiring pattern represented by AR3 for the set latch SL. FIG. 13 is a logic circuit diagram showing a comparative example employing a selector that receives the output of a register and an aluminum master cell that can be selected by the selector. FIG. 14 is a flowchart showing a schematic manufacturing process of the liquid crystal drive control device when the set latch SL and the reset latch RSL are employed in the control register. FIG. 15 is an explanatory diagram of a general γ characteristic. FIG. 16 is a block diagram showing a specific example of a gradation voltage generation circuit that receives γ adjustment data as an example of use of control data set in the control register. FIG. 17 is an explanatory diagram illustrating the significance of the gradation voltage characteristic adjustment by the γ adjustment data.

Explanation of symbols

3 Liquid Crystal Drive Control Device 6 Accelerator Tacc Host Interface Terminal 5 Processor Tprc Host Interface Terminal 11 Host Interface Circuit (HIF)
12 Control register circuit (CREG)
13 Index circuit (IDX)
15 Address counter (ACUNT)
17 Display memory (GRAM)
18 Timing control circuit (TGNR)
19 Source driver (SOCDRV)
20 Gradation voltage generator (TWVG)
26 gradation voltage S1 to Sn signal terminal 22 gate driver (GTDRV)
G1 to Gm Scan terminal 40 Control register sd Initialization control signal RES Reset signal RES
e Latch enable control signal d Input data AR1 Pattern of semiconductor region such as diffusion region AR2 Gate wiring pattern AR3 First layer metal wiring pattern 40_1 Amplitude adjustment register (AMPLTD)
40_2 Inclination adjustment register (GRDENT)
40_3 Fine adjustment register (FINTUN)
DESCRIPTION OF SYMBOLS 50 Ladder resistance circuit 51-54 Variable resistance 56-61 Resistance voltage dividing circuit 66-71 Selector circuit 75-82 Buffer amplifier 90 Output ladder resistance circuit 91, 92 Resistance 93-97 Resistance voltage dividing circuit

Claims (13)

A semiconductor device having a circuit and a register in which control data for adjusting the circuit is stored,
A first latch circuit for latching a logical value of 1 in response to a first state of an initialization control signal and a first state of a latch enable control signal corresponding to the control data to be initialized; An array with a second latch circuit that latches a logical value of 0;
The first latch circuit and the second latch circuit have the same pattern of a semiconductor layer and a gate wiring formed on a semiconductor substrate, and different patterns of one wiring layer connected to the semiconductor region and the gate wiring. A semiconductor device.   The semiconductor device according to claim 1, wherein the initialization control signal is set to a first state in response to a reset instruction level by a reset signal to the semiconductor device, and is set to a second state in response to reset release by the reset signal.   The first latch circuit and the second latch circuit are configured to detect a signal supplied to the data input terminal in response to the initialization control signal being set to the second state and the latch enable control signal being set to the first state. The semiconductor device according to claim 2, wherein a value corresponding to a logical value is latched. A semiconductor device that generates a gradation voltage, selects a voltage corresponding to display data from the generated gradation voltage, and outputs a display drive signal of the display,
A register for storing control data for generating the gradation voltage in accordance with the characteristics of the display;
A first latch circuit for latching a logical value of 1 in response to a first state of an initialization control signal and a first state of a latch enable control signal corresponding to the control data to be initialized; An array with a second latch circuit that latches a logical value of 0;
The first latch circuit and the second latch circuit have the same pattern of a semiconductor layer and a gate wiring formed on a semiconductor substrate, and different patterns of one wiring layer connected to the semiconductor region and the gate wiring. A semiconductor device.   The semiconductor device according to claim 4, wherein the latch is connected to the outside of the register through a wiring of a wiring layer formed in an upper layer of the one wiring layer.   The semiconductor device according to claim 4, wherein the initialization control signal is set to a first state in response to a reset instruction level by a reset signal to the semiconductor device, and is set to a second state in response to reset release by the reset signal.   The first latch circuit and the second latch circuit are configured to detect a signal supplied to the data input terminal in response to the initialization control signal being set to the second state and the latch enable control signal being set to the first state. The semiconductor device according to claim 6, wherein a value corresponding to a logical value is latched.   8. The semiconductor device according to claim 7, further comprising a system interface for receiving a command and data from outside, wherein the system interface controls the latch enable control signal to a first state for a predetermined period in response to a write command to the register. One of the first latch circuit and the second latch circuit has a data input terminal and a terminal to which the initialization control signal is input, and is activated by the first state of the latch enable control signal. A two-input NOR gate circuit deactivated by the second state, and an input signal connected to the output of the two-input NOR gate circuit and receiving the output signal of the two-input NOR gate circuit in the first state of the latch enable control signal In the second state of the latch enable control signal, and the other latch circuit has a data input terminal and a terminal to which an inverted signal of the initialization control signal is input. A two-input NAND gate circuit activated by a first state of a signal and inactivated by a second state; and the two-input NAND gate Is connected to the output of road inputs an output signal of the two-input NAND gate circuit in a first state of the latch enable control signal, having a static latch for latching the input signal in a second state of the latch enable control signal, wherein Item 8. A semiconductor device according to Item 7. The semiconductor device according to claim 4, wherein the control data is γ adjustment data for generating a drive signal in accordance with a γ characteristic of the display. A first resistance voltage dividing circuit for resistance-dividing the reference voltage;
A selection circuit that selects a voltage to be used for generating a gradation voltage from a plurality of voltages divided by the first resistance voltage dividing circuit in units of a plurality of increments;
A second resistance voltage dividing circuit for generating a gradation voltage based on a plurality of voltages selected by the selection circuit;
A first variable resistor located between the first resistor voltage divider circuit and the reference voltage;
A second variable resistor positioned between the first resistor voltage divider circuit and the ground;
11. The semiconductor device according to claim 10, wherein the control data initially set in the register adjusts the amplitude of the gradation voltage by determining resistance values of the first variable resistor and the second variable resistor. A third variable resistor disposed in the middle of the first resistance voltage dividing circuit;
Said register initially set the control data further, before Symbol gradation number by determining the resistance value of the third variable - resistance - adjusting the inclination of the central area of the gradation voltage characteristic, a semiconductor according to claim 11 apparatus.   13. The semiconductor device according to claim 12, wherein the control data initialized in the register further finely adjusts the gradation voltage by determining a selection voltage by the selection circuit.

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