JP5120418B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device constituting an integrated circuit having a high potential portion and a low potential portion.

Conventionally, in an integrated circuit used as a high-voltage driver for control driving such as a power supply device, a layout in which a high potential portion and a low potential portion are separated is employed. As the separation structure of the high potential portion and the low potential portion, those using a pn junction (junction separation structure) and those using a dielectric such as SiO ₂ (dielectric separation structure) are generally used.

  In the junction isolation structure, for example, a wafer having a configuration in which a low-concentration n-type epitaxial layer is stacked on the surface of a p-type semiconductor substrate is used. An island of the n-type semiconductor layer is three-dimensionally formed by a pn junction formed by forming a deep p-type semiconductor layer by diffusion in the n-type epitaxial layer. A driver circuit composed of a CMOS circuit is built in. A reverse bias voltage is applied between the island of the n-type semiconductor layer and the p-type semiconductor substrate, and the island of the n-type semiconductor layer is electrically isolated by the junction capacitance, thereby realizing a high breakdown voltage.

  In the junction isolation structure, when a reverse bias voltage is applied between the separated n-type semiconductor region and the p-type semiconductor substrate, the parallel plate junction corresponding to the bottom of the planar junction is depleted in parallel to the substrate surface. Although the layer spreads, the depletion layer is generally difficult to spread at the end of the n-type semiconductor region, and the electric field tends to concentrate. In order to alleviate this electric field concentration, a RESURF (Reduced SURface electric field) structure or a double RESURF structure is used.

In the RESURF structure, the concentration of the separated n-type semiconductor region is set to be low so that the end portion is easily depleted. In the double RESURF structure, a low-concentration p ⁻ semiconductor region is added to the surface of the end portion of the separated n-type semiconductor region, and the p ⁻ semiconductor region and the p ⁻ semiconductor substrate on the surface side of the end portion of the n-type semiconductor region are added. The depletion layer spreads from both interfaces. Note that in this specification and the accompanying drawings, a layer or region with n or p is a sign that electrons or holes are carriers. Further, ⁺ or ⁻ attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively.

On the other hand, in the dielectric isolation structure, for example, a circuit is fabricated in a silicon region electrically isolated by SiO ₂ selectively formed on a silicon substrate. High breakdown voltage is realized by operating the circuit with different reference potentials for each separated silicon region. Also, in the junction isolation structure, an isolation structure that is regarded as a kind of self-isolation structure is known in which a normal silicon wafer is used instead of the epitaxial wafer as described above, and the junction isolation is performed only by planar bonding (for example, , See Patent Document 1). Also, an isolation structure combining a junction isolation structure and a trench isolation structure is known (see, for example, Patent Document 2, Patent Document 3, Patent Document 4, and Patent Document 5).

The structure and operation of an integrated circuit having a conventional double RESURF structure will be described below. FIG. 15 is a plan view showing a configuration of a high voltage driver composed of an integrated circuit having a conventional double RESURF structure. As shown in FIG. 15, in the high voltage IC chip 90, floating potential reference circuit forming regions 901a, 901b and 901c for the upper arms of the U phase, V phase and W phase and a GND reference circuit forming region 902 are formed. Has been. The GND reference circuit formation region 902 uses the ground potential GND as a reference potential. The floating potential reference circuit formation regions 901a, 901b, and 901c have potentials different from the ground potential GND (V _UL , V _VL , and V _WL described later) as reference potentials. Each floating potential reference circuit formation region 901a, 901b, 901c is surrounded by high voltage junction termination structures 903a, 903b, 903c, respectively.

FIG. 16 is a cross-sectional view showing a configuration at section line CC ′ across U-phase floating potential reference circuit formation region 901a and GND reference circuit formation region 902 in FIG. FIG. 17 is a cross-sectional view showing a configuration taken along section line DD ′ across U-phase and V-phase floating potential reference circuit forming regions 901a and 901b in FIG. As shown in FIG. 16, an n semiconductor region 92a to be a floating potential reference circuit formation region 901a and an n semiconductor region 702 to be a GND reference circuit formation region 902 are formed on the surface layer of a p ⁻ semiconductor substrate 910 apart from each other. Has been. The high breakdown voltage junction termination structure 903 a is formed in the n semiconductor region 98 a that is in contact with the n semiconductor region 92 a and is separated from the n semiconductor region 702.

In addition, as shown in FIG. 17, an n semiconductor region 92 a to be a U-phase floating potential reference circuit formation region 901 a and an n semiconductor region to be a V-phase floating potential reference circuit formation region 901 b are formed on the surface layer of the p ⁻ semiconductor substrate 910. The semiconductor region 92b is formed apart from the semiconductor region 92b. The U-phase and V-phase n semiconductor regions 92a and 92b are in contact with the n semiconductor regions 98a and 98b in which the high-breakdown-voltage junction termination structures 903a and 903b are formed, respectively. The U-phase n semiconductor region 98a and the V-phase n semiconductor region 98b are formed apart from each other, and may be formed at the same time in the same process as the n semiconductor regions 92a and 92b.

  In each of the n semiconductor regions 92a, 92b, and 702, various semiconductor elements for forming a control circuit are formed. In the illustrated example, one P-channel MOS (metal-oxide-semiconductor) transistor and one N-channel MOS transistor are formed. Each N channel MOS transistor is formed in p semiconductor regions 93a, 93b, 703 in each n semiconductor region 92a, 92b, 702. Hereinafter, the P-channel MOS transistor is a P-MOS, and the N-channel MOS transistor is an N-MOS.

The potential of the p ⁻ semiconductor substrate 910 becomes the ground potential GND. The potential of the n semiconductor region 702 in the GND reference circuit formation region 902 becomes the power supply potential _{Vcc of the} lower arm (not shown). The potential of the p semiconductor region 703 in the n semiconductor region 702 becomes the ground potential GND that is the reference potential of the GND reference circuit formation region 902. The power supply potential _Vcc of the lower arm with respect to the ground potential GND, that is, the power supply voltage of the lower arm is arbitrary, and is set to about 10 to 20 V, for example.

On the other hand, the potentials of the n semiconductor regions 92a and 92b in the floating potential reference circuit forming regions 901a and 901b become the power supply potentials V _UH and V _VH of the floating potential reference circuit. The potentials of the p semiconductor regions 93a and 93b in the n semiconductor regions 92a and 92b become the reference potentials V _UL and V _VL of the floating potential reference circuit. The power supply voltage of the upper arm is given by the potential difference ([V _UH −V _UL ], [V _VH −V _VL ]) between the power supply potentials V _UH and V _VH of the floating potential reference circuit and the reference potentials V _UL and V _VL. , And is set to about 10 to 20 V, for example.

A p ⁻ semiconductor region is provided in the surface layer of the n semiconductor regions 98a and 98b of the high breakdown voltage junction termination structures 903a and 903b. The potential of the p ⁻ semiconductor region is the ground potential GND. Note that the cross-sectional configuration across the V-phase or W-phase floating potential reference circuit formation regions 901b and 901c and the GND reference circuit formation region 902 is the same as that in FIG. Further, the cross-sectional configuration across the V-phase and W-phase floating potential reference circuit forming regions 901b and 901c is the same as that in FIG.

The wiring to which the reference potential V _{UL of the} U-phase floating potential reference circuit is applied includes the emitter of the U-phase upper arm IGBT (insulated gate bipolar transistor) (not shown) driven by the high voltage driver and the collector of the lower arm IGBT. Connected to the connection node. Therefore, the reference potential V _UL varies greatly depending on switching of the IGBTs of the upper and lower arms, for example, about 0 to 600 V in the 600 V specification and about 0 to 1200 V in the 1200 V specification. The same applies to the V-phase and the W-phase, and the reference potentials V _VL and V _WL of the floating-phase reference circuit for the V-phase and the W-phase fluctuate greatly according to the switching of the IGBTs of the upper and lower arms of the V-phase and the W-phase, respectively. To do. The rate of change dV / dt of these reference potentials V _UL , V _VL , V _WL may reach about 10,000 to 20000 V / μs.

Incidentally, each of the pn junctions formed in the above-described integrated circuit has a junction capacitance. That is, it is the same as that a capacitor is formed at each pn junction. When the capacitance value of one capacitor is C, when a voltage with a steep change (dV / dt) waveform is applied to the capacitor, the charging current (displacement) represented by [C × (dV / dt)] Current) flows over the entire junction surface of the pn junction. As a result, as shown in FIGS. 16 and 17, a parasitic transistor 911 made of p semiconductor region 93a, n semiconductor region 92a and p ⁻ semiconductor substrate 910, n semiconductor region 92a, p ⁻ semiconductor substrate 910 and n semiconductor region 702 The parasitic transistor 912 and the parasitic transistor 913 including the n semiconductor region 92a, the p ⁻ semiconductor substrate 910, and the n semiconductor region 92b may be operated to cause malfunction of the circuit and element destruction.

18 and 19 are cross-sectional views showing latch-up currents flowing in the cross-sectional configurations shown in FIGS. 16 and 17, respectively. As shown in FIGS. 18 and 19, in the case of the conventional self-isolation structure, a latch-up current 915 by a parasitic thyristor including a p semiconductor region 93a, an n semiconductor region 92a, a p ⁻ semiconductor substrate 910, and an n semiconductor region 702, , A latch-up current 916 by a parasitic thyristor including the p semiconductor region 93a, the n semiconductor region 92a, the p ⁻ semiconductor substrate 910, and the n semiconductor region 92b may flow. The same applies to the V phase and the W phase.

  Therefore, in order to prevent a latch-up current from flowing, an integrated circuit in which a deep guard ring 917 is formed by ion implantation and thermal diffusion around a diffusion layer in which an element is formed is known as shown in FIG. . However, when the guard ring 917 is formed, the diffusion layer also spreads in the lateral direction, so it is necessary to widen the interval between the diffusion layers in which the elements are formed. This is not preferable because it increases the chip size. Note that FIG. 20 illustrates a configuration in a cross section corresponding to the cutting line C-C ′ of FIG. 15.

  On the other hand, the dielectric isolation structure has an advantage that the parasitic operation as described above does not occur because there is no parasitic thyristor or parasitic transistor, but there is a disadvantage that the manufacturing cost of the wafer is high. Moreover, the structure combining the junction isolation structure and the trench isolation structure disclosed in Patent Documents 2 to 5 requires 600-1200 V class isolation between the high potential portion and the low potential portion on one chip. It cannot be applied to high voltage ICs. Therefore, the present inventors have previously proposed a semiconductor device in which the operation of a parasitic element of a high breakdown voltage IC is suppressed using a trench isolation structure (see, for example, Patent Document 6).

FIG. 21 is a cross-sectional view for explaining the configuration of the semiconductor device disclosed in Patent Document 6. In FIG. As shown in FIG. 21, instead of the guard ring 917 of FIG. 20, a trench structure 918 deeper than the diffusion layer is formed around the diffusion layer where the element is formed. In the trench structure 918, an electrode 919 having a ground potential GND is provided. A p ⁺ semiconductor region 920 is provided along the trench wall. With such a configuration, it is possible to suppress the operation of the parasitic element while suppressing an increase in the chip area.

JP-A-9-55498 Japanese Patent Laid-Open No. 57-143843 JP-A-60-97661 JP-A-8-148553 JP 2001-135719 A US Patent Application Publication No. 2002/0195659

However, the trench isolation structure shown in FIG. 21 has the following problems. That is, in order to bring the characteristics (breakdown voltage, threshold value, etc.) of the MOS transistor formed in the n semiconductor region 92a of the floating potential reference circuit formation region 901a to a desired level, the concentration of the n semiconductor region 92a may be made too high. Can not. The same applies to the n semiconductor region 702 in the GND reference circuit formation region 902. For example, the concentrations of the n semiconductor region 92a and the n semiconductor region 702 are 1 × 10 ¹⁷ / cm ³ or less. In order to prevent electric field concentration at the high voltage junction terminating structure 903a, p ^- semiconductor concentration of the substrate 910 also can not be too high, for example, the specific resistance of 1200V products about 200Omucm (in the impurity concentration of 6 × 10 ¹³ / Cm ³ ).

  In the case of such a concentration, when a particularly high dV / dt is applied to the floating potential reference circuit in a high temperature environment, the parasitic element may be operated. In order to prevent this, it is necessary to form the n semiconductor region 92a and the n semiconductor region 702 to a depth of, for example, 20 μm or more. However, when the n semiconductor regions 92a and 702 are deepened, the trench structure 918 has to be deepened correspondingly, so that there is a problem that an advanced manufacturing technique is required.

  An object of the present invention is to provide a semiconductor device excellent in manufacturability that can be used as a high breakdown voltage driver that is less prone to malfunction and element destruction in order to eliminate the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the invention of claim 1 includes a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer stacked on the semiconductor substrate, An element isolation region having a trench structure that penetrates the semiconductor layer from the surface of the second conductivity type semiconductor layer and reaches the semiconductor substrate, and the second conductivity type semiconductor layer are separated from each other by the element isolation region. The second conductivity type first semiconductor region and the second conductivity type second semiconductor region, and the first conductivity type drain region and the first conductivity selectively provided in the first semiconductor region, respectively. A first conductivity type first insulated gate semiconductor element having a source region of a type; a first conductivity type third semiconductor region selectively provided on a surface layer of the first semiconductor region; Each in the third semiconductor region A second conductivity type second insulated gate semiconductor element having a drain region of a second conductivity type and a source region of a second conductivity type provided selectively, the first semiconductor region and the semiconductor A buried layer of the second conductivity type having a higher concentration than the first semiconductor region and the second semiconductor region, respectively, between the substrate and between the second semiconductor region and the semiconductor substrate; One of the first semiconductor region and the second semiconductor region is a semiconductor region with a floating potential as a reference, and the other is a semiconductor region with a ground potential as a reference, and the trench structure has In the semiconductor device, a conductive film is provided therein, and the conductive film is connected to a ground point of the semiconductor region with the ground potential as a reference.

  According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the first conductive type drain region and the first conductive type source region are provided selectively in the second semiconductor region, respectively. A third insulated gate semiconductor element of the first conductivity type, a fourth semiconductor region of the first conductivity type selectively provided on a surface layer of the second semiconductor region, and the fourth semiconductor region And a second conductive type fourth insulated gate semiconductor element having a second conductive type drain region and a second conductive type source region, each of which is selectively provided.

  According to the first or second aspect of the present invention, the first conductive type third semiconductor region is used as the emitter, the second conductive type first semiconductor region and the second conductive type buried layer are used as a base, and the first conductive type is used. Since the base concentration of the parasitic transistor using the conductive semiconductor substrate as the collector can be increased, the operation of the parasitic transistor or the parasitic thyristor can be suppressed.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect of the present invention, the conductive film is made of first conductivity type polysilicon doped at a high concentration. To do.

  According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first or second aspect of the present invention, wherein the semiconductor region of the first semiconductor region and the second semiconductor region is based on the floating potential. A high-voltage junction termination structure is provided in contact with the trench structure around the periphery.

  According to a fifth aspect of the present invention, in the semiconductor device according to the first or second aspect, the first conductivity type semiconductor region having a higher concentration than the semiconductor substrate is provided at the bottom of the trench structure. It is characterized by being. According to the fifth aspect of the present invention, the first conductivity type semiconductor region having a higher concentration than the semiconductor substrate is provided at the bottom of the trench structure. The operation of the base parasitic transistor can be further suppressed.

  According to the semiconductor device of the present invention, a parasitic transistor or a parasitic thyristor that is parasitically formed in the semiconductor device without forming a deep trench that requires advanced manufacturing technology is a large-capacity power supply semiconductor such as an IGBT. It is possible to more effectively suppress a parasitic operation such as a bipolar operation or a latch-up operation due to a steep voltage change due to the switching operation. Therefore, there is an effect that it is possible to easily realize a high voltage driver that is unlikely to cause malfunctions and element destruction.

It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 1 of this invention. 1 is a plan view showing a configuration of a semiconductor device including an integrated circuit according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 6 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 7 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 8 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 9 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 10 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 11 of this invention. It is sectional drawing which shows the structure of the semiconductor device provided with the integrated circuit concerning Embodiment 12 of this invention. It is a top view which shows the structure of the integrated circuit which has the conventional double RESURF structure. FIG. 16 is a cross-sectional view showing a configuration taken along section line C-C ′ of FIG. 15. It is sectional drawing which shows the structure in the cutting line D-D 'of FIG. FIG. 17 is a cross-sectional view illustrating a latch-up current that flows in the cross-sectional configuration illustrated in FIG. 16. FIG. 18 is a cross-sectional view showing a latch-up current flowing in the cross-sectional configuration shown in FIG. 17. It is sectional drawing which shows the structure of the integrated circuit which has the conventional guard ring. It is sectional drawing which shows the structure of the integrated circuit which has the conventional trench isolation structure.

Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the following description and the accompanying drawings, a layer or region with n or p is a sign that electrons or holes are carriers. Further, ⁺ or ⁻ attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively. 1 to 14, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 2 is a plan view showing the configuration of the semiconductor device including the integrated circuit according to the first embodiment of the present invention. As shown in FIG. 2, the high voltage IC chip 10 is formed with floating potential reference circuit forming regions 21a, 21b, and 21c for the upper arms of the U phase, V phase, and W phase, and a GND reference circuit forming region 22. Has been. The floating potential reference circuit forming regions 21a, 21b, and 21c are surrounded by high-voltage junction termination structures 23a, 23b, and 23c, respectively. The high breakdown voltage junction termination structures 23a, 23b, 23c and the GND reference circuit formation region 22 are surrounded by a trench structure 7 serving as an element isolation region.

The GND reference circuit formation region 22 uses the ground potential GND as a reference potential. The floating potential reference circuit forming regions 21a, 21b, and 21c have potentials V _UL , V _VL , and V _WL that are different from the ground potential GND as reference potentials. In the high voltage driver composed of the high voltage IC chip 10, the high voltage junction termination structures 23a, 23b, and 23c can have a double RESURF structure.

  Next, the cross-sectional configuration of the integrated circuit shown in FIG. 2 will be described. The cross-sectional configuration along the cutting line AA ′ across the U-phase floating potential reference circuit formation region 21a and the GND reference circuit formation region 22, Since each of the W phases has the same configuration in the cross section corresponding to the cutting line AA ′, here, the cross section in the cutting line AA ′ with respect to the U phase on behalf of the U phase, the V phase, and the W phase. The configuration will be described, and description of the configuration in the cross section corresponding to the cutting line AA ′ for each of the V phase and the W phase will be omitted. In the following description, the reference numerals of the floating potential reference circuit forming regions 21a, 21b, and 21c are represented by 21, and the reference numerals of the high-voltage junction termination structures 23a, 23b, and 23c are represented by 23. These are the same in other embodiments.

FIG. 1 is a cross-sectional view showing a configuration at a cutting line AA ′ across a floating potential reference circuit formation region 21 and a GND reference circuit formation region 22 of a semiconductor device including an integrated circuit according to a first embodiment of the present invention. It is. As shown in FIG. 1, p ⁺ on the semiconductor substrate 1, p ⁺ p epitaxial layer 27 of low impurity concentration than the semiconductor substrate 1 are laminated. Then, on the surface layer of the p epitaxial layer 27, an n semiconductor region 2 as a first semiconductor region that becomes the floating potential reference circuit formation region 21 and an n semiconductor region as a second semiconductor region that becomes the GND reference circuit formation region 22. The semiconductor region 202 is formed apart from the semiconductor region 202.

The high breakdown voltage junction termination structure 23 is formed in the n semiconductor region 8 that surrounds the n semiconductor region 2 and is separated from the n semiconductor region 202. A trench structure 7 that reaches the p ⁺ semiconductor substrate 1 from the surface of the p epitaxial layer 27 through the p epitaxial layer 27 is formed so as to surround the periphery of the n semiconductor region 2 and the n semiconductor region 202. FIG. 1 shows only a portion between the n semiconductor region 2 and the n semiconductor region 202 in the trench structure 7 surrounding the n semiconductor region 2 and the n semiconductor region 202.

  Various semiconductor elements for forming a control circuit are formed in the n semiconductor region 2 of the floating potential reference circuit formation region 21. As an example, P− which is one first insulated gate semiconductor element. A MOS 401 and an N-MOS 402 which is one second insulated gate semiconductor element are formed. The N-MOS 402 is formed in the p semiconductor region 3 which is a third semiconductor region provided in the surface layer of the n semiconductor region 2. Here, when the pn junction between the p epitaxial layer 27 and the n semiconductor region 2 is a first pn junction, when a reverse bias voltage is applied to the first pn junction, the first pn junction It is desirable to select the thickness and impurity concentration of the n semiconductor region 2 so that the tip of the first depletion layer extending in the n semiconductor region 2 does not reach the p semiconductor region 3.

  In the n semiconductor region 202 of the GND reference circuit formation region 22, as an example of various semiconductor elements for constituting a control circuit, one P-MOS 403 that is a third insulated gate semiconductor element, and one An N-MOS 404, which is a fourth insulated gate semiconductor element, is formed. The N-MOS 404 is formed in the p semiconductor region 203 which is a fourth semiconductor region provided in the surface layer of the n semiconductor region 202. A plurality of P-MOSs may be formed in each of the n semiconductor regions 2 and 202, and a plurality of N-MOSs may be formed in each of the p semiconductor regions 3 and 203.

In FIG. 1, D, G, and S of each P-MOS 401 and 403 and each N-MOS 402 and 404 represent a drain electrode, a gate electrode, and a source electrode, respectively. The drain electrode D is electrically connected via a metal electrode 17 to a p ⁺ semiconductor region (in the case of P-MOS) or an n ⁺ semiconductor region (in the case of N-MOS) serving as a drain region. The source electrode S is electrically connected via a metal electrode 17 to a p ⁺ semiconductor region (in the case of P-MOS) or an n ⁺ semiconductor region (in the case of N-MOS) serving as a source region. Each gate electrode G is formed on the surface of a predetermined semiconductor region via an insulating film (not shown).

A ground potential GND is applied to the p ⁺ semiconductor substrate 1 through the metal electrode 18 that is in ohmic contact with the p ⁺ semiconductor layer 301 provided on the back surface of the substrate. The n semiconductor region 2 of the floating potential reference circuit forming region 21 is connected to the power supply potential V _UH (in the case of U phase) of the floating potential reference circuit via a metal electrode 17 that is in ohmic contact with the n ⁺ semiconductor region provided on the surface. ) Is applied. The p semiconductor region 3 in the n semiconductor region 2 receives the reference potential V _UL (in the case of the U phase) of the floating potential reference circuit through the metal electrode 17 that is in ohmic contact with the p ⁺ semiconductor region provided on the surface thereof. Applied.

V _UH and V _UL are V _VH and V _{VL in} the case of the V phase, and V _WH and V _{WL in} the case of the W phase. Normally, U phase V _UH , V phase V _VH, and W phase V _WH are the same, and U phase V _UL , V phase V _VL, and W phase V _WL are the same. In the description, the power supply potential and the reference potential of the floating potential reference circuit of each phase are represented by V _UH and V _UL , respectively (the same _applies to other embodiments).

The power supply voltage of the upper arm during normal use is given by the potential difference ([V _UH −V _UL ]) between the power supply potential V _UH of the floating potential reference circuit and the reference potential V _UL . This potential difference is arbitrary and is set to about +10 to 20V, for example. The wiring to which the reference potential V _UL of the floating potential reference circuit is applied can be connected to a connection node between the emitter of the upper arm IGBT and the collector of the lower arm IGBT (not shown) driven by the high voltage driver.

The power supply potential V _{cc of the} lower arm (not shown) is applied to the n semiconductor region 202 of the GND reference circuit forming region 22 through the metal electrode 17 that is in ohmic contact with the n ⁺ semiconductor region provided on the surface thereof. A ground potential GND that is a reference potential of the GND reference circuit formation region 22 is applied to the p semiconductor region 203 in the n semiconductor region 202 through the metal electrode 17 that is in ohmic contact with the p ⁺ semiconductor region provided on the surface thereof. Is done. The power supply potential V _cc of the lower arm with respect to the ground potential GND, that is, the power supply voltage of the lower arm is arbitrary, and is set to about +10 to 20 V, for example.

The n semiconductor region 8 of the high breakdown voltage junction termination structure 23 is provided in contact with the n semiconductor region 2 of the floating potential reference circuit forming region 21. Therefore, the potential of the n semiconductor region 8 becomes the power supply potential V _UH of the same floating potential reference circuit as that of the n semiconductor region 2. The n semiconductor region 8 may be formed simultaneously by the same process as the n semiconductor region 2. On the surface layer of the n semiconductor region 8, a p semiconductor region and a p ⁻ semiconductor region having a lower impurity concentration are formed in contact with each other. The ground potential GND is applied to the p semiconductor region formed in the n semiconductor region 8 through the metal electrode 17 that is in ohmic contact with the p semiconductor region.

Therefore, the pn junction between the p epitaxial layer 27 and the n semiconductor region 8 is the second pn junction, and the p semiconductor region and the p ⁻ semiconductor region formed in the n semiconductor region 8 and the n semiconductor region 8 are connected. When the pn junction is the third pn junction, both the second and third pn junctions are in a state where a reverse bias is applied. In such a reverse bias state, the second depletion layer extending on both sides of the second pn junction and the third depletion layer extending on both sides of the third pn junction are coupled by the n semiconductor region 8, and third depletion layer, p semiconductor region in the n semiconductor region 8 and p ^- to reach the surface of the semiconductor region, p semiconductor region in the n semiconductor region 8 and p ^- may be formed the semiconductor region. The structure of the high withstand voltage junction termination structure 23 can be variously changed in addition to the above-described configuration.

The trench structure 7 includes a trench wall p ⁺ semiconductor region 51 having a concentration higher than that of the p ⁺ semiconductor substrate 1 and an electrode 16 made of a conductive film containing a metal material such as aluminum. The trench wall p ⁺ semiconductor region 51 is provided along the side surface and the bottom surface of the trench. Trench bottom portion of the trench wall p ⁺ semiconductor region 51 is in contact with the p ⁺ semiconductor substrate 1, the trench wall p ⁺ semiconductor region 51 is electrically connected to the p ⁺ semiconductor substrate 1. The electrode 16 is provided in the trench and is in ohmic contact with the trench wall p ⁺ semiconductor region 51. A ground potential GND is applied to the electrode 16. Therefore, the potential of the p epitaxial layer 27 electrically connected to the electrode 16 via the trench wall p ⁺ semiconductor region 51 on the side surface of the trench becomes the ground potential GND.

In forming the trench structure 7, a trench reaching the p ⁺ semiconductor substrate 1 from the surface of the p epitaxial layer 27 is formed. For example, boron is ion-implanted as a p-type impurity into the p ⁺ type semiconductor substrate 1 along the side and bottom surfaces of the trench to form a high concentration trench wall p ⁺ semiconductor region 51. In the trench, an electrode 16 containing a metal such as aluminum is formed by sputtering, and the electrode 16 is brought into ohmic contact with the trench wall p ⁺ semiconductor region 51.

Thus, since trench wall p ⁺ semiconductor region 51 is electrically connected to p ⁺ semiconductor substrate 1, trench wall p ⁺ semiconductor region 51 has the same potential as p ⁺ semiconductor substrate 1, that is, ground potential GND. Become. As described above, since the potential of the n semiconductor region 202 in the GND reference circuit formation region 22 is the power supply potential _Vcc of the GND reference circuit, the potential of the trench wall p ⁺ semiconductor region 51 is higher than the potential of the n semiconductor region 202. Is kept low.

Here, the pn junction between the p epitaxial layer 27 and the n semiconductor region 202 of the GND reference circuit formation region 22 is a fourth pn junction. Further, the built-in potential between the p epitaxial layer 27 and the n semiconductor region 202 is set to V _bi . In a state where a reverse bias voltage of the voltage value V _cc to a fourth pn junction is applied, the potential V ₁ of the p epitaxial layer 27 in a fourth depletion layer tip extending p epitaxial layer 27 from the fourth pn junction It is desirable to form the trench structure 7 so that the following inequality is always satisfied during operation.

V ₁ <V _cc + V _bi

Next, effects obtained by providing the trench structure 7 with the trench wall p ⁺ semiconductor region 51 will be described. In the configuration shown in FIG. 1, there is a parasitic thyristor having a pnpn structure including a p semiconductor region 3, an n semiconductor region 2, a p epitaxial layer 27 and a p ⁺ semiconductor substrate 1, and an n semiconductor region 202.

Therefore, when a voltage with a steep change (dV / dt) waveform is applied to the p semiconductor region 3, the pn junction between the p epitaxial layer 27 and the n semiconductor region 2 is displaced in proportion to its junction capacitance C. A current [C × (dV / dt)] flows. At that time, a charging current corresponding to the displacement current flows in the p ⁺ semiconductor substrate 1 and the p epitaxial layer 27. As a result, a portion of p ⁺ semiconductor substrate 1 and p epitaxial layer 27 whose potential is equal to or higher than the ground potential GND level is generated.

In the absence of the trench wall p ⁺ semiconductor region 51, when the change in applied voltage (dV / dt) of the p semiconductor region 3 increases, the charging current increases, so that the p ⁺ semiconductor substrate 1 and the p epitaxial layer 27 The potential rise increases. As a result, when the potential of the p epitaxial layer 27 becomes high and a forward bias state is established between the p epitaxial layer 27 and the n semiconductor region 202, the gate current of the parasitic thyristor flows. When the gate current value increases and reaches a predetermined value, the potential difference between the p semiconductor region 3 corresponding to the anode of the parasitic thyristor and the n semiconductor region 202 corresponding to the cathode is greater than the breakover voltage of the parasitic thyristor. Even if it is low, the thyristor is turned on and a latch-up phenomenon occurs. Overcurrent flows due to the occurrence of the latch-up phenomenon, and the semiconductor device is destroyed.

However, if there is a trench wall p ⁺ semiconductor region 51 as in this embodiment, the electrodes 16 on the trench walls p ⁺ semiconductor region 51 is the role of the gate electrode. As described above, by connecting the electrode 16 to the ground point and fixing the potential at the ground potential GND level, the ratio of the current flowing into the trench structure 7 in the charging current is increased. Thereby, the current flowing in the p epitaxial layer 27 around the n semiconductor region 202 is reduced, and the potential increase of the p epitaxial layer 27 around the n semiconductor region 202 can be suppressed. It is possible to prevent the gate current of the parasitic thyristor from flowing by being forward-biased. In other words, the parasitic thyristor is difficult to latch up.

According to the first embodiment, the base of the parasitic npn transistor including the n semiconductor region 2 in the floating potential reference circuit formation region 21, the p epitaxial layer 27 and the p ⁺ semiconductor substrate 1, and the n semiconductor region 202 in the GND reference circuit formation region 22. Since the concentration can be increased, the structure of the parasitic npn transistor is extremely difficult to operate. Therefore, since the n semiconductor regions 2 and 202 and the trench structure 7 do not have to be deepened, the process cost can be reduced. Further, as described above, a structure in which the parasitic thyristor is difficult to latch up is obtained.

As shown in FIG. 3, a lateral high voltage MIS (metal-insulating film-semiconductor) transistor 405 may be formed in the n semiconductor region 8 of the high voltage junction termination structure 23. The configuration shown in FIG. 3 corresponds to the cross-sectional configuration along the cutting line BB ′ in FIG. D, G, and S of the MIS transistor 405 represent a drain electrode, a gate electrode, and a source electrode, respectively. The drain electrode D is electrically connected to the n semiconductor region serving as the drain region surrounded by the p ⁻ semiconductor region 9 in the surface layer of the n semiconductor region 8 through the metal electrode 17. The source electrode S, the source region where the source electrode S is electrically connected via the metal electrode 17, and the gate electrode G are provided outside the p ⁻ semiconductor region 9 on the trench structure side in the surface layer of the n semiconductor region 8. It has been.

Embodiment 2. FIG.
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device including the integrated circuit according to the second embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ in FIG. As shown in FIG. 4, the second embodiment is different from the first embodiment shown in FIG. 1 in the configuration of the trench structure 7, and the other configurations are the same as those shown in FIG. It is. Therefore, the other processes are the same as those in the first embodiment except for the process of manufacturing the trench structure 7.

In the second embodiment, the trench structure 7 has a structure in which the inside of the trench wall p ⁺ semiconductor region 51 is buried with a buried p ⁺ semiconductor region 41 made of polysilicon. The buried p ⁺ semiconductor region 41 through the metal electrode 17 in ohmic contact with the buried p ⁺ semiconductor region 41, the same ground potential GND and p ⁺ semiconductor substrate 1 is applied.

In forming the trench structure 7 of the second embodiment, a trench reaching the p ⁺ semiconductor substrate 1 is formed in the same manner as in the first embodiment, and a high concentration trench wall is formed by ion implantation of p-type impurities such as boron. A p ⁺ semiconductor region 51 is formed. Next, a buried p ⁺ semiconductor region 41 is formed in the trench by burying polysilicon doped with a p-type impurity at a high concentration by a CVD (chemical vapor deposition) method or the like. Then, the metal electrode 17 is formed on the surface of the buried p ⁺ semiconductor region 41, and the metal electrode 17 is brought into ohmic contact with the buried p ⁺ semiconductor region 41.

  According to the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. In Embodiment 1, since the metal electrode 16 is formed in the trench by sputtering, the width of the trench is about the same as the trench depth, for example, about 5 to 10 μm in consideration of the covering property of the metal film to be the electrode 16. On the other hand, in the second embodiment, since the trench is filled with polysilicon, the width of the trench can be set to about 3 μm, for example. Therefore, a smaller semiconductor device can be realized.

Embodiment 3 FIG.
FIG. 5 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the third embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ in FIG. As shown in FIG. 5, the third embodiment is different from the first embodiment shown in FIG. 1 in the structure of the trench structure 7 and its peripheral part, and the other structure is shown in FIG. It is the same as the structure shown. Therefore, the other processes are the same as those of the first embodiment except for the process of manufacturing the trench structure 7 and its peripheral part.

In the third embodiment, the trench structure 7 has a trench embedded with an insulator 61 and a trench bottom p ⁺ semiconductor region 52 having a higher concentration than the p ⁺ semiconductor substrate 1 is provided at the bottom of the trench structure 7. It becomes the composition. The trench bottom p ⁺ semiconductor region 52 is electrically connected to the p ⁺ semiconductor substrate 1. In the third embodiment, the ground potential GND is applied to the p epitaxial layer 27 around the trench structure 7 through the metal electrode 17 and the p ⁺ semiconductor region in which the metal electrode 17 is in ohmic contact.

In forming the trench structure 7 of the third embodiment, a trench reaching the p ⁺ semiconductor substrate 1 is formed in the same manner as in the first embodiment. Then, a p-type impurity such as boron is ion-implanted into the trench bottom to form a high concentration trench bottom p ⁺ semiconductor region 52. Next, an insulator 61 is embedded in the trench. Thereafter, a high-concentration p ⁺ semiconductor region is formed on the surface of the p epitaxial layer 27 around the trench structure 7 in which the insulator 61 is buried, and the metal electrode 17 is formed on the surface of the p ⁺ semiconductor region. The metal electrode 17 is brought into ohmic contact with the p ⁺ semiconductor region.

  According to the third embodiment, as in the first embodiment, since the potential increase of the p epitaxial layer 27 can be suppressed, a structure in which the parasitic thyristor is difficult to latch up is obtained.

Embodiment 4 FIG.
FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the fourth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ in FIG. As shown in FIG. 6, the fourth embodiment is different from the first embodiment shown in FIG. 1 in the n semiconductor region 2 in the floating potential reference circuit formation region 21, the n semiconductor region 8 in the high breakdown voltage junction termination structure 23, and The configuration of the n semiconductor region 202 in the GND reference circuit formation region 22, the configuration of the trench structure 7, and the configuration of the high voltage junction termination structure 23 are different, and the other configurations are the same as those shown in FIG. 1. is there. Therefore, the other processes are the same as those in the first embodiment except for the process of manufacturing the n semiconductor regions 2, 8, 202, the trench structure 7 and the high breakdown voltage junction termination structure 23.

The n semiconductor regions 2 and 8 and the n semiconductor region 202 pass through the n epitaxial layer 2a stacked on the p epitaxial layer 27 from the surface thereof to the p ⁺ semiconductor substrate 1 through the n epitaxial layer 2a and the p epitaxial layer 27. It is formed by separating with a trench structure 7 that reaches. Therefore, both n semiconductor region 8 and n semiconductor region 202 are adjacent to trench structure 7.

In the fourth embodiment, the trench structure 7 is provided with an insulating film 25 on the sidewall of the trench, an electrode 16 is provided along the inside of the insulating film 25 and along the bottom of the trench, and a p ⁺ semiconductor substrate is formed at the bottom of the trench structure 7. The trench bottom p ⁺ semiconductor region 52 having a concentration higher than 1 is provided. The electrode 16 is insulated from the n semiconductor region 8 and the n semiconductor region 202 by the insulating film 25 on the trench sidewall. The electrode 16 is electrically connected to the p ⁺ semiconductor substrate 1 through the trench bottom p ⁺ semiconductor region 52. Since the ground potential GND is applied to the electrode 16, the potential of the trench bottom p ⁺ semiconductor region 52 becomes the same ground potential GND as that of the p ⁺ semiconductor substrate 1.

In forming the trench structure 7 of the fourth embodiment, a trench reaching the p ⁺ semiconductor substrate 1 is formed in the same manner as in the first embodiment. Then, after an insulating film 25 such as a thermal oxide film is formed on the sidewall and bottom of the trench, the bottom of the trench of the insulating film 25 is etched by an anisotropic oxide film etcher to form a contact portion. Next, a p-type impurity such as boron is ion-implanted into the bottom of the trench to form a high concentration trench bottom p ⁺ semiconductor region 52. Thereafter, a metal film to be the electrode 16 is formed inside the trench by sputtering or the like, and the electrode 16 is brought into ohmic contact with the trench bottom p ⁺ region 52.

In the fourth embodiment, the high withstand voltage junction termination structure 23 is in contact with the p semiconductor region 46 and the p semiconductor region 46 to which the ground potential GND is applied via the metal electrode 17 to the surface layer of the n semiconductor region 8. The p ⁻ semiconductor regions 9a and 9b having a lower impurity concentration are provided. One p ⁻ semiconductor region 9 a is provided between the p semiconductor region 46 and the n semiconductor region 8 of the floating potential reference circuit forming region 21. The other p ⁻ semiconductor region 9 b is provided between the p semiconductor region 46 and the trench structure 7.

The p ⁻ semiconductor region 9b facilitates depletion of the portion of the n semiconductor region 8 below the p ⁻ semiconductor region 9b. Of the p ⁻ semiconductor regions 9a and 9b, a higher potential is applied to the p ⁻ semiconductor region 9a on the floating potential reference circuit formation region 21 side, so the width of the p ⁻ semiconductor region 9a is p ⁻ on the trench structure 7 side. It is larger than the width of the semiconductor region 9b.

Embodiment 5 FIG.
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the fifth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ of FIG. As shown in FIG. 7, the fifth embodiment is different from the fourth embodiment shown in FIG. 6 in the configuration of the trench structure 7, and the other configurations are the same as those shown in FIG. It is. Therefore, the other processes are the same as those in the fourth embodiment except for the process of manufacturing the trench structure 7.

In the fifth embodiment, the trench structure 7 has a configuration in which the inner side of the insulating film 25 on the sidewall of the trench is buried with a buried p ⁺ semiconductor region 41 made of polysilicon. The buried p ⁺ semiconductor region 41 is electrically connected to the p ⁺ semiconductor substrate 1 via the trench bottom p ⁺ semiconductor region 52. The buried p ⁺ semiconductor region 41 through the metal electrode 17 in ohmic contact with the buried p ⁺ semiconductor regions 41, since the same ground potential GND and p ⁺ semiconductor substrate 1 is applied, the trench bottom p ⁺ semiconductor regions 52 Is the same ground potential GND as that of the p ⁺ semiconductor substrate 1.

Embodiment 6 FIG.
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the sixth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the section line AA ′ of FIG. As shown in FIG. 8, the sixth embodiment is different from the fourth embodiment shown in FIG. 6 in the configuration of the trench structure 7, and the other configurations are the same as those shown in FIG. It is. Therefore, the other processes are the same as those in the fourth embodiment except for the process of manufacturing the trench structure 7.

In the sixth embodiment, the trench structure 7 has a trench embedded with an insulator 61 and a trench bottom p ⁺ semiconductor region 52 having a higher concentration than the p ⁺ semiconductor substrate 1 is provided at the bottom of the trench structure 7. It becomes the composition. This trench structure 7 is the same as the trench structure of the third embodiment.

Embodiment 7 FIG.
FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to a seventh embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ of FIG. As shown in FIG. 9, the seventh embodiment differs from the fourth embodiment shown in FIG. 6 in that the p epitaxial layer 27 is not provided and the low concentration p ⁻ semiconductor substrate 101 is used instead of the p ⁺ semiconductor substrate 1. Is used. Therefore, trench bottom p ⁺ semiconductor region 52 is electrically connected to p ⁻ semiconductor substrate 101.

Further, in the seventh embodiment, the n semiconductor regions 2, 202 are located near the boundary between the n semiconductor regions 2, 202 and the p ⁻ semiconductor substrate 101 in the floating potential reference circuit formation region 21 and the GND reference circuit formation region 22, respectively. A higher concentration n ⁺ buried layer 24 is provided. The n ⁺ buried layer 24 provided in the GND reference circuit formation region 22 is in contact with the trench structure 7.

n ⁺ in the structure buried layer 24 is in contact with the trench structure 7, if a trench structure 7, as shown in FIG. 1, when a structure having a trench wall p ⁺ semiconductor region 51 around the trench, n ⁺ buried layer When 24 and the trench wall p ⁺ semiconductor region 51 are in contact with each other, a problem arises because the junction breakdown voltage is low. In order to avoid this, in the seventh embodiment, the trench wall p ⁺ semiconductor region 51 is not provided, and the insulating film 25 is formed on the trench side wall, whereby the electrodes 16 and p in the trench structure 7 are formed on the trench side wall. ^The semiconductor substrate 101 is insulated and the electrode 16 is electrically connected to the p ⁻ semiconductor substrate 101 via the trench bottom p ⁺ semiconductor region 52 only at the trench bottom. Other configurations are the same as those shown in FIG.

According to the seventh embodiment, the base concentration of the parasitic pnp transistor including the p semiconductor region 3, the n semiconductor region 2 and the n ⁺ buried layer 24, and the p ⁻ semiconductor substrate 101 in the floating potential reference circuit formation region 21 can be increased. As a result, the parasitic pnp transistor becomes difficult to operate. Therefore, it is not necessary to form the n semiconductor region 2 and the n semiconductor region 202 as deeply as in the prior art. Therefore, the trench structure 7 can be easily formed, and the process cost can be reduced.

Embodiment 8 FIG.
FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the eighth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the section line AA ′ of FIG. As shown in FIG. 10, the eighth embodiment is different from the seventh embodiment shown in FIG. 9 in the configuration of the trench structure 7, and the other configurations are the same as those shown in FIG. It is. Therefore, the other processes are the same as those in the seventh embodiment except for the process of manufacturing the trench structure 7.

In the eighth embodiment, the trench structure 7 has a configuration in which the inside of the insulating film 25 on the trench sidewall is buried with a buried p ⁺ semiconductor region 41 made of polysilicon. This trench structure 7 is the same as the trench structure of the fifth embodiment. The trench structure 7 is in contact with the n ⁺ buried layer 24 provided in the GND reference circuit formation region 22. Therefore, in the eighth embodiment, as in the seventh embodiment, the buried p ⁺ semiconductor region 41 and the p ⁻ semiconductor substrate 101 in the trench structure 7 are insulated on the trench sidewall by the insulating film 25 on the trench sidewall, The buried p ⁺ semiconductor region 41 is electrically connected to the p ⁻ semiconductor substrate 101 through the trench bottom p ⁺ semiconductor region 52 only at the bottom.

Embodiment 9 FIG.
FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the ninth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ of FIG. As shown in FIG. 11, the ninth embodiment is different from the seventh embodiment shown in FIG. 9 in the configuration of the trench structure 7, and the other configurations are the same as those shown in FIG. It is. Therefore, the other processes are the same as those in the seventh embodiment except for the process of manufacturing the trench structure 7. In the ninth embodiment, the trench structure 7 has a structure in which a trench is embedded with an insulator 61 as in the third embodiment.

Embodiment 10 FIG.
FIG. 12 is a cross-sectional view showing a configuration of the semiconductor device including the integrated circuit according to the tenth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ of FIG. As shown in FIG. 12, the tenth embodiment is different from the fourth embodiment shown in FIG. 6 in that each of the n semiconductor regions 2 and 202 of the floating potential reference circuit formation region 21 and the GND reference circuit formation region 22 is p-epitaxial. In the vicinity of the boundary with the layer 27, an n ⁺ buried layer 24 having a higher concentration than the n semiconductor regions 2 and 202 is provided.

The n ⁺ buried layer 24 provided in the GND reference circuit formation region 22 is in contact with the trench structure 7. Therefore, in the tenth embodiment as well as in the seventh embodiment, the insulating film 25 on the trench side wall insulates the electrode 16 in the trench structure 7 from the p ⁺ semiconductor substrate 1 on the trench side wall and the electrode only on the bottom of the trench. 16 is electrically connected to the p ⁺ semiconductor substrate 1 through the trench bottom p ⁺ semiconductor region 52. Other configurations are the same as those shown in FIG. By providing the n ⁺ buried layer 24, the operation of the parasitic element can be further suppressed as compared with the fourth embodiment.

Embodiment 11 FIG.
FIG. 13 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the eleventh embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ in FIG. As shown in FIG. 13, the eleventh embodiment is different from the fifth embodiment shown in FIG. 7 in that each of the n semiconductor regions 2 and 202 of the floating potential reference circuit formation region 21 and the GND reference circuit formation region 22 is p-epitaxial. In the vicinity of the boundary with the layer 27, an n ⁺ buried layer 24 having a higher concentration than the n semiconductor regions 2 and 202 is provided.

The n ⁺ buried layer 24 provided in the GND reference circuit formation region 22 is in contact with the trench structure 7. Therefore, in the eleventh embodiment, as in the seventh embodiment, the buried p ⁺ semiconductor region 41 and the p ⁺ semiconductor substrate 1 in the trench structure 7 are insulated on the trench side wall by the insulating film 25 on the trench side wall. The buried p ⁺ semiconductor region 41 is electrically connected to the p ⁺ semiconductor substrate 1 through the trench bottom p ⁺ semiconductor region 52 only at the bottom. Other configurations are the same as those shown in FIG. By providing the n ⁺ buried layer 24, the operation of the parasitic element can be further suppressed as compared with the fifth embodiment.

Embodiment 12 FIG.
FIG. 14 is a cross-sectional view showing a configuration of a semiconductor device including an integrated circuit according to the twelfth embodiment of the present invention, and shows a cross-sectional configuration corresponding to the cutting line AA ′ of FIG. As shown in FIG. 14, the twelfth embodiment is different from the sixth embodiment shown in FIG. 8 in that each of the n semiconductor regions 2 and 202 of the floating potential reference circuit formation region 21 and the GND reference circuit formation region 22 is p-epitaxial. In the vicinity of the boundary with the layer 27, an n ⁺ buried layer 24 having a higher concentration than the n semiconductor regions 2 and 202 is provided. Other configurations are the same as those shown in FIG. By providing the n ⁺ buried layer 24, the operation of the parasitic element can be further suppressed as compared with the sixth embodiment.

In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. For example, a trench structure in which an insulating film is formed on the trench sidewall as shown in FIG. 9 may be applied to a configuration without an n ⁺ buried layer. In each of the embodiments described above, the first conductivity type is p-type and the second conductivity type is n-type. However, in the present invention, the first conductivity type is n-type and the second conductivity type is p-type. The same holds true.

  As described above, the semiconductor device according to the present invention is useful for an integrated circuit having a high-potential portion and a low-potential portion, and particularly suitable for an integrated circuit used as a high-voltage driver for control drive such as a power supply device. ing.

1 First conductivity type semiconductor substrate (p ⁺ semiconductor substrate)
2 First semiconductor region of second conductivity type (n semiconductor region)
2a Second conductivity type semiconductor layer (n epitaxial layer)
3 Third semiconductor region of first conductivity type (p semiconductor region)
7 Trench structure 16 Conductive film (electrode)
DESCRIPTION OF SYMBOLS 21 Floating potential reference circuit formation area 22 GND reference circuit formation area 23 High voltage | pressure-resistant junction termination structure 24 Embedded layer (n ⁺ embedded layer) of 2nd conductivity type
27 First conductivity type epitaxial layer (p epitaxial layer)
41 First conductivity type polysilicon (buried p ⁺ semiconductor region)
51 High-concentration first conductivity type semiconductor region (trench wall p ⁺ semiconductor region)
52 High concentration first conductivity type semiconductor region (trench bottom p ⁺ semiconductor region)
61 Insulator 101 Semiconductor substrate of first conductivity type (p ^- semiconductor substrate)
202 Second conductivity type second semiconductor region (n semiconductor region)
203 4th semiconductor region of 1st conductivity type (p semiconductor region)
401 1st conductivity type 1st insulated gate semiconductor element (P-MOS)
402 Second conductivity type second insulated gate semiconductor element (N-MOS)
403 Third conductivity type third insulated gate semiconductor element (P-MOS)
404 Second conductivity type fourth insulated gate semiconductor element (N-MOS)

Claims (5)

A first conductivity type semiconductor substrate;
A second conductive type semiconductor layer stacked on the semiconductor substrate;
An element isolation region having a trench structure that penetrates the semiconductor layer from the surface of the second conductivity type semiconductor layer and reaches the semiconductor substrate;
A second conductive type first semiconductor region and a second conductive type second semiconductor region formed by separating the second conductive type semiconductor layer from each other by the element isolation region;
A first conductivity type first insulated gate semiconductor element having a first conductivity type drain region and a first conductivity type source region selectively provided in each of the first semiconductor regions;
A third semiconductor region of a first conductivity type selectively provided on a surface layer of the first semiconductor region;
A second conductivity type second insulated gate semiconductor element having a second conductivity type drain region and a second conductivity type source region selectively provided in the third semiconductor region, respectively.
The first semiconductor region and the semiconductor substrate, and the second semiconductor region and the semiconductor substrate, each having a higher concentration than the first semiconductor region and the second semiconductor region, respectively. Having a buried layer of two conductivity types;
One of the first semiconductor region and the second semiconductor region is a semiconductor region with a floating potential as a reference, and the other is a semiconductor region with a ground potential as a reference,
The trench structure has a conductive film therein, and the conductive film is connected to a ground point of a semiconductor region with the ground potential as a reference. A first conductivity type third insulated gate semiconductor element having a first conductivity type drain region and a first conductivity type source region selectively provided in each of the second semiconductor regions;
A fourth semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor region;
A second conductivity type fourth insulated gate semiconductor element having a second conductivity type drain region and a second conductivity type source region selectively provided in each of the fourth semiconductor regions;
The semiconductor device according to claim 1, further comprising:   3. The semiconductor device according to claim 1, wherein the conductive film is made of a first conductivity type polysilicon doped at a high concentration.   Of the first semiconductor region and the second semiconductor region, a high voltage junction termination structure is provided in contact with the trench structure around the semiconductor region based on the floating potential. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein a semiconductor region of a first conductivity type having a concentration higher than that of the semiconductor substrate is provided at a bottom portion of the trench structure.

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