JP5114304B2 - Semiconductor switch integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor switch integrated circuit that switches high-frequency signals, and more particularly to a circuit that is reduced in size and reduced in distortion.

  In devices such as mobile phones and mobile radio communications that handle high-frequency signals, semiconductor switch integrated circuits using MES FETs, HJFETs, and the like, which are field effect transistors made of GaAs compound semiconductors, are used to switch high-frequency signals. Yes. In recent years, with the drastic miniaturization of devices such as mobile phones and mobile radio communications, there has been a strong demand for miniaturization of individual components, and it is important to reduce the chip size that leads to miniaturization of components in semiconductor switch integrated circuits. It has become a challenge.

A semiconductor switch integrated circuit as described above is generally constituted by combining a plurality of basic units as necessary, with a SPST (Single Pole Single Throw) switch circuit being a basic unit of the switch circuit as a minimum basic unit. It is.
FIG. 11 shows a configuration example of the SPST switch circuit. Hereinafter, the configuration and the like will be described with reference to FIG.
In the figure, the SPST switch circuit 210B is configured with two transistors Q1B and Q2B connected in series as main components.

The transistors Q1B and Q2B are field effect transistors (hereinafter referred to as “FETs”), and a depletion type or an enhancement type is used depending on the use conditions of the switch circuit.
Further, the resistance elements R1B to R4B are provided for supplying a bias voltage, and usually a high resistance of several kΩ to several tens of kΩ is used.

  In such a configuration, when the SPST switch is turned off, the control voltage supply power supply 209B supplies the drain and source potentials of the FET supplied by the first voltage supply power supply 207B and the second voltage supply power supply 208B. The gate potential to be set is set lower than the pinch-off voltage of the transistors Q1B and Q2B. Thus, the drain and source of the transistors Q1B and Q2B are in a high resistance state. For example, even when a high frequency signal is input from the input terminal 201B, no high frequency signal is output to the output terminal 202B.

On the other hand, when the SPST switch is turned on, the gate potential supplied by the control voltage supply power source 209B is set higher than the drain potential and the source potential when the transistors Q1B and Q2B are depletion type. In the case where the transistors Q1B and Q2B are of the enhancement type, the drains and sources of the transistors Q1B and Q2B are set in a low resistance state, that is, an on state by setting the potentials to be higher than the Schottky barrier potential of the gates.
As a result, the high-frequency signal input from the input terminal 201B is output from the output terminal 202B.

When two such SPST switches are combined, an SPDT (Single Pole Dual Throw) switch can be configured. When three such SPST switches are combined, an SP3T (Single Pole 3 Throw) switch must be configured. Can do.
In addition, in these switches, high isolation characteristics can be realized by inserting an SPST switch between the line through which the high-frequency signal passes and the ground.

  The amount of power that can be switched in the SPST switch that realizes various configurations as described above is determined by the characteristics and circuit configuration of the FET used and the voltage applied from the outside. For example, the power Pmax that can be handled by the SPST switch in the on state is in accordance with Equation 1 below.

Pmax = Idss ² × Z0 / 2 Formula 1

  Here, Idss is the drain-source saturation current of the FET used, and Z0 is the characteristic impedance.

  On the other hand, the power Pmax that can be handled by the SPST switch in the off state is in accordance with Equation 2 below.

Pmax = 2n {Vp−Vgs (off) ² } / Z 0 Formula 2

  Here, n is the number of FETs connected in series, Vp is the voltage applied between the gate and drain of the FET and between the gate and source, and Vgs (off) is the pinch-off voltage of the FET.

  In this SPST switch, when considering the measures to increase the power that can be handled, particularly focusing on the OFF state of the SPST switch, first, in order to increase Pmax, the pinch-off of the FET is It can be understood that (Vp−Vgs (off)) may be increased by increasing the voltage, increasing the voltage applied to the gate from the outside, or both.

It is also possible to increase the number of FETs connected in series, that is, to increase n in Equation 2.
By the way, normally, the pinch-off voltage of the FET to be used depends on the device design and cannot be changed greatly. Furthermore, increasing the applied voltage is based on the premise that a battery is used when considering a mobile terminal. Therefore, the size and the like are naturally limited, and cannot be freely set.
For this reason, it is common to satisfy the demand for high power by taking a circuit measure to increase the number of FETs connected in series.

  By the way, in order to operate the semiconductor switch integrated circuit in which a plurality of FETs are connected in series as described above, it is important that the potential relationship between the gate, drain, and source of the FET is determined. In order to determine this potential relationship, in the circuit shown in FIG. 11 described above, the high-frequency signal input terminal 204B and output terminal 205B are connected to the external power sources 207B and 208B using the bias circuits 211B and 212B. The same voltage is applied, and the control voltage terminal 206B connected to the gates of the transistors Q1B and Q2B is applied with a voltage for switching the transistors Q1B and Q2B to the on state or the off state from the control voltage supply power source 209B. To do.

Thus, when the SPST switch is in the on state, that is, when the transistors Q1 and Q2 are in the on state, the connection between the drain and source of the transistors Q1B and Q2B is in a low resistance state. To the potential applied to the input terminal 204B and the output terminal 205B.
On the other hand, when the SPST switch is in an off state, that is, when the transistors Q1B and Q2B are in an off state, the connection between the drain and the source of the transistors Q1B and Q2B is in a high resistance state. Also, it is electrically disconnected from the output terminal 205B, resulting in an unstable potential state.

In such a state, the off-state of the SPST switch is not surely determined, leading to deterioration of the switch characteristics such as deterioration of distortion characteristics. In order to avoid such a state, in the circuit shown in FIG. 11, high resistance elements R3B and R4B are connected in advance between the drains and sources of the transistors Q1B and Q2B, and the potential of the connection point 203B is determined. .
A semiconductor switch integrated circuit having a circuit configuration as shown in FIG. 11 is disclosed in, for example, Patent Document 1 and the like.

FIG. 12 shows another circuit configuration example for determining the potential at the connection point between the transistors Q1B and Q2B, and the contents thereof will be described below with reference to FIG. In addition, about the component same as the component shown by FIG. 11, the same code | symbol is attached | subjected, the detailed description is abbreviate | omitted, and below, it demonstrates centering on a different point.
In this circuit configuration example, a favorable switching characteristic is realized by connecting a resistance element R5C to the connection point 203B of the transistors Q1B and Q2B and applying a voltage from the external power source 214C.
A semiconductor switch integrated circuit having a circuit configuration as shown in FIG. 12 is disclosed in, for example, Patent Document 2.
Japanese Patent Laying-Open No. 2005-323030 (page 5-8, FIGS. 1 to 7) Japanese Patent No. 3790227 (page 6-10, FIGS. 1-7)

However, providing a resistance element for determining the potential relationship as described above causes an increase in the layout area in an integrated circuit as the number of elements increases.
For example, FIG. 13 shows an actual layout example of the SPST switch shown in FIG. 11, and FIG. 14 shows an actual layout example of the SPST switch shown in FIG.
Looking at these two layout examples, in the case of the resistance element provided for realizing the low distortion characteristic, that is, in the case of the circuit configuration example shown in FIG. 11, the resistance elements R3B and R4B are denoted by reference numeral 101B-3 in FIG. , 101B-4, and is arranged adjacent to the FET, but separately arranged outside the FET, which contributes to an increase in the occupied area as the SPST switch. It has become.

The same applies to R5C in the configuration example shown in FIG. That is, the resistance element R5C is realized by a resistor denoted by reference numeral 101C-5 in FIG. 14, but all are arranged outside the FET.
In both layout examples of FIGS. 13 and 14, an FET is formed by the ohmic electrode layer 102B, the wiring metal layer 103B, the element isolation layer 104B, and the Schottky electrode layer 105B.

In such a layout, it is necessary to secure some distance from other elements in the periphery of the resistance element in order to reduce the effect of element isolation and parasitic components. These elements cannot be arranged.
For this reason, providing a resistance element for realizing low distortion requires an area larger than the size of the resistance element itself.

In particular, in recent mobile terminal systems, a plurality of high-frequency signals such as a plurality of communication methods such as GSM and CDMA are incorporated in one terminal and a plurality of frequency bands are used in one communication method. Accordingly, the circuit configuration of the semiconductor switch integrated circuit has become complicated.
In such a semiconductor switch integrated circuit, a large number of SPST switches, which are the basic units described above, are arranged in one chip, and the influence of an increase in chip layout area due to the use of resistance elements for realizing low distortion is not affected. Become enormous.

Such an increase in chip chip layout area leads to an increase in cost and a significant decrease in product competitiveness.
Further, as described above, in the conventional layouts shown in FIGS. 13 and 14, since the resistance elements are arranged away from the FET body, parasitic capacitance is formed between the peripheral elements and wiring. There is a drawback in that coupling due to is likely to occur. Such parasitic capacitance often causes damage to the characteristics of the semiconductor switch integrated circuit such as deterioration of isolation and distortion characteristics.

  The present invention has been made in view of the above circumstances, and in a switch circuit configured by connecting a plurality of FETs in series, a resistance element necessary for the operation of the FETs is provided without causing an increase in layout area. A semiconductor switch integrated circuit having a possible layout is provided.

In order to achieve the above object of the present invention, a semiconductor switch integrated circuit according to the present invention includes:
A semiconductor unit that can selectively select a high-frequency signal passing path by combining basic units formed by connecting a plurality of field-effect transistors in series according to the number of desired high-frequency signal passing paths. A switch integrated circuit,
The basic unit includes a resistance element connected between the drain and source of each of the plurality of field-effect transistors connected in series, while the plurality of field-effect transistors are adjacent to each other, and The drain and source layers have a layout disposed so as to face each other, and the resistance element is disposed between the plurality of field effect transistors facing each other.
In order to achieve the object of the present invention, a semiconductor switch integrated circuit according to the present invention includes:
A semiconductor unit that can selectively select a high-frequency signal passing path by combining basic units formed by connecting a plurality of field-effect transistors in series according to the number of desired high-frequency signal passing paths. A switch integrated circuit,
The basic unit has a resistance element for supplying power from the outside at a connection point of the plurality of field-effect transistors connected in series, while the plurality of field-effect transistors are adjacent to each other, and It is also preferable that each of the drain and source layers has a layout disposed so that the layers are opposed to each other, and the resistance element is disposed between the plurality of field effect transistors facing each other.

  According to the present invention, since the resistance element necessary for the FET is arranged in the gap between the field effect transistors connected in series, the resistance element connected to the FET for low distortion operation. Unlike the conventional case, the semiconductor switch integrated circuit can be provided without increasing the chip area, and a semiconductor switch integrated circuit having favorable characteristics can be provided in a small size and at low cost.

Hereinafter, embodiments of the present invention will be described with reference to FIGS.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first configuration example of the semiconductor switch integrated circuit according to the embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a layout example for making the SPST switch circuit 210 shown in FIG. 3 into a semiconductor integrated circuit.

First, the circuit configuration of the SPST switch circuit 210 shown in FIG. 3 will be described.
As is conventionally known, the SPST switch circuit 210 is a circuit of a minimum basic unit constituting a semiconductor switch integrated circuit, that is, a basic unit. The SPST switch circuit 210 includes the SPST switch circuit 210B in the conventional circuit previously shown in FIG. They basically have the same configuration.
That is, the SPST switch circuit 210 is configured by using two transistors Q1 and Q2 connected in series as main components, and the transistors Q1 and Q2 include a depletion type, or depending on the use conditions of the switch circuit, or the like. An enhancement type field effect transistor (hereinafter referred to as “FET”) is used.

The two transistors Q1, Q2 have a configuration in which either one drain and the other source are connected in series.
One end of the resistance element R1 is connected to the gate of the transistor Q1, and one end of the resistance element R2 is connected to the gate of the transistor Q2. The other ends of the resistance elements R1 and R2 are connected to each other. It can be connected to the outside.
Further, a resistance element R3 is connected between the drain and source of the transistor Q1, and a resistance element R4 is connected between the drain and source of the transistor Q2.
By providing the resistance elements R3 and R4 in this way, the potential at the connection point 203 between the transistors Q1 and Q2 is determined stably, the operation is stable even when a large power is input, and a low distortion switch operation is achieved. It is possible.

FIG. 1 is a layout example for realizing the SPST switch circuit 210 having the above-described circuit configuration, and a portion denoted as FET is a portion where the transistors Q1 and Q2 in FIG. 3 are formed.
The transistors Q1 and Q2 include ohmic electrode layers 102a and 102b that form the drain and source of the FET, metal thin film wiring layers 103a and 103b that connect them, element isolation layers 104a and 104b, and a channel layer of the FET. Each of the gate electrode layers 105a and 105b forming a Schottky junction is formed.
In the embodiment of the present invention, the two FETs are laid out so as to face each other. That is, in the configuration example of FIG. 1, the gate electrode layers 105a and 105b are formed in a so-called comb shape, and the layers 102a and 102b forming the drain and source are formed in the comb shape of the respective gate electrode layers 105a and 105b. It is formed in a strip shape so as to be parallel, and has a layout in which one end portion of the strip faces each other.

The resistance elements R1 and R2 are respectively formed by the resistors 101a and 101b, and the resistance elements R3 and R4 are respectively formed by the resistors 101c and 101d.
As described above, in the layout example shown in FIG. 1, the two FETs are separated by the element isolation layers 104a and 104b. Therefore, a wiring layer connecting the two FETs is provided between the two FETs. Since the resistors 101c and 101d are formed and disposed between them, there is a resistance element connected between the drain and source of the FET that plays an important role in reducing the distortion operation. Unlike the prior art, the structure can be arranged without protruding from the layout area of the FET.

The resistors 101a to 101d may use semiconductor layers connected to the drain and source of the FET. It is also preferable to use another layer different from the layer constituting the FET, such as a high-resistance metal thin film.
In general, the distance between the two FETs shown in FIG. 1 is as narrow as about 10 μm to several tens of μm. Therefore, the resistors 101c and 101d may not be able to obtain a sufficient resistance.

  FIG. 2 shows a second layout example in such a case. Hereinafter, the second layout example will be described with reference to FIG. The same components as those shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and different points will be mainly described below.

In the second layout example, the length of the resistor can be sufficiently secured as compared with the example shown in FIG.
That is, the resistors 101c ′ and 101d ′ are connected to the drain or source facing each other so as to obtain a desired resistance value.

Next, a third layout example will be described with reference to FIGS.
The same components as those shown in FIGS. 1 and 3 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
FIG. 4 shows a layout example for making the SPST switch circuit 210A shown in FIG. 5 into a semiconductor integrated circuit.

First, the circuit configuration of the SPST switch circuit 210A shown in FIG. 5 will be described.
The SPST switch circuit 210A has basically the same configuration as the SPST switch circuit 210C in the conventional circuit previously shown in FIG.
That is, the SPST switch circuit 210A is constituted by two transistors Q1 and Q2 connected in series as main components, and this configuration is basically the same as the SPST switch circuit 210 shown in FIG. is there.
In the SPST switch circuit 210A, a resistance element R5 is connected to a connection point 203 between the transistors Q1 and Q2, and a voltage can be applied from the outside via the resistance element R5.

FIG. 4 shows a layout example for realizing the SPST switch circuit 210A having the above-described circuit configuration. Hereinafter, the configuration will be described with reference to FIG.
In this layout example, one end of the resistor 101e forming the resistance element 5 in FIG. 5 is connected to a portion corresponding to a connection portion between two FETs (a portion corresponding to the connection point 203 in FIG. 5). It arrange | positions so that it may pass between two FET, and the other end is located in the pole vicinity of the outer side of 2 FET. With this layout, the terminal for supplying a voltage to the connection point 203 can be arranged at a position very close to the FET, which contributes to a reduction in layout area.

Next, a fourth layout example will be described with reference to FIG.
The The same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below.
In this layout example, the Schottky electrode layers 105a and 105b for forming the gate electrode are formed in a comb shape in the layout examples shown in FIGS. The difference is that it has a meander shape.
When the gate electrode is formed in a meander shape and the resistor is simply arranged as shown in FIGS. 1, 2 and 4, a portion intersecting with the gate electrode is generated. As is clear from the layout example, the resistor and the gate electrode do not cross each other in the portion functioning as the FET by arranging the two FETs so as to pass between the opposing portions of the gate electrodes. The crossing outside the element isolation layers 104a and 104b remains. The intersection at this portion does not affect the electrical characteristics of the FET, and the layout example shown in FIG. 6 is effective for an FET having a meander-shaped gate electrode.

  Any of the above-described examples is an example of an SPST switch circuit including two FETs connected in series. However, in view of the gist of the present invention, the FETs connected in series need not be limited to two. Of course, the number of FETs connected in series is not limited as long as it is two or more, and the gate electrode may be comb-shaped or meander-shaped.

Next, a layout example of an SP4T (Single Pole Four Throw) switch circuit to which the above layout example is applied will be described with reference to FIGS.
First, the circuit configuration of the SP4T switch circuit will be described with reference to FIG.
This SP4T switch circuit has one high-frequency signal input / output common terminal 301 and four high-frequency signal input / output individual terminals 302 to 305, and the high-frequency signal input / output common terminal 301 and four high-frequency signal input / output individual terminals 302. ˜305 can be selected as a signal passing path as desired.

The SP4T switch circuit includes FETs Q11 to Q26 that function as switch elements, and these FETs Q11 to Q26 are applied to the gates through control signal input terminals 312 to 315 and gate resistance elements R27 to R42. Each operation is controlled by the control voltage.
That is, between the high frequency signal input / output common terminal 301 and the high frequency signal input / output individual terminal 302, FETs Q11 to Q14 and resistance elements R11 to R14 are connected in series from the high frequency signal input / output common terminal 301 side. Is provided. The mutual connection points of the resistance elements R11 to R14 are respectively connected to the mutual connection points of the FETs Q11 to Q14, that is, the corresponding connection points of the drain or source of one FET and the source or drain of the other FET, respectively. It is connected.

In this example, the mutual connection point between the resistance elements R11 and R12 is the mutual connection point between the FETs Q11 and Q12, and the mutual connection point between the resistance elements R12 and R13 is the mutual connection point between the FETs Q12 and Q13. The mutual connection point between the elements R13 and R14 is connected to the mutual connection point between the FETs Q13 and Q14.
The gate of the FET Q11 is connected through the resistor element R27, the gate of the FET Q12 is connected through the resistor element R28, the gate of the FET Q13 is connected through the resistor element R29, and the gate of the FET Q14 is connected through the resistor element R30. Both are connected to the control signal input terminal 312.

Also, between the high frequency signal input / output common terminal 301 and the high frequency signal input / output individual terminal 303, FETs Q15 to Q18 and resistance elements R15 to R18 are connected in series from the high frequency signal input / output common terminal 301 side. Is provided. The mutual connection points of the resistance elements R15 to R18 are connected to the mutual connection points of the FETs Q15 to Q18, that is, the corresponding connection points of the drain or source of one FET and the source or drain of the other FET, respectively. It is connected.
Specifically, the connection point between the resistance elements R15 and R16 is the connection point between the FETs Q15 and Q16, and the connection point between the resistance elements R16 and R17 is the connection point between the FETs Q16 and Q17. The mutual connection points of the resistance elements R17 and R18 are respectively connected to the mutual connection points of the FETs Q17 and Q18.
Further, the gate of the FET Q15 is passed through the resistance element R31, the gate of the FET Q16 is passed through the resistance element R32, the gate of the FET Q17 is passed through the resistance element R33, and the gate of the FET Q18 is passed through the resistance element R34. Both are connected to the control signal input terminal 313.

Further, between the high frequency signal input / output common terminal 301 and the high frequency signal input / output individual terminal 304, FETs Q19 to Q22 and resistance elements R19 to R22 are connected in series from the high frequency signal input / output common terminal 301 side. Is provided. The mutual connection points of the resistance elements R19 to R22 are respectively connected to the mutual connection points of the FETs Q19 to Q22, that is, the corresponding connection points of the drain or source of one FET and the source or drain of the other FET, respectively. It is connected.
Specifically, the connection point between the resistance elements R19 and R20 is the connection point between the FETs Q19 and Q20, and the connection point between the resistance elements R20 and R21 is the connection point between the FETs Q20 and Q21. The connection points of the resistance elements R21 and R22 are connected to the connection points of the FETs Q21 and Q22, respectively.
Further, the gate of the FET Q19 is passed through the resistance element R35, the gate of the FET Q20 is passed through the resistance element R36, the gate of the FET Q21 is passed through the resistance element R37, and the gate of the FET Q22 is passed through the resistance element R38. Both are connected to the control signal input terminal 314.

Further, between the high frequency signal input / output common terminal 301 and the high frequency signal input / output individual terminal 305, FETs Q23 to Q26 and resistance elements R23 to R26 are connected in series from the high frequency signal input / output common terminal 301 side. Is provided. The mutual connection points of the resistance elements R23 to R26 are respectively connected to mutual connection points of the FETs Q23 to Q26, that is, corresponding connection points of the drain or source of one FET and the source or drain of the other FET. It is connected.
Specifically, the connection point between the resistance elements R23 and R24 is the connection point between the FETs Q23 and Q24, and the connection point between the resistance elements R24 and R25 is the connection point between the FETs Q24 and Q25. The mutual connection points of the resistance elements R25 and R26 are respectively connected to the mutual connection points of the FETs Q25 and Q26.
Further, the gate of the FET Q23 is passed through the resistance element R39, the gate of the FET Q24 is passed through the resistance element R40, the gate of the FET Q25 is passed through the resistance element R41, and the gate of the FET Q26 is passed through the resistance element R42. Both are connected to the control signal input terminal 315.

FIG. 7 shows a layout example when the circuit configuration described above is integrated, and the method described above with reference to FIGS. 1, 2, and 4 is applied.
For example, in FIG. 7, R11 to R14, R15 to R18, R19 to R22, and R23 to R26 apply the layout example shown in FIG.

On the other hand, FIG. 15 shows a layout example according to the conventional method for the circuit configuration shown in FIG.
In this layout example, R11 to R14, R15 to R18, R19 to R22, and R23 to R26 are all arranged outside the FET region.
Therefore, in the layout according to the embodiment of the present invention shown in FIG. 7, the chip size can be reduced by about 10% as compared with the conventional layout shown in FIG. Therefore, it is possible to increase the degree of freedom in selecting an on-board package.

FIG. 9 shows a change characteristic example of the isolation and passage loss with respect to the frequency change in the SP4T switch circuit adopting the layout according to the above-described embodiment of the present invention, together with a similar characteristic example of the SP4T switch circuit having the conventional layout. Hereinafter, this figure will be described.
First, in the figure, the horizontal axis represents a change in frequency, and the vertical axis represents isolation and the other represents passage loss. In the same figure, the characteristic line of the SP4T switch circuit in the embodiment of the present invention is indicated by a solid line, and the characteristic line of the conventional circuit is indicated by a dotted line.

  According to FIG. 9, it can be confirmed that the SP4T switch circuit according to the embodiment of the present invention is surely improved as compared with the conventional circuit in both the isolation characteristic and the passage loss characteristic. This is considered to be because the parasitic capacitance is reduced by the layout in the embodiment of the present invention described above.

Next, FIG. 10 shows a change characteristic example of the second harmonic with respect to the input power change in the SP4T switch circuit adopting the layout according to the embodiment of the present invention, which is similar to that of the SP4T switch circuit having the conventional layout. It is shown together with a characteristic example, and the figure will be described below.
In the figure, the horizontal axis represents a change in input power, and the vertical axis represents a change in second harmonic. In the same figure, the characteristic line of the SP4T switch circuit in the embodiment of the present invention is indicated by a solid line, and the characteristic line of the conventional circuit is indicated by a dotted line.

  According to the figure, it can be confirmed that the second harmonic of the SP4T switch circuit in the embodiment of the present invention is reliably reduced as compared with the conventional circuit, and that a good distortion characteristic is realized. This is considered to be due to the same reason as the improvement of the isolation characteristic and the passage loss characteristic described above.

It is a schematic diagram which shows typically the 1st layout example of the SPST switch circuit in embodiment of this invention. It is a schematic diagram which shows typically the 2nd layout example of the SPST switch circuit in embodiment of this invention. FIG. 3 is a circuit diagram showing a circuit configuration example of an SPST switch circuit in an embodiment of the present invention to which the layout shown in FIGS. 1 and 2 is applied. It is a schematic diagram which shows typically the 3rd layout example of the SPST switch circuit in embodiment of this invention. FIG. 5 is a circuit diagram showing a circuit configuration example of an SPST switch circuit in an embodiment of the present invention to which the layout shown in FIG. 4 is applied. It is a schematic diagram which shows typically the 4th layout example of the SPST switch circuit in embodiment of this invention. It is a schematic diagram which shows typically the example of a layout of SP4T switch circuit in embodiment of this invention. FIG. 8 is a circuit diagram showing a circuit configuration example of an SP4T switch circuit in an embodiment of the present invention to which the layout shown in FIG. 7 is applied. It is a characteristic diagram which shows the change characteristic example of the isolation and passage loss with respect to the frequency change in the SP4T switch circuit which employ | adopted the layout in embodiment of this invention with the characteristic example of the SP4T switch circuit which has the conventional layout. It is a characteristic diagram which shows the example of the change characteristic of the 2nd harmonic with respect to the input power change in the SP4T switch circuit which employ | adopted the layout in embodiment of this invention with the example of a characteristic of SP4T switch circuit which has the conventional layout. It is a circuit diagram which shows the general structural example of a SPST switch circuit. It is a circuit diagram which shows the other general structural example of a SPST switch circuit. It is a schematic diagram which shows typically the example of a layout of the conventional SPST switch circuit. It is a schematic diagram which shows typically the other layout example of the conventional SPST switch circuit. It is a schematic diagram which shows typically the example of a layout of the conventional SP4T switch circuit.

Explanation of symbols

101a to 101e ... resistors 102a, 102b ... ohmic electrode layers 103a, 103b ... metal thin film wiring layers 104a, 104b ... element isolation layers 105a, 105b ... gate electrode layers

Claims (2)

A semiconductor unit that can selectively select a high-frequency signal passing path by combining basic units formed by connecting a plurality of field-effect transistors in series according to the number of desired high-frequency signal passing paths. A switch integrated circuit,
The basic unit includes a resistance element connected between the drain and source of each of the plurality of field-effect transistors connected in series, while the plurality of field-effect transistors are adjacent to each other, and A semiconductor switch integrated circuit having a layout in which layers for forming a drain and a source are arranged to face each other, and wherein the resistance element is arranged between the plurality of field effect transistors facing each other. A semiconductor unit that can selectively select a high-frequency signal passing path by combining basic units formed by connecting a plurality of field-effect transistors in series according to the number of desired high-frequency signal passing paths. A switch integrated circuit,
The basic unit has a resistance element for supplying power from the outside at a connection point of the plurality of field-effect transistors connected in series, while the plurality of field-effect transistors are adjacent to each other, and A semiconductor switch integrated circuit having a layout in which layers forming each drain and source face each other, and the resistance element is arranged between the plurality of field effect transistors facing each other. circuit.

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