JP5108037B2 - CDR circuit - Google Patents

Description

  The present invention relates to a CDR circuit that regenerates a clock that is phase-synchronized with input data and performs retiming of input data using this clock.

  In the PON (Passive Optical Network) system, which is being developed as a means for realizing FTTH (Fiber To The Home), it is necessary to handle burst data. In these systems, a CDR (Clock Data Recovery) circuit that instantaneously establishes phase synchronization with respect to burst data received asynchronously on the station side, extracts a clock, and retimes data in synchronization with this clock is provided. It is essential. This type of circuit can be referred to in Non-Patent Document 1, for example.

  FIG. 11 shows a configuration example of a CDR circuit used for such a purpose. When the input data 4 is input to the gating circuit 10, a pulse synchronized with the edge of the input data 4 is output. When an edge pulse from the gating circuit 10 is input to a gated VCO (hereinafter referred to as G-VCO) 11 which is a gated VCO (Voltage Controlled Oscillator), the G-VCO 11 The oscillation phase is adjusted to match the phase of the edge pulse (that is, the phase of the input data 4) with the timing of the above, that is, the voltage value deviation point as a trigger. The phase-adjusted oscillation signal is output from the G-VCO 11 as a recovered clock 7 in phase with the input data 4. The reproduction clock 7 is input to a clock terminal of a flip-flop (hereinafter referred to as F / F) 3 and used for retiming of input data 4 input to a data input terminal of F / F 3. As a result, the reproduction data 6 is output from the F / F 3.

  On the other hand, the sub-VCO 12 having the same configuration as the G-VCO 11 forms a PLL (Phase-Locked Loop) together with the frequency comparator 2. The sub VCO 12 oscillates at a frequency in the vicinity of the reference clock 5 having a frequency equal to the data rate of the input data 4 or the reference clock 5 having a frequency that is a fraction of an integer of that frequency. The frequency comparator 2 compares the frequency of the output clock output from the sub-VCO 12 with the frequency of the reference clock 5. If the frequency of the output clock of the sub-VCO 12 is higher than the frequency of the reference clock 5, the frequency comparator 2 determines the oscillation frequency of the sub-VCO 12. A control signal 8 for controlling to lower is output, and if the frequency of the output clock of the sub VCO 12 is lower than the frequency of the reference clock 5, the control signal 8 for controlling to increase the oscillation frequency of the sub VCO 12 is output. The control signal 8 output from the frequency comparator 2 is supplied to the frequency control terminal of the sub-VCO 12 and simultaneously supplied to the frequency control terminal of the G-VCO 11. As a result, the frequency of the clock output from the sub-VCO 12 and the frequency of the recovered clock 7 output from the G-VCO 11 are controlled to be the same.

  According to the conventional configuration shown in FIG. 11, the data rate of the input data 4 and the frequency of the reproduction clock 7 output from the G-VCO 11 should always match, so that when the input data 4 is input, the G-VCO 11 It is sufficient to match only the phase, and it can be expected that synchronization with the input data 4 is instantly established.

M. Nogawa, et al., “A 10Gb / s Burst-Mode CDR IC in 0.13μm CMOS”, in 2005 IEEE International Solid-State Circuits Conference Digest, p.228-229, Feb.2005

  However, in order for the configuration as shown in FIG. 11 to operate ideally, it is necessary that the G-VCO 11 and the sub-VCO 12 are completely identical. Even if these VCOs are integrated on the IC with the same configuration, it is virtually impossible to form exactly the same VCO due to process variations. Therefore, in the configuration shown in FIG. 11, there is a possibility that a deviation occurs between the oscillation frequency of the sub-VCO 12 and the frequency of the reproduction clock 7 output from the G-VCO 11, thereby causing an increase in jitter. Furthermore, even if the same VCO can be configured, the oscillation frequency of the G-VCO 11 is controlled by feedforward, so that the oscillation frequency can be kept strictly constant, unlike the sub-VCO 12 that is PLL-controlled. However, there is an essential problem that jitter is increased due to frequency error. Further, in the configuration shown in FIG. 11, the phase of the reproduction clock 7 is matched with the phase of the input data 4. Therefore, if there is jitter in the input data 4, the jitter appears as it is in the reproduction clock 7 and the reproduction data 6. There was also a problem.

  An object of the present invention is to solve the above-described conventional problems and provide a CDR circuit capable of generating a reproduction clock with high frequency stability and low jitter.

The CDR circuit of the present invention matches the timing of the gating circuit that outputs a pulse when input data transitions, the first voltage-controlled oscillator arranged in the phase-locked loop, and the output pulse of the gating circuit A second voltage-controlled oscillator that outputs a reproduction clock that matches the input data by adjusting the phase of the reproduction clock, and a data identification circuit that performs data identification of the input data based on the reproduction clock And a reference clock having a frequency equal to the data rate of the input data or an output clock of the first voltage-controlled oscillator is input as an injection signal to the second voltage-controlled oscillator.
The CDR circuit of the present invention includes a gating circuit that outputs a pulse when input data transitions, a first voltage-controlled oscillator arranged in a phase locked loop, and a timing of an output pulse of the gating circuit. By adjusting the phase of the output clock to match the input data, a second voltage-controlled oscillator that outputs an output clock that matches the input data and a cascade connection is provided behind the second voltage-controlled oscillator. N (n is an integer of 1 or more) third voltage controlled oscillators that adjust the phase of the output clock so as to match the timing of the output pulses of the voltage controlled oscillator, and the data identification of the input data And a data identification circuit that performs based on a clock output from the last voltage-controlled oscillator of the third voltage-controlled oscillator, Wherein the output clock of the reference clock or said first voltage controlled oscillator rate equal frequency as an injection signal second, is characterized in that it has entered at least one of the third voltage controlled oscillator.

In one configuration example of the CDR circuit of the present invention, the second voltage controlled oscillator includes a first gate circuit in which an output of the gating circuit is input to one input terminal, and the first gate circuit. And a first feedback oscillation circuit that outputs a clock having a frequency corresponding to a frequency control signal input from the outside. The other input terminal of the first gate circuit is connected to the first input terminal. The output of the feedback oscillation circuit and the injection signal are input.
Further, in one configuration example of the CDR circuit of the present invention, the third voltage controlled oscillator inputs a second gate circuit in which one input terminal is set to a constant voltage and an output of the second gate circuit. And a second feedback oscillation circuit that outputs a clock having a frequency according to a frequency control signal input from the outside, and the output of the voltage control oscillator of the previous stage is connected to the other input terminal of the second gate circuit. And the output of the second feedback oscillation circuit and the injection signal are input.

Further, one configuration example of the CDR circuit of the present invention further includes a buffer amplifier or an attenuator for attenuating the injection signal input to at least one of the second and third voltage controlled oscillators. It is what.
Further, one configuration example of the CDR circuit of the present invention is further provided between an output terminal of the second voltage controlled oscillator and an input terminal of a leading voltage controlled oscillator among the n third voltage controlled oscillators. Buffer amplifier for attenuating the output of the voltage controlled oscillator in at least one of the n third voltage controlled oscillators between the output terminal of one voltage controlled oscillator and the input terminal of the immediately following voltage controlled oscillator Alternatively, an attenuator is provided.
Also, one configuration example of the CDR circuit of the present invention is characterized in that all the voltage controlled oscillators have the same configuration.
Further, in one configuration example of the CDR circuit of the present invention, the phase-locked loop compares the first voltage controlled oscillator with the reference clock and the output signal of the first voltage controlled oscillator to compare the frequency control signal. Is supplied to a frequency control terminal of the first voltage controlled oscillator, and the frequency comparator transmits the frequency control signal to at least one of the second and third voltage controlled oscillators. The voltage control oscillator is also supplied to a frequency control terminal.

  According to the present invention, a gating circuit that outputs a pulse when input data transitions, a first voltage-controlled oscillator arranged in a phase-locked loop, and an output pulse timing of the gating circuit are matched. A second voltage-controlled oscillator that adjusts the phase of the recovered clock, and a highly stabilized clock signal called a reference clock having a frequency equal to the data rate of the input data or an output clock of the first voltage-controlled oscillator is used as an injection signal By inputting to the second voltage controlled oscillator, it is possible to generate a recovered clock with high frequency stability and little jitter. As a result, the present invention can contribute to the improvement of the data transfer efficiency and the dynamic range of the PON system using the CDR circuit.

  In the present invention, the gating circuit that outputs a pulse when input data transitions, the first voltage controlled oscillator arranged in the phase locked loop, and the timing of the output pulse of the gating circuit are matched. A second voltage-controlled oscillator that adjusts the phase of the output clock, and cascaded behind the second voltage-controlled oscillator, and adjusts the phase of the output clock so as to match the timing of the output pulse of the voltage-controlled oscillator in the previous stage. Third voltage-controlled oscillators, and a highly stabilized clock signal called a reference clock having a frequency equal to the data rate of the input data or an output clock of the first voltage-controlled oscillator is used as the injection signals for the second and third. By inputting to at least one of the voltage controlled oscillators, a regenerated clock with higher frequency stability and less jitter can be generated. It is possible. As a result, the present invention can contribute to the improvement of the data transfer efficiency and the dynamic range of the PON system using the CDR circuit.

  Further, in the present invention, by providing a buffer amplifier or an attenuator that attenuates an injection signal input to at least one of the second and third voltage controlled oscillators, a recovered clock that is more synchronized with the phase of the input data can be obtained. Can be generated.

  Further, in the present invention, between the output terminal of the second voltage controlled oscillator and the input terminal of the leading voltage controlled oscillator among the n third voltage controlled oscillators, among the n third voltage controlled oscillators. By providing a buffer amplifier or attenuator for attenuating the output of the voltage controlled oscillator at least at one position between the output terminal of one voltage controlled oscillator and the input terminal of the immediately following voltage controlled oscillator, jitter of the recovered clock Can be further reduced.

1 is a block diagram showing a configuration of a CDR circuit according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a configuration of a G-VCO in the CDR circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows an example of a structure of VCO in the CDR circuit based on the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 5th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 6th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 7th Embodiment of this invention. It is a block diagram which shows the structure of the CDR circuit which concerns on the 8th Embodiment of this invention. It is a block diagram which shows the structure of the conventional CDR circuit.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a CDR circuit according to the first embodiment of the present invention. The CDR circuit according to the present embodiment includes a frequency comparator 2, an F / F 3, a gating circuit 10, a VCO 12, and a G-VCO 13. The difference from the conventional CDR circuit shown in FIG. 11 is that the output clock of the VCO 12 is injected as an injection signal 9 into the G-VCO 13 which is the main VCO.

  If the reference clock 5 having a frequency equal to the data rate of the input data 4 is input to the VCO 12, the frequency stability in synchronization with the reference clock 5 is very high regardless of whether or not the input data 4 is input to the CDR circuit. Output a high clock. By injecting such a highly stable clock into the G-VCO 13 as the injection signal 9, the G-VCO 13 that has been stabilized only by the feedforward control of the frequency control signal in the past is kept in a highly stable state. Therefore, even when the input data 4 includes a lot of jitter, the recovered clock 7 with reduced jitter can be recovered. The operation of the CDR circuit of this embodiment will be described in detail below.

  When the input data 4 transitions from “0” to “1”, the gating circuit 10 outputs, for example, a pulse having a width of T / 2 (T is the period of the input data 4). Alternatively, the gating circuit 10 may output a pulse when the input data 4 transitions from “1” to “0”. Thus, the gating circuit 10 detects the edge of the input data 4 and generates an edge pulse that becomes an oscillation phase control signal. The output pulse of the gating circuit 10 is input to the input terminal of the G-VCO 13.

  The phase of the recovered clock 7 output from the G-VCO 13 is controlled by the output pulse of the gating circuit 10. That is, the G-VCO 13 is reset when, for example, a pulse having a value “0” is output from the gating circuit 10, and outputs “0”. Oscillation starts as soon as it becomes “1”, and oscillation continues while the output of the gating circuit 10 is “1”. Thus, in the G-VCO 13, the phase of the reproduction clock 7 is adjusted so as to match the phase of the input data 4.

The F / F 3 serving as a data identification circuit retimes the input data 4 at a predetermined timing of the reproduction clock 7 (for example, the rising edge of the reproduction clock 7), and outputs the reproduction data 6.
On the other hand, the VCO 12 and the frequency comparator 2 constitute a frequency control circuit and oscillate at the same frequency as the reference clock 5 having the same frequency as the data rate of the input data 4.

  The control signal 8 output from the output terminal of the frequency comparator 2 is supplied to the frequency control terminal of the VCO 12 and also to the frequency control terminal of the G-VCO 13. Since the G-VCO 13 and the VCO 12 have the same circuit configuration, they oscillate at the same frequency when the same control signal 8 is supplied. Therefore, the oscillation frequency of the VCO 12 and the frequency of the recovered clock 7 are controlled to be the same. The G-VCO 13 and the VCO 12 are configured by including a gate circuit capable of controlling the oscillation start timing in a normal ring oscillation circuit configured by, for example, a multistage variable delay inverter.

  The above operation is the same as that of the conventional CDR circuit shown in FIG. 11, but in this embodiment, the output clock of the VCO 12 is further injected into the G-VCO 13 as the injection signal 9. FIG. 2 is a circuit diagram showing an example of the configuration of the G-VCO 13. The G-VCO 13 has one input terminal connected to the input terminal of the G-VCO 13 and the other input terminal connected to the output terminal and injection terminal of the G-VCO 13 and an inverter 131 that receives the output of the NAND 130 as input. And an inverter 132 whose output terminal is connected to the output terminal of the G-VCO 13, and one end of which is connected to the output terminal of the inverter 131 and the input terminal of the inverter 132, and a capacity control terminal (not shown). 2) is composed of a variable capacitance element (varactor diode) 133 connected to the frequency control terminal of the G-VCO 13.

  The VCO 12 can also be realized with the same circuit configuration as the G-VCO 13. However, in the case of the VCO 12, one input terminal of the NAND of the input stage (the input terminal that receives the edge pulse from the gating circuit 10 in the G-VCO 13 shown in FIG. 2) is pulled up, and the other input terminal of the NAND It is sufficient that only the output clock of the VCO 12 is input to. Thereby, it can be used as a VCO that constantly oscillates.

  As described above, the oscillation frequency of the VCO 12 is controlled to be the same as the frequency of the reference clock 5 by the closed loop control by the frequency comparator 2. Therefore, if the same control signal as the control signal 8 of the VCO 12 is input to the variable capacitance element 133 of the G-VCO 13, it is expected that the VCO 12 and the G-VCO 13 oscillate at the same frequency. However, strictly speaking, it is impossible to make the characteristics of the two VCOs completely the same. In addition, since the oscillation frequency of the G-VCO 13 is controlled by feedforward, the fluctuation of the oscillation frequency of the G-VCO 13 is controlled. It is very difficult to suppress this.

  Therefore, in this embodiment, the output clock of the VCO 12 is injected as the injection signal 9 into the input terminal receiving the feedback of the reproduction clock 7 out of the two input terminals of the NAND 130 in the G-VCO 13. . The oscillation frequency of the G-VCO 13 is further stabilized by being influenced by the output clock of the VCO 12 that is highly stabilized by the reference clock 5. The oscillation frequency of the G-VCO 13 is stabilized because the clock of the VCO 12 injected at the rising stage of the oscillation plays a role of the ignition of the oscillation and the stabilization means against the frequency fluctuation of the input data 4. This is to fulfill such a role. As a result, in the present embodiment, it is possible to generate a highly stable reproduction clock 7 that suppresses frequency fluctuations.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the CDR circuit according to the second embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG. The present embodiment is a modification of the first embodiment, in which an attenuator 30 is provided between the output terminal of the VCO 12 and the injection terminal of the G-VCO 13.

  According to the first embodiment, it is possible to generate a highly stable reproduction clock 7 with suppressed frequency fluctuation, but the injection signal 9 delays establishment of phase synchronization with respect to the input data 4. There are also side effects. Therefore, in the present embodiment, by providing the attenuator 30 for attenuating the injection signal 9, the phase of the recovered clock 7 is not controlled by the injection signal 9 even when the injection signal 9 becomes high level. Thus, the injection signal 9 can be weakened, and the reproduction clock 7 synchronized with the phase of the input data 4 can be generated.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing a configuration of a CDR circuit according to the third embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG. The difference between the present embodiment and the first embodiment shown in FIG. 1 is that instead of injecting the injection signal 9 from the VCO 12 into the G-VCO 13, the output terminal of the G-VCO 13 and the clock terminal of the F / F 3 The VCO 14 is provided between the two and the injection signal 9 is injected into the input terminal of the VCO 14.

  The VCO 14 preferably has the same circuit configuration as the VCO 12 and the G-VCO 13. FIG. 5 is a circuit diagram showing an example of the configuration of the VCO 14. The VCO 14 has one input terminal pulled up, the other input terminal connected to the input terminal of the VCO 14 and the output terminal of the VCO 14, an inverter 141 that receives the output of the NAND 140, and the output of the inverter 141 as input. The output terminal of the inverter 142 is connected to the output terminal of the VCO 14, one end is connected to the output terminal of the inverter 141 and the input terminal of the inverter 142, and the capacitance control terminal (not shown) is connected to the frequency control terminal of the VCO 14. The variable capacitance element 143 is formed. As described above, the injection signal 9 is injected into the input terminal of the VCO 14.

If the G-VCO 13, VCO 12, and VCO 14 have the same configuration, the three VCOs oscillate at the same frequency by inputting the control signal 8 generated by the closed loop control using the VCO 12 to the G-VCO 13 and the VCO 14 as well. It is expected.
In the present embodiment, by adding the VCO 14 to the CDR circuit of the first embodiment, even when the input data 4 includes jitter, the jitter of the recovered clock 7 can be further reduced. Can do. This jitter reduction effect is due to the fact that jitter can be reduced in two stages, the G-VCO 13 and the VCO 14 to which the injection signal 9 is input.

  Furthermore, in this embodiment, since the recovered clock 7 is generated by inputting the clock generated by the G-VCO 13 to the VCO 14 instead of the pulse from the gating circuit 10, the phase synchronization with respect to the input data 4 is further improved. It can be realized reliably. Therefore, it is possible to generate the recovered clock 7 with higher stability and less jitter.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 6 is a block diagram showing a configuration of a CDR circuit according to the fourth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. The present embodiment is a modification of the third embodiment, in which a buffer amplifier 15 is provided between the output terminal of the G-VCO 13 and the input terminal of the VCO 14.

  As the buffer amplifier 15, a buffer amplifier whose driving power is preferably weaker than that of the final stage buffer of the VCO 14 (inverter 142 in the example of FIG. 5) is used. In the present embodiment, provision of the buffer amplifier 15 makes it possible to suppress transmission of unnecessary signal components such as jitter to the VCO 14. The phase of the recovered clock 7 output from the VCO 14 is adjusted to match the phase of the output clock of the G-VCO 13 (that is, to match the phase of the input data 4), but the influence of the G-VCO 13 is small. Therefore, the phase of the output clock of the G-VCO 13 does not follow instantaneously. Therefore, even when there is jitter in the input data 4, it is difficult to be affected by this jitter, so that the jitter of the recovered clock 7 can be reduced.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 7 is a block diagram showing a configuration of a CDR circuit according to the fifth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. This embodiment is a modification of the third embodiment, in which a buffer amplifier 16 is provided between the output terminal of the VCO 12 and the input terminal of the VCO 14.

  In the present embodiment, by providing the buffer amplifier 16 for attenuating the injection signal 9, the injection signal 9 is injected so that the phase of the recovered clock 7 is not controlled by the injection signal 9 even when the injection signal 9 becomes high level. The level of the signal 9 can be adjusted, and a recovered clock 7 that is more synchronized with the phase of the input data 4 can be generated.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of a CDR circuit according to the sixth embodiment of the present invention, and the same reference numerals are given to the same configurations as those in FIGS. This embodiment is a modification of the third embodiment, in which an attenuator 31 is provided between the output terminal of the VCO 12 and the input terminal of the VCO 14.

  In the present embodiment, by providing the attenuator 31 for attenuating the injection signal 9, the level of the injection signal 9 can be adjusted so that the phase of the recovered clock 7 is not controlled by the injection signal 9. A reproduction clock 7 that is more synchronized with the phase can be generated.

  In addition, you may combine 4th Embodiment and 5th Embodiment, and you may combine 4th Embodiment and 6th Embodiment. Further, the buffer amplifier 15 of the fourth embodiment may be replaced with an attenuator.

[Seventh Embodiment]
Next, a seventh embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of the CDR circuit according to the seventh embodiment of the present invention, and the same reference numerals are given to the same configurations as those in FIGS. The difference between this embodiment and the fourth embodiment shown in FIG. 6 is that the injection signal 9 is also injected into the injection terminal of the G-VCO 13.

  In the present embodiment, a VCO 14 is provided in the same manner as in the third embodiment, and an injection signal 9 is injected into the input terminal of the VCO 14, and at the injection terminal of the G-VCO 13 as in the first embodiment. Further, by injecting the injection signal 9 and further providing the buffer amplifier 15 as in the fourth embodiment, it is possible to reduce the jitter of the recovered clock 7 and more reliably realize phase synchronization with the input data 4. Therefore, a further highly stable operation can be achieved.

[Eighth Embodiment]
Next, an eighth embodiment of the present invention will be described. FIG. 10 is a block diagram showing a configuration of a CDR circuit according to the eighth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. The difference between this embodiment and the fifth embodiment shown in FIG. 7 is that the injection signal 9 is also injected into the injection terminal of the G-VCO 13, and that the output terminal of the VCO 12 and the injection of the G-VCO 13 are The attenuator 31 is provided between the terminal and the input terminal of the buffer amplifier 16.

  In the present embodiment, a VCO 14 is provided as in the third embodiment, a buffer amplifier 16 is provided between the output terminal of the VCO 12 and the input terminal of the VCO 14 as in the fifth embodiment, and the Similarly to the sixth embodiment, the injection signal 9 is injected into the injection terminal of the G-VCO 13 and the input terminal of the buffer amplifier 16 through the attenuator 31, thereby reducing the jitter of the reproduction clock 7 and the input data 4 Therefore, it is possible to realize the phase synchronization with respect to the above in a more reliable manner, and to achieve a further highly stable operation.

  Note that the present invention is not limited to the seventh and eighth embodiments, and in the seventh embodiment, a buffer amplifier and an attenuator are further provided in the injection path of the injection signal 9 as in the eighth embodiment. It does not matter. The buffer amplifier 16 in the eighth embodiment may be an attenuator. The injection signal 9 may be injected by any one of the G-VCO 13 and the VCO 14.

  In the first to eighth embodiments, the output clock of the VCO 12 is used as the injection signal 9. However, the present invention is not limited to this, and the reference clock 5 having a frequency equal to the data rate of the input data 4 is injected. It may be used as the signal 9.

In the third to sixth embodiments, the G-VCO 13 may inject the injection signal 9.
Further, n VCOs 14 (n is an integer of 1 or more) may be connected in cascade. Further, a buffer amplifier or an attenuator may be provided between the output terminal of one VCO 14 and the input terminal of the VCO 14 immediately after that.

  The present invention can be applied to a technique for reproducing a clock that is phase-synchronized with input data and performing retiming of the input data using this clock.

  2 ... frequency comparator, 3 ... flip-flop, 4 ... input data, 5 ... reference clock, 6 ... reproduction data, 7 ... reproduction clock, 8 ... control signal, 9 ... injection signal, 10 ... gating circuit, 12, 13 , 14 ... VCO, 15, 16 ... buffer amplifier, 30, 31 ... attenuator.

Claims (8)

A gating circuit that outputs a pulse when input data transitions;
A first voltage controlled oscillator disposed in a phase locked loop;
A second voltage-controlled oscillator that outputs a reproduction clock that is in timing with the input data by adjusting the phase of the reproduction clock so as to match the timing of the output pulse of the gating circuit;
A data identification circuit for performing data identification of the input data based on the recovered clock,
A CDR circuit, wherein a reference clock having a frequency equal to a data rate of the input data or an output clock of the first voltage controlled oscillator is inputted as an injection signal to the second voltage controlled oscillator. A gating circuit that outputs a pulse when input data transitions;
A first voltage controlled oscillator disposed in a phase locked loop;
A second voltage-controlled oscillator that outputs an output clock that is in timing with the input data by adjusting the phase of the output clock to match the timing of the output pulse of the gating circuit;
N (n is an integer of 1 or more) third voltages that are cascade-connected behind the second voltage controlled oscillator and adjust the phase of the output clock so as to match the timing of the output pulse of the preceding voltage controlled oscillator. A controlled oscillator;
A data identification circuit for performing data identification of the input data based on a clock output from the last voltage-controlled oscillator among the n third voltage-controlled oscillators,
A reference clock having a frequency equal to the data rate of the input data or an output clock of the first voltage controlled oscillator is inputted as an injection signal to at least one of the second and third voltage controlled oscillators. CDR circuit. The CDR circuit according to claim 1 or 2,
The second voltage controlled oscillator is:
A first gate circuit in which an output of the gating circuit is input to one input terminal;
An output of the first gate circuit is used as an input, and the first feedback oscillation circuit outputs a clock having a frequency corresponding to a frequency control signal input from the outside.
A CDR circuit, wherein the output of the first feedback oscillation circuit and the injection signal are input to the other input terminal of the first gate circuit. The CDR circuit according to claim 2 or 3,
The third voltage controlled oscillator includes:
A second gate circuit in which one input terminal is set to a constant voltage;
An output of the second gate circuit is used as an input, and the second feedback oscillation circuit outputs a clock having a frequency corresponding to a frequency control signal input from the outside.
A CDR circuit, wherein an output of a previous voltage-controlled oscillator, an output of the second feedback oscillation circuit, and the injection signal are input to the other input terminal of the second gate circuit. The CDR circuit according to any one of claims 1 to 4,
The CDR circuit further comprises a buffer amplifier or an attenuator for attenuating the injection signal input to at least one of the second and third voltage controlled oscillators. The CDR circuit according to any one of claims 1 to 5,
Further, between the output terminal of the second voltage controlled oscillator and the input terminal of the leading voltage controlled oscillator among the n third voltage controlled oscillators, 1 of the n third voltage controlled oscillators. A CDR circuit comprising a buffer amplifier or an attenuator for attenuating the output of the voltage controlled oscillator at at least one position between the output terminal of each voltage controlled oscillator and the input terminal of the immediately following voltage controlled oscillator. The CDR circuit according to any one of claims 1 to 6,
A CDR circuit characterized in that all the voltage controlled oscillators have the same configuration. The CDR circuit of claim 7,
The phase-locked loop is
The first voltage controlled oscillator;
A frequency comparator that compares the reference clock with an output signal of the first voltage controlled oscillator and supplies a frequency control signal to a frequency control terminal of the first voltage controlled oscillator;
The CDR circuit supplies the frequency control signal to a frequency control terminal of at least one of the second and third voltage controlled oscillators.

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