JP5105359B2 - Central processing unit, selection circuit and selection method - Google Patents

Description

  The present invention relates to a central processing unit, a selection circuit, and a selection method.

  2. Description of the Related Art Conventionally, techniques such as CMP (Chip-level Multi Processor) and SMT (Simultaneous Multi-Thread) are known as techniques for improving multi-thread processing capability. Specifically, CMP and SMT are techniques for executing a plurality of threads in parallel in space or time. Here, the program is composed of at least one thread (usually a plurality), and the thread is an execution unit of the program. For example, when the CPU supports multi-thread execution, processing is performed for each thread.

  CMP is a technology in which a plurality of cores are mounted on one CPU die (semiconductor body) for the purpose of performing multi-thread execution, and each core executes its own thread. For example, in CMP, as shown in (1) of FIG. 9, a plurality of cores are mounted on one CPU die, and the plurality of cores share a large-capacity L2 cache. With such a configuration, in CMP, each core executes its own thread, thereby executing a plurality of threads in parallel in space or time.

  In addition, SMT is a technique for executing a plurality of threads simultaneously by causing a single-core CPU to act as a plurality of CPUs (in other words, one core as a plurality of cores) for the purpose of performing multi-thread execution. It is. For example, in SMT, as shown in (2) of FIG. 9, one core is mounted on one CPU die. In such a configuration, in SMT, one core behaves as two cores, thereby executing two threads in parallel spatially or temporally. Note that Patent Document 1 describes various data (for example, data to be used in order for the CPU to execute one thread and then execute the other thread when the processor environment is switched in the SMT. A technique for reducing a load when performing a process of changing a stored register address or the like) is disclosed.

  Conventionally, as a technique for improving the performance of a single thread (a technique for improving the processing speed of individual threads when processing multiple threads in parallel), a thread (hereinafter referred to as this A technique for improving the performance of this thread by executing a subset of a thread (described as a thread) in advance as another thread (hereinafter referred to as a preceding sub thread) is known. Here, a thread is an aggregate of a plurality of instructions. In addition, this thread is a thread targeted for performance improvement among the threads. For example, when executing this thread, it is necessary to execute the preceding sub-thread for the purpose of omitting the process of fetching necessary data from the memory (or shortening the fetching process time). The performance of a single thread is improved by prefetching the correct data from memory.

  As a technique for improving the performance of a single thread as described above, for example, Non-Patent Document 1 discloses a technique called “Slip Stream” (hereinafter referred to as “SS” in the present specification). Non-Patent Document 2 discloses a technique called Dynamic Specific Pre-computation (hereinafter referred to as “DSP” in the present specification).

  Here, the techniques such as “SS” and “DSP” will be described in more detail. In these techniques (“SS” and “DSP”), after the instructions constituting this thread are retired (after execution of this thread), the data sub-analysis between the instructions is performed to select the preceding sub thread. . In other words, in these technologies (“SS” and “DSP”), after executing each instruction of this thread, the execution result obtained as a result of executing each instruction and the data used in each instruction are transferred to other threads. Determine whether it will be used when executing. In these technologies (“SS” and “DSP”), there is a data dependency relationship from the thread (this thread) to improve performance after grasping the data dependency relationship between the instructions in this way. An instruction is detected, and the detected instruction is selected as a preceding subthread. For example, in these technologies (“SS” and “DSP”), when this thread is composed of the instruction (1) to the instruction (8), the instruction (1) and the instruction having a data dependency relationship ( For example, the instruction (6), (7) and (8)) is detected, and the detected instruction is selected as the preceding sub thread (instruction (1), (6), (7) and (8)).

  Further, “SS” will be described with a specific example. In “SS”, (1) an instruction (Un-referenced writes) whose result is not referred to by a subsequent instruction, and (2) the same value as before the update. Are detected at the time of instruction retirement (non-modifying writes) and (3) branch instructions with easy branch prediction. Thereafter, in “SS”, the data dependence analysis between instructions is retroactively performed. At this time, in “SS”, the instructions ((1) to (3)) and an instruction that selects only data necessary for executing the instruction are removed from the thread. In “SS”, the remaining instruction is selected as the preceding sub-thread.

  Further, “DSP” will be described with a specific example. In “DSP”, (4) an instruction that frequently causes a cache miss (Cache-miss) is detected at the time of instruction retirement. Thereafter, in the “DSP”, the data dependence analysis between each instruction is retroactively performed. At this time, the instruction ((4)) and an instruction that selects data necessary for executing the instruction are selected as preceding sub-threads.

Japanese Patent Laid-Open No. 2005-284749 Slip Stream K.M. Sundaramoorty, Z. Purser, and E.M. Rotenberg, “Slipstream Processors: Improving both Performance and Fault Tolerance”, in 9th ASPLOS, Nov. 2000. FIG. 1 Dynamic Special Pre-computation Jamison D.D. Collinsy, Dean M. Tullseny, Hong Wangz, John P .; Shenzy, “Dynamic-Specific Precomputation”, in 34th International Symposium on Micro-architecture, December, 2001. FIG. 1

  By the way, as described below, the conventional technique described above has a problem that a preceding sub thread cannot be selected from the thread that has never been executed.

  Specifically, in the above-described conventional techniques (“SS” and “DSP”), the data dependency analysis between instructions is performed at the time of retirement of the instructions constituting this thread, so that the preceding subthread is identified and selected. A preceding sub thread cannot be selected from this thread that has never been executed. In other words, in the conventional technique (“SS” or “DSP”), the preceding sub-thread is selected after this thread is executed at least once, and from this thread that has never been executed, The predecessor subthread cannot be selected.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and a central processing unit, a selection circuit, and a selection circuit capable of selecting a preceding sub-thread from this thread that has never been executed. The purpose is to provide a selection method.

  In order to solve the above-described problems and achieve the object, the present invention executes one or a plurality of threads that execute a main thread including a plurality of instructions to be executed and prefetch information necessary for a predetermined thread. Is selected from the main thread as a preceding sub-thread and executed prior to the predetermined thread, and the relationship between the instructions obtained by analyzing the execution result of the main thread is as follows: And selecting means for selecting the preceding sub-thread by discriminating the contents instructed by each instruction constituting the thread to the central processing unit.

  Also, the present invention is characterized in that, in the above-mentioned invention, the selection means selects the preceding sub-thread by determining each instruction type constituting the thread as the content.

  Further, the present invention is the above invention, wherein the selecting means determines whether the instruction type corresponds to a store instruction or a floating point arithmetic instruction for storing data stored in a register in a memory, and does not correspond to the instruction The preceding sub-thread is selected by selecting.

  According to the present invention, it is possible to select a preceding sub-thread from this thread that has never been executed.

  Further, according to the present invention, it is possible to easily select the preceding sub thread by simply confirming the instruction type.

  Furthermore, according to the present invention, it is possible to easily select a preceding subthread by simply excluding store instructions and floating point instructions.

  Exemplary embodiments of a central processing unit, a selection circuit, and a selection method according to the present invention will be described below in detail with reference to the accompanying drawings. In the following, the main terms used in the present embodiment, the outline and features of the preceding sub-thread identification circuit according to the present embodiment, the configuration of the central processing unit and the flow of processing will be described in order, and finally various types of the present embodiment will be described. A modified example will be described.

[Explanation of terms]
First, main terms used in this embodiment will be described with reference to FIG. FIG. 9 is a diagram for explaining CMP and SMT. “CPU (Central Process Unit) (corresponding to“ Central processing unit ”described in the claims”) used in the present embodiment is one of the components constituting the computer, and controls and data of each device. Calculate and process. For example, the CPU executes a program stored in a memory, receives data from an input device or a storage device, calculates and processes the data, and outputs the data to an output device or a storage device. The CPU is a CPU die (semiconductor body) on which a core is mounted. The core is an internal circuit that is the core of the CPU, and is a unit in which units related to arithmetic processing such as an arithmetic circuit, a cache memory, and a register are integrated.

  Further, the CPU used in the present embodiment performs multi-thread execution, and for example, this is CMP (Chip-Level Multi Processor) or SMT (Simultaneous Multi-Thread). Here, the program is composed of at least one thread (usually a plurality), and the thread is an execution unit of the program. For example, when the CPU supports multi-thread execution, the CPU performs processing for each thread.

  CMP is a technique in which a plurality of cores are mounted on one CPU die (semiconductor body) in order to perform multi-thread execution, and each core independently executes a thread. For example, in CMP, as shown in (1) of FIG. 9, a plurality of cores are mounted on one CPU die, and the plurality of cores share a large-capacity L2 cache. With such a configuration, in CMP, each core executes its own thread. In addition, in order to perform multi-thread execution, the SMT is configured such that one core CPU behaves as two CPUs (in other words, one core as a plurality of (for example, two) cores), and a plurality of execution threads. Is a technology for simultaneously executing

  In SMT, as shown in (2) of FIG. 9, one core is mounted on one CPU die. With this configuration, in SMT, one core behaves as two cores, thereby executing a plurality of execution threads simultaneously. Note that CMP and SMT are not alternatives, and both can be applied simultaneously.

  Here, for example, even when a program is divided into a plurality of threads and is processed for each thread when supporting multi-thread execution, if the CPU does not support multi-thread execution, the program is a single thread. (As one thread (execution unit) without being divided into a plurality of threads). A thread is an aggregate of a plurality of instructions. In addition, this thread is a thread targeted for performance improvement among the threads.

  The instruction type used in the present embodiment is the kind of content that the above-described instruction instructs the CPU. For example, a “load instruction” for loading data into a register file from a memory (for example, a cache or a memory provided outside the CPU), a “store instruction” for storing data stored in a register file in the memory, There are “floating point arithmetic instructions” for expressing numerical values by “mantissa part” which is a sequence of values of each digit and “exponent part” which represents the position of the decimal point.

  The above-mentioned multi-thread execution is to execute a plurality of execution threads simultaneously. For example, in multi-thread execution in CMP, each of a plurality of cores mounted on one CPU die executes a thread so that one CPU performs a plurality of processes simultaneously. Also, for example, in multi-thread execution in SMT, one CPU (one core) performs multiple processes simultaneously by dividing the CPU processing time into very short units and assigning them to multiple threads in order. It's what it looks like.

  In addition, the CPU used in this embodiment will be described as performing out-of-order execution.

  The above-mentioned out-of-order execution is to execute a plurality of instructions that are not dependent on each other one after another regardless of the order of appearance in the program. In other words, out-of-order execution is a mechanism in which execution is performed from an instruction having data necessary for processing, regardless of the order of instructions described in the program. For example, in out-of-order execution, even if data necessary for the previous instruction processing is not prepared, if data necessary for the subsequent instruction processing is prepared, the subsequent instruction is executed first. In-order execution is executed one after another according to the order of appearance in the program. In other words, in-order execution is a mechanism for executing according to the order of instructions described in a program. The CPU used in this embodiment is described as performing out-of-order execution, but may be performing in-order execution.

  Prefetch is a function in which the CPU reads data in advance into the cache memory.

[Outline and features of preceding sub-thread identification circuit]
First, the outline and features of the preceding subthread identification circuit 11 (corresponding to the “selection circuit” recited in the claims) provided in the CPU 100 according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining the outline and features of the preceding subthread identification circuit.

  As shown in the figure, the CPU 100 according to the first embodiment includes a Decode 10, a preceding sub-thread identification circuit 11, and a Queue 12, which are closely related to the present invention. Here, the Queue 12 stores an instruction waiting to be processed.

  With such a configuration, the CPU 100 according to the first embodiment executes one or a plurality of threads that execute a main thread including a plurality of instructions to be executed and prefetch information necessary for a predetermined thread. This is an overview of selecting an instruction as a preceding subthread (corresponding to the “preceding subthread” recited in the claims) from this thread and executing it in advance of a predetermined thread. The main feature is that it is possible to select a preceding sub-thread from a thread.

  Since this feature is mainly realized by the preceding subthread identifying circuit 11, the following description will focus on the preceding subthread identifying circuit 11, and the execution of this thread in the CPU 100 according to the first embodiment will be described. Will not be described.

  First, in the CPU 100 according to the first embodiment, as illustrated in (1) of FIG. 1, the Decode 10 interprets what the instruction is and transmits the instruction to the preceding subthread identification circuit 11. For example, in the example shown in (1) of FIG. 1, the Decode 10 interprets the contents of each instruction and transmits the instructions (1) to (8) constituting this thread to the preceding subthread identification circuit 11.

  Next, in the CPU 100 according to the first embodiment, as shown in (2) of FIG. 1, the preceding sub-thread identification circuit 11 is not a relationship between instructions obtained by analyzing the execution result of this thread. The preceding sub-thread is selected by discriminating the contents instructed to the CPU 100 by each instruction constituting this thread. For example, in the example shown in (2) of FIG. 1, the preceding sub-thread identification circuit 11 determines a predetermined instruction type, and instructions (1) and (6) which are instructions that are not store instructions or floating-point arithmetic instructions. , (7) and (8) are selected as preceding sub-threads.

  In the CPU 100 according to the first embodiment, the preceding subthread identification circuit 11 transmits only the preceding subthread to the Queue 12 as illustrated in (3) of FIG.

  Here, as described above, the preceding sub-thread identification circuit 11 is executed in a configuration added for multi-thread execution, and thus operates independently of this thread. Then, the preceding subthread identification circuit 11 decodes the instruction of the preceding subthread, identifies an instruction necessary as the preceding subthread according to the decoded instruction type, and transmits it to the Queue 12.

  For this reason, the CPU 100 according to the first embodiment can select the preceding sub-thread from the main thread that has never been executed, as described above.

  In other words, in the conventional method, the CPU selects and executes the preceding subthread by performing data dependency analysis between instructions after the instructions constituting this thread are retired (after execution of this thread). It was. In other words, in the conventional method, an instruction that has never been executed by the thread cannot be executed in advance as a sub thread, which is a limitation on the performance improvement of the thread. In contrast to such a conventional method, the CPU according to the first embodiment can select the preceding sub-thread independently of the execution of this thread regardless of whether or not this thread is executed. There is a feature in a certain point.

[CPU configuration]
Next, the configuration of the CPU 100 according to the first embodiment will be described with reference to FIGS. Here, FIG. 2 is a block diagram showing the configuration of the central processing unit (CMP). FIG. 3 is a diagram illustrating an example of a source, a main thread string, and a preceding sub thread string. FIG. 4 is a diagram illustrating an example of a circuit diagram of the preceding subthread identification circuit 29. FIG. 5 is a diagram for explaining the effect of the preceding subthread identification circuit. In the following, the configuration of the CPU 100 when the present invention is applied to CMP will be described unless otherwise specified.

  First, the connection relationship between each component which comprises CPU100 is demonstrated easily. As shown in FIG. 2, the L2 cache 20 is connected to an I cache 21 and a D cache 23. The I cache 21 is connected to the L2 cache 20, the PC 26, and the Decode 27. Further, the Queue 22 is connected to the Decode 27 and the ROB 24. The D cache 23 is connected to the ROB 24 and the EX 28. The ROB 24 is connected to the Queue 22, the RF 25, the D cache 23, and the EX 28. The RF 25 is connected to the ROB 24. The PC 26 is connected to the I cache 21. The Decode 27 is connected to the I cache 21 and the Queue 22. The EX 28 is connected to the ROB 24, the D cache 23, and the RF 25.

  The L2 (level2) cache is a type of cache memory provided inside the CPU (outside the core), and stores frequently used instructions and data. For example, the L2 cache 20 stores the instructions (1) to (8) shown in FIG. 3 and data (operands) used for instruction execution.

  The I (instruction) cache is a type of cache memory provided in the CPU (inside the core) and stores instructions. For example, the I cache 21 stores the instructions (1) to (8) shown in FIG. Since the I cache 21 is provided inside the core, the PC 26 described later is a cache that is accessed at a higher speed than the L2 cache 20 installed outside the core.

  The Queue 22 is used when waiting for some processing, and specifically stores an instruction waiting to be processed by the EX 28 described later. For example, Queue 22 executes an instruction interpreted by Decode 27, which will be described later, in an in-order rather than an original execution order (in the case of executing out-of-order) In the order of instruction execution).

  The D cache 23 is a type of cache memory provided in the CPU (inside the core), and stores data (operands). Specifically, the contents of the designated address of the D cache 23 are transferred to the ROB 24 described later by the load instruction. Further, the contents of ROB 24 to RF 25 described later are transferred to a specified address of the D cache 23 by a store instruction.

  The ROB 24 (Reorder Buffer) is a buffer provided in the CPU (inside the core) having an out-of-order execution function, and is assigned to instructions stored in the queue, and the instructions are executed out of order. The execution result of the obtained instruction is stored. The ROB 24 supplies source data (operands) necessary for execution of instructions to the EX 28 described later together with the RF 25 described later.

  RF25 (Register File) is a storage element provided in the CPU (inside the core), and is used to hold computations and execution states. For example, data (operand) (for example, when using execution results of other instructions) ) And instruction execution results are stored. Specifically, the execution results of the instructions stored in the ROB 24 are transferred to the RF 25 in the order corresponding to the original execution order when the instructions are committed. At this time, the execution result stored in the ROB 24 is deleted. The RF 25, together with the ROB 24, supplies data (operands) necessary for executing the instruction to the EX 28 described later.

  The PC (instruction control unit) 26 reads (fetches) an instruction from the I cache 21. For example, when the instruction execution timing comes, the PC (instruction control unit) 26 checks whether or not the instruction to be executed is stored in the I cache 21, and if it is stored, reads the instruction to be executed. On the other hand, for example, when the instruction to be executed is not stored in the I cache 21, the PC (instruction control unit) 26 reads the instruction to be executed from the L2 cache 20 and stores the instruction in the I cache 21. Read instructions, etc. In addition, when the instruction to be executed is not stored in the L2 cache 20, the PC (instruction control unit) 26 reads the instruction to be executed from a memory (not shown) provided outside the CPU, and the L2 cache 20 and stored in the I cache 21, and reads an instruction from the I cache 21.

  The Decode 27 interprets what the instruction is (instruction interpretation). For example, when the instruction to be executed is read by the PC 26, the Decode 27 interprets the read instruction. Then, the Decode 27 determines whether or not the Queue 22 has a space. Here, when there is a vacancy in Queue 22, a control signal for executing processing necessary to execute the instruction is sent to Queue 22 in the original execution order. On the other hand, if there is no vacancy in Queue 22, the Decode 27 determines whether there is a vacancy until it is available. The ROB 24 assigns an entry for storing a result when the instruction is stored in the Queue 22.

  The EX 28 obtains an operand necessary for executing the corresponding instruction from the ROB 24 to RF 25. For example, the EX 28 requests the operands required for the ROB 24 to the RF 25 for the instruction stored in the Queue 22. If the instruction is an operation instruction, the EX 28 performs an operation using the obtained operand and stores the result in the assigned ROB 24. On the other hand, if the instruction is a load instruction, the EX 28 performs address calculation using the acquired operand, and requests (requests) data of the corresponding address from the D cache 23. Here, when the necessary data is stored in the D cache 23, the EX 28 acquires the data and stores the acquired data in the assigned ROB 24. On the other hand, the EX 28 requests (requests) the necessary data from the L2 cache 20 when the necessary data is not stored in the D cache 23. Here, when the necessary data is stored in the L2 cache 20, the EX 28 acquires the data, stores the acquired data in the D cache 23, and stores it in the assigned ROB 24. On the other hand, if the necessary data is not stored in the L2 cache 20, the EX 28 waits until the necessary data is stored in the cache or buffer that issued the request. When necessary data is stored, the data is acquired and stored in the assigned ROB 24. To explain in more detail, when the required operand is the execution result of another instruction, the EX 28 executes the other instruction and stores the execution result in the ROB 24. Execution result). If the execution result has already been transferred from the ROB 24 to the RF 25, it is acquired from the ROB 25.

  In the present embodiment, the above-described relationship between EX28, L2 cache 20, Dcache 23, ROB24, and RF25 is used, but the present invention is not limited to this, and EX28 ( Alternatively, the CPU 100) may acquire the operand from an arbitrary cache or buffer. For example, in this embodiment, a case where a two-level cache of an L2 cache and a D cache is provided will be described, but an L3 cache may be provided.

  Further, EX28 (Execution Unit) selects an instruction that can be executed from the instructions stored in the queue, and assigns a processing capacity. For example, the EX 28 determines whether there is a vacancy in the processing capacity of the EX 28. Here, if there is no space in the processing capacity of the EX 28, the EX 28 continues the determination until there is space. On the other hand, when the processing capacity of the EX 28 is available, the EX 28 acquires an instruction that can be executed immediately from the instructions waiting for execution stored in the queue, and assigns the processing capacity. More specifically, the EX 28 acquires, as instructions that can be executed immediately, ones in which operands necessary for executing the instructions are stored in the ROB 24 to RF 25.

  The EX 28 executes (calculates) the instruction. For example, the EX 28 obtains an operand necessary for executing an instruction to which processing capability is assigned from the ROB 24 to RF 25 and executes the instruction. For example, the EX 28 stores the execution result obtained by executing the instruction in the ROB 24.

  Further, the ROB 24 stores the execution results in the RF 25 in an order corresponding to the original execution order. For example, when there is a commit (when it is determined that the processing of the corresponding instruction is to be completed), the ROB 24 transfers the execution results stored in the ROB 24 to the RF 25 in the order corresponding to the original execution order. To do. More specifically, the EX 28 stores the execution result of the instruction 1 shown in FIG. 3 in the ROB 24, then stores the execution result of the instruction 3 in the ROB 24, and then stores the execution result of the instruction 4 in the ROB 24. Then, the execution result of the instruction 2 is stored in the ROB 24, and when there is a commit, the execution result is stored in the RF 25 in the order of the instruction 1, the instruction 3, the instruction 4, and the instruction 2 that are stored in the ROB 24. Instead, the execution result is transferred from the ROB 24 to the RF 25 using the order of the instruction 1, the instruction 2, the instruction 3, and the instruction 4, which is the original execution order.

  The configuration of the CPU described above is a configuration used when executing this thread, and is a configuration that functions in accordance with the conventional technology. Next, a configuration for selecting and executing a preceding sub thread in the present invention will be described. As shown in FIG. 2, I cache 21 (m), Queue 22 (m), D cache 23 (m), D cache 23 (m), ROB 24 (m), RF 25 (m) and EX 28 (m) are This is a configuration added to realize the multi-thread execution function. In the CPU according to the first embodiment, the preceding sub-red identification circuit 29 is provided between the Decode 27 (m) and the Queue 22 (m) for the purpose of selecting the preceding sub-thread in addition to such a configuration of the CPU. ") Corresponding to the" selection circuit "described in the range. In the following description, portions different from the configuration that functions in accordance with the conventional technology will be mainly described, and similar portions will be simply described or description thereof will be omitted.

  First, the connection relation in the configuration added for multi-thread execution used when executing the preceding sub thread according to the present invention will be briefly described. As shown in FIG. 2, the Decode 27 (m) is connected to the I cache 21 (m) and the preceding subthread identification circuit 29. The preceding subthread identification circuit 29 is connected to the Decode 27 (m) and the Queue 22 (m). Further, the Queue 22 (m) is connected to the preceding sub thread identification circuit 29 and the ROB 24 (m).

  The I cache 21 (m) has the same function as the I cache 21, the PC 26 (m) has the same function as the PC 26 and performs the same processing, and the Decode 27 (m) is the same as the Decode 27. It has a function and performs the same processing.

  The D cache 23 (m) stores operands necessary for executing the preceding subthread determined by the preceding subthread identifying circuit 29 described later.

  The ROB 24 (m) is assigned to the preceding subthread determined by the preceding subthread identification circuit 29 described later and stored in the queue, and stores an operand used by the assigned preceding subthread. Further, the ROB 24 (m) stores an execution result obtained by executing the preceding sub thread out of order.

  The RF 25 (m) is a storage element provided in the CPU and used for holding computations and execution states, and stores data. Specifically, the execution result of the preceding sub-thread executed by EX28 (m) described later and stored in ROB 24 (m) is transferred from ROB 24 (m) to RF 25 (m) in the order corresponding to the original execution order. Is done.

  The Queue 22 (m) stores the preceding subthread determined by the preceding subthread identification circuit 29.

  The preceding subthread identification circuit 29 discriminates not the relationship among the threads obtained by analyzing the execution result of this thread, but the contents instructed by the instructions constituting the thread to the central processing unit, and determines the preceding subthread. Select. For example, the preceding subthread identifying circuit 29 selects the preceding subthread by determining each instruction type as the content. As a more detailed example, the preceding subthread identification circuit 29 determines whether the instruction type corresponds to a store instruction or a floating-point operation instruction for storing data stored in the register in the memory, and determines an instruction that does not correspond to the instruction. Select the preceding sub-thread by selecting it.

  Here, the preceding subthread identification circuit 29 by the preceding subthread identification circuit 29 will be further described. The preceding subthread identification circuit 29 determines the preceding subthread from this thread without using the dependency relationship between the instructions. For example, the preceding subthread identifying circuit 29 determines the preceding subthread using only the instruction type without using the data dependency between the instructions. For example, when the instruction type of each instruction of this thread is decoded by the Decode 27 (m) and sent to the Queue 22 (m), the preceding sub-thread identification circuit 29 determines whether the sent instruction is stored in advance. It is determined whether they match (or do not match), a matching instruction (or non-matching instruction) is determined as a preceding subthread, and only the preceding subthread is sent to Queue 22 (m).

  Here, the preceding subthread identification circuit 29 will be described with reference to FIGS. 3 and 4 in more detail. For example, as shown in FIG. 3, when the source shown in (S) below is used, the source is compiled and recognized as the main threads shown in (1) to (8) below as shown in FIG. Is done.

  Here, in the source shown in FIG. 3 (below (S)), “i” is a variable, which indicates that the source is executed after changing from 1 to 1000000 and the process is terminated. Also, in the thread shown in FIG. 3 ((1) to (8) below), “R1” indicates the start address in the array X, “R2” indicates the start address of the array Y, and “R3” indicates , Variable “i” × 4 (bytes), “R4” indicates 1000000—variable “i”, and “FR” indicates a register file.

  Furthermore, the contents of each thread (the following (1) to (8)) shown in FIG. 3 will be described. The instruction (1) is an instruction for storing, in FR1 (register file “1”), the data stored at the address in the memory array X indicated by the value obtained by adding R3 to R1. The instruction (2) is a floating point arithmetic instruction that multiplies the value stored in FR1 by the value stored in FR2 and stores the result of the operation in FR3. The instruction (3) is a floating point arithmetic instruction that adds the value stored in the FR3 and the value stored in the FR4 and stores the operation result in the FR5. The instruction (4) is a floating point arithmetic instruction that divides the value stored in FR6 with respect to the value stored in FR5 and stores the result of the operation in FR7. The instruction (5) is a store instruction for storing the value stored in the FR7 at the address in the memory array Y indicated by the value obtained by adding R3 to R2. The instruction (6) is an instruction for adding 8 to R3. The instruction (7) is an instruction for subtracting 1 from R4. The instruction (8) is an instruction for repeating the processes of the instructions (1) to (8) when R4 is larger than 0.

(S) do i = 11,000,000 Y (i) = (X (i) * B + C) / D) end do
(1) [R1 + R3] → FR1
(2) FR1 × FR2 → FR3
(3) FR3 + FR4 → FR5
(4) FR5 / FR6 → FR7
(5) FR7 → [R2 + R3]
(6) R3 + 8 → R3
(7) R4-1 → R4
(8) Branch Loop if R4> 0

  Here, the source is a source code (program) written using a high-level language. A high-level language is a general term for programming languages that have syntax and concepts that are close to natural language and easy for humans to understand. For example, in a high-level language, source code is mainly described by combining English words and symbols, and a compiler or the like converts (compiles) the source code described in the high-level language into a machine language, and processes a processor (for example, CPU) executes the source code converted into the machine language. Compiling means converting the source code of a program created by a human using a programming language (for example, a high-level language) into a machine language that can be executed on a computer.

  Here, as shown in FIG. 4, when the instruction whose instruction type is decoded by the Decode 27 (m) is sent to the preceding subthread identification circuit 29, the sent instruction is changed to a floating point arithmetic instruction (instruction (2)). To (4)) or a memory store instruction (instruction (5)), the switch is turned on ((1) in FIG. 4), and the instruction is not sent to Queue 22 (m) (((4) in FIG. 4)). 2)). On the other hand, if the sent instruction is not a floating point operation instruction or a memory store instruction, the preceding subthread identification circuit 29 determines that the instruction is an instruction constituting the preceding subthread, and the switch is turned OFF (FIG. 4). (3)). Then, the preceding subthread identification circuit 29 converts the instructions (1), (6) to (8) into the instructions (a) to (d) (instruction (1) constituting the preceding subthread as shown in FIG. ), (Corresponding to (6) to (8)), it is sent (stored) to Queue 22 (m). The ROB 24 (m) assigns an entry for storing the result when each instruction is stored in the Queue 22 (m).

  The EX 28 (m) acquires the operands necessary for executing the corresponding instruction from the ROB 24 (m) to the RF 25 (m). The EX 28 (m) selects an instruction that can be executed immediately from the preceding sub-threads selected by the preceding sub-thread identification circuit 29 and stored in the Queue 22 (m), and assigns processing capability. The EX 28 (m) executes (calculates) the instruction and stores the result in the ROB 24 (m). The RF 25 (m) stores the execution results of the instructions stored in the ROB 24 (m) in an order corresponding to the original execution order when the instructions are committed.

  Here, as described above, the preceding sub-thread identification circuit 29 is executed in a configuration added for multi-thread execution, and thus operates independently of this thread. Then, the preceding subthread identification circuit 29 decodes the instruction of the preceding subthread, identifies the instruction necessary as the preceding subthread according to the decoded instruction type, and sends it to the EX 28 or the like.

  That is, the present invention is characterized in that the preceding subthread can be selected independently of the execution of this thread regardless of whether or not this thread has been executed. As a result, even when this thread is executed for the first time (even if it has never been executed), it is possible to improve the performance of this thread by selecting and executing the preceding sub-thread in advance. This is a feature.

  For example, in the present invention, by executing the preceding sub thread by the EX 28 (m) before the first execution of the thread, the EX 28 (m) obtains an operand necessary for executing the thread from the memory in advance in the L2 cache. 20, the pre-fetch to the D cache 23 and the D cache 23 (m), and when executing this thread, the EX 28 can omit the process of fetching the operand from the memory, and the performance of processing this thread is improved. .

  Here, the characteristics of the present invention will be described anew in comparison with the conventional method. As shown in FIG. 5 (conventional), in the conventional method, after executing this thread once, the data dependency relationship (the execution result obtained as a result of executing each instruction and the data used in each instruction is Whether it is used when executing an instruction), and the preceding subthread is selected by referring to the analysis result. For this reason, when this thread is executed for the first time, the performance of processing this thread cannot be improved. For example, in the example shown in FIG. 5, after analyzing the dependency relationship, the first round of the preceding subthread corresponding to the second round of this thread is executed, and the execution result of the first round of the preceding subthread (for example, the example of FIG. 3). Then, by performing the second round of the preceding sub thread using the value of R3, the value of R4, etc., the performance of processing the third round of the subsequent thread for the first time is improved.

  That is, in the conventional method, in FIG. 5A, in order to load the data stored in [R1 + R3] as a result of the execution of the preceding subthread into FR1, the data stored in [R1 + R3] By performing the prefetch instruction, the performance of processing this instruction (1) in FIG. 5B is improved. In other words, in the example shown in FIG. 5 (conventional), the conventional method does not improve the performance of processing the first and second rounds of this thread.

  Compared with such a conventional method, as shown in (X) of FIG. 5, by applying the present invention, the central processing unit according to the first embodiment is preceded by the execution of this thread. It is characterized in that it is possible to select and execute a sub thread. That is, by applying the present invention, as shown in FIG. 5C, the data stored in [R1 + R3] is loaded into FR1 by the preceding sub thread. From the second round of this thread, this means that the central processing unit according to the first embodiment is instructed to prefetch the data stored in [R1 + R3]. As a result, in the central processing unit according to the first embodiment, the performance for executing this thread (1) shown in FIG. 5D is improved, and the performance for processing this thread is improved. In other words, by applying the present invention as compared with the timing at which the performance of executing this thread is improved in the conventional method, the central processing unit according to the first embodiment has an earlier timing (the book that is executed earlier). Thread), the performance of executing this thread is improved.

  Further, by applying the present invention, the central processing unit according to the first embodiment causes the preceding sub-thread to be executed by EX28 (m) before the first execution of this thread, as shown in FIG. 5 (Y). Therefore, the performance can be improved from the first round of this thread. In other words, in the central processing unit according to the first embodiment, as shown in FIG. 5 (E), the EX 28 (m) executes the preceding sub thread before executing this thread, so that the first round of this thread is performed. Before execution, the data stored in [R1 + R3] is loaded into FR1 by the preceding sub thread. From the first round of this thread, this means that the central processing unit according to the first embodiment has been instructed to prefetch the data stored in [R1 + R3]. As a result, in the central processing unit according to the first embodiment, the performance for executing this thread (1) shown in FIG. 5F is improved, and the performance for processing this thread is improved. In other words, in the conventional method, the performance of the first round of this thread could not be improved, but by applying the present invention, the central processing unit according to the first embodiment can Performance improves from the first round. Note that the timing for selecting and executing the preceding subthread is not limited to the case shown in (X) and (Y) of FIG. 5 described above, and may be selected and executed at any timing.

  Further, the central processing unit according to the first embodiment is characterized in that the memory area can be prevented from being destroyed by executing the preceding subthread by excluding the memory store instruction. In other words, the data stored in the memory is destroyed as the data necessary to execute this thread by executing the preceding sub-thread by performing only the reading process without performing the process of writing the data to the memory. It is possible to avoid doing this. As a result, it is possible to avoid a situation in which the processing of this thread malfunctions by executing the preceding sub thread.

  Floating point arithmetic instructions are rarely used for the purpose of selecting addresses required for memory access, and the time required for execution of floating point arithmetic instructions is not limited to integer arithmetic instructions. Generally larger than instruction execution time. For this reason, the central processing unit according to the first embodiment reduces the processing time required for executing the preceding subthread by excluding the floating-point arithmetic instruction, and also burdens when performing processing on the central processing unit. This is characterized in that the performance at the time of executing this thread can be improved efficiently.

  As shown in FIG. 7, in a typical scientific and engineering calculation program, the ratio of instructions other than memory store instructions and floating point arithmetic instructions is less than 40% of all instructions. By selecting other than the store instruction and the floating-point operation instruction, it is possible to select a preceding subthread that is sufficiently short (processing time is short) for this thread. FIG. 7 is a diagram for explaining the distribution of instruction types.

[Example of processing by preceding subthread identification circuit]
Next, an example of processing performed by the preceding subthread identification circuit 29 in the first embodiment will be described with reference to FIG. FIG. 6 is a flowchart showing an example of processing of the preceding subthread identification circuit 29.

  As shown in the figure, when the preceding sub-thread identification circuit 29 receives an instruction (Yes at Step S101), it determines the instruction content type (Step S102). That is, it determines not the relationship between the instructions obtained by analyzing the execution result of this thread, but the content that each instruction constituting this thread instructs the central processing unit. Then, the preceding subthread identification circuit 29 determines whether it is a store instruction or a floating-point arithmetic instruction (step S103). Here, if the received instruction is not a store instruction or a floating-point operation instruction (No in step S103), the preceding subthread identification circuit 29 selects the received instruction as a preceding subthread and transmits it to Queue 22 ( Step S104). On the other hand, if the received instruction is a store instruction or a floating-point operation instruction (Yes at Step S103), the preceding subthread identification circuit 29 does not transmit to Queue 22 (Step S105). Then, the selection process by the preceding subthread identification circuit 29 is terminated.

[Effect of Example 1]
As described above, according to the first embodiment, not the relationship among the instructions obtained by analyzing the execution result of this thread, but the contents that each of the instructions constituting this thread instructs the central processing unit are determined. Since the preceding subthread is selected, it is possible to select the preceding subthread from this thread that has never been executed.

  Further, according to the first embodiment, the preceding subthread identification circuit 29 discriminates each instruction type as the content and selects the preceding subthread, so that the preceding subthread can be selected simply by confirming the instruction type. Is possible.

  Specifically, in the conventional method, since the preceding thread instruction is identified based on the data dependency analysis result of the retirement instruction of this thread, the required circuit scale is increased. Compared with such a conventional method, by applying the present invention, it is possible to reduce the processing amount required for selecting the preceding sub-thread and the circuit scale required for the processing. As a result, for example, the present invention can be easily implemented.

  Further, according to the first embodiment, the preceding subthread identification circuit 29 determines whether the instruction type corresponds to a store instruction or a floating-point arithmetic instruction that stores data stored in the register in the memory, and does not correspond to the instruction. Since the preceding subthread is selected by selecting, it is possible to easily select the preceding subthread only by excluding the store instruction and the floating-point instruction.

  Although the embodiments of the present invention have been described so far, the present invention may be implemented in various different forms other than the embodiments described above.

  For example, in the first embodiment, the configuration of the CPU 100 when the present invention is applied to CMP has been described. However, the present invention is not limited to this, and the present invention may be applied to SMT. For example, as shown in FIG. 8, the present invention may be implemented by providing a preceding subthread identification circuit between Decode and Queue.

  More specifically, in the first embodiment, in the configuration of the CPU (CMP) shown in FIG. 2, the upper part performs the processing of this thread, and the lower part controls the processing of the preceding sub thread. Here, in the first embodiment, this thread is executed in the upper stage as in the prior art. On the other hand, in the first embodiment, the lower part performs instruction fetching and decoding in the same manner as the upper part, but the decoding result is sent to the preceding subthread identification circuit, and the corresponding circuit is necessary for the preceding execution based on the instruction decoding result. A case has been described in which only a simple instruction is selected as the preceding sub-thread and sent to Queue.

  Implementation of the present invention is not limited to the case where the present invention is applied to such CMP, and the present invention may be applied to SMT as shown in FIG. That is, this thread is executed as in the prior art. In addition, the preceding sub-thread is fetched and decoded in the same way as this thread, but the decoding result is sent to the preceding sub-thread identification circuit, and the corresponding circuit only receives instructions necessary for preceding execution based on the instruction decoding result. Select and send to Queue. In FIG. 8, a PC 26a and an RF 25a are components that execute this thread. The PC 26b and the RF 25b are added to perform a multi-thread execution function, and are used for processing to select and execute a preceding sub thread.

  In the embodiment, the case where the instruction type is used when selecting the preceding sub-thread has been described. However, the present invention is not limited to this, and for example, a register number for storing the instruction execution result is used. May be.

  In the embodiment, the case where the preceding subthread is selected as the instruction type except for the store instruction and the floating-point arithmetic instruction has been described. However, the present invention is not limited to this, and for example, an integer division instruction The preceding subthread may be selected except for.

  The processing procedures, control procedures, specific names, and information including various data and parameters (for example, FIGS. 1 to 6 and FIG. 8) shown in the documents and drawings are arbitrary unless otherwise specified. Can be changed.

  Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. For example, in the function of the EX 28 in FIG. 2, a function of “selecting an instruction that can be executed from the instructions stored in the queue and assigning processing capability” and “in the original execution order” can be configured. The function of “store the execution result in the ROB 24 in the corresponding order” may be separated. Further, for example, the ROB 24 and the RF 25 in FIG. 2 may be integrated.

(Supplementary note 1) This thread configured by a plurality of instructions to be executed is executed, and one or a plurality of instructions for prefetching information necessary for a predetermined thread are selected from the threads as a preceding sub thread. A central processing unit that executes prior to the predetermined thread,
A selection for selecting the preceding sub-thread by determining the contents instructed by the central processing unit by the instructions constituting the thread, not the relationship between the instructions obtained by analyzing the execution result of the thread. A central processing unit comprising means.

(Supplementary note 2) The central processing unit according to supplementary note 1, wherein the selection means discriminates each instruction type constituting the thread and selects the preceding sub-thread as the content.

(Additional remark 3) The said selection means discriminate | determines whether it corresponds to the store instruction | indication which stores the data stored in a register | resistor in a memory, or a floating point arithmetic instruction as said instruction classification, and selects the said instruction | indication by selecting an instruction | indication which does not correspond The central processing unit according to appendix 2, wherein a sub-thread is selected.

(Appendix 4) Executing this thread composed of a plurality of instructions to be executed, and selecting one or more instructions for prefetching information necessary for the predetermined thread from the relevant thread as a preceding sub thread A selection circuit provided in the central processing unit that executes prior to the predetermined thread,
A selection for selecting the preceding sub-thread by determining the contents instructed by the central processing unit by the instructions constituting the thread, not the relationship between the instructions obtained by analyzing the execution result of the thread. A selection circuit comprising steps.

(Additional remark 5) This thread comprised of a plurality of instructions to be executed is executed, and one or a plurality of instructions for prefetching information necessary for the predetermined thread are selected from the current thread as a preceding sub thread. A selection method in the central processing unit that executes prior to the predetermined thread,
A selection for selecting the preceding sub-thread by determining the contents instructed by the central processing unit by the instructions constituting the thread, not the relationship between the instructions obtained by analyzing the execution result of the thread. A selection method characterized by including steps.

  As described above, the present invention is useful for a central processing unit, a selection circuit, and a selection method. In particular, the present thread configured by a plurality of instructions to be executed is executed and is necessary for a predetermined thread. A central processing unit that selects one or more instructions for prefetching information as a preceding sub-thread from this thread and executes it in advance of a predetermined thread, each thread obtained by analyzing the execution result of this thread It is suitable for the realization of a central processing unit, a selection circuit, and a selection method that select the preceding sub-thread by determining the contents instructed by each instruction constituting the thread to the central processing unit.

It is a figure for demonstrating the outline | summary and characteristic of a preceding subthread identification circuit. It is a block diagram which shows the structure of a central processing unit (CMP). It is a figure which shows an example of a source | sauce, this thread | sled row | line | column, and a preceding subthread row | line. It is a figure which shows an example of the circuit diagram of a preceding subthread identification circuit. It is a figure for demonstrating the effect by a preceding subthread identification circuit. It is a flowchart which shows an example of a process of a preceding subthread identification circuit. It is a figure for demonstrating distribution of an instruction classification. It is a block diagram which shows the structure of a central processing unit (SMT). It is a figure for demonstrating CMP and SMT.

Explanation of symbols

10 Decode
11 Predecessor sub-thread identification circuit 12 Queue
20 L2 cache 21 I cache 22 Queue
23 D-cache 24 ROB
25 RF
26 PC
27 Decode
28 EX
29 Leading sub-thread identification circuit

Claims (5)

Execute this thread composed of a plurality of instructions to be executed, and select one or a plurality of instructions for prefetching information necessary for a predetermined thread from the main thread as a preceding sub thread and select the predetermined thread A central processing unit that executes prior to a thread,
A decoder that interprets the instructions;
A queue for storing instructions to be executed;
A central processing unit, comprising: a selection circuit that receives a decoding result by the decoder, selects a preceding subthread from the received decoding result based on an instruction type, and stores the selected preceding subthread in the queue. The selection circuit, the central processing unit according to claim 1 to determine the instruction type of each instruction that constitutes the present thread and selects the leading sub thread.   The selection circuit determines whether the instruction type corresponds to a store instruction or a floating-point arithmetic instruction that stores data stored in a register in a memory, and selects the preceding subthread by selecting an instruction that does not correspond The central processing unit according to claim 2. Execute this thread composed of a plurality of instructions to be executed, and select one or a plurality of instructions for prefetching information necessary for a predetermined thread from the main thread as a preceding sub thread and select the predetermined thread A selection circuit provided in a central processing unit that executes prior to a thread,
A decoding result is received from a decoder that interprets an instruction, a preceding subthread is selected from the received decoding result based on an instruction type, and the selected preceding subthread is stored in a queue that stores an instruction to be executed. Selection circuit. Execute this thread composed of a plurality of instructions to be executed, and select one or a plurality of instructions for prefetching information necessary for a predetermined thread from the main thread as a preceding sub thread and select the predetermined thread A selection method in a central processing unit that executes prior to a thread,
A receiving step for receiving a decoding result from a decoder that interprets the instruction;
A selection step of selecting a preceding subthread based on the instruction type from the received decoding result;
And a storing step of storing the selected preceding subthread in a queue storing instructions to be executed.

Images