JP5102568B2 - Display control device - Google Patents

Description

  The present invention relates to a display control device that controls display by applying a gradation signal to display means such as a liquid crystal panel.

  In a general liquid crystal display device, a gate driver for driving scanning lines of a liquid crystal panel and a source driver for driving signal lines are connected as a driving circuit for the liquid crystal panel. Of these, the source driver drive method is an analog sample-and-hold method in which analog display data is written to the signal line by opening and closing a switch, and a gradation signal corresponding to digital display data is selected and written to the signal line. A modulation signal selection method is known (for example, see Patent Document 1).

  Here, FIG. 4 shows a configuration example of a conventional source driver using the gradation signal selection method. Here, for explanation, it is assumed that the number of source driver output terminals is 960 and the number of gradations is 64.

  First, the circuit configuration will be described. The resistance voltage dividing circuit (gamma circuit) 100 divides the two voltages, the high potential side power supply voltage Vrh and the low potential side power supply voltage Vrl, by a plurality of gamma curve resistors 102 provided in the resistance voltage dividing circuit 100, and the source driver A reference voltage to be output to the output terminals S1 to S960 is created. This is the reference voltage signals tap64 to tap1. These are driven by 64 gradation amplifiers AP1 to AP64, respectively, and output to the gradation signal bus wiring 104 as gradation signals K1 to K64. 960 DAC (digital / analog converter) circuits 106 provided corresponding to the output terminals S1 to S960 are connected to each of the gradation signal bus lines 104 in a bus form, and each of the 64 gradation signals is 960. Input to the DAC circuits 106. Each of the DAC circuits 106 receives digital gradation display data input from an external controller. Based on the gradation display data, the DAC circuit 106 selects a gradation signal Kn of an arbitrary level from the gradation signals of the 64 gradation levels, and outputs it to the source driver output terminals S1 to S960.

  FIG. 5 shows an example of waveforms of the gradation signals K1 to K64. Here, the gradation level decreases as it goes from K1 to K64. In addition, each gradation signal has an alternating waveform in which the polarity is periodically reversed in order to prevent deterioration of the liquid crystal. As shown in FIG. 5, the gradation signal K1 that is the highest gradation level and the gradation signal K64 that is the lowest gradation level have a large amplitude and a large difference in transition level. Further, the amplitude becomes smaller and the transition level difference becomes smaller as the gradation signal becomes an intermediate gradation level. The phase of the gradation signal from the highest gradation level to the intermediate gradation level and the gradation signal from the intermediate gradation level to the lowest gradation level are reversed.

  Although the layout configuration of the source driver is provided, the plurality of DAC circuits 106 are provided corresponding to the output terminals S1 to S960, and thus are arranged in the order of the output terminals S1 to S960. Further, gradation signal bus wirings 104 to which gradation signals K1 to K64 are supplied are arranged in parallel at a minimum interval in parallel with the arrangement direction of the DAC circuit 106. The gradation signals are sequentially supplied to the gradation signal bus wiring 104 from K1 to K64 in the arrangement order. Further, a power supply wiring such as Vss is usually arranged in parallel outside the gradation signal bus wiring 104 to which the gradation signals K1 and K64 are supplied.

  Further, the gradation signal bus wiring 104 and the gradation amplifiers AP1 to AP64 are normally connected near the center of the source driver. This is because when considering the distance from the gradation amplifiers AP1 to AP64 to the far-end source driver output terminals S1 and S960, the gradation amplifier AP1 that outputs the gradation signal K1 to the output terminal S960 or the gradation signal K64. This is because the distance from the gradation amplifier AP64 that outputs the signal to the output terminal S1 is substantially equal, the distance can be minimized, and the delay time can be minimized.

However, on the contrary, the wiring distance from the gradation amplifier AP1 that outputs the gradation signal K1 to the output terminal S960 and the gradation amplifier AP64 that outputs the gradation signal K64 to the output terminal S1 is very long, and the gradation signal K1. , K64 has a problem in that the waveform level becomes dull and the delay time increases because of the large transition level difference as described above.
JP 2003-122325 A

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to provide a display control device that can suppress the waveform dullness of the gradation signal applied to the display means and shorten the delay time. To do.

  In order to achieve the above object, a display control apparatus according to claim 1 of the present invention includes a plurality of gradation signal lines that are arranged in parallel in a predetermined direction and are supplied with a plurality of gradation signals corresponding to a plurality of gradation levels. The gradation signal line to which the highest gradation signal corresponding to the highest gradation level among the plurality of gradation levels is supplied is supplied with a gradation signal in phase with the highest gradation signal. A gradation signal line provided in parallel between the two gradation signal lines to which the lowest gradation signal corresponding to the lowest gradation level among the plurality of gradation levels is supplied is the lowest gradation level. A plurality of gradation signal lines arranged in parallel between two gradation signal lines to which a gradation signal having the same phase as the signal is supplied, and the plurality of gradation signal lines connected to each of the plurality of gradation signal lines. A plurality of selection means for selecting a gradation signal to be applied to the display means from the plurality of gradation signals supplied to the gradation signal line. It is configured.

  According to a second aspect of the present invention, there is provided a display control apparatus, wherein the display control device is arranged in parallel in a predetermined direction with gradation signal generating means for generating and outputting a plurality of gradation signals corresponding to a plurality of gradation levels. A plurality of gradation signal lines to which a plurality of gradation signals are supplied, and a plurality of gradation signals lines connected to each of the plurality of gradation signal lines and supplied to the plurality of gradation signal lines connected thereto. A plurality of selection means for selecting a gradation signal to be applied to the display means from the gradation signal, and a plurality of gradation signals generated corresponding to the plurality of gradation signals and generated by the gradation signal generation means; A plurality of connection wirings connecting the output terminals of the gradation signal generating means and the plurality of gradation signal lines to be supplied to each of the plurality of gradation signal lines, the gradation signal generating means; The highest gradation signal corresponding to the highest gradation level among the plurality of gradation levels is output. A connection wiring for connecting an output terminal to the gradation signal line provided in parallel between two gradation signal lines to which a gradation signal in phase with the highest gradation signal is supplied, and generation of the gradation signal An output terminal for outputting the lowest gray level signal corresponding to the lowest gray level among the plurality of gray levels, and two levels to which a gray level signal in phase with the lowest gray level signal is supplied. And a plurality of connection wirings including connection wirings for connecting the gradation signal lines arranged in parallel between the modulation signal lines.

  In the first and second aspects of the invention, each of the gradation signal lines to which the highest gradation signal and the lowest gradation signal are supplied is supplied with two gradation signals in phase with each other. It is arrange | positioned in the state pinched | interposed into. Accordingly, each of the gradation signal lines to which the highest gradation signal and the lowest gradation signal are supplied is arranged next to the power supply voltage line and the gradation signal line to which the reverse-phase gradation signal is supplied. There is nothing. As a result, the amount of charge / discharge with respect to the coupling capacitance with the wirings arranged on both sides can be reduced, the waveform dullness of the highest-order gradation signal and the lowest-order gradation signal having particularly large amplitude can be suppressed, and the delay time can be shortened.

  According to a third aspect of the present invention, in the display control device according to the first or second aspect, the two gradation signal lines to which the gradation signal in phase with the most significant gradation signal is supplied are the plurality of gradation signal lines. The gradation signal lines to which the gradation signals having the second and third highest gradation levels are supplied, and two gradation signals having the same phase as the lowest gradation signal are supplied. The gradation signal line is a gradation signal line to which a gradation signal having a second and third lowest gradation level among the plurality of gradation levels is supplied.

  A gradation signal having a gradation level close to that of the most significant gradation signal is not only in phase with the most significant gradation signal, but also has a close amplitude and a close difference in polarity transition level. Therefore, the gradation signal line to which the highest gradation signal is supplied is the second gradation signal having the second highest gradation level and the third gradation signal having the second highest gradation level. Is placed between the gradation signal lines to be supplied, the waveform transitions faster and the delay time is longer than that between the gradation signal lines to which other gradation signals are supplied. Shorter. Similarly, the gradation signal line to which the lowest gradation signal is supplied is also disposed between the gradation signal lines to which the gradation signals having the second and third lowest gradation levels are supplied. As a result, the transition of the waveform is accelerated and the delay time is shorter than that between the other gradation signal lines.

  As described above, according to the present invention, it is possible to suppress the waveform dullness of the gradation signal applied to the display means and to shorten the delay time.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  [First Embodiment]

  In this embodiment, a source driver of a liquid crystal display device in which a gate driver that drives a scanning line of a liquid crystal panel and a source driver that drives a signal line are connected as a driving circuit of the liquid crystal panel will be described. The source driver of this embodiment is a grayscale signal selection type driver that selects a grayscale signal corresponding to digital grayscale display data and writes it to a signal line.

  FIG. 1 is a circuit configuration diagram of a source driver according to the present embodiment. Here, a case where the number of source driver output terminals is 960 and the number of gradations is 64 will be described as an example. However, the present invention is not limited to this.

  The source driver includes a resistance voltage dividing circuit (gamma circuit) 10, 64 gradation amplifiers APn (n is an integer of 1 to 64), 64 gradation signal bus lines 12, and DAC (digital analog). Converter) 14 and 960 output terminals Sm (m is an integer of 1 to 960).

  In this source driver, first, a resistance voltage dividing circuit (gamma circuit) 10 generates a plurality of gamma curve resistors provided in the resistance voltage dividing circuit 10 by applying two voltages, a high potential side power supply voltage Vrh and a low potential side power supply voltage Vrl. The reference voltage is divided by 20 and output to the output terminals S1 to S960 of the source driver. This is the reference voltage signals tap64 to tap1. More specifically, the respective gamma curve resistors 20 constituting the resistance voltage dividing circuit 10 are connected in series, and the high-potential side power supply voltage Vrh and the low-potential side are connected to the ends of the resistance voltage dividing circuits 10 connected in series. Two voltages of the power supply voltage Vrl are given. The reference voltage signals tap64 to tap1 are obtained from the nodes N1 to N64 between the respective gamma curve resistors 20. Note that the reference voltage signal gradually decreases because the distance from the high potential side increases from the node N1 to N64.

  Any one of the gradation amplifiers AP1 to AP64 is connected to the nodes N1 to N64 via the connection line 22, respectively. Further, one end of the connection line 24 is connected to the output end of each of the gradation amplifiers AP1 to AP64, and one of the gradation signal bus lines 12 is connected to the other end of the connection line 24. The reference voltage signals tap64 to tap1 are driven by 64 gradation amplifiers AP1 to AP64, respectively, and output to the gradation signal bus wiring 12 as gradation signals K1 to K64 from the output terminals of the gradation amplifiers AP1 to AP64. The The circuit constituted by the resistance voltage dividing circuit 10 and the gradation amplifiers AP1 to AP64 of the present embodiment corresponds to the gradation signal generating means of the present invention.

  The 960 DAC circuits 14 provided corresponding to the output terminals S1 to S960 are connected to each of the 64 gradation signal bus wirings 12 and the two power supply wirings 16 by the connection lines 26 in a bus form. Are input to the 960 DAC circuits 14. Each DAC circuit 14 is supplied with digital gradation display data separately input from an external controller. Based on the gradation display data, the DAC circuit 14 selects a gradation signal Kn of an arbitrary level among the gradation signals of the 64 gradation levels, and outputs it to the source driver output terminals S1 to S960. That is, the digital gradation display data is converted into the analog gradation signal Kn by the DAC circuit 14.

  FIG. 5 shows an example of waveforms of the gradation signals K1 to K64. Here, the gradation level decreases as it goes from K1 to K64. As shown in FIG. 5, the gradation signal K1 which is the highest gradation level and the gradation signal K64 which is the lowest gradation level have a large amplitude and a large difference in transition level. Further, the amplitude becomes smaller and the transition level difference becomes smaller as the gradation signal becomes an intermediate gradation level. Furthermore, the phase of the gradation signal from the highest gradation level to the intermediate gradation level and the gradation signal from the intermediate gradation level to the lowest gradation level are reversed.

  The plurality of DAC circuits 14 are provided corresponding to the output terminals S1 to S960, and are arranged in the arrangement order of the output terminals S1 to S960. Then, 64 gradation signal bus lines 12 are arranged in parallel at the minimum interval in parallel with the arrangement direction of the DAC circuits 14. A power supply wiring 16 such as Vss is arranged outside the 64 gradation signal bus wirings 12. The gradation amplifiers AP1 to AP64 are connected to a region between the connection position of the DAC circuit 14 corresponding to the output terminal S480 and the connection position of the DAC circuit 14 corresponding to the output terminal S481 in the gradation signal bus line 12. Has been. In the present embodiment, since the number of output terminals is exactly 960, the connection positions of the DAC circuits 14 corresponding to the output terminals S480 and S481 in the gradation signal bus wiring 12 are exactly the connection areas of all the DAC circuits 14. Near the center.

  Conventionally, gradation signals from K1 to K64 are sequentially supplied to each of the gradation signal bus wirings 12 in the order of arrangement. In the present embodiment, gradation signals are supplied as shown in FIG. Supplied.

  FIG. 2 is a diagram showing a layout of the gradation signal bus wiring 12 (output layout of gradation signals K1 to K64). FIG. 2A shows a conventional arrangement relationship, and FIG. 2B shows the arrangement state of the present embodiment. In the present embodiment, the gradation signal K3 corresponding to the third highest gradation level is supplied outside the gradation signal bus wiring 12 to which the gradation signal K1 corresponding to the highest gradation level is supplied. The gradation signal bus wiring 12 is arranged, and the gradation corresponding to the third lowest gradation level is provided outside the gradation signal bus wiring 12 to which the gradation signal K64 corresponding to the lowest gradation level is supplied. The gradation signal bus wiring 12 to which the signal K62 is supplied is arranged.

  As shown in FIG. 5, the gradation signals K2 and K3 and the gradation signal K1 are in phase, and the gradation signals K62 and K63 and the gradation signal K64 are in phase.

  Therefore, in this embodiment, the gradation signal bus wiring 12 to which the gradation signal K1 corresponding to the highest gradation level is supplied is supplied with the gradation signals K2 and K3 in phase with the gradation signal K1. The gradation signal K64 that is arranged in parallel between the two gradation signal bus lines 12 and corresponds to the lowest gradation level is supplied to the gradation signal bus line 12 supplied to the gradation signal K64. They are arranged in parallel between the two gradation signal bus lines 12 to which the adjustment signals K62 and K63 are supplied.

  Note that the gradation signal bus wiring 12 to which the gradation signals K4 to K61 other than the gradation signals K1 to K3 and the gradation signals K62 to K64 are supplied is the gradation signal as in the conventional case. The gradation levels in order from the gradation signal bus line 12 to which the gradation signals K1 to K3 are supplied toward the gradation signal bus line 12 to which the gradation signals K62 to K64 are supplied. Arranged to be low.

  Here, the configuration of the source driver according to the present embodiment will be described focusing attention on the connection relationship between the gradation amplifier APn and the gradation signal bus wiring 12.

  The gradation amplifier APn and the gradation signal bus line 12 are connected through the connection line 24 as follows.

  The output terminal of the gradation amplifier AP3 is connected to the gradation signal bus line 12 arranged immediately next to the upper power supply line 16 in FIG. 1 (just below the upper power supply line 16 in FIG. 1). A gradation signal K3 having the third highest gradation level is supplied. Further, the output terminal of the gradation amplifier AP1 is connected to the gradation signal bus wiring 12 arranged next to the gradation signal bus wiring 12, and the highest gradation signal K1 is supplied. Further, the output terminal of the gradation amplifier AP2 is connected to the gradation signal bus wiring 12 arranged adjacent thereto, and the gradation signal K2 having the second highest gradation level is supplied. As a result, the gradation signal K1 is supplied to the gradation signal bus line 12 sandwiched between the two gradation signal bus lines 12 to which the gradation signals K2 and K3 are supplied.

  On the other hand, the output of the gradation amplifier AP62 is connected to the gradation signal bus line 12 arranged immediately next to the lower side power supply line 16 in FIG. 1 (immediately above the lower side power supply line 16 in FIG. 1). The gradation signal K62 having the third lowest gradation level is supplied. Further, the output terminal of the gradation amplifier AP64 is connected to the gradation signal bus wiring 12 arranged next to it, and the lowest gradation signal K64 is supplied. Further, the output terminal of the gradation amplifier AP63 is connected to the gradation signal bus wiring 12 arranged adjacent thereto, and the gradation signal K63 having the second lowest gradation level is supplied. As a result, the gradation signal K64 is supplied to the gradation signal bus line 12 sandwiched between the two gradation signal bus lines 12 to which the gradation signals K62 and K63 are supplied.

  Note that the gradation signal bus wiring 12 to which the gradation signals K4 to K61 other than the gradation signals K1 to K3 and the gradation signals K62 to K64 are supplied is the gradation signal as in the conventional case. The gradation amplifiers AP4 to AP4 are supplied from the gradation signal bus line 12 to which the gradation signals K1 to K3 are supplied toward the gradation signal bus line 12 to which the gradation signals K62 to K64 are supplied. The output ends of the AP 61 are sequentially connected.

  As described above, the gradation signal bus wiring 12 to which the gradation signal K1 having a large amplitude is supplied is replaced with the two gradation signal bus wirings 12 to which the gradation signals K2 and K3 having the same phase as the gradation signal K1 are supplied. Since it is arranged so as to be sandwiched, coupling with the wirings at both ends is performed rather than arranging the power supply wiring 16 to which the power supply voltage Vss without polarity change is supplied next to the gradation signal bus wiring 12 to which the gradation signal K1 is supplied. The amount of charge / discharge with respect to the capacity can be reduced, the transition of the gradation signal K1 is accelerated, the waveform dullness is suppressed, and the delay time can be shortened.

  Similarly, the gradation signal bus wiring 12 to which the gradation signal K64 having a large amplitude is supplied is sandwiched between the two gradation signal bus wirings 12 to which the gradation signals K62 and K63 having the same phase as the gradation signal K64 are supplied. Since the power supply wiring 16 to which the power supply voltage Vss without a change in polarity is supplied is adjacent to the grayscale signal bus wiring 12 to which the grayscale signal K64 is supplied, the coupling capacitance with the wirings on both sides is arranged. The amount of charge / discharge with respect to can be reduced, the transition of the gradation signal K64 becomes faster, the waveform dullness is suppressed, and the delay time can be shortened.

  In the above description, the gradation signal K1 is sandwiched between the gradation signals K2 and K3. However, even if sandwiched between the gradation signals K4 and K5, there are some effects. However, the gradation signals K2 and K3 whose amplitude is close to K1 are more effective. The same applies to the gradation signal K64. The gradation signals K3 and K62 are adjacent to a fixed-level power supply voltage signal. The gradation signals K3 and K62 have a smaller signal amplitude and a smaller transition level difference than the gradation signals K1 and K64. Therefore, it is not slower than the gradation signals K1 and K64.

  As described above, in the conventional circuit, a fixed level signal flows through the wiring (power supply wiring) arranged on one side of the gradation signal bus wiring to which the highest and lowest gradation signals are supplied. The charging and discharging of the coupling capacitance with the fixed level signal was performed, and the waveform became dull and the delay time was long. However, in this embodiment, the highest level and the highest level are provided by the grayscale signal bus wiring to which the common mode signal is supplied. Since the gradation signal bus wiring to which the lower gradation signal is supplied is sandwiched, the amount of charge / discharge is reduced, the waveform dullness is suppressed, and the delay time can be shortened.

  [Second Embodiment]

  FIG. 3 is a circuit configuration diagram of the source driver of this embodiment. 3, parts that are the same as or equivalent to those in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted. The operation for generating and outputting the grayscale signal is also the same as that in the first embodiment, so that the description thereof is omitted, and a configuration different from that in the first embodiment will be described in detail.

  As in the first embodiment, the resistance voltage dividing circuit (gamma circuit) 30 is configured by connecting the gamma curve resistors 20 in series. However, in this embodiment, the amplitude is equal. Alternatively, wiring is performed by bending between the nodes N32 and N33 in the middle of the resistance voltage dividing circuit 30 so that the distance between the nodes from which a close reference gradation voltage can be obtained is short. Thus, the gradation amplifiers AP1 to AP64 connected to the nodes N1 to N64 are also arranged so that the distances between the gradation amplifiers APn that output gradation signals having the same or similar amplitude are close to each other. Can do.

  In the present embodiment, the connection relationship between the gradation signal bus wiring 12 and the gradation amplifiers AP1 to AP64 is the same as in the case of the conventional source driver. That is, the 64 gradation signal bus lines 12 are connected so that the gradation signals from K1 to K64 are sequentially supplied in the arrangement order. Therefore, the arrangement state of the gradation signal bus wiring 12 (the positional relationship of the transmitted gradation signals) is equal to the state shown in FIG.

  However, in the present embodiment, as shown in FIG. 3, the gradation amplifiers AP1 and AP64 that output the gradation signals K1 and K64 having the largest amplitude are connected to the connection positions of the DAC circuit 14 in the gradation signal bus wiring 12. Arranged near the center of the entire area, the connection position of each of the output terminals of the gradation amplifiers AP1 and AP64 and the gradation signal bus line 12 is the entire area of the connection position of the DAC circuit 14 in the gradation signal bus line 12. The layout is configured to be near the center of the.

  The connection positions of the output terminals of the gradation amplifiers AP2 and AP63 that output the gradation signals K2 and K63 having the second largest amplitude in the gradation signal bus wiring 12 are the levels at which the gradation signals K1 and K64 are output. The connection positions of the output terminals of the gradation amplifiers AP3 and AP62 that output the gradation signals K3 and K62 that are slightly farther from the center than the gradation amplifiers AP1 and AP64 and that output the gradation signals K3 and K62 having the third largest amplitude. The position is far from the center. As described above, in this embodiment, the layout configuration is such that the connection position gradually moves away from the center as the amplitude of the gradation signal decreases.

  Normally, the delay time becomes longer as the signal has a larger amplitude and a larger transition level difference. Therefore, as described in this embodiment, the gradation amplifier that outputs a gradation signal having a large amplitude is arranged near the center, and the connection position with respect to the gradation signal bus wiring 12 is located near the center. By connecting the grayscale amplifier and the grayscale signal bus wiring 12, for the grayscale signal having a large amplitude, the distance from the grayscale amplifier connection position to the DAC circuits 14 on both sides of the farthest end is shortened substantially horizontally. can do. In particular, for the grayscale signals K1 and K64 having the largest amplitude, the distance from the grayscale amplifiers AP1 and AP64 to the farthest end DAC circuit 14 can be made the shortest evenly in the left and right directions, so that waveform dullness is suppressed. The delay time can be shortened.

  With this configuration, as a result, the connection positions of the gradation amplifiers AP32 and AP33 that output the gradation signals K32 and K33 and the two DAC circuits connected to the farthest end in the gradation signal bus wiring 12 are obtained. 14, the gradation signals K32 and K33 have a smaller signal amplitude than the gradation signals K1 and K64, so even if the distance increases, the distance is not so slow.

  [Application example]

  In the above embodiment, a gradation amplifier is provided at the subsequent stage of the resistance voltage dividing circuit to generate a gradation signal, and the gradation signal is selected by the DAC circuit at the subsequent stage according to the gradation display data. Although an amplifier type source driver has been described, the present invention is not limited to this, and is applicable to, for example, a source amplifier type source driver.

  The source amplifier method is a circuit method in which the gradation amplifier type gradation amplifier is deleted and a drive amplifier is arranged after the DAC circuit. The number of amplifiers is the same as the number of source driver output terminals, so the area is large. However, since the load of the heavy source terminal can be directly driven, this is an advantageous method in terms of speed.

  Further, the gradation signal bus is connected to the gradation amplifier and the gradation signal bus wiring 12 as exemplified in the first embodiment, and the highest and lowest gradation signals K1 and K64 are output. The position of the wiring 12 is adjusted, and, as exemplified in the second embodiment, the gradation amplifier APn that outputs a gradation signal having a large amplitude is arranged near the center, and the gradation signal bus wiring 12 has its position. The gradation amplifier APn and the gradation signal bus line 12 may be connected so that the connection position is close to the center. With such a configuration, it is possible to further suppress waveform dullness and shorten the delay time.

It is a circuit block diagram of the source driver of 1st Embodiment. It is a figure which shows the layout (output layout of each gradation signal) of a gradation signal bus wiring. It is a circuit block diagram of the source driver of 2nd Embodiment. It is a figure which shows the structural example of the conventional source driver. It is a figure which shows an example of the waveform of a gradation signal.

Explanation of symbols

10, 30 Resistance voltage dividing circuit 12 Grayscale signal bus wiring 14 DAC circuit 16 Power supply wiring 20 Gamma curve resistors 22, 24, 26 Connection lines AP1 to AP64 Grayscale amplifiers K1 to K64 Grayscale signals N1 to N64 Nodes S1 to S960 Output Terminal

Claims (3)

A plurality of gradation signal lines arranged in parallel in a predetermined direction and supplied with a plurality of gradation signals corresponding to a plurality of gradation levels, corresponding to the highest gradation level among the plurality of gradation levels. A gradation signal line to which the highest gradation signal is supplied is juxtaposed between two gradation signal lines to which a gradation signal in phase with the highest gradation signal is supplied, and the plurality of gradation levels are Among them, the gradation signal line to which the lowest gradation signal corresponding to the lowest gradation level is supplied is parallel between the two gradation signal lines to which the gradation signal in phase with the lowest gradation signal is supplied. A plurality of gradation signal lines provided;
A plurality of selection means connected to each of the plurality of gradation signal lines and selecting a gradation signal to be applied to the display means from the plurality of gradation signals supplied to the connected plurality of gradation signal lines;
A display control device. Gradation signal generating means for generating and outputting a plurality of gradation signals corresponding to a plurality of gradation levels;
A plurality of gradation signal lines arranged in parallel in a predetermined direction and supplied with a plurality of gradation signals according to a plurality of gradation levels;
A plurality of selection means connected to each of the plurality of gradation signal lines and selecting a gradation signal to be applied to the display means from the plurality of gradation signals supplied to the connected plurality of gradation signal lines;
The gradation signal generation is provided so as to correspond to the plurality of gradation signals, and each of the plurality of gradation signals generated by the gradation signal generation means is supplied to each of the plurality of gradation signal lines. A plurality of connection lines connecting the output terminals of the means and the plurality of gradation signal lines, the highest level corresponding to the highest gradation level among the plurality of gradation levels of the gradation signal generating means A connection wiring for connecting an output terminal for outputting a gradation signal and a gradation signal line provided in parallel between two gradation signal lines to which a gradation signal having the same phase as that of the uppermost gradation signal is supplied; An output terminal for outputting the lowest gradation signal corresponding to the lowest gradation level among the plurality of gradation levels of the gradation signal generating means and a gradation signal in phase with the lowest gradation signal are supplied. A plurality of contacts including a connection wiring for connecting the gradation signal lines arranged in parallel between the two gradation signal lines. And wiring,
A display control device.   The two gradation signal lines to which the gradation signal in phase with the most significant gradation signal is supplied are supplied with the gradation signals having the second and third highest gradation levels among the plurality of gradation levels. The two gradation signal lines to which the gradation signal in phase with the lowest gradation signal is supplied are the second and third lowest gradation levels among the plurality of gradation levels. The display control apparatus according to claim 1, wherein the display control device is a gradation signal line to which a gradation signal of a level is supplied.

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