JP5094941B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which an erase unit is a block.

  A flash memory, which is one of nonvolatile semiconductor memory devices, has an erase unit for each block. Specifically, the erase operation of the flash memory is performed by applying a high voltage between the word line and the well & source line of the memory cell.

  When a short circuit between a word line and a bit line or a short circuit between a word line and a well & source line occurs in a memory mat of a flash memory, the word of the memory cell is erased during the erase operation due to a leakage current caused by the short circuit. The level of the high voltage applied between the line and the well & source line is reduced. As a result, an erasure failure occurs in the flash memory. Since the erasure unit of the flash memory is for each block, the erasure defect is also a block unit.

  Therefore, in order to relieve the erasure failure in the flash memory, a spare block for performing replacement in block units is required. When a spare block is mounted on a flash memory, the chip area inevitably increases. Therefore, it is important in the flash memory floor plan (circuit layout design) how to share the peripheral circuit with the normal block and suppress the increase in the chip area.

  The floor plan of the flash memory is also important for suppressing the influence of power supply noise on the peripheral circuits by the high voltage generation circuit unique to the flash memory. Further, the floor plan of the flash memory is important for reducing the aspect ratio (aspect ratio) of the logic circuit band laid out using the automatic placement and routing tool. By reducing the aspect ratio of the logic circuit band, the degree of integration of the flash memory can be improved.

  In addition, when a spare block is mounted in a flash memory, it is important to perform a non-selection process for a defective block caused by a leak current. In the WT (Wafer Test) of the flash memory, a voltage stress application test is performed for all blocks at the same time. At this time, it is necessary to suppress a voltage drop due to a leakage current in a defective block. For this purpose, it is necessary to prevent voltage stress from being applied to the defective block.

  The conventional nonvolatile semiconductor memory device (flash memory) automatically detects a defective address that lowers the output voltage of the booster circuit in the batch write / erase test mode. Then, the defective address is stored in the memory circuit so that the high voltage stress is not applied to the address, thereby realizing a batch write / erase test to the memory cell performed before using the redundant circuit (see, for example, Patent Document 1). .

JP 2001-84800 A

  However, the conventional nonvolatile semiconductor memory device determines a defective block by monitoring a change in potential driven from the drive voltage generation circuit without considering the floor plan. Therefore, there are problems that the chip area is increased and the leakage current of the defective block cannot be directly monitored.

  An object of the present invention is to provide a nonvolatile semiconductor memory device capable of non-selection processing of a defective block while suppressing an increase in chip area.

  A nonvolatile semiconductor memory device according to an embodiment of the present invention electrically connects a plurality of word lines, a plurality of main bit lines, a plurality of sub bit lines, and a plurality of main bit lines and a plurality of sub bit lines according to a control signal. A non-volatile memory array having a plurality of select gates that are connected / separated to each other and an analog circuit that monitors a leak current in the non-volatile memory array. The analog circuit includes an internal high voltage generation circuit that generates a constant internal high voltage, a word line amplifier that amplifies the word line voltage associated with the leakage current of the word line, and an amplification of the selection gate voltage associated with the leakage current of the selection gate. A selection gate amplifier, a first leakage monitor circuit that receives the internal high voltage and the word line voltage and monitors the leakage current of the word line, and a leakage current of the selection gate that receives the internal high voltage and the selection gate voltage A second leak monitor circuit.

  According to the embodiment of the present invention, it is possible to perform non-selection processing of a defective block while suppressing an increase in chip area.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device 1A according to a first embodiment of the present invention. 3 is a circuit diagram showing a configuration of a sense amplifier 70 and column decoders 15 and 25 installed in common with respect to memory mats 10 and 20. FIG. FIG. 10 is a diagram showing signal levels of column control signals in the read operation and verify operation of banks 1 and 2; 1 is a block diagram showing a more detailed block configuration of a memory mat 10 in a nonvolatile semiconductor memory device 1A of Embodiment 1. FIG. It is the block diagram which showed the structure of the non-volatile semiconductor memory device 1B by Embodiment 2 of this invention. FIG. 6 is a circuit diagram showing a circuit configuration of a fuse register 211 according to a second embodiment of the present invention. FIG. 5 is a timing diagram showing operation waveforms of main signals in a read data signal transfer process. FIG. 10 is a circuit diagram showing a circuit configuration of a block address register 221 according to Embodiment 2 of the present invention. FIG. 10 is a timing diagram showing operation waveforms of main signals in a spare block determination signal transfer process. . It is the block diagram which showed the structure of 1 C of non-volatile semiconductor memory devices by Embodiment 3 of this invention. FIG. 6 is a circuit diagram showing a part of a circuit configuration of flash memory 300 according to Embodiment 3 of the present invention. FIG. 14 is a cross-sectional view showing a cross-sectional structure when it is assumed that a short circuit exists in flash memory cell MC00. FIG. 10 is a diagram showing voltage states of respective parts of flash memory cell MC00 when word line leakage current monitoring and selection gate leakage current monitoring. It is the block diagram shown in detail about the analog circuit 93 and its peripheral circuit by Embodiment 3 of this invention. It is the circuit diagram shown about the circuit structure of the leak monitor 934 by Embodiment 3 of this invention. It is a timing diagram for demonstrating the circuit operation | movement of the leak monitor 934 by Embodiment 3 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device 1A according to Embodiment 1 of the present invention.

  Referring to FIG. 1, a nonvolatile semiconductor memory device 1A according to the first embodiment includes a memory array 2 (a portion surrounded by a bold line in FIG. 1) having a planar shape arranged in a U-shape, and an analog circuit 91. A logic circuit 92, control circuits 93 and 94, a data pad 100, a power supply pad 101, and an address pad 110. Memory array 2 includes memory mats 10, 20, 30, 40 (for example, 28 Mb), defective memory cell information storage area 19, memory mats 50, 60 (for example, 8 Mb), spare blocks 11, 22, 22, 31, 32, 41, 42, 51, 52, 61, row predecoders 13, 63, row decoders 14, 24, 34, 44, 54, 64, column decoders 15, 25, 35, 45, 55, 65 , Sense amplifiers 71, 73, 74, 76 and a control circuit 81.

  Memory mat 10 (also referred to as bank 1) includes a spare block 11. Row predecoder 13 and row decoder 14 activate a word line or the like (not shown) of memory mat 10. The column decoder 15 activates a bit line (not shown) of the memory mat 10. The defective memory cell information storage area 19 is a non-volatile memory that cannot be written or erased by the user, and can store good / bad information for each block.

  Memory mat 20 (also referred to as bank 2) includes spare blocks 21 and 22. The row decoder 24 activates a word line (not shown) of the memory mat 20. Column decoder 25 activates a bit line or the like (not shown) of memory mat 20. The sense amplifier 71 is installed in common to the memory mats 10 and 20, and detects and amplifies a potential difference between a bit line pair (not shown) in the memory mats 10 and 20. Here, more detailed configurations and operations of the sense amplifier 70 and the column decoders 15 and 25 installed in common with respect to the memory mats 10 and 20 will be described with reference to the drawings.

  FIG. 2 is a circuit diagram showing a configuration of sense amplifier 70 and column decoders 15 and 25 that are installed in common with respect to memory mats 10 and 20.

  Referring to FIG. 2, sense amplifier 70 includes a read sense amplifier 71R and a verify sense amplifier 71V.

  Column decoder 15 includes N channel MOS transistors N11, N12, N13. N channel MOS transistor N11 is connected between main bit line MBL1 from memory mat 10 and node ND11, and receives column control signal CAL_BANK1 at its gate. N-channel MOS transistor N12 is connected between node ND11 and read sense amplifier 71R, and receives column control signal CAUE_BANK1 at its gate. N-channel MOS transistor N13 is connected between node ND11 and verify sense amplifier 71V, and receives column control signal CAUO_BANK1 at its gate.

  Column decoder 25 includes N channel MOS transistors N14, N15 and N16. N channel MOS transistor N14 is connected between main bit line MBL2 from memory mat 20 and node ND12, and receives column control signal CAL_BANK2 at its gate. N-channel MOS transistor N15 is connected between node ND12 and read sense amplifier 71R, and receives column control signal CAUE_BANK2 at its gate. N-channel MOS transistor N16 is connected between node ND12 and verify sense amplifier 71V, and receives column control signal CAUO_BANK2 at its gate.

  Memory mat 10 includes select gates SG10 and SG11 (both are N-channel MOS transistors) and memory cells MC00, MC01, MC10 and MC11. Select gate SG10 is connected between main bit line MBL1 and sub-bit line SBL10, and the gate is connected to select gate line SGL10. Select gate SG11 is connected between main bit line MBL1 and sub-bit line SBL11, and the gate is connected to select gate line SGL11.

  Memory cell MC00 is connected between sub-bit line SBL10 and source line SL1, and has its gate connected to word line WL10. Memory cell MC01 is connected between source line SL1 and sub-bit line SBL10, and has a gate connected to word line WL11. Memory cell MC10 is connected between sub-bit line SBL11 and source line SL1, and has its gate connected to word line WL10. Memory cell MC11 is connected between source line SL1 and sub-bit line SBL11, and has a gate connected to word line WL11.

  Memory mat 20 includes select gates SG20, SG21 (both are N-channel MOS transistors) and memory cells MC20, MC21, MC30, MC31. Select gate SG20 is connected between main bit line MBL2 and sub-bit line SBL20, and the gate is connected to select gate line SGL20. Select gate SG21 is connected between main bit line MBL2 and sub-bit line SBL21, and the gate is connected to select gate line SGL21.

  Memory cell MC20 is connected between sub-bit line SBL20 and source line SL2, and has its gate connected to word line WL20. Memory cell MC21 is connected between source line SL2 and sub-bit line SBL20, and has its gate connected to word line WL11. Memory cell MC30 is connected between sub-bit line SBL21 and source line SL2, and has its gate connected to word line WL20. Memory cell MC31 is connected between source line SL2 and sub-bit line SBL21, and has a gate connected to word line WL21.

  Read sense amplifier 71R receives signals input via N-channel MOS transistors N12 and N15, and outputs a read output signal SAOUT_READ. Verify sense amplifier 71V receives signals input via N channel MOS transistors N13 and N16, respectively, and outputs a verify output signal SAOUT_VERIFY. Next, the signal level of the column control signal in the read operation and verify operation of banks 1 and 2 will be described.

  FIG. 3 is a diagram showing the signal level of the column control signal in the read operation and verify operation of banks 1 and 2.

  Referring to FIG. 3, in the bank 1 read operation, column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to column decoder 15 are H level (logic high), H level, and L level (logic low), respectively. Become. At this time, the main bit line MBL1 of FIG. 2 and the read sense amplifier 71R are electrically connected. The read sense amplifier 71R receives data read from the main bit line MBL1 and outputs a read output signal SAOUT_READ. On the other hand, the column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are all at the L level. Therefore, all of main bit line MBL2, read sense amplifier 71R and verify sense amplifier 71V in FIG. 2 are electrically cut off.

  During the bank 2 read operation, the column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to the column decoder 15 are all at the L level. Therefore, all of main bit line MBL1, read sense amplifier 71R and verify sense amplifier 71V in FIG. 2 are electrically cut off. On the other hand, column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are at an H level, an H level, and an L level, respectively. At this time, the main bit line MBL2 of FIG. 2 and the read sense amplifier 71R are electrically connected. The read sense amplifier 71R receives data read from the main bit line MBL2 and outputs a read output signal SAOUT_READ.

  During the verify operation of bank 1, the column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to the column decoder 15 are at the H level, the L level, and the H level, respectively. At this time, the main bit line MBL1 of FIG. 2 and the verify sense amplifier 71V are electrically connected. The verify sense amplifier 71V receives data from the main bit line MBL1 and outputs a verify output signal SAOUT_VERIFY. On the other hand, the column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are all at the L level. Therefore, all of main bit line MBL2, read sense amplifier 71R and verify sense amplifier 71V in FIG. 2 are electrically cut off.

  During the verify operation of bank 2, column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to column decoder 15 are all at the L level. Therefore, all of main bit line MBL1, read sense amplifier 71R and verify sense amplifier 71V in FIG. 2 are electrically cut off. On the other hand, column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are at an H level, an L level, and an H level, respectively. At this time, the main bit line MBL2 of FIG. 2 and the verify sense amplifier 71V are electrically connected. The verify sense amplifier 71V receives data from the main bit line MBL2 and outputs a verify output signal SAOUT_VERIFY.

  Next, when the verify operation of bank 2 is performed together with the read operation of bank 1, column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to column decoder 15 are at the H level, H level, and L level, respectively. At this time, the main bit line MBL1 of FIG. 2 and the read sense amplifier 71R are electrically connected. The read sense amplifier 71R receives data read from the main bit line MBL1 and outputs a read output signal SAOUT_READ. On the other hand, column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are at an H level, an L level, and an H level, respectively. At this time, the main bit line MBL2 of FIG. 2 and the verify sense amplifier 71V are electrically connected. The verify sense amplifier 71V receives data from the main bit line MBL2 and outputs a verify output signal SAOUT_VERIFY.

  Next, when the bank 2 read operation is performed together with the bank 1 verify operation, the column control signals CAL_BANK1, CAUE_BANK1, and CAUO_BANK1 input to the column decoder 15 are at the H level, the L level, and the H level, respectively. At this time, the main bit line MBL1 of FIG. 2 and the verify sense amplifier 71V are electrically connected. The verify sense amplifier 71V receives data from the main bit line MBL1 and outputs a verify output signal SAOUT_VERIFY. On the other hand, column control signals CAL_BANK2, CAUE_BANK2, and CAUO_BANK2 input to the column decoder 25 are at an H level, an H level, and an L level, respectively. At this time, the main bit line MBL2 of FIG. 2 and the read sense amplifier 71R are electrically connected. The read sense amplifier 71R receives data read from the main bit line MBL2 and outputs a read output signal SAOUT_READ.

  As described above, performing a read operation for another memory bank during a write, erase or verify operation for a certain memory bank is called BGO (Back Ground Operation). As shown in FIG. 2, the sense amplifier 71 is installed in common with respect to the memory mats 10 and 20, and the column control signal is BGO-controlled. For example, the memory mat 10 can be rewritten by simply switching the address while rewriting the data. Data can be read from the mat 20. Thereby, the memory mats 10 and 20 can not only perform operations such as writing and reading independently but also realize a composite operation by BGO.

  Referring again to FIG. 1, memory mat 30 (also referred to as bank 3) includes spare blocks 31 and 32. The row decoder 34 activates a word line or the like (not shown) of the memory mat 30. The column decoder 35 activates a bit line (not shown) of the memory mat 30. The sense amplifier 73 detects and amplifies a potential difference between a bit line pair (not shown) in the memory mat 30. Memory mat 40 (also referred to as bank 4) includes spare blocks 41 and. The row decoder 44 activates a word line (not shown) of the memory mat 40. Column decoder 45 activates a bit line (not shown) of memory mat 40. The sense amplifier 74 detects and amplifies a potential difference between a bit line pair (not shown) in the memory mat 40.

  Memory mat 50 (also referred to as bank 5) includes spare blocks 51 and 52. The row decoder 54 activates a word line (not shown) of the memory mat 50. Column decoder 55 activates a bit line or the like (not shown) of memory mat 50. Memory mat 60 (also referred to as bank 6) includes spare block 61. Row predecoder 63 and row decoder 64 activate word lines and the like (not shown) of memory mat 60. Column decoder 65 activates a bit line (not shown) of memory mat 60. The sense amplifier 76 is installed in common to the memory mats 50 and 60, and detects and amplifies a potential difference between a bit line pair (not shown) in the memory mats 50 and 60. As a result, the memory mats 50 and 60 can realize not only the operations such as writing and reading independently, but also the combined operation by BGO, as described in FIGS.

  Although not explicitly shown in FIG. 1, the control circuit 81 includes, for example, a WE buffer 120 and an address buffer 140. Details of these will be described later. The analog circuit 91 includes an internal high voltage generation circuit 931, which is not explicitly shown in FIG. The internal high voltage generation circuit 931 and the like will be described later. The logic circuit 92 includes a CUI (Command User Interface) 98 and a CPU (Central Processing Unit) 99, which are not explicitly shown in FIG. The CUI 98 and CPU 99 will be described later.

  Although not clearly shown in FIG. 1, the control circuit 93 includes, for example, a CE buffer 130, a spare block control circuit 210, and a sense control circuit 240s. Details of these will be described later. The control circuit 94 includes a data control circuit 250 and an input / output buffer circuit 260 although not explicitly shown in FIG. The data control circuit 250 and the input / output buffer circuit 260 will be described later.

  The data pad 100 is a pad for exchanging data signals with the outside. The power supply pad 101 extends a charge pump power supply line 102 that supplies a power supply voltage to an internal high voltage generation circuit 931 (not shown) in the analog circuit 91. Further, the power supply pad 101 extends the peripheral circuit power supply wiring 103 for supplying a power supply voltage to the column decoders 15 and 65 and the like. Address pad 110 is a pad for exchanging address signals with the outside.

  When a spare block is mounted, efficient arrangement of spare blocks for realizing BGO is important. When the spare block is separated from the main array to form a mini-array, circuits such as a row decoder, a column decoder, and a sense amplifier are required for each spare block. As a result, the so-called area penalty increases. In order to avoid this area penalty, it is necessary to arrange a spare block for each memory bank and share the normal block and the circuit in the same memory bank.

  In the nonvolatile semiconductor memory device 1A of the first embodiment shown in FIG. 1, spare blocks are arranged for each of the memory mats 10 to 60, and a sense amplifier 71 is provided for the memory mats 10 and 20. The sense amplifiers 76 are installed in common with respect to the memory mats 50 and 60. As a result, an increase in circuit area can be minimized while realizing BGO.

  Further, in the conventional floor plan, the memory mat occupying a large area in the chip is preferentially arranged due to restrictions such as a chip vertical and horizontal size (aspect ratio) to be put into a package and the number of memory mat banks. As a result, the logic circuit and the analog circuit are arranged in a vacant place with a high aspect ratio, which causes a problem that the circuit arrangement efficiency is deteriorated.

  The logic circuit is usually laid out using an automatic placement and routing tool. For this reason, in a high aspect ratio region, the wiring rule tends to be easily formed, and the degree of integration tends to decrease. Therefore, in the region where the logic circuit is arranged, it is necessary to improve the degree of integration by reducing the aspect ratio and securing the wiring area.

  The analog circuit includes a charge pump circuit that consumes much power. Therefore, when the analog circuit is disposed at a position far from the power supply pad, the power supply capability may be reduced due to a voltage drop due to the power supply wiring resistance. In addition, if the power supply wiring for the charge pump circuit and the power supply wiring for the peripheral circuit such as the decoder are shared, there is a problem that an access delay is caused by the operation delay of the peripheral circuit due to the power supply voltage drop during the charge pump operation. .

  In the nonvolatile semiconductor memory device 1A according to the first embodiment, as shown in FIG. 1, the memory array 2 including the memory mats 10 to 60 is arranged in a U-shape, and the empty area where the memory array 2 is not arranged is arranged. An analog circuit 91 including a logic circuit 92 and a charge pump circuit is arranged.

  When the flash memory is mounted on an MCP (Multi Chip Package), another chip may be mounted on the flash memory. Therefore, it is necessary to arrange the pad band on the side surface instead of the center as in a DRAM (Dynamic Random Access Memory). If the memory array 2 is arranged in a square shape like a conventional flash memory, it is difficult to exchange power supply voltage and signals between the peripheral circuit arranged in the square shape and the pad band. Become. On the other hand, when the memory array 2 is arranged in a U-shape, it becomes easy to exchange power supply voltages and signals between peripheral circuits such as the logic circuit 92 and pad bands such as the power supply pads 101 and the data pads 100.

  Further, by disposing the logic circuit 92 in an empty area where the memory array 2 is not disposed, the logic circuit 92 can be disposed with a reduced aspect ratio, so that the degree of integration during automatic placement and routing is improved. Can do.

  In addition, by arranging the analog circuit 91 in an empty area where the memory array 2 is not arranged, the analog circuit 91 is close to the power supply pad 101, so that a voltage drop due to power supply wiring resistance can be suppressed and the power supply pad 101 is in the vicinity. Thus, it becomes possible to separate the charge pump power supply wiring 102 and the peripheral circuit power supply wiring 103. Here, the peripheral circuit refers to an access system circuit, and includes a logic circuit 92, for example.

  Thereby, it is possible to avoid the influence of the noise generated during the charge pump operation by the internal high voltage generation circuit 931 or the like on the peripheral circuits. Next, a more detailed block configuration of the memory mat 10 will be described.

  FIG. 4 is a block diagram showing a more detailed block configuration of the memory mat 10 in the nonvolatile semiconductor memory device 1A of the first embodiment.

  As shown in FIG. 4, the memory mat 10 includes normal blocks 10n1 to 10n7 (all 32 kW) which are batch erase units. The memory mat 10 includes boot blocks 10b1 to 10b8 (all 4 kW) existing in the NOR type flash memory. The boot blocks 10b1 to 10b8 have a smaller batch erase unit than the normal blocks 10n1 to 10n7, and are used, for example, for storing boot codes. “W” indicates a unit of storage capacity “word”.

  Each of the 4KW boot blocks 10b1 to 10b8 has a memory size different from that of each of the 32KW normal blocks 10n1 to 10n7, and may be distorted in terms of layout. Therefore, the boot blocks 10b1 to 10b8 having a total capacity of 32 KW are arranged in areas physically different from the normal blocks 10n1 to 10n7. Therefore, there is a problem that nothing is arranged in the normal block area originally assigned to the boot block.

  In the memory mat 10 in the nonvolatile semiconductor memory device 1A of the first embodiment shown in FIG. 4, this area is used as the spare block 11. The spare block 11 is a block that replaces the normal blocks 10n1 to 10n7 when the normal blocks 10n1 to 10n7 are defective. Thereby, the normal block area originally assigned for the boot block can be effectively used.

  As described above, according to the first embodiment, the memory array 2 including the memory mats 10 to 60 is arranged in a U-shape, and the logic circuit 92 and the analog circuit 91 are provided in the empty area where the memory array is not arranged. By disposing, it is possible to avoid the influence of noise generated during the charge pump operation on peripheral circuits such as a decoder while suppressing an increase in chip area.

[Embodiment 2]
When a spare block is mounted as in the nonvolatile semiconductor memory device 1A of the first embodiment, as described above, the non-selection process of the leaky defective block is important. In a WT of a nonvolatile semiconductor memory device (flash memory), a voltage stress application test is performed on all blocks at once. At that time, in order to suppress a voltage drop due to a leak component in the defective block, it is necessary not to apply voltage stress to the defective block.

  In order to realize this, it is necessary to arrange a register for storing good / bad information for each block in each block address decoder. In general, this register is often volatile. In this case, there is a problem that information is lost when the power is turned off for each test. On the other hand, when different information for each chip is given from the tester for each test, there is a problem that the test coincidence number is reduced.

  Here, the good / defective information for each block includes spare block replacement information indicating which defective block is replaced by which spare block, and defective spare block information indicating a spare block which cannot be replaced because it is defective. Point to. When the data of the defective spare block information is “1”, it is necessary to erase all the data to make the data “1”, and the previous data must be rewritten. Therefore, the defective spare block information needs to be data “0” in order to enable overwriting when the spare block is changed from a good product to a defective product during the test.

  If the chip is in a state before LT (Laser Trimming) at the time of WT, it is necessary to transfer spare block replacement information stored in the nonvolatile memory area in the chip to the fuse register. Note that the fuse information in the fuse register is used as it is after LT. The spare block replacement information transferred to the fuse register needs to be transferred to a register for storing good / bad information for each block arranged in each block address decoder.

  In order to transfer spare block replacement information in one stage, it is necessary to store good / bad information for each block in a nonvolatile memory area in the chip. In order to transfer the good / bad information of each block arranged in each block address decoder to the register, signal lines corresponding to the number of blocks are required. The number of blocks in a chip increases as the capacity of the chip increases. When the number of blocks increases, there is a problem that the layout is restricted and the chip has a signal line regulation. Next, the nonvolatile semiconductor memory device 1B of the second embodiment that solves the above problems will be described.

  FIG. 5 is a block diagram showing a configuration of nonvolatile semiconductor memory device 1B according to the second embodiment of the present invention.

  Referring to FIG. 5, nonvolatile semiconductor memory device 1B of the second embodiment includes logic circuit 92, flash memory array 200, X gate 201, Y gate & sense amplifier 202, spare block control circuit 210, and the like. And row decoders 220N and 220S.

  The logic circuit 92 includes a CUI 98 and a CPU 99. The CUI 98 receives a write enable signal / WE, a data signal DQ, an address signal ADD, and the like from the outside, and decodes these commands. The CPU 99 receives the result of decoding by the CUI 98 and controls the entire nonvolatile semiconductor memory device 1B including the flash memory array 200. The CPU 98 starts the operation when the write state machine information signal CXHRDY transitions from the H level to the L level.

  The flash memory array unit including the flash memory array 200, the X gate 201, and the Y gate & sense amplifier 202 is controlled by the CPU 99. The flash memory array 200 includes both the memory mats 10 to 60 and the defective memory cell information storage area 19 described in the first embodiment, but in FIG. The function of the defective memory cell information storage area 19 for storing defect information is mainly described. The Y gate & sense amplifier 202 outputs a read data signal RDO read from the data stored in the flash memory array 200 to the spare block control circuit 210.

  Spare block control circuit 210 includes a fuse register 211, an address selection circuit 212, and an address determination circuit 213. Fuse register 211 receives register initialization signal ISPRST, read data signal RDO, address decode signal ADDDEC, and information switching signal IPROMSEL, and outputs register output signal ROUT to address determination circuit 213.

  The register initialization signal ISPRST controls the initialization of the fuse register 211. The address decode signal ADDDEC is used when the read data signal RDO read from the data stored in the flash memory array 200 is transferred to the fuse register 211. The information switching signal IPROMSEL selects which of the fuse information stored in the fuse register 211 and the read data signal RDO stored in the flash memory array 200 is to be used. A specific circuit configuration of the fuse register 211 will be described later.

  The address selection circuit 212 selects one of the internal address signals AE <22:15> and AO <22:15> and outputs the selected address to the address determination circuit 213. Address determination circuit 210 receives internal address signal and register output signal ROUT output from address selection circuit 212, and outputs spare block determination signal SPBLKSEL to row decoders 220N and 220S, respectively.

  The row decoder 220N is for a normal block (not shown), and includes a block address register 221, a word line decoder 222N, a selection gate decoder 223N, and a source line & well decoder 224N. The block address register 221 receives the block selection control signal BLKSEL0, the spare block determination signal SPBLKSEL, and the data fetch strobe signal ISTRB, and outputs a block determination signal BLKSEL for determining whether the block is good or bad. The data fetch strobe signal ISTRB is used to fetch the spare block determination signal SPBLKSEL into the block address register 221. A specific circuit configuration of the block address register 221 will be described later.

  The word line decoder 222N receives the block determination signal BLKSEL and decodes the word line signal. The selection gate decoder 223N receives the block determination signal BLKSEL and decodes the signal of the selection gate. The source line & well decoder 224N receives the block determination signal BLKSEL and decodes the source line and well signals.

  The row decoder 220S is for a spare block (not shown), and includes a word line decoder 222S, a selection gate decoder 223S, and a source line & well decoder 224S. The word line decoder 222S receives the spare block determination signal SPBLKSEL and decodes the word line signal. The selection gate decoder 223S receives the spare block determination signal SPBLKSEL and decodes the signal of the selection gate. The source line & well decoder 224S receives the spare block determination signal SPBLKSEL and decodes the source line and well signals. Note that the normal block and spare block (not shown) are collectively referred to as a memory block in the second embodiment.

  Hereinafter, a read data signal transfer process for transferring the read data signal RDO read from the flash memory array 200 to the fuse register 211, and a spare block for transferring the spare block determination signal SPBLKSEL output from the address determination circuit 210 to the block address register 211. This will be broadly described as a block determination signal transfer process. By transferring the spare block replacement information in two stages as described above, it becomes unnecessary to directly transfer the spare block replacement information to each spare block, and the signal line for transferring the spare block replacement information from the flash memory 200 to each spare block is eliminated. The number can be reduced. First, a specific circuit configuration of the fuse register 211 that is important in the read data signal transfer process will be described.

  FIG. 6 is a circuit diagram showing a circuit configuration of fuse register 211 according to the second embodiment of the present invention.

  Referring to FIG. 6, fuse register 211 of the second embodiment includes a P-channel MOS transistor P21, N-channel MOS transistors N21, N22, N23, a fuse F21, and inverters I21, I22, I23.

  P-channel MOS transistor P21 is connected between a power supply node and node ND21, and receives a register initialization signal ISPRST at its gate. N channel MOS transistor N21 has a drain connected to node ND21, a source connected to fuse F21, and a gate receiving information switching signal IPROMSEL. Fuse F21 is connected between N-channel MOS transistor N21 and the ground node.

  N channel MOS transistors N22 and N23 are connected in series between node ND21 and the ground node. N channel MOS transistor N22 receives read data signal RDO at its gate. N channel MOS transistor N23 receives address decode signal ADDDEC at its gate. Inverters I21 and I22 are connected in a ring between node ND21 and node ND22. Inverter I23 has an input terminal connected to node ND22, and outputs a register output signal ROUT. Next, the circuit operation in the read data signal transfer process including the circuit operation of the fuse register 211 will be described with reference to operation waveforms of main signals.

  FIG. 7 is a timing diagram showing operation waveforms of main signals in the read data signal transfer process.

  Referring to FIG. 7A, write enable signal / WE falls from H level to L level at time t1, and rises from L level to H level at time t2. In response to this, a command signal CMD1 is generated in the data signal DQ [7: 0]. Write enable signal / WE falls from H level to L level at time t3, and rises from L level to H level at time t4. In response to this, the command signal CMD2 is generated in the data signal DQ [7: 0].

  At time t5, the write state machine information signal CXHRDY falls from the H level to the L level. In response to this, the CPU 98 in FIG. 5 starts the operation. At time t6, the information switching signal IPROMSEL falls from the H level to the L level. Thereby, referring to FIG. 6, fuse F21 and node ND21 are electrically disconnected. As a result, referring to FIG. 5, a transition is made from a state in which information in fuse register 211 is used to a state in which data stored in flash memory 200 is used.

  At time t7, register initialization signal ISPRST falls from H level to L level. As a result, the node ND21 in FIG. 6 is precharged to the H level. As a result, the fuse register 211 is initialized. At time t8, register initialization signal ISPRST rises from L level to H level. At time t9, the internal address signal AO [3: 0] is incremented. The operation of various signals from when the internal address signal AO [3: 0] is incremented at time t9 until it is incremented again at time t15 will be described with reference to FIG.

  Referring to FIG. 7B, internal CPU clock signals PK1, PK2 change complementarily. The CPU 98 in FIG. 5 increments the internal address signal AO [3: 0] in synchronization with the internal CPU clock signals PK1 and PK2. The sense control signal TXLATDO falls from the H level to the L level at time t10, and rises from the L level to the H level at time t11. At time t12, the read data signal RDO [8: 0] is switched from the invalid state (invalid) to the valid state (valid).

  Address decode signal ADDDEC rises from L level to H level at time t13 in synchronization with internal CPU clock signals PK1, PK2. As a result, N channel MOS transistor N23 of FIG. 6 conducts. As a result, information of read data signal RDO is reflected on node ND21 in FIG. That is, read data signal RDO is taken into fuse register 211. At time t14, address decode signal ADDDEC falls from the H level to the L level in synchronization with internal CPU clock signals PK1, PK2.

  Returning to FIG. 7A, at time t16, the write state machine information signal CXHRDY rises from the L level to the H level. In response to this, the CPU 98 in FIG. 5 ends the operation. However, the information switching signal IPROMSEL is fixed to the L level because the fuse F21 and the node ND21 need to be electrically disconnected continuously. Next, a specific circuit configuration of the block address register 221 that is important in the spare block determination signal transfer process will be described.

  FIG. 8 is a circuit diagram showing a circuit configuration of block address register 221 according to the second embodiment of the present invention.

  Referring to FIG. 8, block address register 221 of the second embodiment includes inverters I31-I36, NOR circuit 321, NAND circuit 322, and transfer gate TG31.

  The inverter I31 inverts the block selection control signal BLKSEL0. Inverter I32 inverts the signal output from inverter I31. NOR circuit 321 receives the signal output from inverter I31 and data take-in strobe signal ISTRB. The inverter I33 inverts the signal output from the NOR circuit 321. Transfer gate TG31 electrically connects / disconnects spare block determination signal SPBLKSEL and node ND31 in accordance with the signal output from NOR circuit 321.

  Inverter I34 has an input terminal connected to node ND31, and an output terminal connected to node ND32. Inverter I35 has an input terminal connected to node ND32, and an output terminal connected to node ND31. The operation of the inverter I35 is turned on / off according to the inverted signal of the signal output from the NOR circuit 321. Inverter I36 has an input terminal connected to node ND32. NAND circuit 322 receives signals output from inverters I32 and I36, and outputs block determination signal BLKSEL. Next, the circuit operation in the spare block determination signal transfer process including the circuit operation of the block address register 221 will be described with reference to operation waveforms of main signals.

  FIG. 9 is a timing chart showing operation waveforms of main signals in the spare block determination signal transfer process.

  Referring to FIG. 9A, write enable signal / WE falls from H level to L level at time t1, and rises from L level to H level at time t2. In response to this, a command signal CMD1 is generated in the data signal DQ [7: 0]. Write enable signal / WE falls from H level to L level at time t3, and rises from L level to H level at time t4. In response to this, the command signal CMD2 is generated in the data signal DQ [7: 0].

  At time t5, the write state machine information signal CXHRDY falls from the H level to the L level. In response to this, the CPU 98 in FIG. 5 starts the operation. At time t6, the internal address signal AO [22:15] is incremented. The operation of various signals from when the internal address signal AO [22:15] is incremented at time t6 until it is incremented again at time t9 will be described with reference to FIG.

  Referring to FIG. 9B, internal CPU clock signals PK1, PK2 change complementarily. The CPU 98 in FIG. 5 increments the internal address signal AO [22:15] in synchronization with the internal CPU clock signals PK1 and PK2. At time t6, the block selection control signal BLKSEL0 and the spare block determination signal SPBLKSEL are switched to a valid state (valid). At time t7, data take-in strobe signal ISTRB falls from the H level to the L level in synchronization with internal CPU clock signals PK1, PK2.

  Thereby, referring to FIG. 8, when block selection control signal BLKSEL0 is at H level, NOR circuit 321 outputs a signal at H level. As a result, transfer gate TG31 becomes conductive, and information of spare block determination signal SPBLKSEL is reflected on node ND31. That is, the spare block determination signal SPBLKSEL is taken into the block address register 221.

  Referring to FIG. 8, the block determination signal BLKSEL is an L level (data “0”) signal when the block selection control signal BLKSEL0 is at the H level and the block address register 221 receives the L level signal. Is output. By using this data “0” as defective spare block information, overwriting can be performed when the spare block is changed from a good product to a defective product during the test. At time t8, data take-in strobe signal ISTRB rises from L level to H level in synchronization with internal CPU clock signals PK1, PK2. Returning to FIG. 9A, at time t10, the write state machine information signal CXHRDY rises from the L level to the H level. In response to this, the CPU 98 in FIG. 5 ends the operation.

  As described above, the read data signal transfer process for transferring the read data signal RDO read from the flash memory array 200 to the fuse register 211 and the spare block determination signal SPBLKSEL output from the address determination circuit 210 are transferred to the block address register 211. By transferring spare block replacement information in two stages with the spare block determination signal transfer process, the number of signal lines required to transfer spare block replacement information can be reduced.

  As described above, according to the second embodiment, it is necessary to transfer spare block replacement information by transferring spare block replacement information in two stages of a read data signal transfer process and a spare block determination signal transfer process. Thus, the number of signal lines can be reduced, and an increase in chip area can be suppressed.

[Embodiment 3]
In order to determine a defective block in the nonvolatile semiconductor memory device 1B of the second embodiment, it is necessary to monitor the leakage current for each block. Since it takes time to determine this leakage current monitor with a tester, it is necessary to provide a leakage current determination circuit inside the chip. The current determination level needs to be determined based on the relationship between the influence on the reliability due to the magnitude of the leakage current and the yield of the chip as a product. For this reason, the current determination level needs to be tunable. Further, it is necessary to discriminate whether the leak current is a current flowing from the word line side of the memory cell or a current flowing from the well & source line side (selection gate side) of the memory cell. Next, a nonvolatile semiconductor memory device 1C according to the third embodiment that solves such a problem will be described.

  FIG. 10 is a block diagram showing a configuration of a nonvolatile semiconductor memory device 1C according to the third embodiment of the present invention.

  Referring to FIG. 10, nonvolatile semiconductor memory device 1C of the third embodiment includes WE buffer 120, CE buffer 130, address buffer 140, logic circuit 92, analog circuit 93, and spare block control circuit 210. A flash memory array 300, a row predecoder 220p, a row decoder 220, a column decoder 230, a sense amplifier 240, a sense control circuit 240s, a data control circuit 250, and an input / output buffer 260.

  The WE buffer 120 receives a write enable signal / WE from the outside and performs buffer processing. The CE buffer 130 receives a chip enable signal CE from the outside and performs buffer processing. Address buffer 140 receives an address signal ADD from the outside and performs buffer processing.

  The logic circuit 92 includes a CUI 98 and a CPU 99. The CUI 98 receives signals output from the WE buffer 120, the CE buffer 130, and the address buffer 140, respectively, and decodes these commands. The CPU 99 receives the result of decoding by the CUI 98 and controls the entire nonvolatile semiconductor memory device 1C including the flash memory array 300. The CPU 98 starts the operation when the write state machine information signal CXHRDY transitions from the H level to the L level.

  Analog circuit 93 includes internal high voltage generation circuit 931, word line amplifier 932, selection gate amplifier 933, and leak monitors 934WL and 934SG, and operates by receiving analog circuit control signal ACTR from logic circuit 92. Internal high voltage generation circuit 931 generates internal high voltage signal VPS. The word line amplifier 932 amplifies the word line signal in the flash memory 300. The selection gate amplifier 933 amplifies the signals of the selection gate and well & source line in the flash memory 300. The leak monitor 934WL monitors a leak current flowing from the word line side and outputs a word line leak signal VVWL2. Leak monitor 934SG monitors the leak current flowing from the select gate and well & source line side, and outputs select gate leak signal VVSG.

  Spare block control circuit 210 includes a fuse register 211 and an address determination circuit 213. The fuse register 211 receives the register initialization signal ISPRST, the address decode signal ADDDEC, the information switching signal IPROMSEL output from the logic circuit 92, and the read data signal RDO output from the data control circuit 250, and receives the address determination circuit 213. Register output signal ROUT. Address determination circuit 213 receives internal address signals AO and AE and register output signal ROUT, and outputs spare block determination signal SPBLKSEL to row decoder 220.

  The row predecoder 220p receives the output from the address buffer 140 and outputs a block selection control signal BLKSEL0 to the row decoder 220. The row decoder 220 includes an internal high voltage signal VPS, a word line leak signal VVWL2, a select gate leak signal VVSG output from the analog circuit 93, a data take-in strobe signal ISTRB output from the logic circuit 92, and a spare block control circuit. The spare block determination signal SPBLKSEL output from 210 operates.

  The sense control circuit 240 s receives the output from the address buffer 140 and controls the sense amplifier 240. The input / output buffer 260 buffers the data signal DQ input / output from / to the outside and outputs a command signal to the CUI 98. Next, the part from which the leak current flows in the flash memory 300 will be described. The flash memory 300 corresponds to the memory mats 10 to 60 and their spare blocks in the first embodiment.

  FIG. 11 is a circuit diagram showing a part of the circuit configuration of flash memory 300 according to the third embodiment of the present invention.

  Referring to FIG. 11, flash memory 300 includes a Y gate transistor YG, select gates SG00, SG01, SG10, SG11 (all N channel MOS transistors), flash memory cells MC00, MC01, MC10, MC11, MC20, MC21, MC30, MC31 are included.

  Y gate transistor YG is connected between main bit line MBL from column decoder 230 shown in FIG. 10 and node ND41 on main bit line MBL. Y gate transistor YG electrically connects / disconnects column decoder 230 and flash memory 300 (node ND41) according to a control signal from Y gate select line YGL connected to the gate.

  Select gate SG00 is connected between main bit line MBL and sub-bit line SBL00, and the gate is connected to select gate line SGL00. The selection gate SG01 is connected between the main bit line MBL and the sub bit line SBL01, and the gate is connected to the selection gate line SGL01. The selection gate electrically connects / disconnects the main bit line and the sub bit line in accordance with a control signal from the selection gate line.

  Flash memory cell MC00 is connected between sub-bit line SBL00 and source line SL, and has its gate connected to word line WL0. Flash memory cell MC01 is connected between source line SL and sub-bit line SBL00, and has a gate connected to word line WL1. Flash memory cell MC10 is connected between sub-bit line SBL10 and source line SL, and has its gate connected to word line WL0. Flash memory cell MC11 is connected between source line SL and sub-bit line SBL10, and has its gate connected to word line WL1.

  Flash memory cell MC20 is connected between sub bit line SBL01 and source line SL, and has its gate connected to word line WL0. Flash memory cell MC21 is connected between source line SL and sub-bit line SBL01, and has its gate connected to word line WL1. Flash memory cell MC30 is connected between sub-bit line SBL11 and source line SL, and has its gate connected to word line WL0. Flash memory cell MC31 is connected between source line SL and sub-bit line SBL11, and has a gate connected to word line WL1.

  Select gate SG10 is connected between main bit line MBL and sub-bit line SBL10, and the gate is connected to select gate line SGL10. The selection gate SG11 is connected between the main bit line MBL and the sub bit line SBL01, and the gate is connected to the selection gate line SGL11. A specific structure when it is assumed that a short circuit exists in the flash memory cell MC00 will be described next.

  FIG. 12 is a cross-sectional view showing a cross-sectional structure when it is assumed that a short circuit exists in the flash memory cell MC00.

  Referring to FIG. 12, flash memory cell MC00 includes a substrate 301, a well layer 302, a floating gate layer 303, a word line layer 304, N-type high concentration impurity regions 305 and 306, a drain contact layer 307, , A sub bit line layer 308 and a source line layer 309.

  A well layer (PW) 302 is formed on the substrate (BN) 301. A floating gate layer 303 is formed above the well layer 302. A word line layer 304 is formed above the floating gate layer 303. N-type high concentration impurity regions 305 and 306 having relatively high impurity concentrations are formed on both sides of the floating gate layer 303 from the main surface of the substrate 301 to a predetermined depth. A drain line layer 307 is formed on the N-type high concentration impurity region 305. A sub bit line layer 308 is formed on the drain contact layer 307. A source line layer 309 is formed on the upper portion of the N-type high concentration impurity region 305.

  As shown in FIG. 12, the flash memory cell MC00 has a short 310 between the word line layer 304 and the source line layer 309. The flash memory cell MC00 has a short 311 between the word line layer 304 and the drain contact layer 307. The shorts 310 and 311 cause a word line leakage current or a selection gate leakage current. Next, the voltage state of each part of the flash memory cell MC00 during the word line leakage current monitoring and the selection gate leakage current monitoring will be described.

  FIG. 13 is a diagram showing the voltage state of each part of the flash memory cell MC00 when the word line leakage current is monitored and when the selection gate leakage current is monitored.

  As shown in FIG. 13, when monitoring the word line leakage current, the word line WL is set to a predetermined high voltage VP, the well PW, the source line SL and the sub bit line SBL are set to a predetermined low voltage VN, and the substrate BN is set. Set to power supply potential VCC. Thereby, a potential difference is generated from the word line WL to the well PW and the source line SL, and the leakage current is measured from the shorts 310 and 311. On the other hand, when monitoring the select gate leakage current, well PW, substrate BN and source line SL are set to a predetermined high voltage VP, word line WL is set to a predetermined low voltage VN, and sub-bit line SBL is set to VP-Vd (Vd is a PN diffusion potential). Thereby, a potential difference is generated from the well PW and the source line SL to the word line WL, and the leakage current is measured from the shorts 310 and 311.

  Thus, by setting the voltage state of each part of the flash memory cell MC00, it is possible to monitor the word line leakage current and the selection gate leakage current of the flash memory cell MC00. Next, the analog circuit 93 and its peripheral circuits shown in FIG. 10 will be described in more detail.

  FIG. 14 is a block diagram showing in more detail the analog circuit 93 and its peripheral circuits according to the third embodiment of the present invention.

  Referring to FIG. 14, analog circuit 93 includes an internal high voltage generation circuit 931, a word line amplifier 932, a selection gate amplifier 933, and leak monitors 934WL and 934SG. Internal high voltage generation circuit 931 generates internal high voltage signal VPS. The word line amplifier 932 receives the internal high voltage signal VPS and outputs a monitor input signal VIN_WL. The selection gate amplifier 933 receives the internal high voltage signal VPS and outputs a monitor input signal VIN_SG.

  Leak monitor 934WL receives internal high voltage signal VPS, monitor input signal VIN_WL, and leak monitor activation signals LEAKMON_WL, ILEAKMON_WL, and outputs word line leak signal VVWL2 and leak monitor determination output signal SAOUT_WL. The leak monitor activation signal ILEAKMON_WL is a complementary signal to the leak monitor activation signal ILEAKMON_WL.

  Leak monitor 934SG receives internal high voltage signal VPS, monitor input signal VIN_SG, and leak monitor activation signals LEAKMON_SG, ILEAKMON_SG, and outputs select gate leak signal VVSG and leak monitor determination output signal SAOUT_SG. The leak monitor activation signal ILEAKMON_SG is a complementary signal to the leak monitor activation signal ILEAKMON_SG.

  The data control circuit 250 receives the leak monitor determination output signals SAOUT_WL and SAOUT_SG and outputs a leak monitor determination result via the input / output buffer 260. Next, a circuit configuration of the leak monitor 934 typified by the leak monitors 934_WL and 934_SG will be described.

  FIG. 15 is a circuit diagram showing a circuit configuration of leak monitor 934 according to the third embodiment of the present invention.

  Referring to FIG. 15, leak monitor 934 includes P channel MOS transistors P51-P56, N channel MOS transistors N51-N57, and an inverter I51.

  P-channel MOS transistor P51 is connected between nodes ND51 and ND52 and receives leak monitor activation signal LEAKMON at its gate. N channel MOS transistor N51 is connected between nodes ND51 and ND52 and receives leak monitor activation signal ILEAKMON at its gate. Leak monitor activation signal ILEAKMON is a complementary signal to leak monitor activation signal ILEAKMON. A monitor input signal VIN is input from the node ND51, and a monitor output signal VOUT is output from the node ND52. A path through which the monitor output signal VOUT is output via the node ND52 is referred to as a path 1.

  P-channel MOS transistor P52 is connected between nodes ND51 and ND53 and receives leak monitor activation signal ILEAKMON at its gate. P-channel MOS transistor P53 is connected between nodes ND53 and ND52, and has its gate connected to node ND52. P channel MOS transistor P54 is connected between nodes ND53 and ND54, and has its gate connected to node ND52. A high voltage of internal high voltage signal VPS is applied to each well of P channel MOS transistors P51 to P54. A path through which the monitor output signal VOUT is output via the node ND53 is referred to as a path 2.

  N channel MOS transistor N52 is connected between node ND54 and the ground node, and receives at its gate a leak monitor activation signal ILEAKMON. N-channel MOS transistor N53 is connected between nodes ND54 and ND55, and has its gate connected to node ND54. N-channel MOS transistor N54 is connected between nodes ND56 and ND55, and has its gate connected to node ND54. N-channel MOS transistor N55 is connected between node ND55 and the ground node, and receives leak monitor activation signal LEAKMON at its gate.

  P-channel MOS transistor P55 is connected between a power supply node of power supply potential VCC and node ND56, and has its gate connected to the ground node. As a result, the P-channel MOS transistor P55 is always turned on. The amount of load current Iload flowing through P channel MOS transistor P55 can be adjusted by changing the size of P channel MOS transistor P55 (the ratio of channel width W to channel length L). The size of the P channel MOS transistor P55 is tunable.

  P-channel MOS transistor P56 is connected between a power supply node of power supply potential VCC and node ND57, and has a gate connected to node ND56. N channel MOS transistor N56 is connected between nodes ND57 and ND58, and has its gate connected to node ND56. N-channel MOS transistor N57 is connected between node ND58 and the ground node, and has its gate connected to the power supply node of power supply potential VCC. Thereby, N channel MOS transistor N57 is always turned on.

  P channel MOS transistor P56 and N channel MOS transistors N56 and N57 form an inverter circuit. Inverter I51 has an input terminal connected to node ND57, and outputs a leak monitor determination output signal SAOUT. Next, the circuit operation of the leak monitor 934 will be described.

  FIG. 16 is a timing chart for explaining the circuit operation of leak monitor 934 according to the third embodiment of the present invention.

  Referring to FIG. 16, internal high voltage signal VPS maintains a constant high voltage (for example, 10 V) regardless of whether or not it is in the leak monitoring period. The monitor input signal VIN maintains a constant voltage (for example, 9 V) lower than the internal high voltage VPS regardless of whether or not it is the leak monitoring period. Hereinafter, description will be made by dividing into a normal operation period before time t1 or after time t2 and a leak monitoring period from time t1 to t2.

  First, in the normal operation period, the leak monitor activation signals ILEAKMON and LEAKMON are at the H level (internal high voltage VPS) and the L level (for example, 0 V), respectively. In response, P channel MOS transistor P51 and N channel MOS transistors N51, N52 are turned on. On the other hand, P channel MOS transistor P52 and N channel MOS transistor N55 are turned off.

  Thereby, referring to FIG. 15, monitor output signal VOUT becomes equal to monitor input signal VIN via path 1. Further, since both P-channel MOS transistors P52 and P53 are turned off, the leakage current Ileak does not flow through the path 2. As a result, the leak current Ileak through the current mirror does not flow through the node ND56, and the node ND56 becomes the power supply potential VCC. In response, node ND57 goes to L level. Therefore, leak monitor determination output signal SAOUT is at the H level (power supply potential VCC).

  Next, in the leak monitoring period, the leak monitor activation signals ILEAKMON and LEAKMON become L level (for example, 0 V) and H level (internal high voltage VPS), respectively. In response, P channel MOS transistor P51 and N channel MOS transistors N51, N52 are turned off. On the other hand, P channel MOS transistor P52 and N channel MOS transistor N55 are turned on.

  As a result, referring to FIG. 15, the monitor output signal VOUT is given a voltage that is somewhat lower than the monitor input signal VIN via the path 2. The monitor output signal VOUT in the leak monitoring period is lower when there is no current leak because the voltage drop becomes larger.

  Leakage current Ileak flowing through path 2 is current mirrored to node ND54 by P channel MOS transistors P53 and P54. Leakage current Ileak flowing through node ND54 is further current mirrored to node ND56 by N channel MOS transistors N53 and N54. Therefore, the potential level of node ND56 is determined by the magnitude relationship between load current Iload flowing through P channel MOS transistor P55 and leak current Ileak flowing through N channel MOS transistor N54.

  When the load current Iload is larger than the leak current Ileak (no current leak), the node ND56 becomes the power supply potential VCC. In response, node ND57 goes to L level. Therefore, leak monitor determination output signal SAOUT is at the H level (power supply potential VCC). On the other hand, when the leak current Ileak is larger than the load current Iload (there is a current leak), the node ND56 becomes the ground potential. In response, node ND57 goes to H level. Therefore, leak monitor determination output signal SAOUT is at L level (eg, 0 V).

  The load current Iload needs to be determined by the relationship between the influence on the reliability due to the magnitude of the leakage current Ileak and the yield of the chip as a product. In nonvolatile semiconductor memory device 1C of the third embodiment, the amount of load current Iload can be adjusted by changing the size of P-channel MOS transistor P55.

  As described above, according to the third embodiment, the leakage current of the defective block is directly monitored by monitoring the leakage current while adjusting the amount of load current Iload using the leakage monitors 934_WL and 934_SG. Is possible.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

  1A, 1B, 1C Nonvolatile semiconductor memory device 10, 20, 30, 40, 50, 60 Memory mats 11, 21, 22, 31, 32, 41, 42, 51, 52, 61 Spare blocks 13, 63 Row predecoder, 14, 24, 34, 44, 54, 64 row decoder, 15, 25, 35, 45, 55, 65 column decoder, 19 defective memory cell information storage area, 71, 73, 74, 76 sense amplifier, 71R read sense amplifier, 71V verify sense amplifier, 81, 93, 94 control circuit, 91 analog circuit, 92 logic circuit, 98 CUI, 99 CPU, 100 data pad, 101 power pad, 110 address pad, 120 WE buffer, 130 CE Buffer, 140 address buffer, 200,300 Rush memory array, 201 X gate, 202 Y gate & sense amplifier, 210 spare block control circuit, 211 fuse register, 212 address selection circuit, 213 address determination circuit, 220p row predecoder, 220, 220N, 220S row decoder, 221 block Address register, 222S, 222N word line decoder, 223S, 223N selection gate decoder, 224S, 224N source line & well decoder, 230 column decoder, 240 sense amplifier, 240s sense control circuit, 250 data control circuit, 260 I / O buffer.

Claims (1)

A plurality of word lines, a plurality of main bit lines, a plurality of sub bit lines, and a plurality of selection gates for electrically connecting / separating the plurality of main bit lines and the plurality of sub bit lines according to a control signal, respectively. A non-volatile memory array;
An analog circuit for monitoring leakage current in the nonvolatile memory array,
The analog circuit is:
An internal high voltage generation circuit for generating a constant internal high voltage;
A word line amplifier for amplifying a word line voltage associated with the leakage current of the word line;
A selection gate amplifier that amplifies a selection gate voltage associated with a leakage current of the selection gate;
A first leak monitor circuit that receives the internal high voltage and the word line voltage and monitors a leak current of the word line;
A non-volatile semiconductor memory device comprising: a second leak monitor circuit that receives the internal high voltage and the select gate voltage and monitors a leak current of the select gate.

Images