JP5082969B2 - Receiving device, receiving method, and program - Google Patents

Description

  The present invention relates to a receiving device, a receiving method, and a program, and more particularly to a receiving device, a receiving method, and a program that can prevent occurrence of jitter by a holding unit.

  In digital broadcasting, video, audio, and other necessary data as a broadcast program are sent from the broadcast station as MPEG (Moving Picture Experts Group) 2-TS (Transport Stream) (hereinafter simply referred to as a transport stream as appropriate). Is transmitted. This transport stream is composed of TS packets having a data length of 188 bytes.

  Usually, the clock is not synchronized between the transmission side and the reception side of the transport stream. When the transport stream as a digital broadcast signal is decoded on the receiving side without synchronizing the clock, the decoder FIFO (First In First Out) buffer overflow or underflow occurs, and the video is skipped or the same video is repeated. Displayed (the same video is displayed continuously). For this reason, in the digital broadcast receiving apparatus on the receiving side, a clock recovery process for synchronizing the clock with the transmitting side is performed (for example, see Patent Documents 1 to 3).

  In the clock recovery process, clock synchronization is performed using time information (time stamp) at the time of encoding stored in the TS packet. Specifically, the system clocks of the encoder and the decoder are synchronized using PCR (Program Clock Reference) data in the TS packet.

  The structure of the TS packet will be described with reference to FIG.

  A TS packet may be composed of a header and a payload, or may be composed only of a header, and may be composed of a header and a payload, and may or may not have an adaptation field.

  The first row (top row) of FIG. 1 shows three types of TS packets: a TS packet 1A without an adaptation field, a TS packet 1B with an adaptation field, and a TS packet 1C composed only of a header. ing.

  The second row from the top in FIG. 1 shows the detailed configuration of the header 2 of the TS packet 1A without the adaptation field, and the header 2 when the TS packet does not have the adaptation field is arranged at the head thereof. It consists of an 8-bit synchronization byte 11, a 4-bit cyclic counter (CC) 12 arranged at the end, and other fields 13.

  The third row from the top in FIG. 1 shows the detailed configuration of the header 2 of the TS packet 1B having an adaptation field. The header 2 when the TS packet has an adaptation field has the adaptation field. An adaptation field 14 is added to the case where there is not.

  The fourth row from the top in FIG. 1 shows the detailed configuration of the adaptation field 14, and the adaptation field 14 is composed of an option field 21, a flag 22, and other fields 23. A portion where there is no data to be inserted is filled with a stuffing byte 24. The flag 22 has five flags including a PCR flag indicating whether or not PCR data exists in the option field 21, and is constituted by five bits.

  When the PCR flag is “1”, this indicates that the PCR field 31 exists in the adaptation field 21 as shown in the fifth row from the top of FIG. When the PCR flag is “0”, it indicates that the PCR field 31 does not exist even if the TS packet 1B has the adaptation field 21. The PCR field 31 is composed of 42 bits consisting of an upper 33-bit base field and a lower 9-bit extension field.

  Note that MPEG data is inserted into the payload 3 of the TS packet.

  In a digital broadcast receiver, invalid data may be inserted between 188 bytes of valid data due to noise during transmission, etc., and may be received discontinuously (non-burst), or invalid data. May not be inserted, and 188-byte data (packet data) may be received continuously (in a burst).

  In the decoder, even if TS packets are received discontinuously, the received packet data is temporarily stored so that it can be processed as continuous data in a subsequent decoding processing block or the like. Input to FIFO buffer. The FIFO buffer removes invalid data and outputs 188-byte continuous packet data (shaped TS packet) obtained as a result to the subsequent block.

  With reference to FIGS. 2 and 3, the conventional input / output control by the FIFO buffer will be described.

  First, input / output control when invalid data is not inserted and TS packets are received in bursts will be described with reference to FIG.

  FIG. 2 is a timing chart of the start signal, valid signal, and data signal input to the FIFO buffer, and the start signal, valid signal, and data signal output from the FIFO buffer when TS packets are received in bursts. Is shown.

  In the following description, the start signal, the valid signal, and the data signal input to the FIFO buffer are appropriately converted into a start-in signal (Start_in), a valid-in signal (Valid_in), and a data-in signal (Data_in) as needed. ), And a start signal, a valid signal, and a data signal output from the FIFO buffer are referred to as a start-out signal (Start_out), a valid-out signal (Valid_out), and a data-out signal (Data_out), respectively.

  FIG. 2 shows an example in which packet data 51, 52, 53, 54, 55, 56,... Are sequentially input to the FIFO buffer, and packet data 51, 53, and 54 include PCR data is included, and packet data 52, 55, and 56 do not include PCR data.

The start-in signal becomes high (Hi) level for a predetermined time (T ₁ hour) at the timing when the head data (data of the synchronization byte 11) of the TS packet is input. In the example of the packet data 51, T ₁ hour from the time t ₁₁ to time t _12, the start-in signal is at high level. Note that the interval at which the top data of the TS packet is input to the FIFO buffer is constant at T ₂ hours.

The valid in signal is at a high level while the data signal is valid data. 2, because it is an example of a case where TS packets are received in bursts, for example, T ₃ to start in the signal at time t ₁₁ from becoming a high level, the input of the TS packets of the consecutive 188 byte is finished until the time t ₁₃ after hours, effective in signal becomes a high level, then, between from the time t ₁₃ to the time t _21, the effective-in signal becomes low (low) level.

  The FIFO buffer holds a data signal when the valid-in signal represents valid data, that is, a data signal whose valid-in signal is at a high level, as valid TS packet data.

Then, the FIFO buffer starts output to the subsequent stage at the timing when the final data of the valid data of the TS packet, that is, the 188th byte of the valid data is input. In the example of the packet data 51, FIFO buffer, and sets a start out signal to the high level only ₁ hour T from the time t _13, set the valid out signal to a high level, it starts to output the data signal. The output of the packet data 51 to the subsequent stage ends at time t ₂₂ after T ₃ hours from time t ₁₃ .

  For the packet data 52, 53,... After the packet data 51, packet data is input / output at the same timing.

  In the clock recovery process, PCR data included in the packet data output from the FIFO buffer is extracted by the PCR parser, and PCR (i) (i = 0, 1, 2,...) That is a count value obtained from the PCR data. )) And STC (i) (i = 0, 1, 2,...) Which is the count value of the system time clock (STC) counter in the decoder at the same time as the PCR (i) is acquired. ..) Are compared, and the reference clock signal in the decoder is adjusted so that the count times of PCR (i) and STC (i) are synchronized.

The PCR difference ΔPCR (i) and the PCR data acquisition timing STC difference ΔSTC (i), respectively,
ΔPCR (i) = PCR (i + 1) −PCR (i) (i = 0, 1, 2,...)
ΔSTC (i) = STC (i + 1) −STC (i) (i = 0, 1, 2,...)
However, when TS packets are received in bursts without jitter on the transmission path, the relationship between the PCR difference ΔPCR (i) and the STC difference ΔSTC (i) is as follows: Can be expressed as:

  ΔPCR (i) = ΔSTC (i)

  That is, as shown in FIG. 2, ΔPCR (0) = PCR (1) −PCR (0) is equal to ΔSTC (0) = STC (1) −STC (0) (ΔPCR (0) = ΔSTC (0)), ΔPCR (1) = PCR (2) −PCR (1) and ΔSTC (1) = STC (2) −STC (1) are also equal (ΔPCR (1) = ΔSTC (1) ).

  Next, a conventional FIFO buffer input / output control when a TS packet is received in a non-burst will be described with reference to FIG.

  In the timing chart shown in FIG. 3, in order to facilitate comparison with FIG. 2, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 3 shows an example in which packet data 51 ′, 52, 53 ′, 54, 55, 56 ′,... Are sequentially input / output, and packet data 51 ′, 53 ′, and 56 ′. The valid data itself is the same as the packet data 51, 53, and 56 in FIG. 2, but invalid data of α, β, or γ bytes (α, β, γ> 0) is inserted between them. Is different.

In the packet data 51 ′, invalid data of α bytes (α> 0) is included between the head data and the final data, and the final data is input to the FIFO buffer as compared with FIG. The time it takes becomes slower. More specifically, 'the time t ₁₄ after T ₄ hours from the time t ₁₁ the head data is input, the packet data 51' packet data 51 is the last data is input to the FIFO buffer, the time t ₁₄ is , it is delayed by ₅ hours T than the time t ₁₃ in FIG. 1. Here, T ₅ hours is the time invalid data α byte is input, equal to the difference between T ₄ hours and T ₃ hours _{(T 5 = T 4 -T 3} ).

The valid in signal is low for T ₅ hours when invalid data is input to the FIFO buffer, and the FIFO buffer must remove data signals for which the valid in signal is low. (By not holding it), the shaped packet data is generated.

As described in FIG. 2, the FIFO buffer starts output of the shaped packet data to the subsequent stage at the timing when the final data of valid data of the TS packet is input. output to the subsequent stage will be started at time t _14. Therefore, the output timing of the shaped packet data to the subsequent stage when invalid data is included is later than the output timing when invalid data is not included.

Input / output control is similarly performed on packet data 53 ′ including invalid data of β bytes and packet data 56 ′ including invalid data of γ bytes, and the output timing to the subsequent stage of the FIFO buffer is delayed. Arise. For example, since the input start time of the final data of the packet data 53 ′ including invalid data of β bytes into the FIFO buffer is also delayed by β bytes, the output to the subsequent stage of the packet data 53 after shaping is also β bytes. Only slow down. However, the time interval T ₂ the start-in signal is at a high level, because it is a constant, even though contains invalid data, from the time that the first data is input to the FIFO of the TS packet, the T ₂ hours The input of the final data of the valid data of the TS packet is necessarily finished.

  When the output start time to the subsequent stage of the packet data 51 after shaping is delayed, the time for acquiring the PCR (i) included in the packet data is accordingly delayed, and the timing at the same time when the PCR (i) is acquired. Since the timing for obtaining the count value from the STC counter is delayed, the difference ΔSTC (i) until the next STC changes.

In FIG. 3, the count value of the STC counter when acquiring PCR (0) is STC (0) ′, the count value of the STC counter when acquiring PCR (1) is STC (1) ′, and PCR (2). Assuming that the count value of the STC counter when acquiring STC (2) ′ is the difference ΔSTC (0) ′ = STC (1) ′ − STC (0) ′ and ΔSTC (1) ′ = STC (2) ′ − STC (1) ′ is compared with the differences ΔSTC (0) and ΔSTC (1) when TS packets are received in bursts.
ΔSTC (0) <ΔSTC (0) '
ΔSTC (1)> ΔSTC (1) '
It becomes. In FIG. 3, in order to facilitate comparison, the differences ΔSTC (0) ′ and ΔSTC (1) are indicated by solid lines, and the differences ΔSTC (0) and ΔSTC (1) are indicated by dotted lines.

On the other hand, even if the TS packet is received in a non-burst, the PCR data included in the packet data is not changed, and ΔPCR (0) = ΔSTC (0), ΔPCR when the TS packet is received in a burst. (1) = ΔSTC (1) holds, so
ΔPCR (0) <ΔSTC (0) '
ΔPCR (1)> ΔSTC (1) '
It becomes. If the difference between the PCR difference ΔPCR (i) and the STC difference ΔSTC (i) ′ is larger than the jitter amount ε (allowable jitter ε) within the allowable range for the clock recovery process, the video and audio are adversely affected. . That is, the video is skipped or the same video is repeatedly displayed.

US Patent Application Publication No. 2001/0043621 JP 2002-176663 A JP 2005-151523 A

  As described above, in the conventional FIFO buffer input / output control, when a TS packet is received in a non-burst, jitter that cannot be adjusted by the clock recovery processing may occur.

  The present invention has been made in view of such circumstances, and is intended to prevent the occurrence of jitter by the holding means.

  A receiving apparatus according to an aspect of the present invention removes invalid data generated by passing through a transmission path from a TS packet transmitted from another apparatus through a predetermined transmission path, and obtains a shaping obtained as a result. Holding means for holding a TS packet is provided, and the holding means outputs the held shaped TS packet to the subsequent stage at the timing when input of the next received TS packet is started.

  In the reception method according to one aspect of the present invention, the holding unit of the reception device including holding unit that holds a TS packet transmitted from another device via a predetermined transmission path is configured to transmit the transmission path from the TS packet. The invalid data generated by passing is removed, the shaped TS packet obtained as a result is held, and the received shaped TS packet is received at the timing when the input of the next received TS packet is started. Output to the subsequent stage.

  A program according to one aspect of the present invention is obtained as a result of removing invalid data generated through a transmission path from a TS packet transmitted from another apparatus to the computer through a predetermined transmission path. The shaped TS packet is held, and at the timing when the input of the next received TS packet is started, a process of outputting the held shaped TS packet to the subsequent stage is executed.

  In one aspect of the present invention, invalid data generated through a transmission path is removed from a TS packet transmitted from another device through a predetermined transmission path, and the resulting shaped TS packet is obtained as a result. Is retained. The held shaped TS packet is output to the subsequent stage at the timing when the input of the next received TS packet is started.

  According to one aspect of the present invention, it is possible to prevent the occurrence of jitter by the holding unit.

  FIG. 4 shows a configuration example of an embodiment of a digital broadcast receiving apparatus to which the present invention is applied.

  4 includes a tuner 111, a VCO (Voltage Controlled Oscillator) 112, and a decoding unit 113. The decoding unit 113 further includes a FIFO buffer 121, a demultiplexing unit 122, a video decoder 123, and an audio decoder. 124, a video output unit 125, an audio output unit 126, and a clock control unit 127.

  The tuner 111 receives a digital broadcast signal via an antenna (not shown), selects a channel, detects and demodulates it, and supplies a TS packet of a predetermined channel to the FIFO buffer 121.

  The VCO 112 generates an oscillation signal having a predetermined frequency and supplies it as a reference clock signal to each unit of the decoding unit 113. The VCO 112 can adjust (control) the frequency of the oscillation signal (reference clock signal) to be generated in response to the control signal supplied from the clock control unit 127 of the decoding unit 113.

  The FIFO buffer 121 of the decoding unit 113 holds the TS packet supplied from the tuner 111 for a predetermined time, and then supplies it to the demultiplexing unit 122 and the clock control unit 127. When the TS packet supplied from the tuner 111 includes invalid data, the FIFO buffer 121 shapes the data into 188-byte valid continuous data (shaped TS packet) and demultiplexes and demultiplexer 122 and clock controller 127. Output to.

  The demultiplexing unit 122 analyzes the TS packet supplied from the FIFO buffer 121, separates it into video data and audio data, and supplies the video data to the video decoder 123 and the audio data to the audio decoder 124, respectively.

  The video decoder 123 decodes the video data supplied from the demultiplexing unit 122 and supplies a video signal of a predetermined format obtained as a result to the video output unit 125. The audio decoder 124 decodes the audio data supplied from the demultiplexing unit 122 and supplies the audio signal of a predetermined format obtained as a result to the audio output unit 126.

  The video output unit 125 is configured by, for example, an LCD (Liquid Crystal Display) or the like, and displays a video of a program based on the video signal. The audio output unit 126 includes, for example, a speaker and outputs sound based on the audio signal. Note that the video output unit 125 and the audio output unit 126 include output terminals, and can output a video signal and an audio signal to an external device.

  The clock control unit 127 includes a PCR parser 131, an STC counter 132, a comparator 133, and a control signal generation unit 134.

  The PCR parser 131 is supplied with a TS packet shaped from the FIFO buffer 121 (shaped TS packet). The PCR parser 131 extracts the PCR data included in the TS packet, and supplies PCR (i) (i = 0, 1, 2,...), Which is a count value obtained from the PCR data, to the comparator 133. To do.

  The STC counter 132 supplies STC (i), which is a count value based on the reference clock signal, to the comparator 133. The comparator 133 calculates the difference between the PCR (i) supplied from the PCR parser 131 and the STC (i) supplied from the STC counter 132 and supplies the result to the control signal generator 134.

  The control signal generation unit 134 generates a control signal for increasing or decreasing the frequency of the reference clock signal output from the VCO 112 so that the difference supplied from the comparator 133 becomes zero, and supplies the control signal to the VCO 112.

  The digital broadcast receiving apparatus 100 configured as described above receives a digital broadcast signal transmitted as a transport stream from a broadcast station (not shown), and displays an image obtained by decoding the digital broadcast signal. Audio is also output.

  In the digital broadcast receiving apparatus 100 on the receiving side, in order to prevent the video from being skipped or the same video from being repeatedly displayed (the same video is continuously displayed), It is necessary to decode the transport stream in synchronization with the clock.

  The clock control unit 127 controls the reference clock signal so that the difference between the PCR (i) extracted from the PCR data included in the TS packet and the STC (i) generated in its own device becomes zero. Perform clock recovery processing.

  In the clock recovery process, the STC counter 132 issues STC (i) at the same timing as the PCR parser 131 acquires PCR (i).

  In the conventional digital broadcast receiving apparatus, at the timing when the final data of the valid data of the TS packet, that is, the 188th byte of the valid data is input to the FIFO buffer, the shaped packet data is sent to the demultiplexer and the PCR parser. It was made to output. Therefore, when the TS packet is received in a non-burst, that is, when invalid data of a predetermined number of bytes is inserted between the first data and the last data of the TS packet, the packet data after the shaping is subjected to PCR. Since the timing of output to the parser changes depending on the number of invalid packet data bytes, STC (i) also changes accordingly, and the difference between PCR (i) and STC (i) is the clock recovery processing. May exceed the allowable jitter ε that can be adjusted.

  Therefore, even if invalid packet data is inserted in the received TS packet, the FIFO buffer 121 of the digital broadcast receiving apparatus 100 in FIG. 4 may exceed the allowable jitter ε that can be adjusted by the clock recovery process. The packet data after shaping is output to the multiplexing / separating unit 122 and the PCR parser 131 so that there is no such problem. In other words, the FIFO buffer 121 eliminates the occurrence of jitter due to its own output, and controls the jitter only on the transmission path by clock recovery processing.

  The output timing of the packet data after shaping by the FIFO buffer 121 of the digital broadcast receiving apparatus 100 will be described with reference to FIG.

  In FIG. 5, the conditions of the TS packet input to the FIFO buffer 121 are the same as those in FIG.

  That is, in FIG. 5, the start-in signal, the valid-in signal, the data-in signal, and the packet data 51 ′, 52, 53 ′, 54, 55, 56 ′ input to the FIFO buffer 121 are the same as those in FIG. is there. Further, the point that the shaped packet data 51, 52, 53, 54, 55, and 56 is output from the FIFO buffer 121 is the same as in FIG.

  On the other hand, in FIG. 5, the timing at which the FIFO buffer 121 outputs the shaped packet data 51, 52, 53, 54, 55, 56 to the demultiplexing unit 122 and the PCR parser 131 at the subsequent stage is the same as that in FIG. Different.

  The FIFO buffer 121 holds valid packet data of 188 bytes, and then the timing at which the head data of the next TS packet is input, in other words, the timing at which the start-in signal changes to high level (the rise of the start-in signal ), Output to the demultiplexing unit 122 and the PCR parser 131 at the subsequent stage is started.

In the example of FIG. 5, at time t _14, but the last data of the packet data 51 'is input to the FIFO buffer, wherein the FIFO buffer 121, without outputting the packet data 51 after shaping the latter stage, the packet at time t ₂₁ is timing when the input of the packet data 52 is the next packet data of the data 51 'is started, starts the output to the subsequent packet data 51 that has been held.

Similarly, the FIFO buffer 121 starts outputting the shaped packet data 52 at time t ₃₁ when the input of the packet data 53 ′ that is the packet data next to the packet data 52 is started.

The point that the start-out signal is set to the high level for the time T _{1 at the} start of the packet data output, and the point that the valid out signal is set to the high level until the end of the packet data output after the shaping of 188 bytes is shown in FIG. Same as 3.

Since the time interval at which the TS packet is input to the FIFO buffer 121 is constant at T ₂ hours, the time interval at which the FIFO buffer 121 outputs the shaped packet data to the demultiplexer 122 and the PCR parser 131 at the subsequent stage is also included. , Constant (T ₂ hours) regardless of the presence of invalid packet data.

  In other words, ΔSTC (0) "(= STC (1)"-STC (0) ") and ΔSTC (1)" (= STC (2) "-STC (1)") in FIG. 2 is the same as ΔSTC (0) and ΔSTC (1) in FIG.

  Therefore, since the timing at which ΔSTC (i) "is output to the PCR parser 131 does not change depending on the number of invalid bytes of packet data, the jitter to be adjusted is only the jitter caused by passing through the transmission line. can do.

  That is, in the digital broadcast receiving apparatus 100 of FIG. 4, even when the TS packet is received in a non-burst, the jitter caused by the delay in the timing at which the FIFO buffer 121 outputs the shaped packet data to the PCR parser 131 is delayed. Occurrence can be prevented.

  The packet data input / output control process of the FIFO buffer 121 will be further described with reference to the flowchart of FIG. This process is started when the power is turned on, for example.

  First, in step S1, the FIFO buffer 121 determines whether a new TS packet has been input, that is, whether the start-in signal has changed to a high level.

If it is determined in step S1 that the start-in signal has changed to a high level, the process proceeds to step S2, and the FIFO buffer 121 is a TS packet that has been input and held _two hours ago. Then, the shaped packet data from which the invalid data is removed is output to the demultiplexer 122 and the PCR parser 131 at the subsequent stage. Note that when the start-in signal first changes to high level immediately after activation, there is no TS packet that has been held, and thus the process of step S2 is omitted.

  On the other hand, if it is determined in step S1 that the start-in signal has not changed to high level, or after the processing in step S2, the FIFO buffer 121 shapes and holds the input packet data in step S3. To do. That is, based on the valid in signal, the FIFO buffer 121 holds the input packet data if it is valid data, and removes it (does not hold it) if it is invalid data. ).

  In step S4, the FIFO buffer 121 determines whether or not the power of the digital broadcast receiving apparatus 100 is turned off. If it is determined that the power is not turned off, the process returns to step S1. Thereby, the processes of steps S1 to S4 are repeated until the power of the digital broadcast receiving apparatus 100 is turned off.

  On the other hand, when it is determined in step S4 that the power of the digital broadcast receiving apparatus 100 is turned off, the packet data input / output control process ends.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 12 is a block diagram illustrating a hardware configuration example of a computer that executes the above-described series of processing by a program.

  In a computer, a central processing unit (CPU) 201, a read only memory (ROM) 202, and a random access memory (RAM) 203 are connected to each other by a bus 204.

  An input / output interface 205 is further connected to the bus 204. The input / output interface 205 includes an input unit 206 composed of a keyboard, mouse, microphone, etc., an output unit 207 composed of a display, a speaker, etc., a storage unit 208 composed of a hard disk or nonvolatile memory, and a communication unit 209 composed of a network interface. A drive 210 for driving a removable medium 211 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is connected.

  In the computer configured as described above, the CPU 201 loads, for example, the program stored in the storage unit 208 to the RAM 203 via the input / output interface 205 and the bus 204 and executes the program. Is performed.

  The program executed by the computer (CPU 201) is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.), a magneto-optical disk, or a semiconductor. The program is recorded on a removable medium 211 that is a package medium composed of a memory or the like, or provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  In this specification, the steps described in the flowcharts include processes that are executed in parallel or individually even if they are not necessarily processed in time series, as well as processes that are executed in time series in the described order. Is also included.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

It is a figure explaining the structure of TS packet. It is a figure explaining the input / output control by the conventional FIFO buffer. It is a figure explaining the input / output control by the conventional FIFO buffer. It is a block diagram which shows the structural example of one Embodiment of the digital broadcast receiver to which this invention is applied. FIG. 5 is a diagram for explaining the output timing of packet data by the FIFO buffer of FIG. 4. It is a flowchart explaining packet data input / output control processing. It is a block diagram which shows the structural example of one Embodiment of the computer to which this invention is applied.

Explanation of symbols

  100 digital broadcast receiver, 121 FIFO buffer

Claims (3)

From the TS packet transmitted from another device via a predetermined transmission path, the invalid data generated by passing through the transmission path is removed, and holding means for holding the shaped TS packet obtained as a result,
The holding unit outputs the held shaped TS packet to the subsequent stage at a timing when input of the next received TS packet is started. The holding unit of the receiving device including a holding unit that holds a TS packet transmitted from another device via a predetermined transmission path,
From the TS packet, remove invalid data caused by passing through the transmission path, hold the resulting shaped TS packet,
A receiving method of outputting the held shaped TS packet to the subsequent stage at a timing when input of the received TS packet is started. On the computer,
From the TS packet transmitted from another device via a predetermined transmission path, remove invalid data caused by passing through the transmission path, hold the resulting shaped TS packet,
A program for executing a process of outputting the held shaped TS packet to the subsequent stage at a timing when input of the received TS packet is started.

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