JP5077309B2 - Solid-state imaging device, solid-state imaging device, and method for manufacturing solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, a solid-state imaging device, and a method for manufacturing a solid-state imaging device.

  Conventionally, in a solid-state imaging device, an electrode layer such as a photoelectric conversion device and a readout electrode, and a color filter or an on-chip lens are formed on the surface side of a semiconductor substrate, and imaging is performed by entering light from the surface side. It has a configuration.

In the solid-state imaging device having such a configuration, for example, the potential of the semiconductor well region formed around the photoelectric conversion element is wired from the surface side of the semiconductor substrate (single crystal silicon layer), that is, from the surface side of the semiconductor well region. The minority carriers generated in the photoelectric conversion element are extracted through the semiconductor well region.
Note that the photoelectric conversion element has a potential gradient, and the fractional carriers generated in the photoelectric conversion element naturally flow out to the semiconductor well region.

  By the way, in the case of a solid-state imaging device having such a configuration (so-called surface irradiation type), incident light is absorbed or reflected by an electrode layer or the like formed on the surface side, and the photoelectric conversion efficiency with respect to the incident light is low, and the sensitivity Is a problem.

  Therefore, in recent years, as a configuration for solving such a problem, an electrode layer such as a readout electrode is formed on the front surface side of the semiconductor substrate, and a color filter or an on-chip lens is formed on the back surface side of the semiconductor substrate. A so-called back-illuminated solid-state image sensor that increases the aperture ratio for receiving light by suppressing light absorption or reflection by allowing light to enter from the back side. It has been used (see, for example, Patent Document 1).

JP 2003-031785 A

  By the way, the back-illuminated solid-state imaging device having such a configuration has a thickness of a semiconductor substrate (single crystal silicon layer) as thin as several μ (for example, 5 μ) as compared with the front-illuminated type. The resistance value in the single crystal silicon layer is high.

  However, in the back-illuminated solid-state image sensor, when the minority carriers generated in the photoelectric conversion element are extracted by the same configuration as the above-described front-illuminated solid-state image sensor, that is, as described above, When the potential of the semiconductor well region formed around the conversion element is grounded through the wiring from the surface side of the single crystal silicon layer, the following problems occur.

Of the light that has entered the photoelectric conversion element from the back side of the single crystal silicon layer, for example, positive light generated by long-wavelength light (infrared light) that reaches a deep region (front side) of the photoelectric conversion element The holes flow to the semiconductor well region and are easily extracted from the surface side of the single crystal silicon layer through the wiring.
On the other hand, for example, in the case of holes generated by short wavelength light (ultraviolet light) that reaches only the back side of the photoelectric conversion element, after flowing into the semiconductor well region, from the back side to the front side of the semiconductor well region Since it is necessary to move, it becomes difficult to be pulled out under the influence of the high resistance value of the semiconductor well region.
In this case, holes are gradually accumulated in the semiconductor well region, and the residence time of the holes in the semiconductor well region becomes long. Therefore, it is difficult for holes to flow from the photoelectric conversion element to the semiconductor well region. Therefore, holes are likely to be accumulated in the photoelectric conversion element. For this reason, since the electric field applied to the photoelectric conversion element is affected and becomes weak, majority carriers accumulated in the photoelectric conversion element, that is, electrons (signal charges) cannot be read out correctly.

  As a result, the saturation charge amount (Qs) in the photoelectric conversion element does not become constant, and for example, a transient phenomenon occurs in which characteristics change or sensitivity decreases with time.

  In view of the above, the present invention provides a solid-state imaging device, a solid-state imaging device, and a method for manufacturing the solid-state imaging device that are configured so that minority carriers generated in the photoelectric conversion element can easily escape to the outside.

A solid-state imaging device according to the present invention includes a photoelectric conversion element formed in a semiconductor substrate, an insulating layer provided on the surface side of the semiconductor substrate, a plurality of wiring layers formed in the insulating layer, And a semiconductor region formed in a semiconductor substrate around the photoelectric conversion element. In addition, the conductive material layer formed in contact with at least part of the semiconductor region, the electrode layer for connection to the external wiring formed in the insulating layer, and the electrode layer exposed from the back side of the semiconductor substrate Opening . And an electrode layer is formed in the same layer as the wiring layer currently formed in the most photoelectric conversion element side, and the photoelectric conversion element is equipped with the structure by which light is irradiated from the back surface side of a semiconductor substrate.

  According to the above-described solid-state imaging device according to the present invention, the semiconductor region is formed in the semiconductor substrate around the photoelectric conversion element, and the semiconductor region (for example, the semiconductor well region or the element isolation region) is formed from the back side of the semiconductor substrate. Since the conductive material layer is formed at least in part, minority carriers generated on the back surface side of the photoelectric conversion element can be extracted through the conductive material layer formed in the semiconductor region. And, for example, if the configuration is such that a positive potential or a negative potential is applied to the conductive material layer so that the ground potential or minority carriers are extracted by the voltage application means provided outside, the minority carriers can be easily extracted. become.

A solid-state imaging device according to the present invention includes the solid-state imaging device of the present invention and a unit that applies a voltage to the solid-state imaging device, and a ground potential is applied to the conductive material layer from the voltage applying unit. Is provided.

  In the solid-state imaging device according to the present invention described above, the semiconductor region is formed in the semiconductor substrate around the photoelectric conversion element, and the conductive material layer is formed in at least a part of the semiconductor region from the back surface side of the semiconductor substrate. A solid-state imaging device and means for applying a voltage to the solid-state imaging device, and a ground potential is applied to the conductive material layer from this means. The minority carriers generated in the step can be easily extracted through the conductive material layer formed in the semiconductor region. Thereby, it is possible to prevent minority carriers from being accumulated in the photoelectric conversion element. In addition, since the ground potential is applied, minority carriers can be extracted with a simple configuration.

A solid-state image pickup device according to the present invention includes the solid-state image pickup device of the present invention described above and means for applying a voltage to the solid-state image pickup device. Minority carriers can be extracted from the voltage application means to the conductive material layer. It has a configuration in which a positive potential or a negative potential is applied.

  According to the solid-state imaging device of the present invention, the semiconductor region is formed in the semiconductor substrate around the photoelectric conversion element, and the conductive material layer is formed in at least a part of the semiconductor region from the back side of the semiconductor substrate. A solid-state imaging device; and means for applying a voltage to the solid-state imaging device. From this means, a positive potential or a negative potential is applied to the conductive material layer so that minority carriers can be extracted. Therefore, minority carriers generated on the back side of the photoelectric conversion element can be easily extracted through the conductive material layer formed in the semiconductor region. Thereby, it is possible to prevent minority carriers from being accumulated in the photoelectric conversion element. In addition, since a voltage is applied so that minority carriers are extracted, it is possible to efficiently extract minority carriers by controlling the voltage.

The method for manufacturing a solid-state imaging device according to the present invention includes a step of forming an element isolation region and a photoelectric conversion region in a semiconductor layer on one main surface side of a semiconductor substrate on which a buried oxide film is formed, and a gate on the semiconductor layer. Forming an electrode, forming a source region and a drain region in the semiconductor layer, and forming a transistor. Forming an insulating layer on the semiconductor layer; forming a wiring layer and an electrode layer for external connection on the insulating layer; forming an insulating layer and a wiring layer on the wiring layer and the electrode layer; A step of forming a multilayer wiring layer; and a step of attaching a support substrate on the multilayer wiring layer. Furthermore, the method includes a step of removing the semiconductor layer on the other main surface side of the semiconductor substrate, and a step of removing the insulating layer and the semiconductor layer on the electrode layer to form an opening from which the electrode layer is exposed. In addition, a step of forming a conductive material layer by forming an opening exposing the wiring layer in the semiconductor layer and the insulating layer and filling the opening with a conductive material, and a light shielding covering a part of the photoelectric conversion region on the semiconductor layer Forming a film.

  According to the method for manufacturing a solid-state imaging device according to the present invention, a step of forming a semiconductor region in a semiconductor substrate, a step of forming a photoelectric conversion device in the semiconductor region, and a wiring layer and an insulating layer covering the wiring layer are provided. In addition to forming, an electrode layer is formed in the pad region and covered with an insulating layer, and an opening reaching the electrode layer is formed in the pad region, and at the same time, a hole reaching the wiring layer through the semiconductor region is formed. And a step of forming a hole in the semiconductor region at the same time as forming the opening reaching the electrode layer in the pad region, and performing the step of forming the hole in the semiconductor region. A hole for embedding the material layer can be formed at the same time. Thereby, the process of forming the resist mask for opening formation, and the process of forming the resist mask for hole formation can be performed by one process.

According to the solid-state imaging device and the solid-state imaging device according to the present invention, it is possible to prevent the fractional carriers from being accumulated in the photoelectric conversion element, and it is possible to always keep the saturation signal amount in the photoelectric conversion element constant.
Thereby, since it can suppress that a transient phenomenon arises, the fall of a sensitivity is suppressed and the solid-state image sensor and solid-state imaging device which can respond, for example to a long-time moving image etc. can be obtained.
Therefore, a solid-state imaging device and a solid-state imaging device having high performance and high reliability can be realized.

  According to the method for manufacturing a solid-state imaging device according to the present invention, the process of forming the resist mask can be simplified, and therefore the manufacturing process of the solid-state imaging device can be reduced.

1 is a schematic configuration diagram (plan view) of a solid-state imaging device according to an embodiment of the present invention. It is a schematic sectional drawing (enlarged view) of the imaging area | region and optical black area | region of FIG. FIGS. 3A to 3C are manufacturing process diagrams (part 1) illustrating a manufacturing method of the solid-state imaging device of FIGS. 1 and 2; FIGS. DF is a manufacturing process diagram (part 2) illustrating the manufacturing method of the solid-state imaging device of FIGS. 1 and 2; FIG. GH is a manufacturing process diagram (No. 3) showing the manufacturing method of the solid-state imaging device of FIGS. 1 and 2; FIG. IJ The manufacturing process figure (the 4) which shows the manufacturing method of the solid-state image sensor of FIG.1 and FIG.2. It is a schematic sectional drawing (enlarged view) which shows other embodiment of the solid-state image sensor of one embodiment of this invention. It is a schematic sectional drawing (enlarged view) which shows other embodiment of the solid-state image sensor of one embodiment of this invention. It is a schematic sectional drawing which shows other embodiment of the solid-state image sensor of one embodiment of this invention. It is an expanded sectional view showing other forms of a conductive material layer.

  Embodiments of the present invention will be described below with reference to the drawings.

First, as an embodiment of the present invention, the configuration of a back-illuminated solid-state image sensor, for example, a CMOS solid-state image sensor will be described with reference to FIGS.
FIG. 1 is a schematic plan view of a back-illuminated solid-state image sensor, for example, a CMOS solid-state image sensor. FIG. 2 shows an enlarged sectional view taken along line XX of FIG.

The CMOS solid-state imaging device 1 includes an imaging region 41 in which pixels are arranged in a matrix, an optical black region 42 formed around the imaging region 41, and a pad formed around the optical black region 42. It consists of a region 43 and the like.
The optical black area 42 has a configuration in which dark current correction pixels are arranged around the pixels of the imaging area 41, and one main surface side of the pixels is covered with a light shielding film. Then, noise such as dark current is removed by correcting the signal output from the imaging region 41 with reference to the signal output from the optical black region 42. The pad region 43 is a region where a pad connected to an external wiring is provided, for example. A peripheral circuit region made up of a transistor (not shown) is formed outside the imaging region 41 and the optical black region 42.

  In the imaging region 41, as shown in FIG. 2, photoelectric conversion including an N-type semiconductor region in a unit pixel region delimited by an element isolation region 5 formed in a semiconductor substrate (for example, a single crystal silicon layer) 4. Element 7 is formed. This photoelectric conversion element 7 is formed of a charge storage region 8 made of an N-type semiconductor region and a positive charge storage region 9 made of a high-concentration P-type semiconductor region.

A color filter 11 is formed on one main surface side of the single crystal silicon layer 4, that is, the back surface side (upper side in the drawing) via an antireflection film (oxide film and nitride film) 10. An on-chip lens 12 is formed at a position corresponding to the photoelectric conversion element 7.
On the other main surface side of the single crystal silicon layer 4, that is, on the surface side (lower side in the drawing), for example, a MOS transistor Tr 1 or the like is formed corresponding to the photoelectric conversion element 7. A multilayer wiring layer 13 is formed.

  In the imaging region 41, although not shown, a floating diffusion portion that converts the signal charge accumulated in the photoelectric conversion element into a voltage is formed. In addition, an output unit (output amplifier) that outputs a voltage converted in the floating diffusion unit, a reset gate unit that sweeps out signal charges accumulated in the floating diffusion unit, and the like are formed. The floating diffusion part, the output part, and the reset gate part are formed for each photoelectric conversion element.

  The MOS transistor Tr1 has a configuration in which a gate electrode 14 is formed on the surface side between a pair of source region and drain region formed in the single crystal silicon layer 4 via a gate insulating film. Note that the source region, the drain region, and the channel region of the transistor Tr1 are formed at predetermined positions in the single crystal silicon layer 14 although not illustrated.

The wiring layer 13 has four layers of wiring.
Specifically, in the insulating layer 15 formed on the surface side of the single crystal silicon layer 4, the first wiring 131 and the 2 formed on the first wiring 131 via the insulating layer 15. It is formed on the second layer wiring 132, the third layer wiring 133 formed on the second layer wiring 132 via the insulating layer 15, and on the third layer wiring 133 via the insulating layer 15. And a fourth-layer wiring 134.

  A planarizing film 16 is formed on the insulating layer 15, and a support substrate 18 is bonded to the planarizing film 16 with an adhesive layer 17 interposed therebetween.

In the optical black region 42, the light shielding film 19 is formed on the back surface side of the single crystal silicon layer 4 via the antireflection film 10. Also in the optical black region 42, the photoelectric conversion element 7, the transistor Tr 1, and the wiring layer 26 are formed as in the imaging region 41.
The light shielding film 19 is formed so as to cover all of the photoelectric conversion elements in the optical black region 42.

  In the periphery of the optical black region 42, a semiconductor well region 6 made of a P-type semiconductor region is formed. The semiconductor well region 6 is formed at least over the entire imaging region 41 and the optical black region 42.

  In the pad region 43, the electrode layer 20 is formed on the same surface as the wiring 131 and the wiring 26 in the imaging region 41 and the optical black region 42 in the insulating layer 15 on the surface side of the single crystal silicon layer 4. An opening 21 reaching 20 is formed from the back side of the single crystal silicon layer 4. Although not shown, an insulating film is formed on the side wall in the opening 21.

  The photoelectric conversion element 7 has a potential gradient, and minority carriers generated in the photoelectric conversion element 7 naturally flow out to the semiconductor well region 6.

  In the CMOS solid-state imaging device 1 having such a configuration, image light is incident from the back side of the single crystal silicon layer 3.

  In the present embodiment, in particular, the conductive material layer 25 is formed in the semiconductor well region 6 at the periphery of the optical black region 42. The conductive material layer 25 penetrates from the back surface side to the front surface side in the semiconductor well region 6 and is embedded in the hole 27 reaching the wiring 26 formed in the insulating layer 15 on the front surface side of the semiconductor well region 6. Is formed.

  The conductive material layer 25 can be made of a conductive material, for example, a metal material such as AlCu, Al, AlSi, or W. When such a metal material is used, the resistance value of the conductive material layer 25 is lower than the resistance value in the semiconductor well region 6.

The conductive material layer 25 is configured to be applied with a voltage by a voltage applying unit provided outside (not shown). That is, the solid-state imaging device is configured by including the solid-state imaging device 1 having the above-described configuration and voltage application means provided outside the solid-state imaging device 1.
As this voltage application means, for example, a voltage control circuit that is provided outside or inside the solid-state imaging device 1 and generates a voltage to be applied to the conductive material layer 25 from a voltage from a power source, and a voltage generated by the voltage control circuit And a wiring (a wire or a wiring layer in the solid-state imaging device 1) for guiding the light to the conductive material layer 25.

  As a solid-state imaging device having such a configuration, in the present embodiment, the wiring 26 formed in the insulating layer 15 on the surface side of the single crystal silicon layer 4 and the electrode layer of the pad region 43 connected to the wiring 26. 20 is used to form a means for applying a voltage to the conductive material layer 25. A voltage is applied to the conductive material layer 25 through the electrode layer 20. The wiring 26 and the electrode layer 20 are connected in a region not shown.

  As an embodiment of the above-described solid-state imaging device, a ground voltage (0 V) is applied to the conductive material layer 25 from the voltage application unit.

When the solid-state imaging device is configured such that the ground voltage is applied to the conductive material layer 25 in this way, minority carriers (holes) generated in the photoelectric conversion element 7 in the solid-state imaging element 1 are transferred to the semiconductor well region. 6 can be easily pulled out through the conductive material layer 25 in 6.
At this time, the conductive material layer 25 is formed so as to penetrate from the back surface side to the front surface side of the semiconductor well region 6, and is formed of a metal material. Thus, holes generated on the back surface side of the photoelectric conversion element are not easily extracted, and the holes can be easily extracted by the conductive material layer 26 having a resistance value lower than that of the semiconductor well region 6.

For this reason, in the solid-state imaging device 1, it is possible to prevent holes from being easily accumulated in the photoelectric conversion element 7, and the saturation signal amount in the photoelectric conversion element 7 can always be constant.
As a result, the saturation charge amount (Qs) in the photoelectric conversion element 7 can be prevented from fluctuating and the saturation charge amount (Qs) can be made constant. For example, the color changes over time. It is possible to solve the time dependency problem. In addition, a decrease in sensitivity can be prevented.

  Further, since the conductive material layer 25 is grounded, holes can be extracted with a simple structure.

Although it is considered that the light shielding film formed in the optical black region is also grounded, in this case, for example, after forming the light shielding film, a grounding wiring is connected to the light shielding film from the outside. ing.
On the other hand, in the solid-state imaging device 1 of the present embodiment, since the conductive material layer 25 is formed to reach the grounding wiring 26 formed in the insulating layer 15, the light shielding film 19 is also It is grounded through the conductive material layer 25 and the wiring 26. Thereby, it is not necessary to connect the grounding wiring to the light shielding film 19.

  Further, as another form of the above-described solid-state imaging device, a positive voltage or a negative voltage that can draw minority carriers from the voltage applying unit to the conductive material layer 25 can be applied. .

  That is, in the solid-state imaging device 1 shown in FIGS. 1 and 2, the photoelectric conversion element 7 is formed from an N-type semiconductor region, and the semiconductor well region 6 is formed from a P-type semiconductor region. Therefore, a negative voltage is applied to the conductive material layer 25 from the voltage applying means. The negative voltage is set to a voltage that does not affect the characteristics of the solid-state imaging device 1, for example, a voltage lower than the readout voltage.

  When the solid-state imaging device is configured such that a negative voltage is applied to the conductive material layer 25 as described above, the voltage is controlled in addition to the same effect as that in the case of applying the ground voltage. The carrier can be pulled out.

  In the case of using a solid-state imaging device in which the photoelectric conversion element is formed from a P-type semiconductor region and the semiconductor well region is formed from an N-type semiconductor region, the conductive material layer 25 formed in the semiconductor well region. By applying a positive voltage to the above, it is possible to obtain the same effect as when the negative voltage described above is applied. In this case as well, it goes without saying that a positive voltage that does not affect the characteristics of the solid-state imaging device 1 is applied.

As still another form of the solid-state imaging device described above, a ground voltage or a negative voltage can be applied to the conductive material layer 25 from the back surface side (upper side in FIG. 1) of the single crystal silicon layer 4. .
Specifically, for example, a wire or the like is connected to the light shielding film 19 in the optical black region 42, and a voltage is applied to the conductive material layer 25 through the light shielding film 19.
Even when the solid-state imaging device is configured such that the ground voltage or the negative voltage is applied to the conductive material layer 25 from the back surface side of the single crystal silicon layer 4 as described above, the front surface side of the single crystal silicon layer 4 (FIG. 1). The same effect as when applying a ground voltage or a negative voltage from the lower side is obtained.

  As described later, the configuration in which the voltage is applied from the back side of the single crystal silicon layer 4 in this way is a solid-state imaging device having a configuration in which a conductive material layer is formed in the element isolation region in the optical black region, or a semiconductor well The present invention can also be applied to a solid-state imaging device having a configuration in which a conductive material layer is formed partway from the interface on the back surface side in the region. That is, as in the imaging region 41, the color filter 11 and the on-chip lens 12 are formed on the back side of the single crystal silicon layer 4, and voltage application wiring and electrodes are provided on the back side of the single crystal silicon layer 4. The present invention can be applied to a case where a solid-state imaging device other than the configuration in which the conductive material layer 25 is formed in a portion that is difficult to form is used.

  As described above, in the solid-state imaging device according to the present embodiment, the conductive material layer 25 is formed in the semiconductor well region 6 around the optical black region 42, and the single crystal silicon layer is formed with respect to the conductive material layer 25. Since a voltage (positive voltage or negative voltage) capable of extracting the ground voltage or minority carriers is applied from the voltage application means from the front surface side or the rear surface side, minority carriers accumulate in the photoelectric conversion element 7. The saturation signal amount in the photoelectric conversion element can always be kept constant.

  When the solid-state imaging device is configured so that a voltage is applied to the conductive material layer 25 from the back surface side of the single crystal silicon layer 4, the conductive material layer 25 is not necessarily connected to the front-side wiring as shown in FIG. 26 may not be connected. For example, the conductive material layer 25 may be formed from the back side interface to the front side interface of the single crystal silicon layer 4. Also with this configuration, holes can be extracted from the front and back sides of the semiconductor well region 6 through the conductive material layer 25 and the light shielding film 19.

Next, a method for manufacturing the solid-state imaging device 1 shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 6 are schematic cross-sectional views around the imaging region 41, the optical black region 42, and the optical black region 42 of the solid-state imaging device 1 shown in FIG. Moreover, the same code | symbol is attached | subjected to the part corresponding to FIG.1 and FIG.2.
Note that the manufacturing process shown below is performed using as a reference an alignment mark (not shown) formed through a predetermined position of a single crystal silicon layer described later.

First, as shown in FIG. 3A, for example, an SOI substrate 30 in which a single crystal silicon layer 4 is formed on a silicon substrate 2 via a buried oxide film (so-called BOX layer) 3 is prepared.
Note that the thickness of the buried oxide film 3 and the single crystal silicon layer 4 can be set arbitrarily.

  Next, in the optical black region 42 from the imaging region 41, a P-type semiconductor well region 6 is formed in the single crystal silicon layer 4 by a known technique, and then a known position is placed in a predetermined position in the semiconductor well region 6. The element isolation region 5 is formed by a technique. Then, an N-type semiconductor region (charge storage region) 8 for forming a photoelectric conversion element is formed by a known technique at a predetermined position in the element formation region delimited by the element isolation region 5 (see FIG. 3B above). ).

Next, as shown in FIG. 3C, in the imaging region 41 and the optical black region 42, a MOS type comprising a source region and a drain region paired with the gate electrode 14 via the insulating layer on the single crystal silicon layer 4, respectively. A transistor Tr1 is formed.
Note that a channel region, a source region, and a drain region of the transistor Tr1 are formed at predetermined positions in the single crystal silicon layer 4 although not illustrated.

  Next, as shown in FIG. 4D, a multilayer wiring layer 13 is formed on the single crystal silicon layer 4 via an insulating layer 15.

Specifically, first, after the insulating layer 15 is formed on the single crystal silicon layer 4 and planarization is performed, the wiring 131 serving as the first layer is formed in a predetermined pattern.
Next, the insulating layer 15 is formed again on the entire surface including the first-layer wiring 131 and planarized, and then the second-layer wiring 132 is formed in a predetermined pattern.
Thereafter, such a process is repeated until the predetermined number of layers is reached.
In the case shown in FIG. 4D, the case where the wiring layer 13 has four layers is shown, but in the case of four or more layers, such a process is repeated.
Further, a planarizing film made of, for example, a SiN film or a SiON film is formed on the insulating layer 15.

  In the formation process of the wiring 13, when forming the first layer wiring 131 of the imaging region 41 and the optical black region 42, in the peripheral portion of the optical black region 42, grounding is performed on the same surface as the wiring 131. The wiring 26 is formed in a predetermined pattern. Although not shown, an electrode layer is formed in a predetermined pattern on the same surface as the wiring 131 and the wiring 26 in the pad region.

  Next, as shown in FIG. 4E, an adhesive layer 17 is applied on the planarizing film, and a support substrate 18 is bonded thereto. Thus, the reason why the support substrate 18 is bonded to the surface side of the SOI substrate 30 is to ensure mechanical strength when the SOI substrate 30 is thinned in a process described later.

Next, the silicon substrate 2 of the SOI substrate 30 is placed on the upper surface by turning upside down. Then, the silicon substrate 2 and the buried oxide film 3 are sequentially removed so that the single crystal silicon layer 4 of the SOI substrate 30 is exposed as shown in FIG. 4F.
Then, a high concentration of P is formed on the back surface side of the charge storage region 8 by a known technique (for example, a thin oxide film is formed on the upper surface of the single crystal silicon layer 4 and then a resist mask is formed and ion implantation is performed). A positive charge accumulation region 9 made of a type semiconductor region is formed. Thereby, the photoelectric conversion element 7 is formed. Note that the process of forming the positive charge accumulation region 9 is not limited to the state shown in FIG. 4F, and various other methods such as formation from the surface side of the single crystal silicon layer 4 as in the case of the charge accumulation region 8. Is possible.

Next, as shown in FIG. 5G, in order to connect the contact wiring from the outside to the electrode layer 20 embedded in the insulating layer 15 in the pad region 43, the single crystal silicon layer 4 and the insulating layer 15 are connected from the back side. Are sequentially removed by etching to form an opening 21 reaching the electrode layer 20.
At this time, in the present embodiment, a hole 27 reaching the wiring 26 is simultaneously formed in the semiconductor well region 6.
That is, the electrode layer 20 in the pad region 43 is formed on the same surface as the wiring 131 and the wiring 26 in the imaging region 41 and the optical black region 42 as described above. Therefore, when the opening 21 reaching the electrode layer 20 is formed in the pad region 43, the hole 27 reaching the wiring 26 can be formed simultaneously in the optical black region 42.

Specifically, in a state where the single crystal silicon layer 4 of the SOI substrate 30 is exposed (see FIG. 4F), after forming an antireflection film on the single crystal silicon layer, a photoresist film is formed on the antireflection film. And a resist mask having a pattern for forming openings and holes is formed using a known lithography technique.
Next, by etching away the single crystal silicon layer using this resist mask as a mask, holes are formed at predetermined positions in the single crystal silicon layer 4 in the optical black region 42 and the pad region 43 as shown in FIG. 5G. 27 and the opening 21 can be formed, respectively.

  Next, the conductive material layer 25 is formed on the single crystal silicon layer 4 including the holes 27. Then, by removing only the conductive material layer 25 on the surface of the single crystal silicon layer 4, the conductive material layer 25 is embedded in the hole 27 as shown in FIG. 5H.

  Next, as shown in FIG. 6I, a light shielding film 19 is formed on the single crystal silicon layer 4 in the optical black region 42. At this time, in the imaging region 41, the single crystal silicon layer 4 is covered with a mask. The light shielding film 19 is formed so as to cover the periphery of the optical black region 42.

  Thereafter, as shown in FIG. 6J, the on-chip microlens 12 is formed via the color filter 11 in a part corresponding to the photoelectric conversion element 7 on the back surface side of the single crystal silicon layer 4 in the imaging region 41.

  In this way, the back-illuminated CMOS solid-state imaging device 1 having the configuration shown in FIGS. 1 and 2 can be manufactured.

  According to the manufacturing method described above, the conductive material layer 25 is embedded in the periphery of the optical black region 42 when the opening 21 for connecting the contact wiring from the outside to the electrode layer 20 is formed in the pad region 43. Since the holes 27 are formed at the same time, the step of forming the resist mask for forming the holes 27 and the step of forming the resist mask for forming the openings 21 can be performed in one step. As a result, the resist mask forming process can be simplified.

  In the manufacturing method described above, the solid-state imaging device 1 is manufactured from the SOI substrate 30 composed of a plurality of layers in which the single crystal silicon layer 4 is laminated on the silicon substrate 2 via the buried oxide film 3. Applied to the case explained. However, for example, the present invention can also be applied to a case where a solid-state imaging device having the above-described configuration is manufactured from a single-layer semiconductor substrate (single crystal silicon layer) having a thin layer thickness.

  In the manufacturing method described above, the silicon substrate 2 and the buried oxide film 3 are removed and the single crystal silicon layer 4 of the SOI substrate 30 is exposed in the steps shown in FIGS. 4E to 4F. It is also possible to remove only the substrate 2 and leave the buried oxide film 3.

Next, another embodiment of the solid-state imaging device of the present invention will be described.
In the solid-state imaging device 1 of the embodiment described above, the conductive material layer 25 is formed in the semiconductor well region 6 formed in the peripheral portion of the optical black region 42 as shown in FIG. In the solid-state imaging device 31, as shown in FIG. 7, in the imaging region 41, the conductive material layer 25 is formed in the element isolation region 5 made of a P-type semiconductor region that separates adjacent photoelectric conversion elements 7.
Since other configurations such as a material used for the conductive material layer 25 are the same as the configurations of the solid-state imaging device 1 of the above-described embodiment, a duplicate description is omitted.

When a solid-state imaging device is configured using such a solid-state imaging device 31 having a configuration in which the conductive material layer 25 is formed in the element isolation region 5 of the imaging region 41, the single crystal silicon layer 4 of the imaging region 41 is used. Since the color filter 11, the on-chip lens 12, and the like are formed on the back surface side, a voltage applying unit is configured to apply a voltage to the conductive material layer 25 from the front surface side of the single crystal silicon layer 4. As described above, the voltage application means is configured to apply a voltage that can remove the ground voltage and minority carriers.
That is, as described above, for example, a voltage is applied to the conductive material layer 25 by a voltage applying unit provided outside via the wiring 26 and the electrode layer 20 in the pad region 43.

  When the solid-state imaging device is configured using the solid-state imaging device 31 having the configuration in which the conductive material layer 25 is formed in the element isolation region 5 of the imaging region 41 as described above, in the solid-state imaging device 31 as described above, It is possible to prevent holes from being easily accumulated in the photoelectric conversion element 7, and the saturation signal amount in the photoelectric conversion element 7 can be always constant. As a result, the saturation charge amount (Qs) in the photoelectric conversion element 7 can be prevented from fluctuating and the saturation charge amount (Qs) can be made constant. For example, the color changes over time. It is possible to solve the time dependency problem. In addition, a decrease in sensitivity can be prevented.

Next, still another embodiment of the solid-state imaging device of the present invention will be described.
In the solid-state imaging device 32 of the present embodiment, in the optical black region 42, the conductive material layer 25 is formed in the element isolation region 5 made of a P-type semiconductor region that separates the adjacent photoelectric conversion elements 7.
Since other configurations such as a material used for the conductive material layer 25 are the same as the configurations of the solid-state imaging device 1 of the above-described embodiment, a duplicate description is omitted.

When the solid-state imaging device is configured using the solid-state imaging device 32 having the configuration in which the conductive material layer 25 is formed in the element isolation region 5 of the optical black region 42, the surface side of the single crystal silicon layer 4 is used. The voltage applying means is configured to apply a voltage to the conductive material layer 25 from the first to second. As described above, the voltage application means is configured to apply a voltage that can remove the ground voltage and minority carriers.
That is, as described above, for example, a voltage is applied to the conductive material layer 25 by a voltage applying unit provided outside via the wiring 26 and the electrode layer 20 in the pad region 43.
In the case of the solid-state imaging device having such a configuration, voltage application is performed so that a voltage is applied to the conductive material layer 25 not from the front surface side of the single crystal silicon layer 4 but from the back surface side of the single crystal silicon layer 4. Means can also be configured. In this case, as described above, for example, a wire or the like is connected to the light shielding film 19 in the optical black region 42 so that a voltage is applied to the conductive material layer 25 through the light shielding film 19.

  Even when the solid-state imaging device is configured using the solid-state imaging device having the configuration in which the conductive material layer 25 is formed in the element isolation region 5 of the optical black region 42 as described above, the photoelectric conversion element 7 in the solid-state imaging device 32 is used. It is possible to prevent holes from being easily accumulated therein, and the saturation signal amount in the photoelectric conversion element 7 can be always kept constant. As a result, the saturation charge amount (Qs) in the photoelectric conversion element 7 can be prevented from fluctuating and the saturation charge amount (Qs) can be made constant. For example, the color changes over time. It is possible to solve the time dependency problem. In addition, a decrease in sensitivity can be prevented.

  7 and 8, in the configuration in which the conductive material layer 25 is formed in the element isolation region 5, it may be formed in each of the plurality of element isolation regions 5 that separate the photoelectric conversion elements 7. Is possible.

In each of the above-described embodiments (and other embodiments), the conductive material layer 25 is formed so as to penetrate from the back surface side to the front surface side of the semiconductor well region 6. As shown in FIG. 9, the conductive material layer 25 may be formed from the interface on the back surface side of the semiconductor well region 6 to the middle. FIG. 9 shows an enlarged cross-sectional view around the conductive material layer 25.
In the case of forming the conductive material layer 25 having such a configuration, the hole 27 may be formed under the condition that it does not penetrate to the surface side of the single crystal silicon layer 4 in the step of forming the hole 27 shown in FIG. 5G.

  When the solid-state imaging device is configured using the solid-state imaging device having such a configuration, since the conductive material layer 25 does not reach the surface side of the single crystal silicon layer 4, a voltage is applied to the surface side of the single crystal silicon layer 4. Cannot be configured to be applied. Accordingly, the voltage is applied to the back surface side of the single crystal silicon layer 4.

  As described above, even when the solid-state imaging device is configured using the solid-state imaging device having the configuration in which the conductive material layer 25 is formed partway from the interface on the back surface side of the semiconductor well region 6 as described above, Therefore, it is possible to prevent holes from being easily accumulated in the photoelectric conversion element 7, and the saturation signal amount in the photoelectric conversion element 7 can be always constant. As a result, the saturation charge amount (Qs) in the photoelectric conversion element 7 can be prevented from fluctuating and the saturation charge amount (Qs) can be made constant. For example, the color changes over time. It is possible to solve the time dependency problem. In addition, a decrease in sensitivity can be prevented.

In the above-described embodiment, the description has been made on the assumption that the semiconductor well region 6 and the element isolation region 5 are formed in the groundable region. However, for example, in the region where it is difficult to ground the semiconductor When the well region 6, the element isolation region 5, or the like is formed, for example, an insulating film or a PN junction region is formed at the boundary between the regions 5 and 6 and the conductive material layer 25. Try to insulate.
Thereby, for example, it is possible to prevent the influence of the characteristics of the peripheral circuit portion formed on the outer periphery of the imaging region 41 and the optical black region 42.

In the above-described embodiment, a metal material is used as the conductive material layer 25. However, the material used for the conductive material layer 25 is not limited to the above-described types of metal materials as long as the material has high conductivity. . Note that when a metal material is used, minority carriers are easily extracted because of its low resistance as described above.
Note that, when a metal material is used in this way, for example, a case where the metal material embedded in the hole 27 diffuses into the single crystal silicon layer 4 can be considered. Therefore, as shown in FIG. 10, it is possible to form a barrier metal film 33 on the side wall of the hole 27 to prevent metal diffusion.

  In the above-described embodiment, one conductive material layer 25 is formed in each of the semiconductor well region 6 and the element isolation region 5, but a plurality of conductive material layers 25 may be formed.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 1,31,32 ... Solid-state image sensor, 2 ... Silicon substrate, 3 ... Embedded oxide film, 4 ... Single crystal silicon layer (semiconductor base | substrate), 5 ... Element isolation region, 6. ..P-type semiconductor well region, 7 ... photoelectric conversion element, 8 ... charge storage region, 9 ... positive charge storage region, 10 ... antireflection film, 11 ... color filter, 12 ... On-chip lens, 13 (131, 132, 133) ... Wiring layer, 14 ... Gate electrode, 15 ... Insulating layer, 16 ... Planarization film, 17 Adhesive layer, 18. ..Support substrate, 19 ... light shielding film, 20 ... electrode layer, 21 ... opening, 25 ... conductive material layer, 26 ... wiring, 27 ... hole, 33 ... barrier Metal film, 41 ... imaging area, 42 ... optical black area, 43 ... pad area

Claims (10)

A photoelectric conversion element formed in the semiconductor substrate;
An insulating layer provided on the surface side of the semiconductor substrate;
A plurality of wiring layers formed in the insulating layer;
A semiconductor region formed in the semiconductor substrate around the photoelectric conversion element;
A conductive material layer formed in contact with at least part of the semiconductor region;
An electrode layer for connection to external wiring formed in the insulating layer;
An opening that exposes the electrode layer from the back side of the semiconductor substrate ,
The electrode layer is formed in the same layer as the wiring layer that is formed closest to the photoelectric conversion element side,
A solid-state imaging device in which the photoelectric conversion element is irradiated with light from the back side of the semiconductor substrate.   The solid-state imaging device according to claim 1, wherein the semiconductor region and the insulating layer are opened in the opening.   The solid-state imaging device according to claim 2, wherein an insulating layer is formed on a side wall of the semiconductor region of the opening.   The solid-state imaging device according to claim 1, further comprising a support substrate on the insulating layer formed on the semiconductor substrate.   2. The solid-state imaging device according to claim 1, wherein the conductive material layer is formed on at least a part of the semiconductor region from a back side of the semiconductor substrate and is in contact with the semiconductor region.   The solid-state imaging device according to claim 5, wherein the conductive material layer is embedded in a hole formed so as to penetrate from the back surface side of the semiconductor region to the front surface side of the semiconductor substrate.   The solid-state imaging device according to claim 6, wherein the conductive material layer is connected to the wiring layer formed closest to the photoelectric conversion element in the insulating layer. A photoelectric conversion element formed in a semiconductor substrate, an insulating layer provided on the surface side of the semiconductor substrate, a wiring layer formed in the insulating layer, and the semiconductor around the photoelectric conversion element A semiconductor region formed in the substrate, a conductive material layer formed in contact with at least a part of the semiconductor region, and an electrode layer for connection to external wiring formed in the insulating layer; And an opening that exposes the electrode layer from the back side of the semiconductor substrate ,
The electrode layer is formed in the same layer as the wiring layer that is formed closest to the photoelectric conversion element side,
A solid-state imaging device in which light is irradiated to the photoelectric conversion element from the back side of the semiconductor substrate;
Means for applying a voltage to the solid-state imaging device,
A ground potential is applied to the conductive material layer from the means. A photoelectric conversion element formed in a semiconductor substrate, an insulating layer provided on the surface side of the semiconductor substrate, a wiring layer formed in the insulating layer, and the semiconductor around the photoelectric conversion element A semiconductor region formed in the substrate, a conductive material layer formed in contact with at least a part of the semiconductor region, and an electrode layer for connection to external wiring formed in the insulating layer; An opening that exposes the electrode layer from the back surface side of the semiconductor substrate, and the electrode layer is formed in the same layer as the wiring layer that is formed closest to the photoelectric conversion element side, and the photoelectric conversion A solid-state imaging device that is irradiated with light from the back side of the semiconductor substrate;
Means for applying a voltage to the solid-state imaging device,
A solid-state imaging device in which a positive potential or a negative potential capable of extracting minority carriers is applied from the means to the conductive material layer. Forming an element isolation region and a photoelectric conversion region in a semiconductor layer on one main surface side of the semiconductor substrate on which the buried oxide film is formed;
Forming a gate electrode on the semiconductor layer, forming a source region and a drain region in the semiconductor layer, and forming a transistor;
Forming an insulating layer on the semiconductor layer;
Forming a wiring layer and an external connection electrode layer on the insulating layer;
Forming a multilayer wiring layer by forming an insulating layer and a wiring layer on the wiring layer and the electrode layer;
Attaching a support substrate on the multilayer wiring layer;
Removing the semiconductor layer on the other main surface side of the semiconductor substrate;
Removing the insulating layer and the semiconductor layer on the electrode layer and forming an opening from which the electrode layer is exposed;
Forming a conductive material layer by forming an opening exposing a wiring layer in the semiconductor layer and the insulating layer and filling the opening with a conductive material;
Forming a light-shielding film that covers a part of the photoelectric conversion region on the semiconductor layer. A method for manufacturing a solid-state imaging device.

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