JP5077069B2 - Circuit system and power supply voltage control method for circuit system - Google Patents

Description

  The present invention relates to a circuit system including a plurality of logic circuit blocks that operate by being supplied with power by a series regulator that steps down the voltage of an input power supply and controls the voltage of an output power supply, and a power supply voltage control method for the circuit system.

In a series regulator that steps down the input power supply and controls the voltage of the output power supply, the efficiency increases as the difference between the input power supply voltage and the output power supply voltage decreases. For example, Patent Document 1 discloses a configuration in which an input power supply voltage of a series regulator is set to be lower than an operation power supply voltage of a regulator control IC.
JP 2001-216037 A

However, in the configuration of Patent Document 1, when it is necessary to use an input power supply for the series regulator that cannot change the output voltage, such as a battery, it is necessary to prepare a step-down means such as a switching power supply separately. There is a problem that the cost increase is inevitable.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a circuit system capable of reducing the difference from the output voltage and improving the efficiency even when the input voltage of the series regulator cannot be changed, and the power supply voltage of the circuit system. It is to provide a control method.

According to the circuit system of claim 1, a plurality of logic circuit blocks are connected in series between the output terminal of the series regulator and the ground, and the power consumption adjusting unit adjusts its own power consumption to these logic circuit blocks. Is placed. Then, when the potential monitoring means monitors the power supply terminal potential for the logic circuit blocks other than those arranged at the uppermost stage, the control means consumes the power consumption adjusting unit of each logic circuit block according to the monitoring result. Give power adjustment command.
That is, by adjusting the power consumption of each logic circuit block, the power supply terminal potential (operating voltage) of each block can be adjusted to an appropriate value. The total operating voltage of each logic circuit block is the output voltage of the series regulator. Therefore, if the number of logic circuit blocks connected in series is set appropriately, the output voltage can be adjusted even when it is difficult to adjust the input voltage of the regulator. The potential difference can be reduced to reduce the loss and improve the efficiency.
In addition, the control means adjusts the power of a plurality of logic circuit blocks arranged at the uppermost stage so as to increase the power consumption when the power supply terminal potential of the logic circuit block immediately below the reference value exceeds the reference value. A command is given, and if the potential is less than or equal to the reference value, a power adjustment command is given to reduce power consumption.
For those other than those arranged at the uppermost stage, when the power supply terminal potential of the logic circuit block is equal to or lower than the reference value, a power adjustment command is given to increase the power consumption, and the potential is lower than the reference value. If it is high, a power adjustment command is given to reduce the power consumption. Therefore, the power supply terminal potentials of a plurality of logic circuit blocks connected in series in multiple stages can be adjusted appropriately according to their connection positions.

  According to the circuit system of claim 2, the potential monitoring unit performs A / D conversion on the monitoring target potential selected by the selection unit by the A / D conversion circuit, so that the power supply terminal potentials of the plurality of logic circuit blocks are It can be converted into data by one A / D conversion circuit.

  According to the circuit system of the third aspect, since the data holding means holds the potential data A / D converted by the A / D conversion circuit, the control means is held even when the number of logic circuit blocks is large. Each potential data can be evaluated in parallel.

According to the circuit system of the fourth aspect , the power consumption adjusting unit changes the set value of the frequency setting means in accordance with the control command given by the control means, and sets the frequency of the operation clock oscillated and output by the clock oscillation circuit. Therefore, the power consumption of the logic circuit block can be adjusted by increasing or decreasing the frequency of the operation clock.

According to the circuit system of the fifth aspect , the power consumption adjusting unit changes the set value of the operation number determining unit in accordance with a control command given by the control unit, and determines the number for operating the plurality of dummy circuit units. Therefore, the power consumption of the logic circuit block can be adjusted by increasing / decreasing the number of dummy circuit portions that perform logic operation.

According to the circuit system of claim 6 , the dummy circuit unit supplies an operation clock to the clock divide-by-2 circuit configured in a loop shape including an odd number of logic inversion gates via the clock gate circuit. Thus, the logic operation can be performed so as to sequentially invert the logic level in synchronization with the operation clock, and power can be consumed.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows the overall configuration of the circuit system. The series power supply (series regulator) 1 generates and outputs a power supply obtained by stepping down a battery power supply VB having a voltage of about 12 V, for example, and three circuit blocks (logic circuit blocks) are provided between the power supply output terminal and the ground. 2A, 2B, 2C are connected in series. The proper operating voltage of these circuit blocks 2A, 2B, and 2C is set to, for example, about 3.3V. In this case, the output voltage of the series power supply 1 is 3.3V × 3 = 9.9V. Set.

The circuit block 2 includes a logic circuit unit 3 and a power consumption adjustment unit 4. The logic circuit unit 3 is a part configured to realize an original function required for the circuit block 2 by a logic circuit. The power consumption adjustment unit 4 is not involved in the above function, and the circuit block 2 It is the part comprised in order to adjust the power consumption.
The power supply terminals of the circuit blocks 2B and 2C are connected to the sensor unit (potential monitoring means) 5, and the sensor unit 5 performs A / D conversion on the power supply terminal potentials (X) and (Y) of the circuit blocks 2B and 2C. The processed data is output to the control unit (control means) 6. The control unit 6 instructs the power consumption adjusting units 4A, 4B, and 4C of the circuit blocks 2A, 2B, and 2C according to the data of the supplied power supply terminal potentials (X) and (Y) (power adjustment command). Is output.

  FIG. 2 shows the internal configuration of the sensor unit 5. The sensor unit 5 includes a selector (selection unit) 7, an A / D conversion unit (A / D conversion circuit) 8, and potential data holding circuits (data holding units) 9X and 9Y. The selector 7 selects whether the analog voltage to be A / D converted is the power supply terminal potential (X) or (Y), and the A / D converter 8 sets the voltage selected by the selector 7 to A / D The D-converted data is output to the potential data holding circuits 9X and 9Y. The potential data holding circuit 9 includes a data latch, and the data held by the holding circuit 9 is output to the control unit 6. The control unit 6 performs input selection in the selector 7, A / D conversion control of the A / D conversion unit 8, and latch control of the potential data holding circuits 9X and 9Y.

  FIG. 3A shows the configuration of the power consumption adjustment unit 4 constituting the circuit block 2 in function blocks. The power consumption adjustment unit 4 includes a clock generation circuit (clock oscillation circuit) 11, a frequency holding circuit (frequency setting means) 12, and a frequency update circuit (frequency setting means) 13. The clock generation circuit 11 is configured to be able to change the oscillation frequency of a clock signal to be generated and output in accordance with a frequency command given through the frequency holding circuit 12, and the clock signal is supplied to the logic circuit unit 3. System clock. The output data of the frequency holding circuit 12 is given to the frequency updating circuit 13, and the frequency updating circuit 13 increases or decreases the data value output to the frequency holding circuit 12 by df in accordance with the power consumption instruction given from the control unit 6. It is supposed to let you.

  FIG. 3B shows a configuration example of the power consumption adjustment unit 4 more specifically. The clock generation circuit 11 is configured as a PLL (Phase Locked Loop) circuit 11A, and multiplies the frequency of a reference clock signal given from an oscillation circuit (not shown) by a multiplication number holding circuit 12A corresponding to the frequency holding circuit 12. Oscillation is performed so as to multiply the frequency according to the data. The PLL circuit 11A may be either an analog system or a digital system.

  The frequency update circuit 13 includes an adder 14, a subtracter 15, and a selector 16 as a multiplication number update circuit 13A. The adder 14 and the subtracter 15 add +1 and −1 respectively to the output data of the multiplication number holding circuit 12A and output it to the selector 16. The selector 16 outputs from the adder 14 and the subtracter 15 according to the power consumption instruction. Any one of the data to be processed is selected and output to the multiplication number holding circuit 12A.

FIG. 4A is a block diagram showing the internal functions of the control unit 6. The control unit 6 includes comparison units 16X and 16Y and an instruction signal generation unit 17. The comparison units 16X and 16Y are magnitude comparators that compare the data of the power supply terminal potentials (X) and (Y) A / D converted by the sensor unit 5 with the data of the reference values X and Y, respectively. When “X)> reference value X], [potential (Y)> reference value Y]”, data “1” is output to the instruction signal generation unit 17. The reference value Y is set to 3.3V, which is the operating voltage of the circuit block 2C, and the reference value X is set to 6.6V, which is twice that value.
Then, the instruction signal generation unit 17 sends the power consumption instructions A to the power consumption adjustment units 4A to 4C of the circuit blocks 2A to 2C based on the logic shown in the drawing according to the output results of the comparison units 16X and 16Y. C is output.

  FIG. 4B shows the control logic of the instruction signal generator 17 by logic gates. That is, among the circuit blocks 2A to 2C, the circuit block 2A located at the uppermost level may be output as a command as it is as the output result of the comparison unit 16X, and the circuit block 2B located at the middle level is output from the comparison unit 16X. The output result is inverted by the NOT gate 18 and output. For the circuit block 2C located at the lowest stage, the output result of the comparison unit 16Y may be inverted by the NOT gate 19 and output.

  Next, the operation of the present embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing a flow of a series of processing by a circuit centering on the control unit 6. The control unit 6 applies each control signal to the sensor unit 5 to A / D convert the power supply terminal potentials (X) and (Y) of the circuit blocks 2B and 2C, respectively, and store the data in the holding circuits 9X and 9Y. (Step S1).

  Then, the potential (X) is compared with the reference value X (step S3). If [potential (X)> reference value X] (YES), the power consumption of the circuit block 2A is increased and the circuit block 2B An instruction is given to reduce power consumption (steps S4 and S5). On the other hand, if [potential (X) ≦ reference value X] (NO), the reverse is true, and an instruction is given to decrease the power consumption of the circuit block 2A and increase the power consumption of the circuit block 2B (step S6). , S7).

Subsequently, the control unit 6 compares the potential (Y) with the reference value Y (step S8), and if [potential (Y)> reference value Y] (YES), the power consumption of the circuit block 2C is reduced. If [potential (Y) ≦ reference value Y] (NO), an instruction is given to increase the power consumption of the circuit block 2C (step S10). These instructions match those shown in FIG.
When a power consumption increase command is given to each of the circuit blocks 2A to 2C, the frequency of the clock signal output from the power consumption adjustment unit 4 increases, so that the power consumption in the logic circuit unit 3 increases and the power consumption decreases. When the command is given, the frequency of the clock signal output by the power consumption adjusting unit 4 is lowered, and the power consumption in the logic circuit unit 3 is reduced.

  If the control unit 6 adjusts the power consumption of each of the circuit blocks 2A to 2C as described above, the power supply terminal potentials of the circuit blocks 2B and 2C are maintained at about 3.3V and 6.6V, respectively. The voltage between these power supply terminals and the GND terminal (of each circuit) is approximately 3.3V, so the voltage between the power supply terminal and the GND terminal of the circuit block 2A is also close to 3.3V, and the output voltage of the series power supply 1 is approximately The state is divided into three equal parts.

  As described above, according to this embodiment, a plurality of circuit blocks 2A to 2C are connected in series between the output terminal of the series power supply 1 and the ground, and the power consumption for adjusting the power consumption of these circuit blocks 2 is adjusted. The power adjustment unit 4 is arranged. When the power supply terminal potentials (X) and (Y) are monitored for the circuit blocks 2B and 2C excluding the circuit block 2A arranged at the uppermost stage via the sensor unit 5, the control unit 6 displays the monitoring result. Accordingly, the power consumption adjustment commands A to C are given to the power consumption adjustment units 4A to 4C of the circuit blocks 2A to 2C, respectively.

  That is, if the power consumption of each circuit block 2A to 2C is adjusted, the voltage between the power supply and the GND terminal (operating voltage) of each circuit block 2 can be adjusted to an appropriate value, and the sum of the operating potentials of each circuit block 2 can be adjusted. Becomes the output voltage of the series power supply 1. Therefore, if the number of series connections of the circuit block 2 is appropriately set, even if it is difficult to adjust the input voltage because the input power source of the series power source 1 is a battery or the like, the potential difference with the output voltage is reduced to reduce loss. And efficiency can be improved.

  Since the sensor unit 5 performs A / D conversion on the monitoring target potential selected by the selector 7, the A / D conversion unit 8 converts the power supply terminal potentials (X) and (Y) of the plurality of circuit blocks 2B and 2C. Data can be converted into data by one A / D converter 8. Further, since the data of the potentials (X) and (Y) A / D converted by the A / D conversion unit 8 are held by the data holding circuits 9X and 9Y, the control unit can be used even when the number of circuit blocks 2 is large. 6 can evaluate the held potential data in parallel.

  Further, for the circuit block 2A arranged at the uppermost stage, the control unit 6 issues a power adjustment command A so as to increase the power consumption when the potential (X) of the circuit block 2B immediately below it exceeds the reference value X. When the potential (X) is less than or equal to the reference value X, the power adjustment command A is given so as to reduce the power consumption. For the other circuit blocks 2B and 2C, the potentials (X) and (Y) are set so as to increase the power consumption when the potentials (X) and (Y) are equal to or lower than the corresponding reference values X and Y. Are higher than the corresponding reference values X and Y, the power adjustment commands B and C are given so as to reduce the power consumption. Therefore, the voltage between the power supply and the GND terminals of the plurality of circuit blocks 2A to 2C that are connected in series in multiple stages can be appropriately adjusted according to each connection position.

  In addition, the power consumption adjustment unit 4 changes the setting value of the frequency setting circuit 12 according to the power consumption command given by the control unit 6 and sets the frequency of the operation clock oscillated and output by the clock generation circuit 12. The power consumption of the circuit block 2 can be adjusted by increasing or decreasing the operation clock frequency of the logic circuit unit 3.

(Second embodiment)
6 and 7 show a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. The A / D conversion circuit 21 of the second embodiment is obtained by replacing the power consumption adjustment unit 4 of the first embodiment with a power consumption adjustment unit 22.
In addition to the logic circuit unit 3, the power consumption adjustment unit 22 includes a power consumption circuit 23 for consuming power without being involved in the original function of the circuit block 2. The power consuming circuit 23 includes a plurality of dummy blocks (dummy circuit units) 26 including a dummy circuit (clock 2 frequency dividing circuit) 24 and a clock gate circuit 25. The clock gate circuit 25 is a circuit that supplies or blocks the clock signal output from the clock generation circuit 27 to the dummy circuit 24. The clock generation circuit 27 also supplies a clock signal to the logic circuit unit 3.

  A clock supply permission signal is given to the clock gate circuit 25 of each dummy block 26 by an operation number determination circuit (operation number determination means) 28. The operation number determination circuit 28 includes a dummy block number holding circuit 29, a block number updating circuit 30, and a decoding circuit 31, and the decoding circuit 31 decodes the operation number data of the dummy block 26 given from the dummy block number holding circuit 29. Then, a clock supply permission signal is individually output to the clock gate circuit 25 of each dummy block 26. The block number update circuit 30 increases or decreases (± 1) the operation number data of the dummy block 26 to be set and held in the dummy block number holding circuit 29 in accordance with the power consumption instruction given from the control unit 6.

  FIG. 7 shows the configuration shown in FIG. 6 more specifically. The dummy circuit 24 forms a clock divide-by circuit by connecting a D flip-flop (F / F) 32 and an odd number, for example, nine NOT gates 33 in a loop. The flip-flop 32 is arranged at the first stage, and the output terminal of the ninth NOT gate 33 as the final stage is connected to the D input terminal of the flip-flop 32. A clock signal is supplied to the clock terminal of the flip-flop 32 via a clock gate circuit 25 configured by, for example, an AND gate. In one dummy circuit 24, two sets of flip-flops 32 and nine NOT gates 33 are arranged.

As the clock generation circuit 27, the PLL circuit 27A is used similarly to the clock generation circuit 11 of the first embodiment. In this case, for example, a fixed value is given to the multiplication data.
The dummy block number update circuit 30 includes an adder 34, a subtractor 35, and a selector 36, like the multiplication number update circuit 13A of the first embodiment. The adder 34 and the subtracter 35 add +1 to -1 to the output data of the dummy block number holding circuit 29 and output the data to the selector 36. The selector 36 outputs the data from the adder 34 and the subtractor 35 according to the power consumption instruction. When either one is selected, it is output to the dummy block number holding circuit 29.

Next, the operation of the second embodiment will be described. In the dummy circuit 24, when a clock signal is supplied via the clock gate circuit 25, the flip-flop 32 operates in synchronization with the rising edge of the clock signal, and the nine NOT gates 33 output the Q output of the flip-flop 32. The signal level of the terminal is sequentially inverted.
Since the number of connection stages of the NOT gate 33 is an odd number, the level determined at the D input terminal according to the level of the Q output terminal of the flip-flop 32 is the inversion of the Q output terminal. Accordingly, in the dummy circuit 24, the Q output terminal level of the flip-flop 32 is sequentially inverted in synchronization with the rising edge of the clock signal (in a cycle twice the clock signal cycle). The logic operation is performed so that the input / output levels are alternately inverted.

  Then, when the operation number determination circuit 28 increases or decreases the operation number of the dummy block 26 according to the power consumption command of the control unit 6 and gives it to the holding circuit 29, the decoding circuit 31 responds to the setting data of the holding circuit 29. Thus, a supply permission signal (high level) is output to the clock gate circuit 25 of each dummy block 26. That is, if the number of operations of the dummy block 26 increases, the power consumption of the circuit block 2 increases, and if the number of operations decreases, the power consumption also decreases.

As described above, according to the second embodiment, the power consumption adjusting unit 22 changes the set value in the operation number determining circuit 28 in accordance with the power consumption command given by the control unit 6, and operates the plurality of dummy blocks 26. Since the number to be determined is determined, the power consumption of the circuit block 2 can be adjusted by increasing or decreasing the number of dummy blocks 26 that perform logic operation.
The dummy block 26 supplies a clock signal to the dummy circuit 24 configured in a loop shape including an odd number of NOT gates 32 via the clock gate circuit 25, so that the dummy block 26 is synchronized with the clock signal. The circuit 24 can be logic-operated and circulated so as to invert the signal levels sequentially to consume power.

(Third embodiment)
FIG. 8 shows a third embodiment of the present invention, and different portions from the first embodiment will be described. Although the first embodiment shows the case where the number of series connections of the circuit block 2 is “3”, the third embodiment is an application extended to the case of “n” including the number of series connections of “4” or more. An example is shown. That is, n circuit blocks 2 (1, 2,..., N−1, n) are connected between the power supply output terminal of the series power supply 1N and the ground (where the ground side is “1”). The sensor unit 5N sequentially switches the potentials V1, V2,... V (n-1) of the circuit blocks 2 (1), 2 (2),. The unit 6N supplies power consumption to the power consumption adjusting unit 4 (not shown) of each circuit block 2 based on the result of comparing the potentials V1, V2,... V (n−1) with the corresponding reference values. Instructions 1 to n are given.

In this case, the power consumption instruction i (i = 1 to n−1) that the control unit 6N outputs to other than the circuit block 2 (n) located at the uppermost stage is determined as follows.
Potential (Vi) ≦ reference value Vi → plus (increase) power consumption instruction i
Potential (Vi)> reference value Vi → minus (decrease) power consumption instruction i
Further, the power consumption instruction n output from the control unit 6N to the circuit block 2 (n) positioned at the uppermost stage is determined as follows.
Potential (Vn−1)> reference value Vn−1 → plus (increase) power consumption instruction n
Potential (Vn−1) ≦ reference value Vn−1 → minus (decrease) power consumption instruction n
By setting as described above, the present invention can be similarly applied even when the number n of series connection stages is “2” or “4” or more.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The input voltage and output voltage of the series regulator, and the proper operating voltage of each circuit block are merely examples, and may be modified as appropriate.
The potential monitoring means may be composed of an analog comparator.
In the second embodiment, the number of clock divide-by-2 circuits arranged in one dummy circuit may be one or three or more.
The input power of the series regulator is not limited to the battery.

1 is a diagram illustrating an overall configuration of a circuit system according to a first embodiment of the present invention. Diagram showing the internal configuration of the sensor unit (A) is a figure which shows the structure of a power consumption adjustment part with a functional block, (b) is a figure which shows the structure more concretely. (A) is a block diagram showing the function of the control unit, (b) is a diagram showing the control logic of the instruction signal generation unit by a logic gate Flow chart showing the flow of processing by a circuit centering on the control unit FIG. 3 (a) equivalent view showing the second embodiment of the present invention. Fig. 3 (b) equivalent FIG. 1 equivalent view showing a third embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a series power supply (series regulator), 2 is a circuit block (logic circuit block), 3 is a logic circuit section, 4 is a power consumption adjustment section, 5 is a sensor section (potential monitoring means), and 6 is a control section ( Control means), 7 a selector (selection means), 8 an A / D converter (A / D conversion circuit), 9 a potential data holding circuit (data holding means), 11 a clock generation circuit (clock oscillation circuit), 12 is a frequency holding circuit (frequency setting means), 13 is a frequency updating circuit (frequency setting means), 22 is a power consumption adjusting unit, 24 is a dummy circuit (clock 2 frequency dividing circuit), 25 is a clock gate circuit, and 26 is a dummy. A block (dummy circuit unit) 28 indicates an operation number determination circuit (operation number determination means).

Claims (7)

A plurality of logic circuit blocks connected in series between the output terminal of the series regulator that controls the output voltage by stepping down the input voltage and the ground;
A power consumption adjustment unit that is arranged in each of the plurality of logic circuit blocks and adjusts the power consumption of each block;
Of the plurality of logic circuit blocks other than those arranged at the uppermost stage, potential monitoring means for monitoring the potential of the power supply terminal; and
In accordance with the monitoring result of each potential by the potential monitoring means, a control means for giving a power adjustment command to each of the power consumption adjusting units of the plurality of logic circuit blocks ,
The control means includes the plurality of logic circuit blocks.
For those arranged at the uppermost stage, when the power supply terminal potential of the logic circuit block immediately below it exceeds the reference value, a power adjustment command is given to increase the power consumption, and the potential is equal to or lower than the reference value. In some cases, give a power adjustment command to reduce power consumption,
For those other than those arranged at the uppermost stage, when the power supply terminal potential of the logic circuit block is equal to or lower than a reference value, a power adjustment command is given to increase power consumption, and the potential is higher than the reference value. A circuit system characterized by giving a power adjustment command so as to reduce power consumption . The potential monitoring means includes
A selection means for selecting a monitoring target potential;
2. The circuit system according to claim 1, further comprising an A / D conversion circuit for A / D converting the potential selected by the selection means.   3. The circuit system according to claim 2, further comprising data holding means for holding potential data A / D converted by the A / D conversion circuit. The power consumption adjustment unit is
A clock oscillation circuit that oscillates and outputs the operation clock of the corresponding logic circuit block at a set frequency; and
Frequency setting means for setting the frequency of an operation clock oscillated and output by the clock oscillation circuit, and configured to change the set value of the frequency setting means in accordance with a control command given by the control means The circuit system according to any one of claims 1 to 3, wherein The power consumption adjustment unit is
A plurality of dummy circuit portions that perform logic operation in synchronization with an operation clock of a corresponding logic circuit block ;
An operation number determining means for determining the number of operating the plurality of dummy circuit sections, and configured to change a set value of the operation number determining means in accordance with a control command given by the control means. The circuit system according to any one of claims 1 to 3 . The dummy circuit section is
A clock gate circuit for controlling the supply of the operation clock; and
A clock divide-by-2 circuit configured in a loop including an odd number of logic inversion gates,
6. The circuit system according to claim 5, wherein the operation clock is supplied to the clock divide-by-2 circuit via the clock gate circuit . A plurality of logic circuit blocks each having a power consumption adjustment unit that adjusts its own power consumption are connected in series between the output terminal of the series regulator that steps down the input voltage and controls the output voltage and the ground.
Among the plurality of logic circuit blocks, those other than those arranged at the uppermost stage are monitored for the potential of the power supply terminal, and the power consumption adjustment commands are respectively sent to the power consumption adjustment units of the plurality of logic circuit blocks according to the monitoring result. To control the power supply terminal potential of each logic circuit block,
Among the plurality of logic circuit blocks, those arranged in the uppermost stage, when the power supply terminal potential of the logic circuit block immediately below it exceeds the reference value, gives a power adjustment command to increase the power consumption, When the potential is less than or equal to the reference value, giving a power adjustment command to reduce power consumption,
For those other than those arranged at the uppermost stage, when the power supply terminal potential of the logic circuit block is equal to or lower than a reference value, a power adjustment command is given to increase power consumption, and the potential is higher than the reference value. A power supply voltage control method for a circuit system , wherein a power adjustment command is given so as to reduce power consumption .

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