JP5076042B2 - Display panel drive circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display panel drive circuit, and more particularly to a drive circuit for a display device using a display panel composed of self-luminous elements such as organic electroluminescence elements.
[Prior art]
An organic electroluminescence (hereinafter referred to as EL) element is known as a self-luminous element for realizing a thin display device with low power consumption. FIG. 4 is a diagram showing a schematic configuration of such an EL element. As shown in the figure, the EL element has at least one layer composed of an electron transport layer, a light emitting layer, a hole transport layer, etc. on a transparent substrate 100 composed of a glass plate or the like on which a transparent electrode 101 is formed. The organic functional layer 102 and the metal electrode 103 are laminated.
[0003]
FIG. 5 is an equivalent circuit that electrically shows the characteristics of the EL element. As shown in the figure, the EL element can be replaced by a capacitive component C and a diode characteristic component E coupled in parallel to the capacitive component.
Here, when a positive voltage is applied to the anode of the transparent electrode 101 and a negative voltage is applied to the cathode of the metal electrode 103 to apply a direct current between the transparent electrode and the metal electrode, charges are accumulated in the capacitive component C. At this time, when the barrier voltage or emission threshold voltage specific to the EL element is exceeded, current starts to flow from the electrode (the anode side of the diode component E) to the organic functional layer serving as the light emitting layer, and the organic function has an intensity proportional to this current. Layer 102 emits light.
[0004]
FIG. 6 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix. In the figure, an ELDP 10 as an EL display panel includes cathode lines (metal electrodes) B _{1 to} B _n that carry the first display line to the nth display line, and an array that intersects each of the cathode lines B _{1 to} B _n. is the m anode lines (transparent electrodes) a ₁ to a _m are formed. EL elements E _{11 to} E _nm having the above-described structure are formed at the intersections of the cathode lines B _{1 to} B _n and the anode lines A _{1 to} Am.
[0005]
Each of these EL elements E _{11 to} E _nm serves as one pixel as the ELDP 10.
The light emission control circuit 1 converts the input image data for one screen (n rows, m columns) into pixel data groups D _{11 to} D D corresponding to the respective pixels of the ELDP 10, that is, the EL elements E _{11 to} E _nm. These are converted to _nm , and these are sequentially supplied to the anode line drive circuit 2 for each row as shown in FIG. For example, the pixel data D _{11 to} D _nm are m data bits that specify whether or not light emission is performed for each of the EL elements E _{11 to} E _nm belonging to the first display line of the ELDP 10. When the logic level is “1”, “light emission” is indicated, and when the logic level is “0”, “non-light emission” is indicated.
[0006]
Further, as shown in FIG. 7, the light emission control circuit 1 scans each of the first display line to the nth display line of the ELDP 10 in order in synchronization with the supply timing of the pixel data for each row. A line selection control signal is supplied to the cathode line scanning circuit 3. First, the anode line drive circuit 2 extracts all the data bits of the logic level “1” designating “light emission” from the m data bits in the pixel data group. Next, the anode line belonging to "columns" corresponding to the data bits each and the extracted selected all from among the anode lines A ₁ to A _m, connects the constant current source only to the selected anode line, predetermined A pixel driving current i is supplied.
[0007]
The cathode line scanning circuit 3 selectively selects a cathode line corresponding to the display line indicated by the scanning line selection control signal from the cathode lines B _{1 to} B _n and sets the cathode line to the ground potential. A predetermined high potential Vcc is applied to each of the other cathode lines. Note that the high potential Vcc is set to be approximately the same value as the voltage across the EL element when the EL element emits light with a desired luminance (voltage determined based on the amount of charge to the parasitic capacitance C).
[0008]
At this time, a light emission driving current flows between the “column” to which the constant current source is connected by the anode line drive circuit 2 and the display line set to the ground potential by the cathode line scanning circuit 3. The EL element formed so as to cross the display line and the “column” emits light according to the light emission drive current. On the other hand, since no current flows between the display line set to the high potential Vcc by the cathode line scanning circuit 3 and the “column” to which the constant current source is connected, the display line and the “column” are crossed. The EL element thus formed remains non-light emitting.
[0009]
When the above operation is performed based on each of the pixel data groups D _{11 to} D _1m , D _{21 to} D _2m ,..., D _{n1 to} D _nm , the input image data is displayed on the ELDP 10 screen. A light emission pattern corresponding to one field, that is, an image is displayed.
[0010]
[Problems to be solved by the invention]
As described above, the output of the anode line drive circuit is a current output, and a current mirror is used for the current output. When the output current varies, the luminance of the organic EL panel varies. For this reason, it is very important to suppress current variation. However, when a current mirror is used, the output current varies due to current variations generated in the current mirror.
[0011]
Here, a conventional circuit configuration is shown in FIG. In the figure, a current mirror configured using N + 1 MOS (Metal Oxide Semiconductor) transistors is shown.
As shown in the figure, the current mirror circuit includes a current source I _org and N + 1 MOS transistors P _OUT0 , P _OUT1 ,..., P _OUTN . Of the N + 1 MOS transistors, one MOS transistor P _{OUT0 and the} current source I _org form a reference current source for the current mirror. Then, output currents from the other N MOS transistors are derived as display panel drive outputs. In this example, outputs from the other N MOS transistors P _{OUT1 to} P _OUTN are combined into one, and the combined output current I _out is derived as a drive output.
[0012]
Here, it is assumed that the sizes of the N + 1 MOS transistors P _{OUT0 to} P _OUTN are all the same. Then, the ratio between the current derived by the MOS transistor P _OUT0 and the current derived by the other N MOS transistors P _{OUT1 to} P _OUTN , that is, the current ratio is 1: N. Therefore, the output current I _{out at} this time is I _out = N × I _org
become.
[0013]
In general, the current variation ΔI depends on the size of the MOS transistor, and the current variation ΔI is large when the size of the MOS transistor is small. Conversely, when the size of the MOS transistor is large, the current variation ΔI is small.
In applications such as driving a display panel, the size of the “N” side MOS transistor having the current ratio of 1: N is much larger than the size of the “1” side MOS transistor. For example, N> 10. Therefore, the current variation ΔI is dominated by the current variation generated from the MOS transistor _Pout on the current ratio “1” side.
[0014]
It is also conceivable to reduce the current ratio of the current mirror. For example, 2: N / 2 or 3: N / 3 may be considered. In this way, the current variation ΔI is reduced. However, since there are as many channels as the number of anode lines, in that case, the amount of current of the current source I _org must be increased. As a result, the power consumption of the IC chip increases.
[0015]
The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to provide a display panel driving circuit capable of reducing current variations without increasing the power consumption of an IC chip. That is.
[0016]
[Means for Solving the Problems]
A display panel driving circuit according to claim 1 of the present invention includes one transistor that is connected to a current source and forms a reference current source, and N transistors (N is a natural number) that form a current mirror circuit together with the transistor. A display panel driving circuit comprising switching means for periodically switching a transistor forming a reference current source among the N + 1 transistors, wherein outputs from the other N transistors are combined into one display panel It is derived as a drive output of the self-luminous element that constitutes .
[0017]
A display panel driving circuit according to a second aspect of the present invention is the display panel driving circuit according to the first aspect , wherein the self-luminous elements are constituted by electroluminescent elements respectively driven by the driving output.
[0018]
In short, by periodically switching the transistors forming the reference current source, it is possible to reduce the current variation generated in the current mirror, and to eliminate the variation in the reference current among a plurality of IC chips. Uniform light emission luminance can be obtained on the display panel.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
FIG. 1 is a diagram showing a configuration of a main part in an embodiment of a display panel driving circuit according to the present invention. The figure shows a current mirror circuit composed of N + 1 MOS transistors.
[0020]
As shown in the drawing, the current mirror circuit includes a current source _Iorg , N + 1 MOS transistors _POUT0 , _POUT1 ,..., _POUTN , and switching circuits SW0, SW1,. It consists of The switching circuits SW0, SW1,..., SWN electrically connect only one of the N + 1 MOS transistors P _OUT0 , P _OUT1 ,..., P _OUTN to the current source I _org . One MOS transistor connected between the current source I _org together with the current source I _org, thereby forming the reference current source of the current mirror. Then, output currents from the other N MOS transistors are derived as display panel drive outputs. In this example, outputs from the other N MOS transistors P _{OUT1 to} P _OUTN are combined into one, and the combined output current I _out is derived as a drive output.
[0021]
In the switching circuits SW0, SW1,..., SWN in the figure, terminals connected to the current source I _org are indicated by ◯, and terminals connected to a signal line for deriving the output current I _out are indicated by ●. Yes. When the switching circuit SW0 is connected to the ◯ side terminal, the other switching circuits SW1 to SWN are connected to the ● side terminal. When the switching circuit SW1 is connected to the ◯ side terminal, the switching circuits SW1 and SW2 to SWN are connected to the ● side terminal. Similarly, the switching circuit connected to the ○ side terminal is sequentially switched. This switching is performed in synchronization with the clock.
[0022]
By controlling the switching circuits SW0 to SWN in this way, the transistors forming the reference current source among the N + 1 MOS transistors P _OUT0 , P _OUT1 ,..., P _OUTN are periodically switched. That is, by switching the switching circuit, all of the N + 1 MOS transistors are sequentially assigned to the “1” side of the current ratio 1: N that is dominant in current variation. Since switching control is performed in this way and time-sharing control (averaged over time) is performed on current variations of all N + 1 MOS transistors, current variations can be suppressed.
[0023]
Here, when the number N of transistors is 3 and the transistor variation is 1%, the current variation is about 1.4% in the related art, but according to the circuit of the present invention, the current variation is It is about 0.01%, and the variation in current is considerably reduced.
FIG. 2 is a timing chart showing the switching timing of the switching circuits SW0 to SWN. In the figure, a clock for switching the switching circuit, an on / off state of each switching circuit, and an output current _Iout are shown. In the figure, it is shown that the high-level switching circuit is in the on state.
[0024]
In the figure, when the switching circuit SW0 is in the ON state, the output current _Iout is N × I _ref + ΔI ₀ . Similarly, when the switching circuit SW1 is on, the output current I _out is N × I _ref + ΔI ₁ , and when the switching circuit SW2 is on, the output current I _out is N × I _ref + ΔI ₂ , and the switching circuit SWN is on. In this case, the output current I _out becomes N × I _ref + ΔI _N. Similarly, the transistors forming the reference current source are periodically switched by the switching circuit.
[0025]
As described above, the amount of current variation can be reduced by periodically switching the transistors forming the reference current source.
Here, a configuration example of the switching circuit is shown in FIG. The switching circuits SW0 to SWN shown in the figure include two analog switches to which currents output from the corresponding MOS transistors P _{OUT0 to} P _OUTN are input, respectively. The switching circuit SW0 is configured by analog switches SW01 and SW02. These analog switches SW01 and SW02 are both constituted by an N-type MOS transistor and a P-type MOS transistor having a common source and drain. A common gate of these N-type MOS transistor and P-type MOS transistor serves as a switching control terminal. Further, in the figure, there are provided a counter 200 that receives the above-mentioned clock and inverters INV0 to INVN that are provided corresponding to the switching circuits SW0 to SWN and invert the outputs 200-0 to 200-N of the counter 200. It has been. Note that the inverters INV0 to INVN are configured by, for example, a well-known CMOS (Complementary Metal Oxide Semiconductor) inverter circuit.
[0026]
While the output of the counter 200 is input as it is to the N-type MOS transistor of the analog switch SW01 and the P-type MOS transistor of the analog switch SW02, the P-type MOS transistor of the analog switch SW01 and the N-type MOS transistor of the analog switch SW02 The output of the counter 200 is logically inverted by the inverter INV0. Therefore, the analog switch SW01 is turned on only when the output 200-0 of the counter 200 is at a high level, and the analog switch SW02 is turned on when it is at a low level.
[0027]
Similarly, for the switching circuit SW1 including the analog switch SW11 and the analog switch SW12, the analog switch SW11 is turned on only when the output 200-1 of the counter 200 is at a high level, and the analog switch SW12 is turned on when the output 200-1 is at a low level. . The same applies to other switching circuits. In the switching circuit SWN, the analog switch SWN1 is turned on only when the output 200-N of the counter 200 is at a high level, and the analog switch SWN2 is turned on when the output is low.
[0028]
As shown in the figure, the output side of the analog switches SW01, SW11,..., SWN1 is connected to the current source I _org described above, and the output side of the analog switches SW02, SW12,. _Are derived as an output current I _out .
In such a configuration, the counter 200 receives the clock in FIG. 2 as an input, and sets only one of the outputs 200-1 to 200-N as a high-level pulse. And the output which makes this high level is shifted in order. By applying a high level pulse while sequentially shifting in this way, the transistor forming the reference current source among N + 1 MOS transistors is periodically switched as shown in FIG. As a result, all the N + 1 MOS transistors are sequentially assigned to the “1” side of the current ratio 1: N that is dominant in the current variation. Since the switching control is performed in this way and the time-sharing control is performed on the current variation of all N + 1 MOS transistors, the current variation can be suppressed. Since the configuration is as described above, current variations can be suppressed without increasing the current amount of the current source _Iorg .
[0029]
Therefore, according to this circuit, the current variation generated in the current mirror can be reduced without increasing the power consumption of the IC chip. Therefore, for example, by switching and controlling the switching circuit with a clock having a repetition frequency of 1000 Hz, it is possible to average the current supplied to the display panel composed of organic EL elements over time. For this reason, uniform light emission luminance is obtained on the display panel.
[0030]
【Effect of the invention】
As described above, according to the present invention, the current variation generated in the current mirror can be reduced by periodically switching the transistors forming the reference current source, and the variation in the reference current among a plurality of IC chips is achieved. Therefore, there is an effect that uniform light emission luminance can be obtained on the display panel.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a main part of a display panel driving circuit according to the present invention.
2 is a timing chart showing switching timing of a switching circuit in the display panel drive circuit of FIG. 1. FIG.
FIG. 3 is a diagram illustrating a configuration example of a switching circuit.
FIG. 4 is a diagram showing a schematic configuration of an EL element.
FIG. 5 is a diagram showing an equivalent circuit that electrically indicates the characteristics of an EL element.
FIG. 6 is a diagram showing a schematic configuration of an EL display device that displays an image using an EL display panel in which a plurality of EL elements are arranged in a matrix.
FIG. 7 is a diagram illustrating the supply timing of pixel data and a scanning line selection signal.
FIG. 8 is a diagram showing a conventional circuit.
[Explanation of symbols]
Light emission control circuit 2 anode line drive circuit 3 cathode line scan circuit 100 transparent substrate 101 transparent electrode 102 organic functional layer 103 metal electrodes 200 counter INV0~INVN inverter I _org current source I _out output current P _OUT0 to P _OUTN transistor SW0~SWN switching Circuits SW01 and SW02
SW11, SW12
SW11, SW12 Analog switch

Claims (2)

A display panel driving circuit comprising one transistor connected to a current source and forming a reference current source, and N (N is a natural number) transistors forming a current mirror circuit together with the transistor, wherein the N + 1 transistors Among them, the transistor that forms the reference current source includes switching means for periodically switching, and the outputs from the other N transistors are combined into one to derive the drive output of the self-luminous elements constituting the display panel. A display panel drive circuit characterized by that. The self-emission device, a display panel driving circuit according to claim 1, characterized in that it is constituted by electroluminescent elements driven respectively by the drive output.

Images