JP5070607B2 - Impedance adjustment device, impedance adjustment method - Google Patents

Description

The present invention relates to an impedance adjusting device and a method thereof.
Specifically, the present invention relates to an impedance adjustment device that performs impedance adjustment of an output buffer of a semiconductor storage device and an output buffer of a memory controller when using the semiconductor storage device.

  In a transmission line between a memory and an LSI (ASIC), impedance mismatch of the transmission line occurs due to variations in manufacturing processes, voltage fluctuations, temperature changes, and the like. In recent years, there has been a tendency to increase the operation speed, so that impedance mismatch in the transmission line cannot be ignored.

  For this reason, a ZQ calibration function has been newly added to DDR3-SDRAM (Double Data Rate 3-Synchronous Dynamic Random Access Memory). This function improves the quality of the transmission line in the direction of DDR3-SDRAM → LSI (ASIC) by adjusting the impedance of the output buffer on the DDR3-SDRAM side. Since data transfer is bidirectional, it is necessary to adjust the impedance of the output buffer on the LSI (ASIC) side in order to improve the quality of the transmission line in the LSI (ASIC) → DDR3-SDRAM direction.

  Here, general impedance adjustment will be described as background art. Note that the impedance adjustment circuit using the ZQ calibration function is described in Patent Documents 1 to 3, for example.

FIG. 7 is a diagram showing a peripheral circuit configuration of the memory.
In FIG. 7, the memory 2 and the internal circuit exchange data.
The internal circuit sends an instruction signal such as read or write to the memory control unit 34.
Then, the memory control unit 34 reads / writes data from / to the memory 2 via the memory interface 35.

Further, the diagnosis device 1 diagnoses the degree of impedance mismatch between the memory interface 35 and the memory 2, and instructs execution of impedance adjustment when a predetermined condition is satisfied.
Specifically, the diagnostic apparatus 1 outputs an IF impedance adjustment activation signal and a memory impedance adjustment activation signal.
The IF impedance adjustment activation signal is a signal for instructing impedance adjustment of the IF output buffer 351 of the memory interface 35.
The memory impedance adjustment activation signal is a signal for instructing impedance adjustment of the output buffer of the memory 2.
A signal from the diagnostic device 1 is output to the impedance adjustment device 3.

The memory 2 performs operations such as data reading / writing, impedance adjustment, and refreshing in response to commands sent from the memory control unit 34.
The memory control unit 34 controls the ZQ adjustment command and other commands such as read, write, and refresh, and outputs them to the memory interface 35.
The memory interface 35 sends commands and data to the memory 2 and receives data from the memory.

  The conventional impedance adjustment device 3 includes a diagnostic interface 31, an IF impedance adjustment unit 32, a memory impedance adjustment unit 33, and an adjustment code holding unit 36.

  The diagnostic interface 31 sends the signal sent from the diagnostic device 1 to the impedance adjusting unit 32 and the memory impedance adjusting unit 33, respectively. That is, the diagnostic interface 31 sends an IF impedance adjustment activation signal to the IF impedance adjustment unit 32, and sends a memory impedance adjustment activation signal to the memory impedance adjustment unit 33.

The IF impedance adjustment unit 32 generates an IF impedance adjustment code for adjusting the impedance of the IF output buffer 351 included in the memory interface 35.
The adjustment code holding unit 36 is a flip-flop circuit for taking in and holding the IF impedance adjustment code sent from the impedance adjustment unit 32.

  The memory impedance adjustment unit 33 issues a ZQ adjustment command that instructs impedance adjustment of the output buffer included in the memory 2.

Next, the operation of the conventional impedance adjusting device 3 will be described.
First, a procedure for adjusting the impedance of the IF output buffer 351 included in the memory interface 35 will be described.
An IF impedance adjustment activation signal is sent from the diagnostic device 1 to the IF impedance adjustment unit 32 via the diagnostic interface 31.
When the IF impedance adjustment activation signal is received, the impedance adjustment unit 32 generates an IF impedance adjustment code for performing impedance adjustment of the IF output buffer 351.

The generated IF impedance adjustment code is continuously output toward the adjustment code holding unit 36 and set in the adjustment code holding unit 36. The impedance adjustment of the IF output buffer 351 is executed based on the value of the IF impedance adjustment code set in the adjustment code holding unit.
The above operation is performed at the time of initialization, and is also periodically executed during normal operation.

Next, a procedure for adjusting the impedance of the output buffer of the memory 2 will be described.
At initialization, a memory impedance adjustment activation signal is sent from the diagnostic device 1 to the memory impedance adjustment unit 33 via the diagnostic interface 31.
When the memory impedance adjustment unit 33 receives the memory impedance adjustment activation signal, it issues a ZQ adjustment command.
The ZQ adjustment command is sent to the memory 2 via the memory control unit 34 and the memory interface 35. Then, the memory 2 executes impedance adjustment of the output buffer.

  During normal operation, the ZQ adjustment command is issued at a fixed period (a range from several ms to 1 s), and the impedance of the output buffer of the memory 2 is readjusted each time.

  As described above, in the conventional impedance adjustment, the impedance adjustment of the IF output buffer 351 of the memory interface 35 and the impedance adjustment of the output buffer of the memory 2 are performed, respectively, and thereby the transmission line between the memory and the memory interface is adjusted. The quality was improved.

JP 2005-198308 JP 2008-017475 JP 2008-228276 A

Incidentally, memory access is prohibited during the period in which the impedance adjustment of the IF output buffer 351 of the memory interface 35 is performed.
In addition, memory access is prohibited during the period when the impedance of the output buffer of the memory 2 is adjusted.
Thus, each impedance adjustment time becomes a memory access prohibition time as it is, and the memory throughput performance is lowered.
Here, in order to reduce the memory access prohibition time, it may be necessary to reduce the number of impedance adjustments. However, if the number of impedance adjustments is reduced, degradation of the transmission line due to impedance mismatch becomes a problem. End up.

  An object of the present invention is to provide an impedance adjusting device that improves the memory throughput as well as the quality of a transmission line.

The impedance adjusting device of the present invention is
An impedance adjustment device for adjusting impedance so as to match the impedance of an output buffer of a memory and the impedance of an output buffer of a memory interface,
A memory impedance adjustment unit that issues a ZQ adjustment command for instructing impedance adjustment of the output buffer of the memory;
An IF impedance adjustment unit that generates and outputs an IF impedance adjustment code for adjusting the impedance of the output buffer of the memory interface; and
An impedance adjustment synchronization unit that provides the IF impedance adjustment code to the memory interface in synchronization with the ZQ adjustment command being issued from the memory impedance adjustment unit.

The impedance adjustment method of the present invention is
An impedance adjustment method for adjusting impedance so as to match the impedance of an output buffer of a memory and the impedance of an output buffer of a memory interface,
Issue a ZQ adjustment command to instruct the impedance adjustment of the memory output buffer,
Generate an IF impedance adjustment code to adjust the impedance of the memory interface output buffer,
The IF impedance adjustment code is provided to the memory interface in synchronization with the ZQ adjustment command being issued.

The figure which shows the structure of 1st Embodiment. 4 is a timing chart showing an initialization sequence in the first embodiment. 5 is a timing chart showing impedance adjustment during normal operation in the first embodiment. 4 is a timing chart showing a second impedance adjustment during normal operation in the first embodiment. The figure which shows the structure of 2nd Embodiment. The figure which shows the structure of 3rd Embodiment. The figure which shows the peripheral circuit structure of memory as description of background art.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be illustrated and described with reference to the reference numerals attached to the respective elements in the drawings.
(First embodiment)
A first embodiment according to the impedance adjusting device of the present invention will be described.
FIG. 1 is a diagram showing a first embodiment.
Here, in FIG. 1, elements corresponding to those of the background art (FIG. 7) are denoted by the same reference numerals, and description thereof is omitted.
1 is different from FIG. 7 in that an impedance adjustment synchronization unit 37 is provided.
The impedance adjustment synchronization unit 37 includes an adjustment code holding unit 371, a two-input OR circuit 372, a selector unit 373, and a flip-flop circuit 374.

The adjustment code holding unit 371 is a flip-flop that holds the IF impedance adjustment code sent from the IF impedance adjustment unit 32.
The 2-input OR circuit 372 outputs a set signal for the adjustment code holding unit 371 to capture data.

The selector unit 373 receives a selection signal from the diagnostic interface 31.
This selection signal indicates “0” until the impedance adjustment of the IF output buffer 351 is completed in the initialization sequence.
After the impedance adjustment of the IF output buffer 351 is completed in the initialization sequence and during normal operation, the selection signal indicates “1”.

  The selection signal is branched and input to the inverting input terminal of the OR circuit 372.

The selector unit 373 receives an initial IF adjustment instruction signal from the diagnostic interface 31 and a ZQ adjustment command completion signal from the memory impedance adjustment unit 33.
Here, the initial IF adjustment signal is input to the terminal of reference numeral 0, and the ZQ adjustment command completion signal is input to the terminal of reference numeral 1. That is, the selector unit 373 selects the initial IF adjustment instruction signal from the diagnostic interface 31 until the impedance adjustment of the IF output buffer 351 is completed in the initialization sequence, and from the memory impedance adjustment unit 33 during normal operation. Select the ZQ adjustment command completion signal.
A signal from the selector unit 373 is input to the IF impedance adjustment unit 32 as an IF impedance adjustment activation signal.

  The flip-flop 374 receives the ZQ adjustment command completion signal from the memory impedance adjustment unit 33 at the clock timing, and outputs it to the selector unit 373.

During normal operation, the memory impedance adjustment unit 33 receives an instruction from the diagnostic device 1 and issues a ZQ adjustment command at a constant period (changeable within a range from several ms to 1 s).
At this time, the memory impedance adjustment unit 33 outputs the ZQ adjustment command completion signal to the flip-flop 374 after outputting the ZQ adjustment command to the memory control unit 34.
Note that it is not necessary to issue a ZQ adjustment command completion signal in the initialization sequence.

The operation of the first embodiment having such a configuration will be described.
First, an impedance adjustment method in the initialization sequence will be described.
FIG. 2 is a timing chart showing an initialization sequence.
In the initialization sequence, after adjusting the impedance of the IF output buffer 351, the impedance adjustment of the output buffer of the memory 2 is executed.
Hereinafter, it demonstrates in order.
At the time of initialization, the selection signal is “0”.
Since the selection signal “0” is input to the inverting input terminal of the OR circuit 372, the output of the OR circuit 372 is H at this time.

During initialization, an initial IF adjustment instruction signal is output from the diagnostic device 1 to the terminal 0 of the selector unit 373 via the diagnostic interface 31 (time T ₀₀ ).
Then, the selector unit 373 selects this initial IF adjustment instruction signal and sends it to the impedance adjustment unit 32 as an IF impedance adjustment activation signal.
The IF impedance adjustment unit 32 that has received the IF impedance adjustment activation signal generates an IF impedance adjustment code “A” for performing the impedance adjustment of the IF output buffer 351 and continues to output this value.

The output IF impedance adjustment code “A” is set in the adjustment code holding unit 371.
Using the adjustment code “A” set in the adjustment code holding unit 371, the impedance adjustment of the IF output buffer 351 is executed (time T ₀₁ ).

After adjusting the impedance of the IF output buffer 351, the diagnostic apparatus 1 lowers the initial IF adjustment instruction signal to L level and sets the selection signal to “1” (time T ₀₂ ). As a result, the IF impedance adjustment activation signal output from the selector unit 373 to the IF impedance adjustment unit 32 stops.

Next, a memory impedance adjustment activation signal is sent from the diagnostic device 1 via the diagnostic interface 31 to the memory impedance adjustment unit 33 (time T ₀₃ ).
When the memory impedance adjustment unit 33 receives the memory impedance adjustment activation signal, it issues a ZQ adjustment command (time T ₀₄ ). The ZQ adjustment command is sent to the memory 2 via the memory control unit 34 and the memory interface 35 (time T ₀₅ ).
Upon receiving this ZQ adjustment command, the memory 2 adjusts the impedance of the output buffer (time T ₀₆ ).

  Thus, during the initialization sequence, the impedance adjustment is executed in the order of the IF output buffer 351 of the memory interface 35 and the output buffer of the memory 2.

Next, an impedance adjustment procedure during normal operation will be described.
FIG. 3 is a timing chart showing impedance adjustment during normal operation.
When the initialization sequence is completed, normal operation is performed.
At this time, the selection signal is fixed at “1”, and the selector unit 373 selects the signal from the flip-flop 374 and outputs it to the IF impedance adjustment unit 32. The memory impedance adjustment unit 33 receives the activation signal from the diagnostic device 1 and issues a ZQ adjustment command at regular intervals.

When the first ZQ adjustment command is sent to the memory 2 via the memory control unit 34 and the memory interface 35, the memory that has received the ZQ adjustment command starts impedance adjustment of the output buffer (time _T07 ).

When the ZQ adjustment command is issued to the memory 2, the memory impedance adjustment unit 33 issues a ZQ adjustment command completion signal to the flip-flop 374 (time _T08 ).
The timing for issuing the ZQ adjustment command completion signal is set such that after the memory interface 35 sends the ZQ adjustment command to the memory 2, a transmission completion signal is sent back to the memory impedance adjustment unit 33. The memory impedance adjustment unit 33 may issue a ZQ adjustment command completion signal after receiving the signal.
Alternatively, a predetermined delay time may be set in the memory impedance adjustment unit 33, and after the ZQ adjustment command is issued, the ZQ adjustment command completion signal may be issued after a predetermined delay time has elapsed.

The ZQ adjustment command completion signal is once latched by the flip-flop 374 and then output to the selector unit 373.
The selector unit 373 selects the ZQ adjustment command completion signal and outputs it to the IF impedance adjustment unit 32 as an IF impedance adjustment activation signal (time T ₀₉ ).
The output from the flip-flop 374 is input to the OR circuit 372 and provided to the adjustment code holding unit 371 as a SET signal.

At this time, since the adjustment code output from the IF impedance adjustment unit 32 is the adjustment code “A” generated during the initialization sequence, the adjustment code holding unit 371 takes in the adjustment code A.
That is, the value of the adjustment code does not change.
Therefore, in this case, as a result, there is no impedance adjustment of the IF output buffer.

Further, when receiving the IF impedance adjustment activation signal, the IF impedance adjustment unit 32 starts generating the impedance adjustment code.
A predetermined time is required to generate the IF impedance adjustment code.
After generating a new adjustment code, the IF impedance adjustment unit 32 continues to output the impedance adjustment code “B” (time T ₁₀ ).

  In this way, the first adjustment sequence in the normal operation is completed.

Moves to the second adjustment sequence during normal operation.
FIG. 4 is a timing chart showing the second impedance adjustment during normal operation.

A second ZQ adjustment command is issued from the memory impedance adjustment unit 33 (time T ₁₁ ). Then, the ZQ adjustment command is sent to the memory 2 via the memory control unit 34 and the memory interface 35 (time T ₁₂ ).
When the ZQ adjustment command is received, the output buffer adjustment of the memory 2 is executed (time T ₁₃ ).

A ZQ adjustment command completion signal is issued from the memory impedance adjustment unit 33 (time T ₁₄ ), and is output to the IF impedance adjustment unit 32 as an IF impedance adjustment activation signal via the flip-flop 374 and the selector unit (time T ₁₅ ). Then, generation of the adjustment code is started in the IF impedance adjustment unit 32.

The output from the flip-flop 374 is also input to the OR circuit 372 and provided to the adjustment code holding unit 371 as a SET signal. Then, the adjustment code holding unit 371 takes in the adjustment code.
At this time, since the adjustment code “B” generated last time is output from the IF impedance adjustment unit 32, the adjustment code holding unit 371 takes in the adjustment code B.
The new adjustment code B is output from the adjustment code holding unit 371 to the memory interface 35. Then, the impedance adjustment of the IF output buffer of the memory interface is executed (time T ₁₆ ).

As described above, in the second adjustment sequence in the normal operation, the impedance adjustment of the IF output buffer 351 is executed together with the adjustment of the output buffer of the memory 2.
At this time, the adjustment of the IF output buffer 351 is started by supplying the ZQ adjustment command completion signal to the adjustment code holding unit 371 as the SET signal via the flip-flop 374 and the OR circuit 372.
Therefore, the impedance adjustment of the IF output buffer 351 is performed while the impedance adjustment of the output buffer of the memory 2 is being performed.

  The third and subsequent adjustment sequences in normal operation are the same as the second adjustment sequence described above.

According to the first embodiment having such a configuration, the impedance adjustment of the IF output buffer 351 is executed in synchronization with the period during which the impedance of the output buffer of the memory 2 is adjusted.
Here, the memory access is prohibited during the impedance adjustment of the output buffer of the memory 2.
Further, the memory 2 cannot be accessed while the impedance adjustment of the IF output buffer 351 is being executed.
Conventionally, the impedance adjustment of the memory output buffer and the impedance adjustment of the IF output buffer 351 have been executed at their own timings, so that the time during which memory access is disabled has been long.

In this regard, according to the present embodiment, the impedance adjustment of the IF output buffer 351 is executed in synchronization with the memory access inhibition time generated for adjusting the impedance of the memory output buffer.
As a result, it is possible to reduce the time during which memory access is disabled and to prevent a decrease in throughput due to impedance adjustment.
In addition, by synchronizing the timing of the impedance adjustment of the memory output buffer and the impedance adjustment of the IF output buffer, the time during which memory access is disabled is reduced, so the frequency of impedance adjustment can be increased compared to the conventional case, and the memory The reliability of the transmission line between the memory and the memory interface can be improved without reducing the throughput performance.

In the present embodiment, when the adjustment code is updated in the adjustment code holding unit 371, the value of the adjustment code generated in the previous adjustment sequence period is captured.
In this regard, the impedance adjustment period is as short as ms, and it can be estimated that the environmental change (for example, change in environmental temperature) during that period is extremely small.
Therefore, the impedance mismatch does not become a problem by using the value one cycle before, but rather, the advantage of the improvement in throughput and the increase in the number of adjustments according to this embodiment is much greater.

(Second embodiment)
Next, a second embodiment of the present invention will be described.
The basic configuration of the second embodiment is the same as that of the first embodiment, but is characterized by the operation when the quality of the transmission line between the memory and the memory interface is good.
FIG. 5 is a diagram illustrating a configuration of the second embodiment.
With reference to FIG. 5, the operation of the second embodiment will be described.

In the second embodiment (FIG. 5), an ECC (Error Check and Correct) circuit 38 performs error data correction and error detection on the read data from the memory 2.
The ECC circuit 38 sends the presence / absence of an error to the diagnostic apparatus 1 via the diagnostic interface 31.

The diagnostic apparatus 1 monitors error detection by the ECC circuit 38.
Here, when an error does not occur for a certain period of time, the apparatus environment is stable, and it is considered that impedance adjustment is not particularly necessary. Therefore, the diagnostic device 1 issues a memory impedance adjustment stop signal when an error does not occur for a certain time.
The memory impedance adjustment stop signal is sent to the memory impedance adjustment unit 33 via the diagnostic interface 31.
When the memory impedance adjustment unit 33 receives the memory impedance adjustment stop signal, the memory impedance adjustment unit 33 stops issuing the ZQ adjustment command.

If an error is detected by the ECC circuit 38, it is considered that impedance adjustment is necessary. Therefore, when the diagnostic device 1 recognizes the occurrence of the error by detecting the error by the ECC circuit 38, the diagnostic device 1 reissues the memory impedance adjustment activation signal.
The memory impedance adjustment activation signal is sent to the memory impedance adjustment unit 33.
When the memory impedance adjustment activation signal is received, the memory impedance adjustment unit 33 cancels the stop of the ZQ adjustment command and issues the ZQ adjustment command at a constant cycle.
The operation when the ZQ adjustment command is issued is the same as that in the first embodiment, and the impedance adjustment of the memory output buffer and the impedance adjustment of the IF output buffer 351 are executed.

  Thus, in the second embodiment, the impedance adjustment is not performed when the quality of the transmission line between the memory and the memory interface is good. Therefore, the memory access prohibition time is reduced and the memory throughput performance is improved.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
The basic configuration of the third embodiment is the same as that of the second embodiment, but the third embodiment is further characterized in the operation when an impedance adjustment stop signal is issued.
FIG. 6 is a diagram illustrating a configuration of the third embodiment.
In FIG. 6, the refresh control unit 39 issues a refresh command necessary for holding data in the memory 2 at a constant cycle.
For example, when the memory 2 is DDR3-SDRAM, a refresh command is issued at a constant cycle (T _REFI = 7.8 μs (0 ° C. ≦ Tcase <85 ° C.), 3.9 μs (85 ° C. ≦ Tcase <95 ° C.)).

The refresh command is output to the memory control unit 34 and sent from the memory control unit 34 to the memory 2 via the memory interface 35.
When the memory 2 receives the refresh command, the memory 2 performs a refresh operation.
In addition, after issuing the refresh command, the refresh control unit 39 sends a refresh issuance completion signal to the impedance adjustment synchronization unit 37.

In the third embodiment, the impedance adjustment synchronization unit 37 further includes a selector unit 375.
The selector unit 375 is disposed in front of the flip-flop 374.
Here, a selection signal is input to the selector unit 375 from the diagnostic device 1 via the diagnostic interface 31.
This selection signal is controlled to be “0” when a memory impedance adjustment start signal is issued, and to “1” when a memory impedance adjustment stop signal is issued.

Also, the selector unit 375 receives the ZQ adjustment command completion signal from the memory impedance adjustment unit 33 and the refresh issue completion signal from the refresh control unit 39.
Here, the ZQ adjustment command completion signal is input to the terminal of reference numeral 0, and the refresh issue completion signal is input to the terminal of reference numeral 1. That is, the selector unit 373 selects the ZQ adjustment command completion signal when the memory impedance adjustment start signal is issued, and selects the refresh issue completion signal when the memory impedance adjustment stop signal is issued. Then, a signal from the selector unit 375 is input to the flip-flop 374.

  A signal from the flip-flop 374 is input to the terminal 1 of the selector unit 373 and is branched and input to the OR circuit 372.

The operation of the third embodiment will be described.
The third embodiment is characterized by an operation when a memory impedance adjustment stop signal is issued, and is otherwise the same as the second embodiment.
Here, the operation when the memory impedance adjustment stop signal is issued will be mainly described.

The refresh control unit 39 periodically issues a refresh command.
Note that the refresh command is periodically issued to hold data regardless of the presence or absence of the memory impedance adjustment stop signal.
The refresh command is sent to the memory 2 via the memory control unit 34 and the memory interface 35.
When the refresh command is received, the memory 2 starts a refresh operation.
After issuing the refresh command, the refresh control unit 39 sends a refresh issuance completion signal to the selector unit 375.

Here, since the memory impedance adjustment stop signal is issued, the selection signal is “1”.
The selector unit 375 selects the refresh issue completion signal and sends it to the flip-flop 374.

The flip-flop 374 latches the refresh issue completion signal once, and then outputs it to the selector unit 373.
The selector unit 373 selects the refresh issue completion signal and sends it to the IF impedance adjustment unit 32 as an IF impedance adjustment activation signal.

The IF impedance adjustment unit 32 that has received the IF impedance adjustment activation signal starts generating the IF impedance adjustment code, and continues to output the IF impedance adjustment code after completion.
The refresh issue completion signal latched by the flip-flop 374 passes through the OR circuit 372 and becomes a set signal for the adjustment code holding unit 371.
As described in the first embodiment, since it takes time to generate the impedance adjustment code, the adjustment code holding unit 371 is set with the impedance adjustment code generated in the previous sequence.
The impedance of the IF output buffer 351 of the memory interface 35 is adjusted by the adjustment code set in the adjustment code holding unit 371.
This impedance change is performed within the memory access prohibition time (tRFC = 110 ns (capacity 1 Gb)) during refresh as defined by the DDR3 specification.

In the third embodiment, impedance adjustment of the IF output buffer 351 is performed while the memory 2 is performing refresh.
Since access to the memory 2 becomes impossible while the memory 2 is performing refresh, the quality of the transmission line from the memory interface to the memory direction can be improved without deteriorating the memory throughput performance.
If the impedance adjustment is stopped as in the second embodiment, there is a possibility that deviation from the optimum state may occur even if no error has occurred.
In this regard, in the third embodiment, at the time of refreshing the memory 2, adjustment is performed to optimize only the impedance value of the IF output buffer of the memory interface. Thereby, the quality of the transmission line can be improved without affecting the memory throughput.

Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.
The configuration of the impedance adjustment synchronization unit is not limited to the above embodiment, and various modifications can be made. For example, the adjustment code holding unit may be a sample and hold circuit in addition to the flip-flop.
Further, the impedance adjustment synchronization unit may be replaced with a computer constituted by a CPU, a ROM, and a RAM, and may be operated as each functional unit described in the above embodiment by an impedance adjustment program.
As the memory, the DDR3-SDRAM has been described as an example. However, the present invention is not limited to this, and various kinds of semiconductor storage devices may be used.

1 ... diagnostic device, 2 ... memory, 3 ... impedance adjustment device, 31 ... diagnostic interface, 32 ... IF impedance adjustment unit, 33 ... memory impedance adjustment unit, 34 ... memory control unit, 35 ... memory interface, 36 ... hold adjustment code 37: Impedance adjustment synchronization unit, 38 ... ECC circuit, 39 ... Refresh control unit, 351 ... IF output buffer, 371 ... Adjustment code holding unit, 372 ... OR circuit, 373 ... Selector unit, 374 ... Flip-flop circuit, 375 ... selector part.

Claims (10)

An impedance adjustment device for adjusting impedance so as to match the impedance of an output buffer of a memory and the impedance of an output buffer of a memory interface,
A memory impedance adjustment unit that issues a ZQ adjustment command for instructing impedance adjustment of the output buffer of the memory;
An IF impedance adjustment unit that generates and outputs an IF impedance adjustment code for adjusting the impedance of the output buffer of the memory interface; and
An impedance adjustment device comprising: an impedance adjustment synchronization unit that provides the IF impedance adjustment code to the memory interface in synchronization with the ZQ adjustment command issued from the memory impedance adjustment unit. In the impedance adjusting device according to claim 1,
The memory impedance adjustment unit issues a ZQ adjustment command completion signal to the impedance adjustment synchronization unit after issuing the ZQ adjustment command to the memory,
The impedance adjustment synchronization unit includes an adjustment code holding unit that takes in the IF impedance adjustment code at a timing when the ZQ adjustment command completion signal is issued and outputs the taken IF impedance adjustment code to the memory interface. Impedance adjustment device. In the impedance adjusting device according to claim 2,
The impedance adjustment synchronization unit includes:
An impedance adjustment apparatus that provides an IF impedance adjustment activation signal that instructs generation of an IF impedance adjustment code to the IF impedance adjustment unit at a timing when the ZQ adjustment command completion signal is issued. In the impedance adjusting device according to any one of claims 1 to 3,
The impedance adjustment apparatus, wherein the memory impedance adjustment unit stops issuing the ZQ adjustment command when a period in which no error is detected in the read data from the memory continues for a predetermined time. In the impedance adjusting device according to claim 4,
When the memory impedance adjustment unit stops issuing the ZQ adjustment command,
When the refresh control unit that causes the memory to perform refresh issues a refresh command after issuing a refresh command,
The impedance adjustment synchronization unit provides the IF impedance adjustment code to the memory interface at a timing when the refresh issue completion signal is issued. An impedance adjustment method for adjusting impedance so as to match the impedance of an output buffer of a memory and the impedance of an output buffer of a memory interface,
Issue a ZQ adjustment command to instruct the impedance adjustment of the memory output buffer,
Generate an IF impedance adjustment code to adjust the impedance of the memory interface output buffer,
The impedance adjustment method, wherein the IF impedance adjustment code is given to the memory interface in synchronization with the ZQ adjustment command being issued. In the impedance adjustment method according to claim 6,
After issuing the ZQ adjustment command, issue a ZQ adjustment command completion signal,
The impedance adjustment method, wherein the generated IF impedance adjustment code is fetched at the timing when the ZQ adjustment command completion signal is issued and is output to the memory interface. In the impedance adjustment method according to claim 7,
An impedance adjustment method, wherein generation of a new IF impedance adjustment code is started at a timing when the ZQ adjustment command completion signal is issued. In the impedance adjustment method according to any one of claims 6 to 8,
The impedance adjustment device, wherein the issuance of the ZQ adjustment command is stopped when a period in which no error is detected in the read data from the memory continues for a predetermined time. In the impedance adjusting device according to claim 9,
If issuance of the ZQ adjustment command is stopped,
Impedance adjustment of the output buffer of the memory interface is executed in synchronization with the refresh of the memory.

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