JP5061429B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a silicide layer on the surface of a semiconductor substrate.

  At present, a silicide layer is formed on the surface layer of a gate electrode or a source / drain region from the viewpoint of reducing the resistance of the source / drain region or the gate electrode of the semiconductor device. A technique for simultaneously forming a silicide layer on the surface layer of the gate electrode and the source / drain region is called a salicide process.

  On the other hand, from the viewpoint of improving the characteristics of the semiconductor device, a silicide layer may not be formed on the surface layer of the source / drain region of a specific transistor constituting the semiconductor device. In addition, in a storage device such as a DRAM or a CMOS image sensor, a silicide layer may not be formed on the surface layer of the source / drain region of a transistor connected to a capacitor or the source / drain region also serving as a photodiode (for example, Patent Document 1).

  A silicide block layer is formed in a specific region (silicide block region) where the silicide layer is not formed. The silicide block layer is formed on the sidewall insulating film after the sidewall insulating film is formed on the entire surface of the semiconductor substrate. As the silicide block layer, for example, a silicon oxide film called NSG (nondoped silicate glass) is used. The silicide block layer is formed by processing NSG by wet etching using a resist mask.

  Conventionally, as a sidewall insulating film, a silicon nitride film is formed by a CVD method using dichlorosilane (DCS) and ammonia as source gases at a film forming temperature of 700 ° C. or more. In the present specification, a silicon nitride film formed using dichlorosilane is referred to as a DCS-SiN film.

  On the other hand, with the miniaturization of devices, it is required to lower the process temperature. Usually, since the sidewall insulating film is formed after the shallow extension region is formed, it is necessary to form the sidewall insulating film at as low a temperature as possible in order to suppress impurity diffusion and inactivation in the extension region. It is.

When forming a silicon nitride film by a CVD method at a film forming temperature of 700 ° C. or lower, hexachlorodisilane (HCD) and ammonia are used as source gases. In this specification, a silicon nitride film formed using hexachlorodisilane is referred to as an HCD-SiN film.
JP 2001-345439 A

  However, the HCD-SiN film formed at a low temperature has a problem of low wet etching resistance. The etching rate of the HCD-SiN film is 7 times or more faster than that of the DCS-SiN film, and the etching selectivity with respect to the NSG film serving as the silicide block layer is 7 or less. As a result, when the NSG film is processed by wet etching, the HCD-SiN film that is the sidewall insulating film is also etched away or becomes very thin.

  If the HCD-SiN film on the gate electrode disappears or becomes thin, the gate electrode under the HCD-SiN film is etched when the sidewall insulating film including the HCD-SiN film is etched back. is there. On the other hand, since the film thickness of the HCD-SiN film is set by the width of the sidewall, it is difficult to increase the thickness of the HCD-SiN film. In particular, since the sidewall width tends to be reduced with the miniaturization of the device in the future, the sidewall insulating film tends to be thinned.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to suppress a reduction in the film thickness of the sidewall insulating film during the formation of the silicide block layer. An object of the present invention is to provide a method of manufacturing a semiconductor device that can suppress the occurrence of variation in width.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a substrate, and an insulating film for sidewalls is formed on the substrate so as to cover the gate electrode. A step of forming an etching stopper film on the sidewall insulating film, a step of forming an insulating layer for silicide block on the etching stopper film, and processing the insulating layer by wet etching to form a silicide Forming a silicide block layer only in a region to prevent the formation, removing the etching stopper film exposed from the silicide block layer, etching back the sidewall insulating film, and forming both sides of the gate electrode Forming a sidewall on the substrate; and a surface of the substrate exposed from the sidewall. And a step of forming a de layer.

In the manufacturing method of the semiconductor device of the present invention, the insulating layer is formed after the etching stopper film is formed on the sidewall insulating film. For this reason, in the process of forming the silicide block layer by processing the insulating layer, the sidewall insulating film is protected by the etching stopper film, so that the thickness of the sidewall insulating film does not decrease.
Since the sidewall insulating film having a uniform thickness remains on the semiconductor substrate and the gate electrode, the etching of the gate electrode is prevented in the step of etching back the sidewall insulating film. Further, by etching back the sidewall insulating film having a uniform thickness, a sidewall having a uniform width is formed on the sidewall of the gate electrode.
After forming the sidewall, a silicide layer is formed on the surface of the substrate exposed from the sidewall. In the region where the silicide block layer is formed, no silicide layer is formed because the substrate is not exposed.

  According to the present invention, it is possible to suppress a decrease in the thickness of the sidewall insulating film during the processing of the silicide block layer, and it is possible to suppress the gate electrode etching and the occurrence of variations in the sidewall width. For this reason, a material having a small etching selection ratio with the insulating layer serving as the silicide block layer can be used as the sidewall insulating film.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment. In the present embodiment, an example of a DRAM will be described as an example.

  An element isolation insulating film 2 for partitioning an active region is formed on a semiconductor substrate 1 made of silicon or the like. A transistor Tr is formed in the active region of the semiconductor substrate 1, and a trench type capacitor C is formed inside the semiconductor substrate 1.

  The transistor Tr includes a gate electrode 4 formed on the semiconductor substrate 1 via the gate insulating film 3, and an extension region 5 and source / drain regions 6 formed on the semiconductor substrate 1 on both sides of the gate electrode 4. The

  The capacitor C is formed around one capacitor electrode 9 embedded in the semiconductor substrate 1, a capacitor insulating film 8 formed so as to surround the capacitor electrode 9, and a capacitor insulating film 8 (not shown). And the other capacitor electrode. The other capacitor electrode is formed by an impurity diffusion layer. The capacitor electrode 9 is electrically connected to the source / drain region 6 of the adjacent transistor Tr.

  A sidewall SW is formed on the side wall of the gate electrode 4. In the present embodiment, the sidewall SW is formed by two layers of the first insulating film 11 and the second insulating film 12. The first insulating film 11 is, for example, a TEOS film, and the second insulating film 12 is an HCD-SiN film. The TEOS film is a silicon oxide film formed using TEOS (tetraethylorthosilicate) as a raw material.

  The extension region 5 is formed in the semiconductor substrate 1 immediately below the sidewall SW, and the source / drain region 6 is formed in the semiconductor substrate 1 outside the extension region 5. In the case of an nMOS transistor, the extension region 5 and the source / drain region 6 are n-type, and in the case of a pMOS transistor, the extension region 5 and the source / drain region 6 are p-type.

  A silicide layer 7 is formed on the surface layer portion of the source / drain region 6 and the gate electrode 4 of the transistor to reduce the resistance. The silicide layer 7 is made of nickel silicide, cobalt silicide, titanium silicide, or the like.

  A silicide block layer 30 is formed on the source / drain region 6 of the transistor Tr connected to the capacitor electrode 9, and the silicide layer 7 is not formed. This is to prevent deterioration of the capacitor characteristics due to the formation of the silicide layer 7 in the source / drain region 6 connected to the capacitor electrode 9.

  As described above, the silicide block layer 30 is formed in the source / drain region 6 connected to the capacitor electrode 9 in the DRAM. There is no limitation on the region where the silicide block layer 30 is formed. Similarly, the silicide block layer 30 may be formed even in a semiconductor device other than a DRAM.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 2A, a trench type capacitor C is formed on a semiconductor substrate 1, an element isolation insulating film 2 that partitions an active region is formed, and a gate insulating film 3 is formed on the semiconductor substrate 1 in the active region. A gate electrode 4 is formed therethrough. In the capacitor C, after forming a trench in the semiconductor substrate 1, an impurity is diffused in the inner wall of the trench to form a diffusion layer (capacitor electrode) (not shown), and a capacitor insulating film 8 covering the inner wall of the trench is formed. It is formed by forming a capacitor electrode 9 that fills the trench. After the capacitor C is formed, an element isolation insulating film 2 made of, for example, STI (Shallow Trench Isolation) is formed. After the element isolation insulating film 2 is formed, a gate insulating film 3 made of, for example, silicon oxide is formed on the semiconductor substrate 1 by a thermal oxidation method, polysilicon is deposited on the gate insulating film 3, and the resist mask is used to polycrystallize. The gate electrode 4 is formed by processing silicon. The height of the gate electrode 4 is, for example, 100 nm.

  Next, as shown in FIG. 2B, extension regions 5 are formed in the semiconductor substrate 1 on both sides of the gate electrode 4 by ion implantation using the gate electrode 4 as a mask. In the case of an nMOS transistor, an n-type extension region 5 is formed by ion implantation of an n-type impurity such as arsenic or phosphorus. In the case of a pMOS transistor, p-type extension regions 5 are formed by ion implantation of p-type impurities such as boron.

  Next, as shown in FIG. 3A, a sidewall insulating film 10 is formed on the semiconductor substrate 1 so as to cover the gate electrode 4. In this embodiment, two layers of the first insulating film 11 and the second insulating film 12 are formed as the sidewall insulating film 10 by the CVD method. As the first insulating film 11, a TEOS film having a thickness of 12 nm is formed at a film forming temperature of 570 ° C. As the second insulating film 12, an HCD-SiN film having a thickness of 15 nm is formed at a film forming temperature of 550 ° C. In this example, in order to form a sidewall SW having a width of 25 nm, the film thicknesses of the first insulating film 11 and the second insulating film 12 are set as described above.

  Next, as shown in FIG. 3B, a first dummy insulating film 21 is formed on the second insulating film 12. The first dummy insulating film 21 is the same TEOS film as the first insulating film 11. The first dummy insulating film 21 serves as an etching stopper when the second dummy insulating film 22 to be subsequently formed is removed with hot phosphoric acid. The first dummy insulating film 21 only needs to have a minimum film thickness that acts as an etching stopper. For example, a TEOS film having a thickness of 5 nm is formed as the first dummy insulating film 21 at a film formation temperature of 570 ° C.

  Next, as shown in FIG. 4A, a second dummy insulating film 22 is formed on the first dummy insulating film 21. The second dummy insulating film 22 is the same HCD-SiN film as the second insulating film 12. The second dummy insulating film 22 only needs to have a film thickness that does not etch all NSG deposited later when wet etching is performed. For example, as the second dummy insulating film 22, an HCD-SiN film having a film thickness of 25 nm is formed at a film forming temperature of 550 ° C.

  Thereby, an etching stopper film 20 having a two-layer structure of the first dummy insulating film 21 and the second dummy insulating film 22 having the same film configuration as the sidewall insulating film 10 is formed. Since the thickness of the first dummy insulating film 21 and the second dummy insulating film 22 can be set regardless of the width of the sidewall SW finally formed, the first dummy insulating film 21 and the second dummy insulating film 22 may be thicker than the above-described film thickness.

  Next, as shown in FIG. 4B, an insulating layer 30a is formed on the etching stopper film 20 so as to bury the gate electrode 4 having a height of about 100 nm. As the insulating layer 30a, for example, NSG having a thickness of 400 nm is formed. NSG is a silicon oxide film containing no impurities.

  Next, as shown in FIG. 5A, the insulating layer 30a is planarized by, eg, CMP (Chemical Mechanical Polishing), and then the insulating layer 30a is etched back. Etch back is performed until the second dummy insulating film 22 on the gate electrode 4 is exposed.

  Next, as shown in FIG. 5B, a resist mask 40 that protects the insulating layer 30a in a specific region (silicide block region) where the silicide layer is not formed is formed.

  Next, as shown in FIG. 6A, the insulating layer 30a is wet-etched using buffered hydrofluoric acid. As a result, all of the insulating layer 30a other than the region protected by the resist mask 40 is removed, and the silicide block layer 30 made of the insulating layer 30a is formed in the region protected by the resist mask 40. At this time, the second dummy insulating film 22 on the gate electrode 4 is etched and thinned with buffered hydrofluoric acid. However, since the initial film thickness is formed as thick as 25 nm, all of the second dummy insulating film 22 is formed. It will not be etched.

Next, as shown in FIG. 6B, after removing the resist mask 40, the second dummy insulating film 22 is removed by wet etching using hot phosphoric acid (H ₃ PO ₄ ). The etching amount is 25 nm. Although the second dummy insulating film 22 on the gate electrode 4 is thin, the first dummy insulating film 21 below the second dummy insulating film 22 acts as an etching stopper, so that the sidewall insulating film 10 is etched. Never happen. In the silicide block region, the second dummy insulating film 22 remains without being etched.

  Next, as shown in FIG. 7A, the first dummy insulating film 21 is removed by wet etching. The etching amount at this time is set to the film thickness of the first dummy insulating film 21. In this example, it is 5 nm. Thereby, the first dummy insulating film 21 on the gate electrode 4 and the side wall of the gate electrode 4 is removed. In the etching of the first dummy insulating film 21, the second insulating film 12 under the first dummy insulating film 21 is not excessively etched. In the silicide block region, the first dummy insulating film 21 remains without being etched.

  Next, as shown in FIG. 7B, the second insulating film 12 is etched back by dry etching. As a result, the second insulating film 12 remains only on the side wall of the gate electrode 4. In this dry etching, the first insulating film 11 functions as an etching stopper. In the silicide block region, the second insulating film 12 remains without being etched.

  Next, as shown in FIG. 8A, the first insulating film 11 is etched back by dry etching. As a result, the first insulating film 11 remains only on the side wall of the gate electrode 4, and the semiconductor substrate 1 is exposed outside the silicide block region. A sidewall SW composed of the first insulating film 11 and the second insulating film 12 is formed on the side wall of the gate electrode 4. The width of the sidewall SW is about 25 nm. In the silicide block region, the first insulating film 11 remains without being etched.

  Next, as shown in FIG. 8B, source / drain regions 6 deeper than the extension region 5 are formed in the semiconductor substrate 1 outside the sidewall SW by ion implantation using the gate electrode 4 and the sidewall SW as a mask. Form. In the case of an nMOS transistor, n-type impurities such as arsenic and phosphorus are ion-implanted to form n-type source / drain regions 6. In the case of a pMOS transistor, a p-type source / drain region 6 is formed by ion implantation of a p-type impurity such as boron.

  Next, a metal film is deposited by covering the entire surface of the semiconductor substrate 1 so as to cover the gate electrode 4, heat treatment is performed to react the metal film with silicon, and then the unnecessary metal film is removed. As the metal film, nickel, cobalt or titanium is used. As a result, a silicide layer 7 is formed in a region of the semiconductor substrate 1 in contact with the metal film, that is, the surface of the source / drain region 6 (see FIG. 1). At the same time, a silicide layer 7 is also formed on the surface of the gate electrode 4. As the silicide layer 7, nickel silicide, cobalt silicide, or titanium silicide is formed.

  As described above, the semiconductor device shown in FIG. 1 is manufactured. As subsequent steps, an interlayer insulating film forming step for covering the transistor Tr and a wiring forming step are performed. The silicide block layer 30 may finally be left or removed.

  In the method of manufacturing the semiconductor device according to the present embodiment, the insulating layer 30a is formed after the etching stopper film 20 is formed on the sidewall insulating film 10. Therefore, in the wet etching when the insulating layer 30a is processed to form the silicide block layer 30, the sidewall insulating film 10 is protected by the etching stopper film 20, so the film of the sidewall insulating film 10 The thickness does not decrease.

  Since the sidewall insulating film 10 having a uniform film thickness remains on the semiconductor substrate 1 and the gate electrode 4, the sidewall insulating film 10 is etched back (FIGS. 7B and 8A). Reference), the gate electrode 4 can be prevented from being etched.

  Further, by etching back the sidewall insulating film 10 having a uniform thickness, the sidewall SW having a uniform width can be formed on the sidewall of the gate electrode 4. For this reason, it is possible to prevent misalignment of the source / drain regions 6 formed by ion implantation using the sidewall SW as a mask, and a transistor having stable characteristics can be obtained.

  When the sidewall insulating film 10 having the two-layer structure of the first insulating film 11 and the second insulating film 12 is used, the two-layer etching of the first dummy insulating film 21 and the second dummy insulating film 22 having the same film type is used. By forming the stopper film 20, the etching of the sidewall insulating film 10 during the formation of the silicide block layer 30 can be easily prevented.

  For this reason, it is possible to use an HCD-SiN film that can be formed at a low temperature as the second insulating film 12, so that the impurity diffusion in the extension region 5 that has already been formed can be prevented and is very shallow. The extension region 5 can be maintained.

The present invention is not limited to the description of the above embodiment.
For example, the material and manufacturing method of the sidewall insulating film 10, the etching stopper film 20, and the insulating layer 30a are not limited. As the second insulating film 12, a silicon nitride film (SiN film) may be formed by an ALD (Atomic Layer Deposition) method in addition to forming an HCD-SiN film by a CVD method. Even in the ALD method, since the silicon nitride film formed at a low temperature has low wet etching resistance like the HCD-SiN film, it is effective to apply the present invention also in this case. Further, as the second insulating film 12, an insulating film other than the HCD-SiN film can be adopted.

  For example, in the present embodiment, an example in which the sidewall insulating film 10 having a two-layer structure is used has been described. However, a single-layer sidewall insulating film 10 may be used. Also, the etching stopper film 20 may be one layer instead of two layers. For example, when a silicon nitride film is used as the insulating layer 30a, the etching stopper film 20 can be formed of one layer of a TEOS film.

  Further, the example of forming the source / drain region 6 after processing the first insulating film 11 and the second insulating film 12 has been described (see FIG. 8B), but after processing the second insulating film 12, It is also possible to form the source / drain region 6 by ion implantation before processing the first insulating film 11. Alternatively, the source / drain regions 6 may be formed by ion implantation before the first insulating film 11 is processed, that is, after the sidewall insulating film 10 shown in FIG. 3A is formed.

Furthermore, in the present embodiment, the DRAM is described as an example of the semiconductor device, but the present invention can also be applied to the manufacture of CMOS image sensors other than DRAM and other semiconductor devices.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Extension region, 6 ... Source-drain region, 7 ... Silicide layer, 8 ... Capacitor insulating film, 9 ... Capacitor electrode DESCRIPTION OF SYMBOLS 10 ... Side wall insulating film, 11 ... 1st insulating film, 12 ... 2nd insulating film, 20 ... Etching stopper film, 21 ... 1st dummy insulating film, 22 ... 2nd dummy insulating film, 30 ... Silicide block layer , 30a ... insulating layer, 40 ... resist mask, SW ... sidewall, Tr ... transistor, C ... capacitor

Claims (4)

Forming a gate electrode on the substrate;
Forming a sidewall insulating film on the substrate so as to cover the gate electrode;
Forming an etching stopper film on the sidewall insulating film;
Forming a silicide block insulating layer having a film thickness for embedding the gate electrode on the etching stopper film;
Thinning the silicide block insulating layer until the etching stopper film on the gate electrode is exposed;
Forming a resist mask on the silicide block insulating layer in a region for preventing silicidation;
Removing the insulating layer for the silicide block other than the region protected by the resist mask by wet etching, and forming a silicide block layer in the region for preventing silicidation;
Removing the etching stopper film exposed from the silicide block layer;
Etching back the sidewall insulating film to form sidewalls on both sides of the gate electrode;
Forming a silicide layer on the surface of the substrate exposed from the side wall. In the step of forming the sidewall insulating film, a stacked film of a first insulating film and a second insulating film having different film types is formed,
The stacked film of a first dummy insulating film made of the same material as the first insulating film and a second dummy insulating film made of the same material as the second insulating film is formed in the step of forming the etching stopper film. Semiconductor device manufacturing method. A step of forming extension regions on the substrate on both sides of the gate electrode by ion implantation using the gate electrode as a mask after the step of forming the gate electrode and before the step of forming the sidewall insulating film. The method for manufacturing a semiconductor device according to claim 1, further comprising: After the step of forming the sidewalls and before the step of forming the silicide layers, by ion implantation using the gate electrode and the sidewalls as a mask, the substrate on both sides of the sidewalls is extended from the extension region. The method of manufacturing a semiconductor device according to claim 3 , further comprising forming a deep source / drain region.

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