JP5034231B2 - Carbon nanotube transistor array and manufacturing method thereof - Google Patents

Description

  The present invention relates to a carbon nanotube transistor array and a method for manufacturing the same, and in particular, is characterized by a structure for easily producing an array of a plurality of carbon nanotube transistors having uniform characteristics or controlled withstand voltage characteristics. The present invention relates to a carbon nanotube transistor array and a manufacturing method thereof.

  In recent years, electronic devices using carbon nanotubes (CNT) have attracted attention. This carbon nanotube is a one-dimensional structure that is a graphene sheet rolled into a cylindrical shape. It is known to show metallic or semiconducting behavior.

  Among these, if carbon nanotubes that exhibit semiconducting behavior are used for the channel, they will operate as transistors, and this carbon nanotube transistor (CNT-Tr) has a high-speed operation and a high breakdown voltage based on theory and some experiments. It is being shown to have features.

  The manufacturing method is roughly classified into two types, that is, a dispersion type (for example, see Patent Document 1) and a position control growth type (for example, see Patent Document 2). The distributed type and the position controlled growth type will be described with reference to FIGS.

See FIG.
FIG. 10 is an explanatory diagram of a dispersion-type CNT-Tr. First, CNTs are grown, the CNTs are collected, and the collected CNTs are dissolved in a solution to create a CNT dispersion.
Next, a CNT dispersion is applied on the insulating substrate 51 to spread the CNTs 52 on the substrate.

  Next, after forming the source / drain electrodes 53 using the lift-off method, an insulating film (not shown) is formed, and then a gate electrode (not shown) is formed on the insulating film, thereby forming the CNT-Tr. It is formed.

See FIG.
FIG. 11 is an explanatory view of a position-controlled growth type CNT-Tr. First, a CNT growth catalyst metal 62 is patterned on an insulating substrate 61 such as a sapphire substrate, and the CNT 63 is laterally arranged between the CNT growth catalyst metals 62. Grow.

Next, a source / drain electrode 64 is formed so as to cover the CNT growth catalyst metal 62 using a lift-off method, and then a CNT-Tr is formed by forming a gate electrode (not shown) on the insulating film. The
JP 2005-101424 A JP 2002-118248 A

  However, in the case of the distributed type, it operates as a CNT-Tr only when a “sincere” semiconducting CNT is “cross-linked” between the source and drain electrodes. It happens to operate as CNT-Tr only when semiconducting CNT grows.

  There is a yield in cross-linking of CNTs between such source / drain electrodes, and whether cross-linked CNTs become metallic or semi-conductive depends on the CNT diameter and chirality even if they are cross-linked. To do.

  Furthermore, even if semiconducting CNTs are cross-linked, the band gap of semiconducting CNTs depends on the CNT diameter and chirality, but it is extremely difficult to control the CNT diameter and chirality with the current technology. There is a problem that the characteristics of the CNT-Tr cannot be controlled.

  In other words, the CNT-Tr formed by the above-mentioned dispersion type or position control type can be produced from the problems of cross-linking yield, CNT diameter and chirality control, but hardly forms an array structure. Further, there is a problem that the characteristics of the produced CNT-Tr are different and it is extremely difficult to align the characteristics of each CNT-Tr constituting the array.

  Therefore, an object of the present invention is to easily produce an array of a plurality of carbon nanotube transistors with uniform characteristics or controlled withstand voltage characteristics.

FIG. 1 is a diagram illustrating the basic configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
See FIG. 1 In order to solve the above-mentioned problem, the present invention is a carbon nanotube transistor array in which a plurality of common long-growth semiconducting carbon nanotubes 2 having a length of 100 μm or more which are grown under position control are divided. And a transistor 5 formed by providing a three-terminal electrode 4 for each carbon nanotube element 3, and the plurality of carbon nanotube elements 3 are separated .

Thus, by forming a plurality of transistors 5 from a single long-growth semiconducting carbon nanotube 2 having a length of 100 μm or more grown under position control and separated from other carbon nanotubes , A carbon nanotube transistor array with uniform characteristics can be constructed without being affected by the cross-linking yield or chirality of carbon nanotubes.

In this case, the length of the long-growth semiconducting carbon nanotubes 2 is 100 μm or more , and it has been reported that carbon nanotubes having a length of several hundred μm to several mm have actually grown.

In this case, since the long-growth semiconductor carbon nanotubes 2 are grown under position control , the transistor 5 can be formed in a predetermined position.

  Further, the source-drain interval of at least one transistor 5 among the transistors 5 formed in each individual carbon nanotube element 3 is configured to be different from the source-drain interval of at least one transistor 5 among the other transistors 5. As a result, the withstand voltage characteristic of each transistor 5 can be arbitrarily controlled.

  In this case, among the transistors 5 having different source-drain intervals, a plurality of transistors 5 having a relatively large source-drain interval are separated from the plurality of transistors 5 having a relatively small source-drain interval. The grown semiconductor carbon nanotubes 2 may be formed, whereby the characteristics of the high breakdown voltage transistor 5 can be made uniform.

  By providing a plurality of common long-growth semiconducting carbon nanotubes 2 on the substrate 1 and making each transistor 5 a two-dimensional matrix array, it is easy to produce a logic circuit with low assembly cost. Become.

In addition, as a manufacturing method, a growth base 6 having a catalytic action is formed on a substrate 1, and a long-growth semiconductor carbon nanotube 2 having a length of 100 μm or more whose position is controlled from the growth base 6 as a growth starting point is obtained. A transistor 5 is formed by forming a three-terminal electrode 4 on each of a plurality of carbon nanotube elements 3 obtained by growing and growing the long-growth semiconducting carbon nanotubes 2, and the plurality of carbon nanotube elements 3 are separated. It ’s fine.

  In this case, a plurality of three-terminal electrodes 4 may be formed on the long-growth semiconducting carbon nanotube 2, and then the long-growth semiconducting carbon nanotube 2 may be cut and separated into individual transistors 5. Alternatively, after separating the long-growth semiconductor carbon nanotubes 2 into a plurality of carbon nanotube elements 3, the three-terminal electrodes 4 may be formed on the individual carbon nanotube elements 3.

  According to the present invention, an array of carbon nanotube transistors, which has conventionally been difficult to manufacture in terms of cross-linking yield, carbon nanotube diameter and chirality control, can be easily manufactured by an easy method. By using a carbon nanotube transistor that is excellent in performance and high pressure resistance, it becomes possible to produce a logic circuit at a low assembly cost.

  In the present invention, a growth base 6 having a catalytic action such as Fe is formed on a substrate, and the position of the growth base 6 is controlled with the growth base 6 as a growth starting point. Carbon nanotubes are grown, and a plurality of source / drain electrodes are formed on the grown long-growth semiconducting carbon nanotubes, and then a gate insulating film is formed, and then a gate electrode is provided between the source and drain. Next, each transistor is separated by cutting each transistor by ion milling or the like.

  In this case, the transistor is formed and then separated, or the long-grown semiconducting carbon nanotube is separated into a plurality of carbon nanotube elements in advance and then the source / drain electrode, the gate insulating film and the gate electrode are formed to form the transistor. To do.

  In addition, interconnect lines are formed to realize a predetermined circuit configuration after the formation and isolation of the transistors, or basic interconnect lines are simultaneously formed in advance when forming the source / drain electrodes and the gate electrode. is there.

Here, with reference to FIG. 2 and FIG. 3, the manufacturing process of the carbon nanotube transistor array of Example 1 of the present invention will be described. Here, in order to simplify the description, only two long carbon nanotubes are described. Is illustrated.
See Figure 2
First, Fe bases 12 and 13 serving as catalysts are formed on a ceramic substrate 11, and then CVD is used, acetylene gas is used as a process gas, and Ar gas or hydrogen gas is used as a carrier gas. In a state where a DC electric field is applied in the direction, the long carbon nanotubes 14 and 15 having semiconducting properties are formed with the Fe bases 12 and 13 as growth starting points at a growth temperature of 600 ° C., for example, at a pressure of 100 Pa.
In this case, the length of the long carbon nanotubes 14 and 15 may be appropriately determined according to the required circuit configuration, and is typically 100 μm or more, and may be 100 μm to several mm in length. .

  Next, Pd (palladium) is deposited by sputtering using a resist pattern (not shown) as a mask, and then the resist pattern is removed to form source electrodes 16 and 17 and drain electrodes 18 and 19.

See Figure 3
Next, an SiO ₂ film is deposited by spin coating and annealing so that the thickness deposited on the surfaces of the long carbon nanotubes 14 and 15 becomes 10 nm, for example, to form the gate insulating film 20.

  Next, again, a sputtering method using a resist pattern (not shown) as a mask, a Ti film having a thickness of, for example, 10 nm, a Pt layer having a thickness of, for example, 100 nm, and a thickness of, for example, 10 nm. Gate electrodes 21 and 22 are formed by sequentially depositing a Ti film and then removing the resist pattern.

  Next, by using an ion milling method, unnecessary portions of the long carbon nanotubes 14 and 15 are removed and separated into the respective CNT transistors 23 and 24, thereby forming a transistor array.

  As described above, in the first embodiment of the present invention, the plurality of CNT transistors 23 and 24 are constituted by one long carbon nanotube 14 and 15, so that they are not affected by the bridging yield.

  In addition, since the CNT transistors 23 (23) formed of the same long carbon nanotubes 14 (15) have the same characteristics, it is possible to configure a stable circuit without variations in characteristics.

Next, the carbon nanotube transistor array according to the second embodiment of the present invention will be described with reference to FIG.
See Figure 4
FIG. 4 is a conceptual plan view of the carbon nanotube transistor array according to the second embodiment of the present invention. In order to construct the CNT transistor 25 having a high breakdown voltage, the source electrode 26 and the drain electrode are compared with the normal CNT transistor 23. 27 is widened.

  In this way, a carbon nanotube transistor having an arbitrary breakdown voltage can be configured by adjusting the distance between the source and drain electrodes. When these CNT transistors are used, a low noise amplifier (LNA) or a phase shifter is configured. The characteristics of individual LNAs and phase shifters can be made uniform.

Next, a CNT phased array antenna chip according to Example 3 of the present invention will be described with reference to FIGS.
See Figure 5
First, after a plurality of CNT transistors 23 and 24 are formed from each long carbon nanotube in the same manner as in the first embodiment, a via hole is formed at a predetermined location, and then the via 29 is formed by filling the via hole with Cu. .

  Next, after depositing a conductor on the entire surface, the wiring 30 is formed by etching into a wiring shape necessary for the circuit configuration.

See FIG.
Next, the LNA 31 and the phase shifter 32 are configured by forming other elements (not shown) such as a condenser necessary for the LNA and the phase shifter.

  Next, after depositing Cu on the back surface of the ceramic substrate 11 using a lift-off method, a patch antenna 33 is formed at a position connected to the via 29 by forming a resist pattern (not shown), whereby a CNT phased array antenna is formed. The basic structure of the chip is completed.

See FIG.
FIG. 7 is a conceptual perspective view of the completed CNT phased array antenna chip as described above.

See FIG.
FIG. 8 is a circuit diagram showing an example of the circuit configuration of the LNA 31 and the phase shifter 32 formed as described above.

  Phased array antennas are likely to be used in in-vehicle radars in the future, and as a structure, patch antennas + low noise amplifiers (LNA) + phase shifters are generally arranged in an array on a ceramic substrate. When the conventional technique is used, low noise amplifiers and phase shifters as components must be mounted one by one on the ceramic substrate on which the patch antenna is formed, which incurs component costs and assembly costs.

  Therefore, as shown in Example 3, by using long carbon nanotubes, a CNT transistor as a low-noise amplifier having many characteristics and a CNT passive element as a phase shifter are aligned and formed on a ceramic substrate at one time. As a result, there is no assembly cost, and the component cost can be reduced, so that the overall cost can be reduced.

Next, a one-chip RF front-end circuit according to the fourth embodiment of the present invention will be described with reference to FIG.
See FIG.
FIG. 9 is a system configuration diagram of an RF system using the one-chip RF front-end circuit according to the fourth embodiment of the present invention, and a portion surrounded by a one-dot chain line in the drawing is an RF front-end circuit.

In the fourth embodiment, the LNA in the RF front-end circuit is configured by the CNT transistor 23 having the normal breakdown voltage shown in FIG. 4, and the power amplifier (PA) is configured by the high breakdown voltage CNT transistor 25 shown in FIG. It is a thing.
The basic circuit configuration of PA is the same as that of LNA.

The RF system is used for a mobile phone or a wireless LAN. Currently, there is a movement to configure the RF front-end part with a one-chip CMOS-MMIC.
However, in order to construct an RF front-end circuit that requires high-speed operation with CMOS, the breakdown voltage must be sacrificed, and as a result, it is very difficult to build a power amplifier.

  Therefore, as shown in the fourth embodiment, by using a CNT transistor instead of the CMOS, it becomes possible to operate at a higher speed than the CMOS, and it is possible to manufacture a power amplifier because the withstand voltage is high.

  Furthermore, since long carbon nanotubes are used, it becomes possible to simultaneously produce transistors having a withstand voltage required for each unit such as a low noise amplifier and a power amplifier. As a result, a one-chip RF front-end MMIC is obtained. Can be realized.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications can be made. For example, it is necessary for the growth of carbon nanotubes. The source gas is not limited to acetylene gas, and hydrocarbon gas such as methane or ethylene or alcohol gas such as methanol may be used, and the growth method is not limited to the CVD method, but arc discharge. Alternatively, other growth methods such as a laser ablation method may be used.

  In the above embodiment, Fe is used as a catalyst. However, the catalyst is not limited to Fe, and Co, Ni, or an alloy containing Fe may be used.

In each of the above embodiments, a ceramic substrate is used as an insulating substrate in order to configure a CNT phased array antenna. However, in the case of configuring a general electronic circuit, the ceramic substrate is not limited to the ceramic substrate. Any insulating substrate that can withstand the growth temperature of carbon nanotubes may be used. For example, heat-resistant glass such as Pyreck (registered trademark) or sapphire may be used, and SiO ₂ may be formed on the surface of a silicon substrate or the like. A substrate provided with an insulating film such as a film may be used.

  In Example 2 described above, the normal withstand voltage CNT transistor and the high withstand voltage CNT transistor are each composed of separate long carbon nanotubes. A CNT transistor and a high withstand voltage CNT transistor may be configured. Furthermore, the withstand voltage of the CNT transistor is not limited to two types, and a CNT transistor having a necessary type of withstand voltage according to the circuit configuration What is necessary is just to form by adjusting the length between drain electrodes.

  In each of the above embodiments, the three-terminal electrode is formed on the long carbon nanotube and then separated into each CNT transistor. However, the long-growth semiconducting carbon nanotube is separated into a plurality of carbon nanotube elements in advance. Thereafter, a three-terminal electrode may be formed to form a CNT transistor.

  In each of the above embodiments, the interconnection wiring for realizing a predetermined circuit configuration is formed after the formation and separation of the CNT transistor. However, when the source / drain electrode and the gate electrode are formed, the basic wiring is formed in advance. Interconnect wiring may also be formed at the same time.

Although not particularly mentioned in each of the above-mentioned examples, in order to grow long carbon nanotubes having semiconducting properties, the size of the catalyst base such as Fe base or the like using the substrate actually used or the like It suffices if the growth conditions are optimized, and if several of the long carbon nanotubes have metallic properties, the electrical properties may be inspected and cut in advance. .
For this purpose, a larger number of long carbon nanotubes than necessary may be grown in advance.

The detailed features of the present invention will be described again with reference to FIG. 1 again.
Reference is again made to FIG. 1 (Appendix 1) A plurality of carbon nanotube elements 3 in which a single long-growth semiconducting carbon nanotube 2 having a length of 100 μm or more grown under position control is partitioned, and the carbon nanotube element 3 A carbon nanotube transistor array having a transistor 5 formed by providing a three-terminal electrode 4 for each, and the plurality of carbon nanotube elements 3 being separated .
(Appendix 2) The source-drain spacing of at least one transistor 5 among the transistors 5 formed for each carbon nanotube element 3 is different from the source-drain spacing of at least one other transistor 5. The carbon nanotube transistor array according to appendix 1.
(Supplementary Note 3 ) A plurality of the common long-growth semiconducting carbon nanotubes 2 are provided on the substrate 1, and a plurality of carbon nanotube elements 3 that divide each long-growth semiconducting carbon nanotube 2 ; Addendum 1 or Addendum 2 characterized in that each of the carbon nanotube elements 3 has a transistor 5 formed by providing a three-terminal electrode 4 and each of the transistors 5 forms a two-dimensional matrix array. Carbon nanotube transistor array.
(Supplementary Note 4 ) A transistor 5 formed on at least one long-growth semiconducting carbon nanotube 2 among the long-growth semiconducting carbon nanotubes 2 is formed on another long-growth semiconducting carbon nanotube 2. 4. The carbon nanotube transistor array according to appendix 3 , wherein the source-drain spacing is wider than the transistor 5 formed .
(Supplementary Note 5) A base 6 for growth having a catalytic action is formed on a substrate 1, and a long-growth semiconductor carbon nanotube 2 having a length of 100 μm or more, whose position is controlled from the growth base 6 as a growth starting point, is grown. separating a step, a step of forming a transistor 5 by forming respectively to the three terminal electrodes 4 of a plurality of carbon nanotubes element 3 obtained by dividing the long growing semiconducting carbon nanotubes 2, carbon nanotube element 3 of the plurality of And a method of manufacturing a carbon nanotube transistor array.
(Supplementary note 6) The method for manufacturing a carbon nanotube transistor array according to supplementary note 5 , wherein the step of separating the plurality of carbon nanotube elements 3 is after the step of forming the transistor 5 .
(Supplementary note 7) The method of manufacturing a carbon nanotube transistor array according to supplementary note 5 , wherein the step of separating the plurality of carbon nanotube elements 3 is before the step of forming the transistor 5 .

  Examples of applications of the present invention are typical carbon nanotube transistor arrays used in phased array antennas and RF systems. However, the present invention is not limited to such applications. It can also be applied to electronic circuits.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the manufacturing process to the middle of the carbon nanotube transistor array of Example 1 of this invention. It is explanatory drawing of the manufacturing process after FIG. 2 of the carbon nanotube transistor array of Example 1 of this invention. It is a notional top view of the carbon nanotube transistor array of Example 2 of the present invention. It is explanatory drawing of the manufacturing process to the middle of the CNT phased array antenna chip of Example 3 of this invention. It is explanatory drawing of the manufacturing process after FIG. 5 of the CNT phased array antenna chip of Example 3 of this invention. It is a conceptual perspective view of a CNT phased array antenna chip. It is a circuit diagram which shows an example of the circuit structure of LNA and a phase shifter. It is a system configuration | structure figure of RF system using the 1-chip RF front-end circuit of Example 4 of this invention. It is explanatory drawing of dispersion type CNT-Tr. It is explanatory drawing of position control growth type CNT-Tr.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Long growth semiconductor carbon nanotube 3 Carbon nanotube element 4 Three-terminal electrode 5 Transistor 6 Growth base 11 Ceramic substrate 12, 13 Fe base 14, 15 Long carbon nanotube 16, 17 Source electrode 18, 19 Drain electrode 20 Gate insulating films 21 and 22 Gate electrodes 23 and 24 CNT transistor 25 CNT transistor 26 Source electrode 27 Drain electrode 28 Gate electrode 29 Via 30 Wiring 31 LNA
32 Phase shifter 33 Patch antenna 51 Insulating substrate 52 CNT
53 Source / drain electrode 61 Insulating substrate 62 CNT growth catalyst metal 63 CNT
64 Source / drain electrodes

Claims (5)

A plurality of carbon nanotube elements in which a single long-growth semiconducting carbon nanotube having a length of 100 μm or more which is grown under position control is divided ;
A transistor formed by providing a three-terminal electrode for each carbon nanotube element;
The carbon nanotube transistor array is characterized in that the plurality of carbon nanotube elements are separated . 2. The carbon according to claim 1, wherein a source-drain interval of at least one transistor among the transistors formed for each carbon nanotube element is different from a source-drain interval of at least one other transistor. Nanotube transistor array. A plurality of common long-growth semiconducting carbon nanotubes are provided on a substrate, and a plurality of carbon nanotube elements dividing each long-growth semiconducting carbon nanotube ,
A transistor formed by providing a three-terminal electrode for each carbon nanotube element;
The carbon nanotube transistor array according to claim 1 or 2, wherein the individual transistors constitute a two-dimensional matrix array. The transistor formed on at least one of the long-growth semiconducting carbon nanotubes in each of the long-growth semiconducting carbon nanotubes has a source- 4. The carbon nanotube transistor array according to claim 3 , wherein the drain interval is wide . Forming a catalytic growth base on a substrate, and growing a long-growth semiconductor carbon nanotube having a length of 100 μm or more, the position of which is controlled from the growth base as a growth starting point;
Forming a transistor by forming a three-terminal electrode on each of a plurality of carbon nanotube elements into which the long-growth semiconducting carbon nanotubes are divided ; and
Separating the plurality of carbon nanotube elements; and a method of manufacturing a carbon nanotube transistor array.

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