JP5029883B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus that outputs a test signal to an object to be tested such as a memory device and performs a test by determining a signal output in accordance with the test signal. The present invention relates to a circuit configuration for determining whether or not a target can be relieved by an ECC (Error Correction Coding) function.

  Conventionally, in a semiconductor test apparatus, a test signal (test pattern) is output to an object to be tested (hereinafter referred to as a DUT) such as a NAND flash memory, which is a kind of memory device, and operation confirmation such as reading, writing, and erasing is performed. The pass or fail is determined by comparing the signal output from the DUT with the expected value. When it is determined as fail, the address of the defective cell of the DUT is recorded in the fail memory or the like as fail information.

  In the NAND flash memory, even if there is a defective cell, there is a case where the ECC function can be used for repair. This ECC function is an error correction function provided on a substrate on which a NAND flash memory is mounted. When this function is used, a cell that is determined to fail for each target range in each block of the DUT in the semiconductor test apparatus. It is determined whether or not relief is possible. If the counted number is less than or equal to a predetermined fail count limit, it can be remedied by the ECC function, and if it is greater than or equal to a predetermined fail count limit, it is determined that the remedy is not possible.

  In the memory test apparatus described in Patent Document 1 below, when the pattern generator is generating the back pattern, the fail bit counter counts the number of fail bits of the fail memory in the previous test, and counts the number of fail bits. Later, a count end signal is given to the pattern generator. After receiving the count end signal, the pattern generator generates a test pattern in the memory under test and an address to shorten the DUT test time (see, for example, Patent Document 1).

JP 2004-348892 A

  Further, in the conventional semiconductor test apparatus, it is determined whether or not the DUT can be relieved by the ECC function as follows. FIG. 5 is an explanatory diagram showing a configuration of a conventional semiconductor test apparatus 200. A DUT, which is a NAND flash memory, is composed of, for example, 8000 blocks, and each block includes 64 pages. Each page is composed of 8 bits × 2048 word cells. Note that the capacity of each block or page is an example, and changes according to the generation of the DUT.

  The semiconductor test apparatus 200 outputs a test signal to the DUT, checks a read or write operation for each address, compares the output signal output from the DUT with an expected value by the comparator 210, and passes or fails. Determine. Information on the test result determined as pass or fail is stored in the fail memory 220 having the same capacity as the DUT.

  When determining whether or not the DUT can be relieved by the ECC function, information on all the test results is stored in the fail memory 220, and then the target range for determining relieving by the ECC function by the CPU 230. For example, the number of cells determined as fail in the fail memory 220 is counted for each page, and if the counted value is less than a predetermined fail count limit, it can be relieved. If there is, it is determined that it cannot be relieved.

  A block including a page that cannot be relieved by the ECC function is not used as a defective block. If the number of defective blocks is less than a certain number, the DUT is regarded as a non-defective product. Yes.

  However, the conventional semiconductor test apparatus 200 has the following problems. That is, when determining whether or not the DUT can be relieved by the ECC function, all the information of the test result determined by comparison by the comparator 210 is stored in the fail memory 220, and then as the target range For example, since the number of defective cells is counted for each page, there is a problem in that it takes a long time to finally determine whether or not the ECC function can be relieved.

  In addition, since all of the test result information once compared and determined by the comparator 210 is stored, it is necessary to prepare a large-capacity fail memory 220 like the DUT, and there is a problem that the cost increases accordingly.

  Accordingly, an object of the present invention is to provide a semiconductor test apparatus capable of efficiently performing a repair determination using an ECC function while reducing cost.

In order to solve the above-described problems, a semiconductor test apparatus according to the present invention performs a test on an object to be tested, and determines a pass or a fail indicating pass / fail from the result, and passes the test by the determination unit. Or, based on the information of a plurality of test results determined as fail, a fail number extracting means for extracting fail number information including the number determined as fail, and the number of failures repeatedly extracted a plurality of times by the fail number extracting means Fail number adding means for accumulating and adding information; fail adding information added by the fail number adding means; a fail comparing means for comparing a predetermined amount; and fail adding by the fail comparing means. As a result of comparing the information with the predetermined quantity, if the fail addition information is larger than the predetermined quantity, the ECC function Determining that already possible not, when a predetermined quantity is greater than the fail addition information, and the ECC determining means for determining that it is possible to repair the ECC function, are set in accordance with the judgment target regions relief by ECC function When the value counted by the number counting means becomes zero, the number counting means for down-counting the number of times the fail number information is extracted by the fail number extracting means in synchronization with a clock signal from the set number of times, Count switching means for switching the set number of times in accordance with a range to be repaired by another ECC function, and each means operates in synchronization with a clock signal.

  With such a configuration, the fail number adding means adds the fail number information repeatedly extracted a plurality of times without performing the process of storing all the information of the plurality of test results determined to be pass or fail. Since it is determined whether or not the ECC function can be relieved, it is possible to efficiently determine the relieving by the ECC function. In addition, since a fail memory for storing all the test result information is not prepared, the determination can be made efficiently while reducing the cost.

  Another semiconductor test apparatus according to the present invention performs a test on an object to be tested, and determines a pass or fail indicating pass / fail from the result, and a plurality of pass or fail determined by the determination unit. Based on the test result information, a fail number extracting unit that extracts fail number information including the number determined to be failed, and a fail number that cumulatively adds the fail number information repeatedly extracted a plurality of times by the fail number extracting unit. Number addition means, fail addition information added by the fail number addition means, and fail comparison means for comparing a predetermined amount with a predetermined amount, and fail addition information and a predetermined quantity are compared with the fail comparison means. As a result, if the fail addition information is larger than the predetermined quantity, it is determined that the ECC function cannot be relieved, and If the quantity is greater than the fail addition information is characterized by and a ECC determining means for determining that it is possible to repair the ECC function.

  In the semiconductor test apparatus described above, the fail number adding means is extracted by the fail holding means for holding the fail addition information, the fail addition information held by the fail holding means, and the fail number extracting means. There may be provided an addition output means for repeating the process of adding the number-of-failure information and outputting it to the fail holding means a plurality of times.

  Further, in the above-described semiconductor test apparatus, the fail number extraction means includes the number of bits determined to be failed based on bit information including a plurality of test results determined to be pass or fail by the determination means. Decimal fail number information may be extracted.

  According to the semiconductor test apparatus of the present invention, it is possible to obtain an effect that it is possible to efficiently perform the repair determination by the ECC function while reducing the cost.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is an explanatory view showing a configuration example of a semiconductor test apparatus 100 which is an embodiment of a semiconductor test apparatus according to the present invention. The semiconductor test apparatus 100 outputs a test signal for performing a test on a DUT that is, for example, a NAND flash memory, and compares the signal output from the DUT with an expected value in response to the test signal to pass or fail. Determine.

  The semiconductor test apparatus 100 includes a fail bit extraction unit 101 that extracts fail number information including the number of bits determined to fail for the DUT. For example, a test result indicating pass or fail is input to the fail bit extraction unit 101 as bit information having a data width of 8 bits from a comparator (not shown). The fail bit extraction unit 101 converts the number of bits determined to be failed from the input 8 bits into binary fail number information, extracts the information, and outputs to the addition unit 102 every time bit information is input. Repeatedly.

  The fail number information extracted by the fail bit extraction unit 101 is output to the addition unit 102. The adder 102 adds the fail addition information held by the flip-flop 103 and the fail number information extracted by the fail bit extraction unit 101 to output to the flip-flop 103. By performing such processing a plurality of times until the end signal is output from the address counter 105 by the adder 102, a fail addition including the number of bits determined to be all failures within the repair target range by the ECC function. Information can be obtained.

  The flip-flop 103 holds the fail addition information output from the adder 102 and returns it to the adder 102 for output. Note that the fail number information first extracted by the fail bit extraction unit 101 is received and held as it is via the addition unit 102. Further, the flip-flop 103 outputs the fail addition information output from the adding unit 102 to the comparing unit 104.

  The comparison unit 104 compares the fail addition information output from the flip-flop 103 with the fail count limit value set in advance by the ECC function in the apparatus. In this fail count limit value, a predetermined quantity is set as a limit value of the number of cells that can be relieved by the ECC function.

  If the comparison unit 104 compares the fail addition information with the fail count limit value and the fail addition information is larger than the fail count limit value, the comparison unit 104 determines that the ECC function cannot repair the fail addition information. The signal is output. On the other hand, when the fail count limit value is larger than the fail addition information, it is determined that the ECC function can be relieved, and the comparison unit 104 does not output a fail signal.

  The semiconductor test apparatus 100 further includes an address counter 105 that counts the number of times the fail bit extraction unit extracts the fail number information in accordance with the set number of times corresponding to the repair target range by the ECC function. The address counter 105 uses the fail bit extraction unit 101 as a determination target range for determining whether or not it can be relieved by the ECC function, for example, according to the number of times set according to the number of cells included in one page in the DUT block. Count the number of times to extract fail number information. Here, as shown in the timing chart of FIG. 3, the fail bit extraction unit 101 and each component in the apparatus operate in synchronization with a clock signal that controls the operation of each component. The address counter 105 counts the number of times the clock signal has been output up to the set number (down counts until it reaches 0).

  Then, when the address counter 105 counts down until the number of times of setting reaches zero, it adds an end signal, assuming that the fail addition information including the number of bits determined to be all failures within the repair target range by the ECC function is added. Output to the unit 102. In addition, a set number of times (for example, 511) corresponding to the number of cells included in another page is input to the address counter 105 again.

  Next, the operation for determining whether or not the ECC function of the semiconductor test apparatus 100 in the present embodiment can be relieved will be described with reference to the flowchart shown in FIG.

  Step S201: The fail bit extraction unit 101 performs processing of extracting fail number information based on bit information including a plurality of test results and outputting the information to the addition unit 102. When bit information having a data width of 8 bits including a plurality of test results determined as pass or fail is output from the comparator in the apparatus, the fail bit extraction unit 101 inputs the bit information, and from this bit information Binary fail number information including the number of bits determined to fail among the 8 bits is extracted. The extracted fail number information is output to the adding unit 102.

  Further, every time bit information is output from the comparator in the apparatus, the fail bit extracting unit 101 repeats a plurality of times, extracts the fail number information by the fail bit extracting unit 101, and outputs it to the adding unit 102.

  Step S202: The adding unit 102 performs a process of accumulating and adding the fail number information output from the fail bit extracting unit 101 a plurality of times. The adding unit 102 adds the fail number information output from the fail bit extracting unit 101 in step S201 and the fail adding information held by the flip-flop 103, and repeatedly outputs the information from the fail bit extracting unit 101 a plurality of times. Accumulate and add the number of failed fail information. Then, the adder 102 outputs and holds the fail addition information obtained by adding the fail number information to the flip-flop 103.

  The adder 102 outputs the number-of-failure information first output from the fail bit extractor 101 to the flip-flop 103 as it is via the adder 102 and holds it.

  Step S203: The address counter 105 counts the number of times the fail bit extraction unit 101 extracts the fail number information, and determines whether or not the error can be relieved by the ECC function. The process of determining whether or not is added.

  As shown in the timing chart of FIG. 3, the address counter 105 sets the number of times that the clock signal is output from the time of first extracting the number-of-failure information to the same number as the set number according to the set number corresponding to the determination target range. That is, it is determined whether or not the fail number information is extracted and added from all within the determination target range by counting down to “0” from the set number of times.

  For example, the number of times the clock signal is output is counted down according to the number of times set according to the number of cells included in one page in the DUT block as the determination target range, and the count is reduced until the number of times reaches “0”. It is counted and it is determined whether or not the fail number information is extracted from all of one page and added.

  If it is not counted down until the determination result is “0” (NO in step S203), the processing of steps S201 to S202 is repeated a plurality of times, and the number of failures is counted until it is counted down to “0”. Are extracted and added.

  Step S <b> 204: When down-counting is performed until the determination result is “0” (YES in Step S <b> 203), the address counter 105 performs a process of outputting an end signal to the adding unit 102. The address counter 105 determines that the fail number information is extracted and added from all within the determination target range, and finishes the process of accumulating and adding the fail number information as shown in the timing chart of FIG. An end signal is output to the adder 102, and the fail addition information is reset.

  At this time, the flip-flop 103 outputs the fail addition information output from the addition unit 102 to the comparison unit 104.

  For example, when the count is down-counted from the set number corresponding to the number of cells included in one page in the DUT block as a determination target range until it becomes “0”, the fail number information is extracted from all in one page. The end signal is output to the adding unit 102.

  Step S205: The comparison unit 104 compares the fail addition information output from the flip-flop 103 in step S204 with the fail count limit value, and performs a process of determining whether or not it can be relieved by the ECC function.

  As a result of comparing the fail addition information with the fail count limit value, if the fail addition information is larger than the fail count limit value, it is determined that the ECC function cannot be relieved and an ECC fail signal is sent to the CPU in the apparatus. Output. If the fail count limit value is larger than the fail addition information, it is determined that the ECC function can be relieved, and no ECC fail signal is output. At this time, not the ECC fail signal but the signal indicating the repairability may be output from the comparison unit 104.

  Step S206: The address counter 105 performs a process of switching the set number of times according to another determination target range. The address counter 105 receives the next Page Start signal in response to down-counting until it reaches “0” in step S203, and is included in the number of times set according to another determination target range (for example, included in another one page). (Set number of times according to the number of cells). Then, the processing in steps S201 to S205 is performed again in another determination target range, and it is determined whether or not it can be relieved by the ECC function.

  As described above, the semiconductor test apparatus 100 according to the present embodiment does not perform the process of collecting the information of a plurality of test results determined to be pass or fail and storing them in the fail memory or the like, so that it is in parallel with the DUT test. Thus, it is possible to efficiently determine whether the data can be relieved by the ECC function. In addition, since a fail memory for storing all the test result information is not prepared, the determination can be made efficiently while reducing the cost.

  Also, it can be determined whether or not each page in the block of the DUT can be relieved by the ECC function, whether or not each block is a defective block, or whether or not the DUT is a good product. Can be determined.

[Other Embodiments]
In the above-described embodiment, the ECC fail memory 106 may be provided which is connected to the comparison unit 104 and stores an ECC fail signal (or a repairable signal). FIG. 4 is an explanatory diagram showing a configuration of the semiconductor test apparatus 110 including the ECC fail memory 106. The semiconductor test apparatus 110 includes an ECC fail memory 106 in addition to the above configuration.

  The ECC fail memory 106 stores information such as an ECC fail for each determination target range output from the comparison unit 104 in the processing of steps S201 to S205 and a block number indicating a block in the determination target range. is there. Then, in response to the input of the ECC fail signal, information such as a block number and bit information “1” indicating a defective block are stored in association with each other.

  With such a configuration, it is possible to grasp the status of a defective block or the like of each block included in the DUT by referring to the contents stored in the ECC fail memory 106 after the test. Since the ECC fail memory 106 stores information such as a block number and bit information “1” indicating a defective block, the ECC fail memory 106 can be a memory having a smaller capacity than the DUT.

  In the above-described embodiment, 8-bit data width bit information including a plurality of test results is output from the comparator in the apparatus, and the fail bit extraction unit 101 inputs this bit information. Information is not limited to a data width of 8 bits.

It is explanatory drawing which shows the structure of the semiconductor test apparatus of this embodiment. It is a flowchart which shows operation | movement of the semiconductor test apparatus of this embodiment. It is a timing chart which shows operation | movement of the semiconductor test apparatus of this embodiment. It is explanatory drawing which shows the structure of the semiconductor test apparatus of other embodiment. It is explanatory drawing which shows the structure of the semiconductor test apparatus of a prior art.

Explanation of symbols

100, 110, 200 Semiconductor test apparatus 101 Fail bit extraction unit 102 Addition unit 103 Flip-flop 104 Comparison unit 105 Address counter 106 ECC fail memory

Claims (3)

A determination means for performing a test on an object to be tested, and determining a pass or a fail indicating the quality from the result;
Fail number extraction means for extracting fail number information including the number determined as fail based on information of a plurality of test results determined as pass or fail by the determination means;
Fail number addition means for accumulating and adding fail number information repeatedly extracted a plurality of times by the fail number extraction means;
Fail comparison means for comparing the fail addition information added by the fail number addition means with a predetermined quantity determined in advance;
As a result of comparing the fail addition information with the predetermined quantity by the fail comparing means, if the fail addition information is larger than the predetermined quantity, it is determined that the ECC function cannot be relieved, and the predetermined quantity is the fail addition information. ECC determining means for determining that the data can be relieved by the ECC function ,
A number counting means for down-counting the number of times the fail number information is extracted by the fail number extracting means in synchronization with a clock signal from a set number of times set according to the range to be determined for repair by the ECC function;
Count switching means for switching the set number of times according to a range to be repaired by another ECC function when the value counted by the number counting unit becomes zero,
Each of the means operates in synchronization with a clock signal. The semiconductor test apparatus according to claim 1 ,
The fail number adding means includes:
Fail holding means for holding the fail addition information;
Addition output means for repeatedly adding the fail addition information held by the fail holding means and the fail number information extracted by the fail number extracting means and repeatedly outputting the information to the fail holding means. A semiconductor test apparatus. The semiconductor test apparatus according to claim 1 or 2 ,
The fail number extraction means includes:
2. A semiconductor test apparatus, comprising: extracting binary fail number information including a number of bits determined to be failed based on bit information including a plurality of test results determined to be pass or fail by the determining means.

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