JP5025638B2 - Signal output device, test device, and program - Google Patents

Description

The present invention relates to a signal output apparatus, a signal detection apparatus, a test apparatus, an electronic device, and a program. In particular, the present invention relates to a signal output apparatus that outputs a pattern signal, a signal detection apparatus that detects an input pattern signal, a test apparatus that tests a device under test, an electronic device, and a program. This application is related to the following Japanese application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
1. Japanese Patent Application No. 2006-116204 Filing Date April 19, 2006

A test apparatus for testing a semiconductor device supplies a test signal to the semiconductor device via a transmission line formed by a socket, a cable, a performance board, etc., and inputs an output signal output from the semiconductor device via the transmission line. (For example, refer to Patent Document 1).
JP 2006-220660 A

  FIG. 1 shows a test signal or output signal that has passed through a transmission line. FIG. 2 shows the phase with respect to the pulse width of the test signal or output signal that has passed through the transmission line.

  Since the test signal and the output signal at the receiving end of the transmission line are cut off from the high frequency component by passing through the transmission line, the inclination of the edge is reduced as shown in FIG. A pattern having a relatively short pulse width is not set due to the slant of the edge. In other words, a pattern with a relatively short pulse width starts a change at the trailing edge before reaching the level to be reached by a change at the leading edge.

  When a logic value signal is generated by binarizing a pattern in which a change in the trailing edge is started without performing such settling with a predetermined threshold, the phase of the transition timing of the logic value is the original value of the logic value signal. This is faster than the phase when the pattern is binarized. That is, a relatively short pulse width pattern causes jitter by passing through the transmission line, and the pulse width becomes shorter than the original width. Such jitter is referred to as “pattern-dependent jitter”. As shown in FIG. 2, the pattern-dependent jitter increases as the pulse width becomes shorter.

  Here, when pattern-dependent jitter occurs in the test signal, the test apparatus cannot supply the test signal to the semiconductor device at the designated timing, and as a result, the semiconductor device may cause an unexpected operation. There is. Also, if pattern-dependent jitter occurs in the output signal, the test equipment cannot detect the output signal at the timing to be acquired, and as a result, the semiconductor device determines that it is defective despite outputting the expected output signal. There is a possibility that.

  Accordingly, an object of the present invention is to provide a signal output device, a signal detection device, a test device, an electronic device, and a program that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

According to the first aspect of the present invention, there is provided a signal output device that outputs a pattern signal, a pattern generation unit that generates waveform data of a pattern signal to be generated, and a timing signal according to a pattern period that the pattern signal should have A timing generation unit that generates a signal, waveform data output from the pattern generation unit, a timing control unit that controls output timing of a timing signal output from the timing generation unit based on the waveform data, and a timing generation unit that outputs A waveform shaping unit that generates a pattern signal corresponding to the data value of the waveform data output from the pattern generation unit in response to the timing signal, and the timing control unit includes first transition data in which the data value transitions in the waveform data; When the interval between the second transition data and the second transition data is smaller than the predetermined interval, The output timing of the corresponding timing signals, to provide a signal output device to delay the output timing determined by the pattern period.

Timing generation unit, and delaying the periodic signal provided to generate a timing signal, the timing control unit may control the delay amount of each of the timing signals.

  The timing control unit includes a jitter amount storage unit in which a pattern-dependent jitter amount generated when edges of pattern signals approach each other when the pattern signal is transmitted through a predetermined transmission path, and each transition data of the waveform data. The proximity determining unit that determines whether or not the interval with the immediately preceding transition data is smaller than a predetermined interval, and the proximity determining unit determines that the interval with the immediately preceding transition data is smaller than the predetermined interval. A delay amount control unit that reduces a delay amount of the timing signal corresponding to the transition data in the timing generation unit according to the pattern dependent jitter amount.

  The pattern generator generates, as waveform data, set pattern data that defines the pattern of the rising edge of the pattern signal to be generated and reset pattern data that defines the pattern of the falling edge of the pattern signal to be generated. The generation unit generates a set timing signal corresponding to the set pattern data and a reset timing signal corresponding to the reset pattern data as a timing signal, and the waveform shaping unit generates a rising edge corresponding to the set pattern data as the set timing. A pattern signal having a timing corresponding to the signal and having a falling edge corresponding to the reset pattern data at a timing corresponding to the reset timing signal is generated, and the timing control unit sets the set pattern data and reset pattern data. Based on the data, it may detect each transition data interval of the waveform data. The timing control unit may control the output timing of the timing signal according to the frequency at which the data value transitions in the waveform data.

According to the second embodiment of the present invention, a test apparatus for testing a device under test, a signal generator for inputting a pattern signal to the device under test, and a signal detection apparatus for detecting an output signal output from the device under test And a determination unit that determines the quality of the device under test based on the output signal detected by the signal detection device. The signal generation device generates a waveform data of a pattern signal to be generated, and a pattern A timing generator that generates a timing signal according to a pattern cycle that the signal should have, and waveform data output by the pattern generator, and controls the output timing of the timing signal output by the timing generator based on the waveform data Waves output by the pattern generator in response to timing signals output from the timing controller and the timing generator Have a waveform shaping section for generating a pattern signal corresponding to the data value of the data, the timing controller includes a first transition data data value transits in the waveform data, the distance between the second transition data predetermined And a test apparatus that delays the output timing of the timing signal corresponding to the second transition data from the output timing determined by the pattern period .

  The timing generation unit generates a timing signal by delaying a given periodic signal, and the timing control unit generates pattern-dependent jitter that occurs when the edges of the pattern signal come close to each other in the transmission path from the signal generation device to the signal detection device. A proximity determination unit that determines whether or not the interval between the immediately preceding transition data is smaller than a predetermined interval with respect to each transition data of the waveform data and a jitter amount storage unit to which the amount is given in advance, and a proximity determination unit A delay amount control unit for reducing the delay amount in the timing generation unit of the timing signal corresponding to the transition data determined to be smaller than a predetermined interval from the immediately preceding transition data according to the pattern-dependent jitter amount; May be included.

The timing control unit may control the delay amount of each timing signal.

The pattern generator generates, as waveform data, set pattern data that defines the pattern of the rising edge of the pattern signal to be generated and reset pattern data that defines the pattern of the falling edge of the pattern signal to be generated. The generation unit generates a set timing signal corresponding to the set pattern data and a reset timing signal corresponding to the reset pattern data as a timing signal, and the waveform shaping unit generates a rising edge corresponding to the set pattern data as the set timing. A pattern signal having a timing corresponding to the signal and having a falling edge corresponding to the reset pattern data at a timing corresponding to the reset timing signal is generated, and the timing control unit sets the set pattern data and reset pattern data. Based on the data, it may detect each transition data interval of the waveform data.

The timing control unit may control the output timing of the timing signal according to the frequency at which the data value transitions in the waveform data.

As the signal output device according to a first embodiment of the present invention, there is provided a program causing an information processing apparatus to function.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

The waveform of the test signal (or output signal) that has passed through the transmission line is shown. The phase with respect to the pulse width of the test signal (or output signal) that has passed through the transmission line is shown. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention, together with a device under test 100. 1 shows a configuration of a signal generator 12 according to an embodiment of the present invention, together with a device under test 100. An example of the configuration of the signal generation timing generation unit 24 and the waveform shaping unit 28 according to the embodiment of the present invention is shown together with the pattern generation unit 20 and the timing control unit 26. An example of waveform data, a set timing signal, and a reset timing signal is shown. 1 shows a configuration of a signal detection apparatus 14 according to an embodiment of the present invention, together with a device under test 100. An example of an output signal, a 1st timing signal, and a 2nd timing signal is shown. The structure of the signal detection apparatus 14 which concerns on the modification of embodiment of this invention is shown with the device under test 100. FIG. 2 shows an exemplary hardware configuration of a computer 1900 according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Test apparatus 12 Signal generator 14 Signal detector 16 Determination part 20 Pattern generation part 22 Period generation part 24 Signal generation timing generation part 26 Timing control part 28 Waveform shaping part 30 Driver 32 Jitter amount storage part 34 Proximity determination part 36 Delay Quantity control unit 42 Set timing generation unit 44 Reset timing generation unit 52-1 First delay setting unit 54-1 First addition unit 56-1 First coarse delay unit 58-1 First minute delay unit 52-2 Second delay Setting unit 54-2 Second addition unit 56-2 Second coarse delay unit 58-2 Second minute delay unit 60 SR latch 62 First comparison unit 64 Second comparison unit 66 Selection control unit 68 Selection unit 70 Signal detection timing Generation unit 72 Delay circuit 74 Proximity determination unit 76 Control unit 80 Central detection timing generation unit 82 Third comparison unit 100 Device under test 1900 Computer 2000 CPU
2010 ROM
2020 RAM
2030 Communication interface 2040 Hard disk drive 2050 Flexible disk drive 2060 CD-ROM drive 2070 Input / output chip 2075 Graphic controller 2080 Display device 2082 Host controller 2084 Input / output controller 2090 Flexible disk 2095 CD-ROM

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the claimed invention, and all combinations of features described in the embodiments are invented. It is not always essential to the solution.

  FIG. 3 shows the configuration of the test apparatus 10 according to this embodiment together with the device under test 100. The test apparatus 10 tests the device under test 100. The test apparatus 10 includes a signal generation device 12, a signal detection device 14, and a determination unit 16. The signal generator 12 inputs a pattern signal to the device under test 100. The signal detection device 14 detects an output signal output from the device under test 100. The determination unit 16 determines pass / fail of the device under test 100 based on the output signal detected by the signal detection device 14.

  FIG. 4 shows the configuration of the signal generator 12 according to this embodiment together with the device under test 100. The signal generator 12 outputs a pattern signal as a test signal to the device under test 100. The signal generation device 12 includes a pattern generation unit 20, a cycle generation unit 22, a signal generation timing generation unit 24, a timing control unit 26, a waveform shaping unit 28, and a driver 30. The pattern generator 20 generates waveform data of a pattern signal to be generated. For example, the pattern generator 20 may generate waveform data indicating the rising edge timing and the falling edge timing of the pattern signal for each test cycle period.

  The period generator 22 generates a periodic signal. For example, the cycle generator 22 may generate a cycle signal indicating the start timing of the test cycle cycle. The signal generation timing generator 24 generates a timing signal in accordance with the pattern period that the pattern signal should have. For example, the signal generation timing generator 24 may generate a timing signal by delaying the periodic signal supplied from the period generator 22 according to the waveform data output from the pattern generator 20.

  The timing control unit 26 receives the waveform data output from the pattern generation unit 20, and controls the output timing of the timing signal output from the signal generation timing generation unit 24 based on the waveform data. As an example, the timing control unit 26 has an interval between the first transition data in which the data value transitions in the waveform data and the second transition data in which the data value transitions immediately after the first transition data is smaller than a predetermined interval. In some cases, the output timing of the timing signal corresponding to the second transition data may be delayed from the output timing determined by the pattern period.

  In addition, when the signal generation timing generator 24 generates the timing signal by delaying the periodic signal, the timing controller 26 may control the delay amount of each timing signal as an example. Further, in the case of controlling the delay amount, the timing control unit 26 may include a jitter amount storage unit 32, a proximity determination unit 34, and a delay amount control unit 36 as an example. When the pattern signal is transmitted through a predetermined transmission path, the jitter amount storage unit 32 is given in advance a pattern-dependent jitter amount that occurs when the edges of the pattern signal are close to each other. That is, when the pattern having a relatively short pulse width passes through the transmission line, the jitter amount storage unit 32 stores the phase shift amount generated in the pattern. For example, the jitter amount storage unit 32 stores the pattern-dependent jitter amount when a pattern having a relatively short pulse width passes through the transmission path from the output end of the waveform shaping unit 28 to the input end of the device under test 100. You can do it.

  The proximity determination unit 34 determines whether or not each transition data of the waveform data has an interval from the immediately preceding transition data smaller than a predetermined interval. The delay amount control unit 36 delays in the signal generation timing generation unit 24 the timing signal corresponding to the transition data determined by the proximity determination unit 34 that the interval from the immediately previous transition data is smaller than a predetermined interval. The amount is reduced according to the amount of pattern dependent jitter. According to such a timing control unit 26, when outputting a pattern in which pattern-dependent jitter occurs because the interval between the first transition data and the second transition data is small, the output timing of the timing signal corresponding to the second transition data Can be output later than the original output timing determined by the pattern period.

  The waveform shaping unit 28 generates a pattern signal corresponding to the data value of the waveform data output from the pattern generation unit 20 according to the timing signal output from the signal generation timing generation unit 24. For example, the waveform shaping unit 28 may generate a pattern signal that rises or falls according to a timing signal. The driver 30 supplies the pattern signal output from the waveform shaping unit 28 to the device under test 100. For example, the driver 30 supplies a pattern signal to the device under test 100 via a transmission line.

  According to such a signal generator 12, when a pattern having a relatively short pulse width is transmitted through a transmission path, a pattern signal in which pattern-dependent jitter generated in the pattern is compensated in advance can be output. Therefore, according to the signal generator 12, even when pattern-dependent jitter is generated by the transmission line, the pattern signal can be input to the device under test 100 that is the reception destination at the designated timing.

  FIG. 5 shows the configuration of the signal generation timing generation unit 24 and the waveform shaping unit 28 according to an example of this embodiment, together with the pattern generation unit 20 and the timing control unit 26. The signal generator 12 may generate waveform data indicating the timing of the rising edge and the timing of the falling edge, and generate a pattern signal based on the timing indicated by these waveform data. The pattern generation unit 20 according to this example generates set pattern data that defines a rising edge pattern of a pattern signal to be generated, and reset pattern data that defines a falling edge pattern of a pattern signal to be generated. Generate as

  The signal generation timing generator 24 according to this example generates a set timing signal corresponding to the set pattern data and a reset timing signal corresponding to the reset pattern data as timing signals. As an example, the signal generation timing generator 24 delays the periodic signal based on the set pattern data to generate a set timing signal, and delays the periodic signal based on the reset pattern data to reset the reset timing signal. And a reset timing generation unit 44 for generating.

  As an example, the set timing generation unit 42 includes a first delay setting unit 52-1, a first addition unit 54-1, a first coarse delay unit 56-1, and a first minute delay unit 58-1. It's okay. The first delay setting unit 52-1 generates a set delay amount indicating the time from the start timing of the test cycle to the timing of the rising edge of the pattern signal for each test cycle based on the set pattern data. The first adder 54-1 adds the set delay amount and the set-side pattern-dependent jitter amount output from the timing controller 26, and outputs the result as a compensated delay amount. The first coarse delay unit 56-1 delays the cycle signal indicating the test pattern cycle generated by the cycle generation unit 22 by the reference clock cycle unit by the time indicated by the corrected delay amount. The first minute delay unit 58-1 delays the periodic signal delayed by the first coarse delay unit 56-1 by a time less than the reference clock period in the corrected delay amount, and outputs the delayed signal as a set timing signal.

  As an example, the reset timing generation unit 44 includes a second delay setting unit 52-2, a second addition unit 54-2, a second coarse delay unit 56-2, and a second minute delay unit 58-2. It's okay. The second delay setting unit 52-2 generates a reset delay amount indicating the time from the test cycle start timing to the falling edge timing of the pattern signal for each test cycle based on the reset pattern data. The second adder 54-2 adds the reset delay amount and the reset-side pattern-dependent jitter amount output from the timing control unit 26, and outputs the result as a post-compensation delay amount. The second coarse delay unit 56-2 delays the cycle signal indicating the test pattern cycle generated by the cycle generation unit 22 by the reference clock cycle unit by the time indicated by the corrected delay amount. The second minute delay unit 58-2 delays the periodic signal delayed by the second coarse delay unit 56-2 by a time less than the reference clock period in the corrected delay amount, and outputs the delayed signal as a reset timing signal.

  The timing control unit 26 detects each transition data interval of the waveform data based on the set pattern data and the reset pattern data. When the timing control unit 26 controls to output the output timing of the set timing signal later than originally intended, the timing control unit 26 outputs the set-side pattern-dependent jitter amount and outputs the output timing of the reset timing signal later than originally intended. When controlling, the reset side pattern dependent jitter amount is output.

  The waveform shaping unit has a pattern signal having a rising edge corresponding to the set pattern data at a timing corresponding to the set timing signal and a falling edge corresponding to the reset pattern data at a timing corresponding to the reset timing signal. Generate. The waveform shaping unit 28 may include an SR latch 60 as an example. The SR latch 60 raises the pattern signal at the timing of the set timing signal and lowers the pattern signal at the timing of the reset timing signal.

  FIG. 6 shows an example of waveform data, a set timing signal, and a reset timing signal input to the signal generation timing generator 24 shown in FIG. When the time interval from the set timing to the reset timing in the pattern that rises and falls as shown by A in FIG. 6 is smaller than a predetermined interval, the timing control unit 26 resets the pattern-dependent jitter amount on the reset side. Is output. When receiving the reset-side pattern dependent jitter amount from the timing control unit 26, the set timing generating unit 42 outputs the output timing of the reset timing signal in the pattern that falls after rising up by the amount corresponding to the reset-side pattern dependent jitter amount.

  Further, the timing control unit 26 determines whether the time interval from the reset timing to the set timing in the pattern that rises after falling as shown by B in FIG. 6 is smaller than the predetermined interval. Outputs the jitter amount. When the set timing generation unit 42 receives the set side pattern dependent jitter amount, the set timing generation unit 42 outputs the output timing of the set timing signal in the pattern that rises and then falls later by the set side pattern dependent jitter amount.

  According to the signal generator 12 as described above, even when the pattern signal is generated based on the set timing signal and the reset timing signal, the pattern dependent jitter generated in the pattern having a relatively short pulse width is compensated in advance. A pattern signal can be output. Therefore, according to the signal generator 12, even when pattern-dependent jitter is generated by the transmission line, the pattern signal can be input to the device under test 100 that is the reception destination at the designated timing.

  For example, the timing control unit 26 may change the output timing of the reset timing signal by a change amount different from the change amount that changes the output timing of the set timing signal. Thereby, according to the signal generator 12, even when there is a difference between the signal rising characteristic and the signal falling characteristic in the driver 30, both the rising edge and the falling edge are covered at the designated timing. The test device 100 can be supplied.

  Further, the timing control unit 26 may control the output timing of the timing signal in accordance with the frequency at which the data value transitions in the waveform data. As an example, when the frequency at which the data value transitions is higher than a predetermined frequency, the timing control unit 26 may increase the output timing of the timing signal earlier than the output timing of the pattern signal determined by the pattern cycle. As a result, according to the signal generator 12, jitter occurs due to a difference in power consumption caused by frequency, for example, a drop in power supply voltage or a rise in temperature of the signal generation timing generator 24, waveform shaper 28, or driver 30. Even if it exists, the pattern signal which compensated the said jitter beforehand can be output.

  FIG. 7 shows the configuration of the signal detection apparatus 14 according to this embodiment together with the device under test 100. The signal detection device 14 inputs an output signal output from the device under test 100 in accordance with the pattern signal supplied from the signal generation device 12 as a pattern signal. Then, the signal detection device 14 detects the logical value of the input pattern signal.

  The signal detection device 14 includes a first comparison unit 62, a second comparison unit 64, a selection control unit 66, a selection unit 68, a signal detection timing generation unit 70, and a delay circuit 72. The first comparison unit 62 detects the logical value of the pattern signal according to the first timing signal given at a predetermined cycle. For example, the first comparison unit 62 detects the logical value of the pattern signal for each cycle by comparing the pattern signal and the threshold at the timing of the first timing signal. The second comparison unit 64 detects the logical value of the pattern signal according to the second timing signal given at a phase different from that of the first timing signal. For example, the second comparison unit 64 detects the logical value of the pattern signal for each cycle by comparing the pattern signal and the threshold at the timing of the second timing signal.

  The selection control unit 66 detects the waveform pattern of the pattern signal based on the logical value of the pattern signal detected by either the first comparison unit 62 or the second comparison unit 64, and each of the pattern signals based on the waveform pattern It is determined whether the logical value detected by the first comparison unit 62 or the logical value detected by the second comparison unit 64 should be selected as the data value in the cycle.

  As an example, the selection control unit 66 may include a proximity determination unit 74 and a control unit 76. The proximity determination unit 74 determines whether the interval between the transition data of the logical values of the pattern signal detected by either the first comparison unit 62 or the second comparison unit is smaller than a predetermined interval. Determine whether or not. The control unit 76 selects the logical value output by the second comparison unit 64 for the cycle corresponding to the transition data determined by the proximity determination unit 74 that the transition data interval is smaller than the predetermined interval. 68, and the logic value output from the first comparison unit 62 may be selected by the selection unit 68 for other cycles. The selection unit 68 selects either the logical value output by the first comparison unit 62 or the logical value output by the second comparison unit 64 for each cycle of the pattern signal based on the determination result in the selection control unit 66. To select and output.

  The signal detection timing generation unit 70 generates a second timing signal having a predetermined period indicating the comparison timing by the second comparison unit 64. For example, the signal detection timing generator 70 generates a second timing signal having a cycle substantially the same as the cycle of the pattern signal. The delay circuit 72 delays the second timing signal and generates a first timing signal having a predetermined period indicating the comparison timing by the second comparison unit 64. For example, the delay circuit 72 may have a delay amount corresponding to a pattern-dependent jitter amount that occurs when the edges of the pattern signal are close to each other when the pattern signal is transmitted through a predetermined transmission path. As a result, the signal detection timing generation unit 70 is advanced in phase by the pattern dependent jitter amount from the first timing signal, and generates a second timing signal having the same period as the first timing signal. Therefore, the second comparison unit 64 can compare the input pattern signals at a timing earlier than the comparison timing by the first comparison unit 62 by the pattern-dependent jitter amount.

  FIG. 8 shows an example of a pattern signal (output signal), a first timing signal, and a second timing signal output from the device under test 100. As an example, the selection control unit 66 has a waveform pattern (for example, the waveform of C in FIG. 8) from the transition from the L logic to the H logic until the next transition from the H logic to the L logic, A waveform pattern (for example, waveform D in FIG. 8) from the transition to the next transition from the L logic to the H logic is detected. When the width of the waveform pattern is smaller than the predetermined width, the selection control unit 66 causes the selection unit 68 to select the logical value output from the second comparison unit 64 for the cycle including the waveform pattern. . Further, when the width of the waveform pattern is equal to or larger than the predetermined width, the selection control unit 66 outputs the logical value output from the first comparison unit 62 to the selection unit 68 for the cycle including the waveform pattern. Let them choose.

  According to such a signal detection device 14, the logical value of the input pattern signal can be detected at two different phases, and either one can be selected and output according to the waveform pattern. For example, the signal detection device 14 detects a logical value of a waveform pattern having a width smaller than a predetermined width at a timing earlier than the detection timing of the logical values of other waveform patterns by a pattern-dependent jitter amount. Thereby, according to the signal detection apparatus 14, the logical value of the pattern signal having a relatively short cycle can be detected at a timing at which the pattern dependent jitter generated in the pattern signal having the relatively short cycle is compensated. Therefore, according to the signal detection device 14, the logical value can be detected from the pattern signal output from the device under test 100 at the timing designated by the device under test 100 that is the transmission source.

  FIG. 9 shows the configuration of the signal detection apparatus 14 according to a modification of the present embodiment, together with the device under test 100. Since the signal detection device 14 according to the modified example of the present embodiment has substantially the same configuration and function as the signal detection device 14 shown in FIG.

  The signal detection device 14 further includes a center detection timing generator 80 and a third comparator 82. The center detection timing generator 80 generates a substantially center timing of each cycle of the pattern signal. The third comparison unit 82 detects the logical value of the pattern signal at substantially the center timing of each cycle of the pattern signal generated by the center detection timing generation unit 80. The selection control unit 66 detects the waveform pattern of the pattern signal based on the logical value detected by the third comparison unit 82, and uses the first comparison unit as a data value in each cycle of the pattern signal based on the waveform pattern. It is determined which of the logical value detected by 62 or the logical value detected by the second comparison unit 64 should be selected.

  According to such a signal detection device 14 according to this modification, the width of the waveform pattern is determined based on the logical value detected at the substantially central timing of each cycle of the pattern signal, so the first timing signal or the second timing is determined. Even when the signal is in the vicinity of the transition point of the pattern signal, the width of the waveform pattern can be accurately determined. Thereby, according to the signal detection device 14 according to the present modification, the waveform pattern in which the pattern-dependent jitter is generated can be accurately determined. Therefore, it is possible to accurately determine whether or not to compensate for the pattern-dependent jitter. it can.

  Further, the test apparatus 10 may be a test circuit provided in the same electronic device together with a circuit under test to be tested. The test circuit is realized as a BIST circuit or the like of an electronic device, and diagnoses the electronic device by testing the circuit under test. Thus, the test circuit can check whether the circuit to be tested can perform the normal operation originally intended by the electronic device.

  The test apparatus 10 may be a test circuit provided on the same board or the same apparatus as the circuit under test to be tested. Such a test circuit can also check whether or not the circuit under test can perform the intended normal operation as described above.

  FIG. 10 shows an example of a hardware configuration of a computer 1900 according to the present embodiment. A computer 1900 according to this embodiment is connected to a CPU peripheral unit having a CPU 2000, a RAM 2020, a graphic controller 2075, and a display device 2080 that are connected to each other by a host controller 2082, and to the host controller 2082 by an input / output controller 2084. Input / output unit having communication interface 2030, hard disk drive 2040, and CD-ROM drive 2060, and legacy input / output unit having ROM 2010, flexible disk drive 2050, and input / output chip 2070 connected to input / output controller 2084 With.

  The host controller 2082 connects the RAM 2020 to the CPU 2000 and the graphic controller 2075 that access the RAM 2020 at a high transfer rate. The CPU 2000 operates based on programs stored in the ROM 2010 and the RAM 2020 and controls each unit. The graphic controller 2075 acquires image data generated by the CPU 2000 or the like on a frame buffer provided in the RAM 2020 and displays it on the display device 2080. Instead of this, the graphic controller 2075 may include a frame buffer for storing image data generated by the CPU 2000 or the like.

  The input / output controller 2084 connects the host controller 2082 to the communication interface 2030, the hard disk drive 2040, and the CD-ROM drive 2060, which are relatively high-speed input / output devices. The communication interface 2030 communicates with other devices via a network. The hard disk drive 2040 stores programs and data used by the CPU 2000 in the computer 1900. The CD-ROM drive 2060 reads a program or data from the CD-ROM 2095 and provides it to the hard disk drive 2040 via the RAM 2020.

  The input / output controller 2084 is connected to the ROM 2010, the flexible disk drive 2050, and the relatively low-speed input / output device of the input / output chip 2070. The ROM 2010 stores a boot program that the computer 1900 executes at startup, a program that depends on the hardware of the computer 1900, and the like. The flexible disk drive 2050 reads a program or data from the flexible disk 2090 and provides it to the hard disk drive 2040 via the RAM 2020. The input / output chip 2070 connects various input / output devices via a flexible disk drive 2050 and, for example, a parallel port, a serial port, a keyboard port, a mouse port, and the like.

  A program provided to the hard disk drive 2040 via the RAM 2020 is stored in a recording medium such as the flexible disk 2090, the CD-ROM 2095, or an IC card and provided by the user. The program is read from the recording medium, installed in the hard disk drive 2040 in the computer 1900 via the RAM 2020, and executed by the CPU 2000.

  A program that is installed in the computer 1900 and causes the computer 1900 to function as the test apparatus 10 includes a signal generation module, a signal detection module, and a determination module. These programs or modules work on the CPU 2000 or the like to cause the computer 1900 to function as the signal generation device 12, the signal detection device 14, and the determination unit 16, respectively.

  A program installed in the computer 1900 and causing the computer 1900 to function as the signal generator 12 includes a pattern generation module, a period generation module, a signal generation timing generation module, a timing control module, a waveform shaping module, and a driver. Module. These programs or modules work with the CPU 2000 or the like to function the computer 1900 as the pattern generation unit 20, the cycle generation unit 22, the signal generation timing generation unit 24, the timing control unit 26, the waveform shaping unit 28, and the driver 30, respectively. Let

  A program installed in the computer 1900 and causing the computer 1900 to function as the signal detection device 14 includes a first comparison module, a second comparison module, a selection control module, a selection module, a signal detection timing generation module, A delay module. These programs or modules work on the CPU 2000 or the like to make the computer 1900 a first comparison unit 62, a second comparison unit 64, a selection control unit 66, a selection unit 68, a signal detection timing generation unit 70, and a delay circuit. Let each function.

  The program or module shown above may be stored in an external storage medium. As the storage medium, in addition to the flexible disk 2090 and the CD-ROM 2095, an optical recording medium such as DVD or CD, a magneto-optical recording medium such as MO, a tape medium, a semiconductor memory such as an IC card, or the like can be used. Further, a storage device such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a recording medium, and the program may be provided to the computer 1900 via the network.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

Claims (11)

A signal output device that outputs a pattern signal,
A pattern generator for generating waveform data of the pattern signal to be generated;
A timing generator that generates a timing signal according to a pattern period that the pattern signal should have;
A timing control unit that receives the waveform data output by the pattern generation unit and controls an output timing of the timing signal output by the timing generation unit based on the waveform data;
A waveform shaping unit that generates the pattern signal according to the data value of the waveform data output by the pattern generator according to the timing signal output by the timing generator;
The timing control unit is configured to output the timing signal corresponding to the second transition data when the interval between the first transition data and the second transition data in which the data value transitions in the waveform data is smaller than a predetermined interval. A signal output device that delays the output timing from the output timing determined by the pattern period . The timing generator generates the timing signal by delaying a given periodic signal,
The signal output device according to claim 1, wherein the timing control unit controls a delay amount of each of the timing signals. The timing controller is
In the case where the pattern signal is transmitted through a predetermined transmission path, a jitter amount storage unit in which a pattern dependent jitter amount generated when edges of the pattern signal are close to each other is given in advance,
For each transition data of the waveform data, a proximity determination unit that determines whether an interval with the immediately preceding transition data is smaller than the predetermined interval;
In the proximity determination unit, the delay amount in the timing generation unit of the timing signal corresponding to the transition data determined that the interval with the immediately preceding transition data is smaller than the predetermined interval is determined as the pattern dependence. A delay amount controller that reduces the amount of jitter according to the amount of jitter
The signal output device according to claim 1 or 2 . The pattern generation unit uses, as the waveform data, set pattern data that defines a rising edge pattern of the pattern signal to be generated and reset pattern data that defines a falling edge pattern of the pattern signal to be generated. Generate
The timing generator generates a set timing signal corresponding to the set pattern data and a reset timing signal corresponding to the reset pattern data as the timing signal;
The waveform shaping unit has a rising edge according to the set pattern data at a timing according to the set timing signal, and a falling edge according to the reset pattern data at a timing according to the reset timing signal. Generating the pattern signal comprising:
The timing control unit detects each transition data interval of the waveform data based on the set pattern data and the reset pattern data.
The signal output device according to any one of claims 1 to 3 . The timing control unit controls the output timing of the timing signal in accordance with the frequency of data value transition in the waveform data.
The signal output device according to claim 1 . As a signal output device according to claim 1, any one of 5, programs for an information processing apparatus to function. A test apparatus for testing a device under test,
A signal generator for inputting a pattern signal to the device under test;
A signal detection device for detecting an output signal output from the device under test;
Based on the output signal detected by the signal detection device, a determination unit that determines the quality of the device under test,
The signal generator is
A pattern generator for generating waveform data of the pattern signal to be generated;
A timing generator that generates a timing signal according to a pattern period that the pattern signal should have;
A timing control unit that receives the waveform data output by the pattern generation unit and controls an output timing of the timing signal output by the timing generation unit based on the waveform data;
Depending on the timing signal the timing generator outputs, have a waveform shaping unit for generating the pattern signal corresponding to the data value of the waveform data in which the pattern generating unit outputs,
The timing control unit is configured to output the timing signal corresponding to the second transition data when the interval between the first transition data and the second transition data in which the data value transitions in the waveform data is smaller than a predetermined interval. The test apparatus which makes the said output timing later than the said output timing defined by the said pattern period . The timing generator generates the timing signal by delaying a given periodic signal,
The timing controller is
In a transmission path from the signal generation device to the signal detection device, a jitter amount storage unit that is given in advance a pattern dependent jitter amount generated when edges of the pattern signal are close to each other;
For each transition data of the waveform data, a proximity determination unit that determines whether an interval with the immediately preceding transition data is smaller than the predetermined interval;
In the proximity determination unit, the delay amount in the timing generation unit of the timing signal corresponding to the transition data determined that the interval with the immediately preceding transition data is smaller than the predetermined interval is determined as the pattern dependence. A delay amount controller that reduces the amount of jitter according to the amount of jitter
The test apparatus according to claim 7 . The timing control unit controls a delay amount of each timing signal.
The test apparatus according to claim 7 or 8 . The pattern generation unit uses, as the waveform data, set pattern data that defines a rising edge pattern of the pattern signal to be generated and reset pattern data that defines a falling edge pattern of the pattern signal to be generated. Generate
The timing generator generates a set timing signal corresponding to the set pattern data and a reset timing signal corresponding to the reset pattern data as the timing signal;
The waveform shaping unit has a rising edge according to the set pattern data at a timing according to the set timing signal, and a falling edge according to the reset pattern data at a timing according to the reset timing signal. Generating the pattern signal comprising:
The timing control unit detects each transition data interval of the waveform data based on the set pattern data and the reset pattern data.
The test apparatus according to any one of claims 7 to 9 . The timing control unit controls the output timing of the timing signal in accordance with the frequency of data value transition in the waveform data.
The test apparatus according to claim 7 .

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