JP5019655B2 - Photoelectric conversion device and imaging device - Google Patents

Description

  The present invention relates to a photoelectric conversion device and an imaging device.

  In recent years, CMOS sensors have become widespread for digital cameras. One major reason is that good S / N can be realized under a wide range of ISO sensitivity conditions such as ISO 100-1600. In realizing a high S / N CMOS sensor, it is effective to use a column amplifier having a gain switching function. This is because it is overwhelmingly random noise to switch the gain in a narrow-band (operating frequency is about several hundred kHz) column amplifier rather than applying a gain in a wide-band (operating frequency of several MHz to several tens of MHz) final output amplifier. It is because it is advantageous to. In general, when an analog signal is amplified, increasing the gain as much as possible is advantageous not only for random noise but also for fixed pattern noise.

  8 and 9 are diagrams extracted from Patent Document 1. FIG. The photoelectric conversion device described in Patent Document 1 will be described with reference to FIGS. The outputs of B1, B2, B3, and B4, which are BASIS type pixel portions, are read from the emitter signal lines, voltage amplified by the column amplifiers A1 to A4, and then written to the holding capacitors G1 to G4. Thereafter, the signals written in the holding capacitors G1 to G4 are read out to the horizontal output line 4 in time series in accordance with the control signal from the scanning circuit 1, and output to the outside through the output amplifier 3. The gains of the column amplifiers A1 to A4 are controlled by the power supply 2. The column amplifiers A1 to A4 may have a narrower band than the output amplifier 3, and can narrow a frequency band in which noise is integrated as compared with the case where the voltage is amplified in the wideband output amplifier 3. , Random noise can be reduced. Further, voltage amplification by the column amplifiers A1 to A4 is also effective for suppressing fixed pattern noise. Fixed pattern noise occurs due to relative variations in the capacitance values of the holding capacitors G1 to G4, parasitic capacitance variations of the switches M41 to M44, and the like. When the voltage is amplified by the output amplifier 3, such fixed pattern noise is also amplified, so it is advantageous to amplify the voltage by the column amplifiers A1 to A4.

JP-A-6-339082

  On the other hand, CMOS sensors are increasing in number of pixels, and in order to achieve the same frame rate, it is necessary to increase the reading speed. For this reason, there is a need for shortening the horizontal blanking period during which reading from the pixel to the storage capacitor is performed. However, the solid-state imaging device that performs gain switching with the above-described column amplifier has the following problems in speeding up.

  In general, in an amplifier circuit, the higher the gain, the narrower the band of the column amplifier. Therefore, the band of the column amplifier is changed by switching the gain, and the band is lowered particularly when the high gain is set, and the responsiveness is deteriorated. In order to improve the responsiveness, it is conceivable to reduce the holding capacitor connected to the output section of the column amplifier and widen the band. However, when the storage capacitor is reduced, the relative variation in the capacitance value between the storage capacitors increases, and thus the fixed pattern noise increases. For this reason, the lower limit of the capacitance value of the storage capacitor is defined by fixed pattern noise, and the upper limit of the capacitance value of the storage capacitor is defined by responsiveness at the time of setting high sensitivity. As speed increases, there is a problem that both requirements cannot be met.

  The present invention has been made with the above problem recognition as an opportunity, for example, in a configuration in which the gain of an amplification unit that amplifies a signal output from a pixel to a pixel signal line can be changed, while suppressing solid pattern noise. The purpose is to increase the reading speed.

  A first aspect of the present invention provides a pixel output line, a pixel that outputs a signal to the pixel output line, an amplifying unit that amplifies the signal output to the pixel output line, and a signal output from the amplifying unit The present invention relates to a photoelectric conversion device that outputs a pixel signal based on a signal held in the holding capacitor. In the photoelectric conversion apparatus, the amplifying unit amplifies a signal output from the variable amplification stage, and a variable amplification stage that amplifies the signal output to the pixel output line with a gain selected from a plurality of gains. And a buffer stage held in the holding capacitor.

  In a preferred embodiment of the present invention, the variable amplifier stage may include a feedback amplifier circuit. The gain of the variable amplification stage can be changed by changing a feedback coefficient.

  In a preferred embodiment of the present invention, a plurality of the pixels may be two-dimensionally arranged, and the pixel output line, the amplification unit, and the storage capacitor may be provided for each column. Here, the photoelectric conversion device includes a second pixel output line, a switch that controls connection between the storage capacitor of each column and the second pixel output line, and a signal output to the second pixel output line. And an output amplifier for amplifying.

  In a preferred embodiment of the present invention, the buffer stage may include a voltage follower.

  In a preferred embodiment of the present invention, the buffer stage may include a source follower.

  A second aspect of the present invention relates to an imaging device, and the imaging device includes the above-described photoelectric conversion device and a processing circuit that processes a signal provided from the photoelectric conversion device.

  According to the present invention, for example, in a configuration in which the gain of an amplifying unit that amplifies a signal output from a pixel to a pixel signal line can be changed, the reading speed can be increased while suppressing solid pattern noise.

It is a block diagram which shows schematic structure of the photoelectric conversion apparatus (solid-state imaging device) of 1st Embodiment of this invention. It is a figure which shows schematic structure of the photoelectric conversion apparatus (solid-state imaging device) of 2nd Embodiment of this invention. It is an equivalent circuit diagram of one pixel. FIG. 3 is a timing diagram illustrating an operation example of the photoelectric conversion apparatus illustrated in FIG. 2. It is a figure which shows the modification of the photoelectric conversion apparatus of 2nd Embodiment of this invention. It is a figure which shows schematic structure of the photoelectric conversion apparatus (solid-state imaging device) of 3rd Embodiment of this invention. 1 is a diagram illustrating a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention. It is a figure which shows the structure of the conventional solid-state imaging device. It is a figure which shows the structure of the column amplifier of the conventional solid-state imaging device.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device (solid-state imaging device) 10 according to the first embodiment of the present invention. The pixel 100 includes a photoelectric conversion element such as a photodiode, and outputs a signal to a vertical output line (first pixel output line) 106 based on a signal obtained by photoelectric conversion of incident light. A pixel array A is configured by the pixels 100 arranged in a plurality of rows and a plurality of columns. The rows are selected by a vertical scanning circuit (not shown), and the columns are selected by a horizontal scanning circuit (not shown). In FIG. 1, for simplification, the pixels 100 arranged in one row × multiple columns are shown.

  The signal output to the vertical output line 106 is provided to the column amplifier (amplifying unit) 130. The column amplifier 130 includes a variable amplification stage 131 and a buffer stage 132 disposed on the subsequent stage side. The variable amplification stage 131 has a configuration capable of selectively setting a plurality of voltage amplification factors (gains). The output impedance of the variable amplification stage 131 is typically high impedance. The buffer stage 132 has a sufficiently low output impedance to drive the storage capacitor 112.

  The holding capacitor 112 temporarily holds the signal amplified by the column amplifier 130. The signals held in the holding capacitor 112 are sequentially read out to a horizontal output line (second pixel output line) 116 by a horizontal scanning circuit (not shown), differentially amplified by an output amplifier 118, and output to the outside as a pixel signal. Is done.

  When the uniform light quantity is incident on each pixel 100 of the pixel array A, the output difference for each column, that is, the fixed pattern noise is sufficient between the capacitance values of the plurality of holding capacitors 112 so that the fixed pattern noise becomes a problem-free level. Relative accuracy is required. In general, the larger the capacitance value of the storage capacitor 112, the less likely it is to receive errors due to variations in line width during manufacturing. On the other hand, when the capacitance value increases, the responsiveness of the column amplifier 130 that drives the capacitance value is limited.

  The variable amplification stage 131 in the column amplifier 130 provides a plurality of voltage amplification factors necessary for switching the sensitivity in the photoelectric conversion device 10. Here, the sensitivity is sensitivity to light incident on the photoelectric conversion device 10 and is generally expressed as ISO sensitivity.

  Here, as a comparative example, a configuration is assumed in which a holding capacitor 112 having a sufficiently large capacitance value is driven by the variable amplification stage 131 in order to ensure relative accuracy. In such a configuration, the band of the variable amplification stage 131 is limited by the storage capacitor 112, and the band changes depending on the voltage amplification factor. For example, when the variable amplification stage 131 is configured by a negative feedback amplifier circuit and the voltage amplification factor is changed by switching the feedback coefficient, the selected voltage amplification factor (corresponding to the closed loop gain) increases. , The bandwidth drops.

  On the other hand, in the photoelectric conversion apparatus 10 according to the preferred embodiment of the present invention, since the holding capacitor 112 is driven by the buffer stage 132, the amplification factor (selected amplification factor) set in the variable amplification stage 131 is set. Regardless, the bandwidth is constant.

  Therefore, according to the photoelectric conversion device 10 of the first embodiment, the fixed pattern noise can be reduced by using a storage capacitor having sufficient relative accuracy, and the response of the column amplifier when a high voltage amplification factor is selected. Is suppressed, and reading speed can be increased.

[Second Embodiment]
FIG. 2 is a diagram illustrating a schematic configuration of a photoelectric conversion device (solid-state imaging device) 20 according to the second embodiment of the present invention. The pixel array A includes a plurality of pixels 100 arranged in a plurality of columns and a plurality of rows. In these pixels 100, color filters R, Gr, Gb, and B according to a Bayer array are formed. In the pixel array A, basic units composed of 2 rows × 2 columns of pixels are two-dimensionally arranged.

  In the following, R pixels are formed as R pixels, Gr pixels are formed as Gr color filters, Gb pixels are formed as Gb color filters, and B color filters are formed. A pixel is called a B pixel.

  The signals of the R pixel and the Gb pixel are read out by a readout circuit arranged below the pixel array A in FIG. The B pixel and Gr pixel signals are read out by a readout circuit (not shown) arranged above the pixel array A.

  FIG. 3 is an equivalent circuit diagram of one pixel 100. The transfer switch 102 is driven by a transfer pulse PTX. The reset switch 103 is driven by a reset pulse PRES. The row selection switch 105 is driven by a row selection pulse PSEL. PTX is a symbol representing PTX1 to PTXn (n is the number of rows). PRES is a symbol representing PRES 1 to n. PSEL is a symbol representing PSEL1 to PSELn.

  FIG. 4 is a timing chart showing an operation example of the photoelectric conversion device 20 shown in FIG. Hereinafter, an operation example of the photoelectric conversion apparatus 20 will be described with reference to FIGS.

  Prior to the reading operation, the photoelectric conversion device 20 is exposed for a set exposure time, and photoelectric charges are accumulated in the photodiode 101. In the following description, it is assumed that a row driven by PRES1, PTX1, and PSEL1 output from the vertical scanning circuit 123 is selected.

  First, the pixel reset pulse PRES changes from the high level to the low level, and the reset of the gate electrode of the amplification MOSFET 104 is released. At this time, the potential corresponding to the dark time is held in the floating diffusion portion FD connected to the gate electrode.

  Subsequently, when the row selection pulse PSEL becomes high level, a dark output corresponding to the potential of the floating diffusion portion FD appears on the vertical output line 106 by the source follower circuit formed by the amplification MOSFET 104 and the constant current source 107. In this state, when the clamp pulse PC0R is activated to a high level, the clamp switch 109 is turned on, the variable amplification stage 131 is in the voltage follower state, and the electrode on the column amplifier side of the clamp capacitor 108 is substantially at the VREF voltage.

  Thereafter, the clamp pulse PC0R is deactivated from the high level to the low level, and the dark output on the vertical output line 106 is clamped.

  Subsequently, the accumulation pulse PTN is activated to a high level, and an amplified dark signal (hereinafter referred to as N output) output from the column amplifier 130 is stored in the storage capacitor 112n via the transfer gate 110n. The N output includes the offset of the column amplifier 130.

Thereafter, the transfer pulse PTX is activated to a high level, whereby the transfer switch 102 is set to a high level for a certain period, and the photoelectric charge accumulated in the photodiode 101 is transferred to the gate electrode of the amplification MOSFET 104. Here, the transferred charge is electrons, and the gate potential is lowered by Q / C _{FD when} the absolute value of the amount of transferred charge is Q and the capacitance of the floating diffusion portion FD is C _FD . Correspondingly, a light-time output appears on the vertical output line 106. Assuming that the source follower gain is G _sf , a change ΔVvl of the potential Vvl of the vertical output line 106 due to switching from the dark output to the bright output is expressed by Expression (1).

ΔV _vl = −Q · G _sf / C _FD (1)
This potential change ΔV _vl is voltage amplified by a variable amplification stage 131 including an operational amplifier 120, a clamp capacitor 108, and a feedback capacitor 121, and an output Vct of the variable amplification stage 131 is expressed by equation (2).

Vct = VREF + Q · (G _sf / C _FD ) · (C ₀ / C _f ) (2)
Here, C ₀ indicates the capacitance of the clamp capacitor 108, and C _f indicates the capacitance values of the feedback capacitors 121 a, 121 b, 121 c that are selected when the sensitivity switching pulses x 1, x 2, x 4 are activated, respectively. . For example, C ₀ = 1 pF. When the feedback capacitor 121a is selected, C _f = 1 pF, when the feedback capacitor 121b is selected, C _f = 0.5 pF, and when the feedback capacitor 121c is selected, C _f = 0.25 pF. . The voltage amplification factors represented by −C ₀ / C _f are −1 times, −2 times, and −4 times, respectively. That is, the change in the system in which negative feedback with respect to operational amplifier 120, by switching whether to select one of a plurality of feedback capacitors 121a-c, the feedback factor determined by the partial pressure ratio between C _f and C ₀ The voltage amplification factor can be switched.

  Note that a negative sign in the voltage amplification factor indicates an inverting amplifier circuit. The output Vct from the variable amplification stage 131 expressed by the equation (2) is impedance-converted by the buffer stage 132 formed of a voltage follower.

  The accumulation pulse PTS is activated to a high level after the transfer pulse is deactivated, and the light output (hereinafter referred to as S output) output from the column amplifier 130 at this time is held via the transfer gate 110s. Accumulated in the capacity 112s.

  Subsequently, the column selection switch 114 is sequentially selected by the scanning pulses COLSEL1, COLSEL2,... Generated by the horizontal scanning circuit 119, and signals of a plurality of columns (S output, N output) are sequentially read out to the horizontal output line 116. It is.

  Here, it is assumed that the variable amplification stage 131 directly drives the storage capacitor 112. In such a configuration, as the voltage amplification factor is increased to 1, 2, and 4, the bandwidth of the variable amplification stage 131 is reduced, which becomes an obstacle to speeding up.

  On the other hand, in the photoelectric conversion device 20 according to the preferred embodiment of the present invention, since the buffer stage 132 by the voltage follower drives the storage capacitor 112, the band is independent of the amplification factor set in the variable amplification stage 131. It becomes constant. In addition, since the holding capacitor 112 having a sufficient capacity to ensure relative accuracy can be used, fixed pattern noise can be reduced. Furthermore, in the case of reading the electric charge from the storage capacitor 112 to the horizontal output lines 116s and 116n, the capacitance division ratio can be set high. That is, assuming that the capacitance values of the storage capacitors 112 s and 112 n are CT, and the capacitance values of the horizontal output lines 116 are CH, the capacity division ratio can be expressed as CT / (CT + CH). To rise. Therefore, if the signal amplitude required outside is constant, the gain in other parts of the photoelectric conversion device can be reduced. Thereby, for example, a secondary effect that the voltage amplification factor in the column amplifier 130 and the voltage amplification factor of the output amplifier 118 can be lowered can be obtained.

  Further, since the voltage follower is used for the buffer stage 132, the level shift does not occur, and the N output written in the storage capacitor 112n can be made substantially VREF. For this reason, the design is facilitated and the buffer stage 132 can be operated at the highest speed.

  However, since the buffer stage 132 essentially converts the high output impedance of the variable amplification stage 131 into a low output impedance, the gain in the buffer stage 132 does not need to be one.

  In the photoelectric conversion device of FIG. 2, the variable amplification stage 131 is configured by an inverting amplifier circuit, but may be configured by a non-inverting amplifier circuit as illustrated in FIG.

[Third Embodiment]
FIG. 6 is a diagram showing a schematic configuration of a photoelectric conversion device (solid-state imaging device) 30 according to the third embodiment of the present invention. The photoelectric conversion device 30 of the third embodiment is different from the photoelectric conversion device 20 of the second embodiment in that the buffer stage 132 in the column amplifier 130 is configured as a source follower.

  A feature of the photoelectric conversion device 30 of the third embodiment is that the number of elements constituting the buffer stage 132 is small. In addition, when the storage capacitor 112 is charged with the column amplifier output corresponding to the saturation light amount, the storage capacitor 112 can be charged without being limited to a constant current value.

  When the signal written to the storage capacitor is in a direction in which the voltage increases as the amount of light increases, the source follower constituting the buffer stage 132 is preferably an NMOS source follower. On the other hand, if the direction is such that the voltage decreases as the amount of light increases, a PMOS source follower is preferable.

  From the above, according to the third embodiment, it is possible to realize a high-speed column amplifier with a small occupation area.

[Application example]
FIG. 7 is a diagram illustrating a schematic configuration of an imaging apparatus according to a preferred embodiment of the present invention. The imaging device 400 includes a solid-state imaging device 1004 represented by the photoelectric conversion devices 10, 20, and 30 of the first, second, and third embodiments.

  An optical image of the subject is formed on the imaging surface of the solid-state imaging device 1004 by the lens 1002. On the outside of the lens 1002, a barrier 1001 serving both as a protection function of the lens 002 and a main switch can be provided. The lens 1002 can be provided with a diaphragm 1003 for adjusting the amount of light emitted therefrom. The imaging signal output from the solid-state imaging device 1004 through a plurality of channels is subjected to various corrections, clamping, and the like by the imaging signal processing circuit 1005. Imaging signals output from the imaging signal processing circuit 1005 through a plurality of channels are analog-digital converted by the A / D converter 6. The image data output from the A / D converter 1006 is subjected to various corrections, data compression, and the like by the signal processing unit 1007. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 operate according to the timing signal generated by the timing generation unit 1008.

  The blocks 1005 to 1008 may be formed on the same chip as the solid-state image sensor 1004. Each block of the imaging apparatus 400 is controlled by the overall control / arithmetic unit 1009. In addition, the imaging apparatus 400 includes a memory unit 1010 for temporarily storing image data and a recording medium control interface unit 1011 for recording or reading an image on a recording medium. The recording medium 1012 includes a semiconductor memory or the like and can be attached and detached. The imaging apparatus 400 may include an external interface (I / F) unit 1013 for communicating with an external computer or the like.

  Next, the operation of the imaging apparatus 400 illustrated in FIG. 7 will be described. When the barrier 1001 is opened, the main power source, the control system power source, and the power source of the imaging system circuit such as the A / D converter 1006 are sequentially turned on. Thereafter, the overall control / calculation unit 1009 opens the aperture 1003 in order to control the exposure amount. A signal output from the solid-state imaging device 1004 passes through the imaging signal processing circuit 1005 and is provided to the A / D converter 1006. The A / D converter 1006 A / D converts the signal and outputs it to the signal processing unit 1007. The signal processing unit 1007 processes the data and provides it to the overall control / arithmetic unit 1009, and the overall control / arithmetic unit 1009 performs an operation for determining the exposure amount. The overall control / calculation unit 1009 controls the aperture based on the determined exposure amount.

  Next, the overall control / calculation unit 1009 extracts a high frequency component from the signal output from the solid-state imaging device 1004 and processed by the signal processing unit 1007, and calculates the distance to the subject based on the high frequency component. Thereafter, the lens 1002 is driven to determine whether or not it is in focus. When it is determined that the subject is not in focus, the lens 1002 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the imaging signal output from the solid-state imaging device 1004 is corrected and the like in the imaging signal processing circuit 1005, A / D converted by the A / D converter 1006, and processed by the signal processing unit 1007. The image data processed by the signal processing unit 1007 is accumulated in the memory unit 1010 by the overall control / calculation 1009.

  Thereafter, the image data stored in the memory unit 1010 is recorded on the recording medium 1012 via the recording medium control I / F unit under the control of the overall control / calculation unit 9. The image data can be provided to a computer or the like through the external I / F unit 1013 and processed.

101: Photodiode 102: Transfer switch 103: Reset switch 104: Amplification MOSFET
105: Row selection switch 106: Vertical output line (first pixel output line)
107: constant current source 108: clamp capacitor 109: clamp switch 110s, 110n: transfer gate 112s, 112n: storage capacitor 114s, 114n: column selection switch 116: horizontal output line (second pixel output line)
118: Output amplifier 119: Horizontal scanning circuit 120: Operational amplifiers 121a, 121b, 121c: Feedback capacitor 123: Vertical scanning circuit 130: Column amplifier (amplifying unit)
131: Variable amplification stage 132: Buffer stage

Claims (8)

  A photoelectric conversion device,
  A plurality of pixel output lines;
  A plurality of pixels that continuously output a first signal that is a dark signal and a second signal that is a light signal to a corresponding pixel output line among the plurality of pixel output lines;
  A plurality of amplifying units for amplifying the first signal and the second signal continuously output to the plurality of pixel output lines and outputting the amplified first signal and the amplified second signal;
  A plurality of constant current sources for passing a constant current through a corresponding pixel output line among the plurality of pixel output lines;
  A plurality of first holding capacitors for holding the amplified first signal and a second holding capacitor for holding the amplified second signal, each of which corresponds to one amplifying unit of the plurality of amplifying units; And the circuit
  A first horizontal output line for outputting the amplified first signal held in the first holding capacitor from each of the plurality of circuits;
  A second horizontal output line for outputting the amplified second signal held in the second holding capacitor from each of the plurality of circuits;
  An output amplifier that differentially amplifies the amplified first signal output to the first horizontal output line and the amplified second signal output to the second horizontal output line;
  The plurality of pixels include an amplification MOSFET, and a source follower circuit is configured by the amplification MOSFET and a corresponding constant current source among the plurality of constant current sources, and the first signal and the second signal are generated by the source follower circuit. A signal is output to a corresponding pixel output line among the plurality of pixel output lines;
  Each of the plurality of amplification units is
  A variable amplification stage that amplifies the first signal and the second signal continuously output to a corresponding pixel output line among the plurality of pixel output lines with a gain selected from a plurality of gains;
  A buffer stage for amplifying a signal output from the variable amplification stage to generate the amplified first signal and the amplified second signal;
  A photoelectric conversion device characterized by that.   The photoelectric conversion apparatus according to claim 1, wherein the variable amplification stage includes a feedback type amplification circuit, and the gain is changed by changing a feedback coefficient. A switch controlling a connection between each of the first storage capacitor and the first horizontal output line of said plurality of circuits,
A switch for controlling connection between the second storage capacitor of each of the plurality of circuits and the second horizontal output line;
The photoelectric conversion device according to claim 1, further comprising: The buffer stage, the photoelectric conversion device according to any one of claims 1 to 3, characterized in that it comprises a voltage Roman word. The buffer stage, the photoelectric conversion device according to any one of claims 1 to 3, characterized in that it comprises a source Roman word.   The variable amplification stage includes:
  A first terminal connected to a corresponding pixel output line among the plurality of pixel output lines, and a clamp capacitor having a second terminal;
  An operational amplifier having a first input terminal connected to the second terminal, a second input terminal to which a reference voltage is input, and an output terminal;
  A first path including a first capacitor having a first capacitance value and a first switch in series, and connecting the first input terminal and the output terminal;
  A second path including a second capacitor having a second capacitance value and a second switch in series, and connecting the first input terminal and the output terminal;
  A clamp switch disposed between the first input terminal and the output terminal,
  The photoelectric conversion device according to any one of claims 1 to 5, wherein   The output impedance of the buffer stage is smaller than the output impedance of the variable amplification stage,
  The photoelectric conversion device according to claim 1, wherein: The photoelectric conversion device according to any one of claims 1 to 7 ,
A processing circuit for processing a signal provided from the photoelectric conversion device;
An imaging apparatus comprising:

Images