JP4984502B2 - BGA type carrier substrate manufacturing method and BGA type carrier substrate - Google Patents
BGA type carrier substrate manufacturing method and BGA type carrier substrate Download PDFInfo
- Publication number
- JP4984502B2 JP4984502B2 JP2005341582A JP2005341582A JP4984502B2 JP 4984502 B2 JP4984502 B2 JP 4984502B2 JP 2005341582 A JP2005341582 A JP 2005341582A JP 2005341582 A JP2005341582 A JP 2005341582A JP 4984502 B2 JP4984502 B2 JP 4984502B2
- Authority
- JP
- Japan
- Prior art keywords
- carrier substrate
- bga type
- conductor layer
- type carrier
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 51
- 239000004020 conductor Substances 0.000 claims description 50
- 238000007747 plating Methods 0.000 claims description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 35
- 229910052802 copper Inorganic materials 0.000 claims description 33
- 239000010949 copper Substances 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 15
- BWGNESOTFCXPMA-UHFFFAOYSA-N Dihydrogen disulfide Chemical compound SS BWGNESOTFCXPMA-UHFFFAOYSA-N 0.000 claims description 10
- 239000000654 additive Substances 0.000 claims description 7
- 230000000996 additive effect Effects 0.000 claims description 7
- ALVPFGSHPUPROW-UHFFFAOYSA-N dipropyl disulfide Chemical compound CCCSSCCC ALVPFGSHPUPROW-UHFFFAOYSA-N 0.000 claims description 3
- 238000013329 compounding Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 72
- 239000010931 gold Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- LMPMFQXUJXPWSL-UHFFFAOYSA-N 3-(3-sulfopropyldisulfanyl)propane-1-sulfonic acid Chemical compound OS(=O)(=O)CCCSSCCCS(O)(=O)=O LMPMFQXUJXPWSL-UHFFFAOYSA-N 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 2
- 239000002202 Polyethylene glycol Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 229910000431 copper oxide Inorganic materials 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001223 polyethylene glycol Polymers 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229920001646 UPILEX Polymers 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Electroplating And Plating Baths Therefor (AREA)
- Electroplating Methods And Accessories (AREA)
Description
本発明は、半導体チップが搭載されるＢＧＡ型キャリア基板の製造方法及びＢＧＡ型キャリア基板に関するものである。 The present invention relates to a method for manufacturing a BGA type carrier substrate on which a semiconductor chip is mounted and a BGA type carrier substrate.
近年の半導体装置は小型化、薄型化及び高密度化がより一層要求されるのに伴い、これらの半導体装置に用いられるパッケージ形態はＱＦＰ（クワッド・フラット・パッケージ）型やＴＣＰ（テープ・キャリア・パッケージ）からバンプ電極をエリアアレイ状に配置したＢＧＡ（ボール・グリッド・アレイ）を使ったＣＳＰ（チップ・サイズ・パッケージ）として大きく市場に展開されている。 With recent demands for smaller, thinner and higher density semiconductor devices, the package forms used in these semiconductor devices are QFP (quad flat package) type and TCP (tape carrier tape). CSP (Chip Size Package) using BGA (Ball Grid Array) in which bump electrodes are arranged in an area array from the package) is widely deployed in the market.
また、半導体大規模集積回路（ＬＳＩ）等の半導体素子では、近年、動作速度がクロック周波数で１ＧＨｚに達するものが出現している。この様な高速半導体素子では、トランジスターの集積度が高く、その結果入出力端子数が１０００を越えるものもある。 In recent years, semiconductor devices such as semiconductor large-scale integrated circuits (LSIs) have appeared that have an operating speed of 1 GHz in terms of clock frequency. In such a high-speed semiconductor device, there are some devices in which the degree of integration of transistors is high, and as a result, the number of input / output terminals exceeds 1000.
このような多端子数の半導体素子をプリント配線基板に実装するために、半導体素子とプリント基板の間にはキャリア基板が配置され、両者の電気的接合の橋渡しを担っている。キャリア基板は、高密度化された半導体素子の端子との接合に対応するため、プリント配線基板よりも非常に薄い層構造で、一方の面に半導体チップを実装するためのバンプが、他方の面にはんだボール電極パッドが形成されてなるＢＧＡ型キャリア基板が用いられている。 In order to mount such a multi-terminal number of semiconductor elements on a printed wiring board, a carrier board is disposed between the semiconductor elements and the printed board, and serves as a bridge for electrical connection between the two. The carrier substrate has a much thinner layer structure than the printed wiring board to support bonding with the high-density semiconductor element terminals, and bumps for mounting the semiconductor chip on one surface are on the other surface. A BGA type carrier substrate having a solder ball electrode pad formed thereon is used.
最近では、さらなる高密度実装への対応、また、高動作周波数化への要望に答えるため、ポリイミド樹脂フィルムなどに配線層を形成したものを積層して多層回路配線板全体の厚さを薄くするとともに、層間接続長を短くすることにより高周波に対応させたものも開発されてきている。 Recently, in order to respond to the demand for higher density mounting and higher operating frequency, the thickness of the entire multilayer circuit wiring board is reduced by laminating a polyimide resin film with a wiring layer formed. At the same time, ones that are compatible with high frequencies by shortening the interlayer connection length have been developed.
図５（ａ）及び（ｂ）は、従来の半導体装置用テープキャリアの一例を示す模式平面図及び模式構成断面図である。
テープキャリア２００は、ポリイミドフィルム等からなる絶縁性フィルム１１１の所定位置に、インナーリード１２１ｃ、配線層１２１ｂ、ランド１２１ａ、デバイスホール１１３、はんだボール電極１３１が設けられている。
5A and 5B are a schematic plan view and a schematic cross-sectional view showing an example of a conventional tape carrier for a semiconductor device.
The tape carrier 200 is provided with an inner lead 121c, a wiring layer 121b, a land 121a, a device hole 113, and a solder ball electrode 131 at predetermined positions of an insulating film 111 made of a polyimide film or the like.
はんだボール電極１３１は、ランド１２１ａの裏面の絶縁性フィルム１１１に形成された開口部１１２内に設けられており、はんだボール電極１３１上にはＡｕ（金）、Ｓｎ（錫）、はんだ等によるめっきが施される。 The solder ball electrode 131 is provided in the opening 112 formed in the insulating film 111 on the back surface of the land 121a, and the solder ball electrode 131 is plated with Au (gold), Sn (tin), solder, or the like. Is given.
さらに、はんだボール電極１３１上には、半田球を搭載、またははんだペーストの印刷、リフローにてはんだボール電極１３１上にはんだボール１４１が形成され（図６参照）、ＩＣチップを搭載、実装して半導体装置が得られる。 Furthermore, solder balls 141 are formed on the solder ball electrodes 131 by mounting solder balls on the solder ball electrodes 131, or by printing and reflowing solder paste (see FIG. 6). A semiconductor device is obtained.
上記はんだボール電極１３１上に半田ボール１４１を形成する際、最近のファインピッチ、高密度実装の流れから、絶縁性フィルム１１１の厚みに対し、開口部１１２の径が小さくなっているため、半田球（又は、はんだペースト）が開口部１１２内のはんだボール電極１３１に接触し難くなる。
この結果、はんだ濡れ不良が生じたり、開口部１１２内にボイドが生じ、はんだボール電極１３１にはんだが接合されないことがある。
When the solder ball 141 is formed on the solder ball electrode 131, the diameter of the opening 112 is smaller than the thickness of the insulating film 111 due to the recent flow of fine pitch and high density mounting. (Or solder paste) is less likely to contact the solder ball electrode 131 in the opening 112.
As a result, solder wetting failure may occur or a void may be generated in the opening 112, and solder may not be joined to the solder ball electrode 131.
このはんだボール電極１３１へのはんだが接合不良問題を解決する方法として、はんだボール電極１３１上の開口部１１２内に電解銅めっきで嵩上げ導体層を形成した半導体装置用テープキャリアが提案されている（例えば、特許文献１参照）。 As a method of solving the problem of poor bonding of solder to the solder ball electrode 131, a tape carrier for a semiconductor device is proposed in which a raised conductor layer is formed by electrolytic copper plating in the opening 112 on the solder ball electrode 131 ( For example, see Patent Document 1).
しかしながら、はんだボール電極１３１上に形成される開口部の径が小さくなってくると、嵩上げ導体層の表面形状が問題になってくる。
図７（ａ）は、ランド１２１ａの裏面の絶縁性フィルム１１１に形成された開口部１１２内にはんだボール電極１３１が形成されたテープキャリアの部分模式構成断面図を示す。
However, as the diameter of the opening formed on the solder ball electrode 131 becomes smaller, the surface shape of the raised conductor layer becomes a problem.
FIG. 7A is a partial schematic cross-sectional view of a tape carrier in which a solder ball electrode 131 is formed in an opening 112 formed in the insulating film 111 on the back surface of the land 121a.
図７（ａ）に示す開口部１１２内のはんだボール電極１３１上に電解銅プラグめっきにより嵩上げ導体層１５１を形成した嵩上げ導体層１５１の表面形状の一例を図７（ｂ）に示す。 An example of the surface shape of the raised conductor layer 151 in which the raised conductor layer 151 is formed by electrolytic copper plug plating on the solder ball electrode 131 in the opening 112 shown in FIG. 7A is shown in FIG. 7B.
図７（ｂ）に示す嵩上げ導体層１５１の表面は凸状の形状をしており、嵩上げ導体層１５１の厚みが、絶縁性フィルム１１１の８割程度に達していると、半田球を搭載する際に嵩上げ導体層１５１上で不安定になり、リフローする際に半田球が落ちたり、はんだボールの位置ズレ等が発生し、問題となっている。
このことから、嵩上げ導体層１５１の表面形状は、平坦か、凹状にすることが好ましい。
The surface of the raised conductor layer 151 shown in FIG. 7B has a convex shape. When the thickness of the raised conductor layer 151 reaches about 80% of the insulating film 111, solder balls are mounted. In this case, it becomes unstable on the raised conductor layer 151, and when reflowing, the solder balls fall or the position of the solder balls is misaligned.
Therefore, the surface shape of the raised conductor layer 151 is preferably flat or concave.
図７（ｂ）に示す嵩上げ導体層１５１表面の凸状の形状は、銅プラグめっきを直流の電解銅めっきで行った場合の事例で、めっき条件等で銅めっき析出形状を制御するのは難しいという問題を有している。
本発明は、上記問題点に鑑み考案されたもので、開口部内のはんだボール電極上に嵩上げ導体層を直流の電解銅めっきにて形成する際、予め電解銅めっきに使用する銅めっき液に銅めっき添加剤（促進剤）を添加することにより、嵩上げ導体層の表面形状を制御するようにしたＢＧＡ型キャリア基板の製造方法及びＢＧＡ型キャリア基板を提供することを目的とする。 The present invention has been devised in view of the above problems. When a raised conductor layer is formed by direct current electrolytic copper plating on a solder ball electrode in an opening, copper is previously used as a copper plating solution used for electrolytic copper plating. It is an object of the present invention to provide a method for producing a BGA type carrier substrate and a BGA type carrier substrate in which the surface shape of the raised conductor layer is controlled by adding a plating additive (accelerator).
本発明に於いて上記課題を達成するために、まず請求項１においては、一方の面に半導体チップを実装するためのパッドが、他方の面にはんだボール電極と嵩上げ導体層とが形成されてなるＢＧＡ型キャリア基板の製造方法において、
前記はんだボール接続バッドの嵩上げ導体層を直流の電解銅めっきにて作製する際、電解銅めっきに使用する銅めっき液にジスルフィド（二硫化物）系銅めっき添加剤（促進剤）として３−スルホプロピル−ジスルフィドを０．０４〜０．１５ｍｌ／Ｌの配合濃度で添加することで、前記はんだボール接続バッドと接する前記嵩上げ導体層の表面を凹状とすることを特徴とするＢＧＡ型キャリア基板の製造方法としたものである。
In order to achieve the above object in the present invention, first, in claim 1, a pad for mounting a semiconductor chip is formed on one surface, and a solder ball electrode and a raised conductor layer are formed on the other surface. In the manufacturing method of the BGA type carrier substrate,
When the raised conductor layer of the solder ball connection pad is formed by DC electrolytic copper plating, the copper plating solution used for electrolytic copper plating is disulfide (disulfide) copper plating additive (accelerator) as 3-sulfo Producing a BGA type carrier substrate characterized in that the surface of the raised conductor layer in contact with the solder ball connection pad is made concave by adding propyl-disulfide in a compounding concentration of 0.04 to 0.15 ml / L. It is a method.
また、請求項２においては、請求項１に記載のＢＧＡ型キャリア基板の製造方法にて作製されたことを特徴とするＢＧＡ型キャリア基板としたものである。 A second aspect of the present invention is a BGA type carrier substrate manufactured by the method for manufacturing a BGA type carrier substrate according to the first aspect.
本発明のＢＧＡ型キャリア基板の製造方法によると、はんだボール電極の嵩上げ導体層の表面形状を凹部状に形成できるので、はんだボールマウント性が安定化し、接合強度に優れたはんだボールを形成できる。
また、ＢＧＡ型キャリア基板は、接合強度に優れたはんだボールを形成できるので、半導
体チップ等を実装して得られた半導体装置は、信頼性に優れた半導体装置となる。
According to the method for manufacturing a BGA type carrier substrate of the present invention, since the surface shape of the raised conductor layer of the solder ball electrode can be formed in a concave shape, the solder ball mountability is stabilized, and a solder ball having excellent bonding strength can be formed.
In addition, since the BGA type carrier substrate can form solder balls with excellent bonding strength, a semiconductor device obtained by mounting a semiconductor chip or the like becomes a semiconductor device with excellent reliability.
以下、本発明の実施の形態につき説明する。
図１は、本発明のＢＧＡ型キャリア基板の製造方法で作製されたＢＧＡ型キャリア基板の一実施例を示す模式構成断面図である。
図２は、はんだボール形成用の嵩上げ導体層３１の周辺部を拡大した部分拡大模式構成断面図である。
Hereinafter, embodiments of the present invention will be described.
FIG. 1 is a schematic cross-sectional view showing an example of a BGA type carrier substrate produced by the method for producing a BGA type carrier substrate of the present invention.
FIG. 2 is a partial enlarged schematic cross-sectional view in which the peripheral portion of the raised conductor layer 31 for forming solder balls is enlarged.
本発明のＢＧＡ型キャリア基板１００は、絶縁基材１１の一方の面にランド２１ａ及び半導体チップを接続するための電極パッド２１ｂと、他方の面にランド２１ａと電気的に接続されたはんだボール形成用の嵩上げ導体層３１とＮｉ／Ａｕめっき層５１とが形成されたものである。
嵩上げ導体層３１の表面形状は、図２に示すように、凹状になっているため、安定したボールマウント性を確保でき、優れたハンダボール接合強度を得ることができる。
The BGA type carrier substrate 100 of the present invention is formed with an electrode pad 21b for connecting a land 21a and a semiconductor chip to one surface of an insulating base material 11, and a solder ball electrically connected to the land 21a on the other surface. A raised conductor layer 31 and a Ni / Au plating layer 51 are formed.
As shown in FIG. 2, the surface shape of the raised conductor layer 31 is concave, so that stable ball mountability can be secured and excellent solder ball bonding strength can be obtained.
以下、本発明のＢＧＡ型キャリア基板の製造方法について説明する。
図３（ａ）〜（ｈ）は、本発明のＢＧＡ型キャリア基板の製造方法の一例を示す模式構成断面図である。
まず、接着材層１２が形成されたポリイミドフィルムフィルム等からなる絶縁基材１１を準備する（図３（ａ）参照）。
Hereinafter, the manufacturing method of the BGA type | mold carrier substrate of this invention is demonstrated.
3A to 3H are schematic cross-sectional views showing an example of a method for manufacturing a BGA type carrier substrate of the present invention.
First, the insulating base material 11 which consists of a polyimide film film etc. in which the adhesive material layer 12 was formed is prepared (refer Fig.3 (a)).
次に、パンチング、レーザー加工等により穴開け加工して、絶縁基材１１の所定位置に開口部１３を形成し、開口部１３内デスミア処理を行う（図３（ｂ）参照）。
この開口部１３は、はんだボール形成用の嵩上げ導体層を形成するためのもので、開口部１３の孔径、加工精度等により穴開け加工方法を選定する。
Next, a hole is formed by punching, laser processing or the like to form an opening 13 at a predetermined position of the insulating base material 11, and a desmear process in the opening 13 is performed (see FIG. 3B).
The opening 13 is used to form a raised conductor layer for forming solder balls, and a drilling method is selected according to the hole diameter, processing accuracy, and the like of the opening 13.
次に、開口部１３が形成された絶縁基材１１の接着材層１２面と銅箔を加圧、加熱して貼り合わせ、開口部１３が形成された絶縁基材１１に導体層２１が形成された積層基材２０を作製する（図３（ｃ）参照）。 Next, the adhesive layer 12 surface of the insulating base material 11 in which the opening 13 is formed and the copper foil are pressed and heated to bond together, and the conductor layer 21 is formed on the insulating base material 11 in which the opening 13 is formed. The laminated base material 20 thus prepared is prepared (see FIG. 3C).
次に、積層基材２０の導体層２１の表面を電気的に保護するために、メンディングテープ等を貼着する等の方法で保護層（特に、図示せず）を形成し、ジスルフィド（二硫化物）系銅めっき添加剤（促進剤）を添加した下記に示す銅めっき液を使用して、導体層２１をカソードにして直流の電解銅プラグめっきを行い、開口部１３内に表面形状が凹状を示す嵩上げ導体層３１を形成する（図３（ｄ）参照）。 Next, in order to electrically protect the surface of the conductor layer 21 of the laminated substrate 20, a protective layer (particularly not shown) is formed by a method such as attaching a mending tape, etc. Using the copper plating solution shown below to which a sulfide) -based copper plating additive (accelerator) is added, DC electrolytic copper plug plating is performed using the conductor layer 21 as a cathode, and the surface shape is formed in the opening 13. A raised conductor layer 31 having a concave shape is formed (see FIG. 3D).
銅めっき液の組成例
硫酸銅濃度：１３０ｇ／Ｌ
硫酸濃度 ：１９０ｇ／Ｌ
塩酸濃度 ：１００ｍｇ／Ｌ
銅めっき液用抑制剤（ポリエチレングリコール）：１５ｍｇ／Ｌ
易溶性酸化銅：適量
ジスルフィド（二硫化物）系銅めっき添加剤（促進剤）：００４〜０６８ｍｌ／Ｌ
上記ジスルフィド（二硫化物）系銅めっき添加剤（促進剤）の配合量は、例えば、３−スルホプロピル−ジスルフィド（ロームアンドハース社製：米国）を使った場合の事例である。
Example of composition of copper plating solution Copper sulfate concentration: 130 g / L
Sulfuric acid concentration: 190 g / L
Hydrochloric acid concentration: 100 mg / L
Inhibitor for copper plating solution (polyethylene glycol): 15 mg / L
Easily soluble copper oxide: appropriate amount disulfide (disulfide) based copper plating additive (accelerator): 004-068 ml / L
The amount of the disulfide (disulfide) -based copper plating additive (accelerator) is, for example, a case where 3-sulfopropyl-disulfide (Rohm and Haas Co., USA) is used.
３−スルホプロピル−ジスルフィド（ロームアンドハース社製：米国）の配合濃度と開口部１３の嵩上げ導体層３１の表面形状との関係は、０．０４〜０．１５ｍｌ／Ｌの配合
濃度で、開口部１３の嵩上げ導体層３１表面は凹状の形状を示す。
０．１５ｍｌ／Ｌから０６８ｍｌ／Ｌに増えるに従って、開口部１３の嵩上げ導体層３１表面は凹状から平坦状になり、０６８ｍｌ／Ｌ以上になると、開口部１３の嵩上げ導体層３１表面は凸状の形状を示す。
このように、通常の銅めっき液にジスルフィド（二硫化物）系銅めっき添加剤（促進剤）を適量添加することにより、直流の電解銅めっきにて、表面形状が凹状の嵩上げ導体層３１を形成することが可能となる。
The relationship between the blending concentration of 3-sulfopropyl-disulfide (Rohm and Haas: USA) and the surface shape of the raised conductor layer 31 of the opening 13 is 0.04 to 0.15 ml / L. The surface of the raised conductor layer 31 of the portion 13 has a concave shape.
The surface of the raised conductor layer 31 of the opening 13 is changed from a concave shape to a flat shape as it increases from 0.15 ml / L to 068 ml / L, and when it is 068 ml / L or more, the surface of the raised conductor layer 31 of the opening portion 13 is convex. Show shape.
In this way, by adding an appropriate amount of a disulfide (disulfide) -based copper plating additive (accelerator) to a normal copper plating solution, the raised conductor layer 31 having a concave surface shape can be formed by DC electrolytic copper plating. It becomes possible to form.
次に、導体層２１上の保護層を剥離処理して、導体層２１上にレジストを形成し、パターン露光、現像等の一連のパターニング処理を行って、レジストパターン４１を形成し、嵩上げ導体層３１面にはメンディングテープ等により保護層４２を形成する（図３（ｅ）参照）。 Next, the protective layer on the conductor layer 21 is stripped to form a resist on the conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41. A protective layer 42 is formed on the 31st surface with a mending tape or the like (see FIG. 3E).
次に、レジストパターン４１をエッチングマスクにして、導体層２１をエッチングし、レジストパターン４１及び保護層４２を剥離処理して、ランド２１、配線層（特に、図示せず）及び半導体チップを接続するための電極パッド２１ｂを形成する（図３（ｆ）参照）。 Next, using the resist pattern 41 as an etching mask, the conductor layer 21 is etched, the resist pattern 41 and the protective layer 42 are peeled off, and the land 21, the wiring layer (not shown) and the semiconductor chip are connected. An electrode pad 21b is formed (see FIG. 3F).
次に、ランド２１が形成されている面の所定位置にＡｕ／Ｎｉめっきを防止するためのレジスト層４３を形成する（図３（ｇ）参照）。 Next, a resist layer 43 for preventing Au / Ni plating is formed at a predetermined position on the surface on which the land 21 is formed (see FIG. 3G).
次に、レジスト層４３をめっきマスクにして、嵩上げ導体層３１及び電極パッド２１ｂ表面にＡｕめっき及びＮｉめっきを行い、Ａｕ／Ｎｉめっき層５１を形成する。
以上の工程により、絶縁基材１１の一方の面にランド２１ａ及び半導体チップを接続するための電極パッド２１ｂと、他方の面にランド２１ａと電気的に接続されたはんだボール形成用の嵩上げ導体層３１とＮｉ／Ａｕめっき層５１とが形成された本発明のＢＧＡ型キャリア基板１００を得ることができる（図３（ｈ）参照）。
Next, using the resist layer 43 as a plating mask, Au plating and Ni plating are performed on the surface of the raised conductor layer 31 and the electrode pad 21b to form an Au / Ni plating layer 51.
Through the above steps, an electrode pad 21b for connecting the land 21a and the semiconductor chip to one surface of the insulating base 11, and a raised conductor layer for forming a solder ball electrically connected to the land 21a on the other surface BGA type carrier substrate 100 of the present invention in which 31 and Ni / Au plating layer 51 are formed can be obtained (see FIG. 3 (h)).
さらに、本発明のＢＧＡ型キャリア基板１００を用いて、ＢＧＡ型キャリア基板１００の嵩上げ導体層３１に半田球をマウント・リフローしてはんだボール６１を形成する。
さらに、ダイアタッチ剤４４を介して半導体チップ７１を搭載し、ボンディングワイヤ７２にて半導体チップ７１と電極パッド２１ｂとをボンディング接続し、ソルダーレジスト４５を形成し、モールド樹脂４６にて成形加工して半導体装置１１０を得ることができる（図４参照）。
Further, using the BGA type carrier substrate 100 of the present invention, solder balls 61 are formed by mounting and reflowing solder balls on the raised conductor layer 31 of the BGA type carrier substrate 100.
Furthermore, the semiconductor chip 71 is mounted via the die attach agent 44, the semiconductor chip 71 and the electrode pad 21b are bonded and connected by the bonding wire 72, the solder resist 45 is formed, and the molding resin 46 is molded. A semiconductor device 110 can be obtained (see FIG. 4).
まず、２５μｍ厚のポリイミドフィルム（ユーピレックスＳ）からなる絶縁基材１１に接着テープ（巴川Ｘ）を貼り合わせて１２μｍ厚の接着材層１２を形成した（図３（ａ）参照）。 First, an adhesive tape (Yodogawa X) was bonded to an insulating substrate 11 made of a 25 μm-thick polyimide film (Upilex S) to form a 12 μm-thick adhesive layer 12 (see FIG. 3A).
次に、パンチングにて穴開け加工して、接着材層１２が形成された絶縁基材１１の所定位置に開口部１３を形成し、開口部１３内デスミア処理を行った（図３（ｂ）参照）。 Next, punching was performed to form an opening 13 at a predetermined position of the insulating base material 11 on which the adhesive layer 12 was formed, and a desmear process in the opening 13 was performed (FIG. 3B). reference).
次に、開口部１３が形成された絶縁基材１１の接着材層１２面と２５μｍ厚の銅箔（３ＥＣ−ＶＬＰ）を加圧、加熱して貼り合わせ、開口部１３が形成された絶縁基材１１に２５μｍ厚の導体層２１が形成された積層基材２０を作製した（図３（ｃ）参照）。 Next, the surface of the adhesive layer 12 of the insulating base material 11 in which the opening 13 is formed and a 25 μm thick copper foil (3EC-VLP) are pressed and heated to bond together, and the insulating base in which the opening 13 is formed. A laminated substrate 20 in which a conductor layer 21 having a thickness of 25 μm was formed on the material 11 was produced (see FIG. 3C).
次に、積層基材２０の導体層２１の表面を電気的に保護するために、メンディングテープ等を貼着する等の方法で保護層（特に、図示せず）を形成し、３−スルホプロピル−ジスルフィド（ロームアンドハース社製：米国）を添加した下記に示す銅めっき液を使用し
て、導体層２１をカソードにして直流の電解銅プラグめっきを行い、開口部１３内に表面形状が凹状を示す４０μｍ厚の（嵩上げ導体層３１を形成した（図３（ｄ）参照）。
Next, in order to electrically protect the surface of the conductor layer 21 of the laminated base material 20, a protective layer (not shown) is formed by a method such as attaching a mending tape or the like, and 3-sulfo Using the following copper plating solution to which propyl-disulfide (Rohm and Haas Co., USA) was added, direct current electrolytic copper plug plating was performed using the conductor layer 21 as a cathode, and the surface shape was formed in the opening 13. A 40 μm-thick concave conductive layer 31 was formed (see FIG. 3D).
銅めっき液の組成例
・硫酸銅濃度：１３０ｇ／Ｌ
・硫酸濃度 ：１９０ｇ／Ｌ
・塩酸濃度 ：１００ｍｇ／Ｌ
・銅めっき液用抑制剤（ポリエチレングリコール）：１５ｍｇ／Ｌ
・易溶性酸化銅：適量
・３−スルホプロピル−ジスルフィド（ロームアンドハース社製：米国）：０．１０ｍｌ／Ｌ
ここで、直流の電解銅プラグめっきは、水平銅めっきライン（シュミット製）を用い、電流密度（設定電流）：２２．５Ａ／ｄｍ２（１２Ａ×４）、搬送速度０．３ｍ／ｍｉｎ、めっき時間１３．８分のめっき条件にて行い、開口部１３内に表面形状が凹状を示す４０μｍ厚の嵩上げ導体層３１を形成した。
Composition example of copper plating solution ・ Concentration of copper sulfate: 130g / L
・ Sulfuric acid concentration: 190 g / L
Hydrochloric acid concentration: 100 mg / L
・ Suppressor for copper plating solution (polyethylene glycol): 15mg / L
-Easily soluble copper oxide: appropriate amount-3-sulfopropyl-disulfide (Rohm and Haas: USA): 0.10 ml / L
Here, DC electrolytic copper plug plating uses a horizontal copper plating line (manufactured by Schmitt), current density (set current): 22.5 A / dm2 (12 A × 4), conveyance speed 0.3 m / min, plating time An elevated conductor layer 31 having a thickness of 40 μm and having a concave surface shape was formed in the opening 13 under the plating conditions of 13.8 minutes.
次に、導体層２１上の保護層を剥離処理して、導体層２１上にレジストを形成し、パターン露光、現像等の一連のパターニング処理を行って、レジストパターン４１を形成し、嵩上げ導体層３１面にはメンディングテープ等により保護層４２を形成した（図３（ｅ）参照）。 Next, the protective layer on the conductor layer 21 is stripped to form a resist on the conductor layer 21, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41. A protective layer 42 was formed on the 31st surface with a mending tape or the like (see FIG. 3 (e)).
次に、レジストパターン４１をエッチングマスクにして、第２塩化銅からなるエッチング液で導体層２１をエッチングし、レジストパターン４１及び保護層４２を剥離処理して、ランド２１、配線層（特に、図示せず）及び半導体チップを接続するための電極パッド２１ｂを形成した（図３（ｆ）参照）。 Next, using the resist pattern 41 as an etching mask, the conductor layer 21 is etched with an etching solution made of second copper chloride, the resist pattern 41 and the protective layer 42 are peeled off, and the land 21 and the wiring layer (in particular, FIG. And electrode pads 21b for connecting the semiconductor chip (see FIG. 3F).
次に、ランド２１が形成されている面の所定位置にＡｕ／Ｎｉめっきを防止するためのレジスト層４３を形成した（図３（ｇ）参照）。 Next, a resist layer 43 for preventing Au / Ni plating was formed at a predetermined position on the surface on which the land 21 was formed (see FIG. 3G).
次に、レジスト層４３をめっきマスクにして、嵩上げ導体層３１及び電極パッド２１ｂ表面にＡｕめっき行い０．５μｍ厚のＡｕ層を、さらにＡｕ層上にＮｉめっきを行い０．５μｍ厚のＮｉ層を形成して、Ａｕ／Ｎｉめっき層５１を形成した。
以上の工程により、絶縁基材１１の一方の面にランド２１ａ及び半導体チップを接続するための電極パッド２１ｂと、他方の面にランド２１ａと電気的に接続されたはんだボール形成用の嵩上げ導体層３１とＮｉ／Ａｕめっき層５１とが形成された本発明のＢＧＡ型キャリア基板１００を得た（図３（ｈ）参照）。
Next, using the resist layer 43 as a plating mask, the surface of the raised conductor layer 31 and the electrode pad 21b is Au plated to form an Au layer having a thickness of 0.5 μm, and Ni is further plated on the Au layer to form a Ni layer having a thickness of 0.5 μm. The Au / Ni plating layer 51 was formed.
Through the above steps, an electrode pad 21b for connecting the land 21a and the semiconductor chip to one surface of the insulating base 11, and a raised conductor layer for forming a solder ball electrically connected to the land 21a on the other surface BGA type carrier substrate 100 of the present invention in which 31 and Ni / Au plating layer 51 were formed was obtained (see FIG. 3 (h)).
１１……絶縁基材
１２……接着材層
１３……開口部
２０……積層基材
２１……導体層
２１ａ……バンプ
２１ｂ……電極パッド
３１……嵩上げ導体層
４１……レジストパターン
４２……保護層
４３……レジスト層
４４……ダイアタッチ剤
４５……ソルダーレジスト
４６……モールド樹脂
５１……Ａｕ／Ｎｉ層
６１……はんだボール
７１……半導体チップ
７２……ボンディングワイヤ
１００……ＢＧＡ型キャリア基板
１１０……半導体装置
１１１……絶縁性フィルム
１１２……開口部
１１３……デバイスホール
１２１ａ……ランド
１２１ｂ……配線層
１２１ｃ……インナーリード
１３１……ハンダボール電極
１４１……ハンダボール
１５１……嵩上げ導体層
DESCRIPTION OF SYMBOLS 11 ... Insulating base material 12 ... Adhesive material layer 13 ... Opening part 20 ... Laminated base material 21 ... Conductive layer 21a ... Bump 21b ... Electrode pad 31 ... Raised conductive layer 41 ... Resist pattern 42 ... ... Protective layer 43 ... Resist layer 44 ... Die attach agent 45 ... Solder resist 46 ... Mold resin 51 ... Au / Ni layer 61 ... Solder ball 71 ... Semiconductor chip 72 ... Bonding wire 100 ... BGA Type carrier substrate 110 ... semiconductor device 111 ... insulating film 112 ... opening 113 ... device hole 121a ... land 121b ... wiring layer 121c ... inner lead 131 ... solder ball electrode 141 ... solder ball 151 …… Raised conductor layer
Claims (2)
前記はんだボール接続バッドの嵩上げ導体層を直流の電解銅めっきにて作製する際、電解銅めっきに使用する銅めっき液にジスルフィド（二硫化物）系銅めっき添加剤（促進剤）として３−スルホプロピル−ジスルフィドを０．０４〜０．１５ｍｌ／Ｌの配合濃度で添加することで、前記はんだボール接続バッドと接する前記嵩上げ導体層の表面を凹状とすることを特徴とするＢＧＡ型キャリア基板の製造方法。 In a method for manufacturing a BGA type carrier substrate in which a pad for mounting a semiconductor chip on one surface and a solder ball electrode and a raised conductor layer are formed on the other surface,
When the raised conductor layer of the solder ball connection pad is formed by DC electrolytic copper plating, the copper plating solution used for electrolytic copper plating is disulfide (disulfide) copper plating additive (accelerator) as 3-sulfo Producing a BGA type carrier substrate characterized in that the surface of the raised conductor layer in contact with the solder ball connection pad is made concave by adding propyl-disulfide in a compounding concentration of 0.04 to 0.15 ml / L. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005341582A JP4984502B2 (en) | 2005-11-28 | 2005-11-28 | BGA type carrier substrate manufacturing method and BGA type carrier substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005341582A JP4984502B2 (en) | 2005-11-28 | 2005-11-28 | BGA type carrier substrate manufacturing method and BGA type carrier substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007149920A JP2007149920A (en) | 2007-06-14 |
| JP4984502B2 true JP4984502B2 (en) | 2012-07-25 |
Family
ID=38210969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005341582A Expired - Fee Related JP4984502B2 (en) | 2005-11-28 | 2005-11-28 | BGA type carrier substrate manufacturing method and BGA type carrier substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4984502B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6029873B2 (en) | 2012-06-29 | 2016-11-24 | 新光電気工業株式会社 | Wiring board, method for manufacturing wiring board, and method for manufacturing semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4480236B2 (en) * | 1999-08-06 | 2010-06-16 | イビデン株式会社 | Electrolytic plating solution, method for producing multilayer printed wiring board using the liquid, and multilayer printed wiring board |
| JP2003124265A (en) * | 2001-10-16 | 2003-04-25 | Hitachi Cable Ltd | Method of manufacturing tape carrier for semiconductor device |
| JP2004158737A (en) * | 2002-11-08 | 2004-06-03 | Hitachi Cable Ltd | Manufacturing method of wiring board |
| JP4540981B2 (en) * | 2003-12-25 | 2010-09-08 | 株式会社荏原製作所 | Plating method |
| DE102004005300A1 (en) * | 2004-01-29 | 2005-09-08 | Atotech Deutschland Gmbh | Process for treating carrier material for the production of powder carriers and application of the process |
| JP4242310B2 (en) * | 2004-03-12 | 2009-03-25 | 株式会社関東学院大学表面工学研究所 | Additive for copper sulfate plating and copper sulfate plating method using the same |
| JP2005272874A (en) * | 2004-03-23 | 2005-10-06 | Sumitomo Bakelite Co Ltd | Method for producing circuit board |
-
2005
- 2005-11-28 JP JP2005341582A patent/JP4984502B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007149920A (en) | 2007-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6943100B2 (en) | Method of fabricating a wiring board utilizing a conductive member having a reduced thickness | |
| US9111818B2 (en) | Packaging substrate | |
| US20100132998A1 (en) | Substrate having metal post and method of manufacturing the same | |
| KR102237870B1 (en) | Printed Circuit Board and Manufacturing Method thereof and Semiconductor Package Using the Same | |
| KR20060061227A (en) | Manufacturing Method of Circuit Board and Manufacturing Method of Electronic Component Mounting Structure | |
| US8671564B2 (en) | Substrate for flip chip bonding and method of fabricating the same | |
| US20150092357A1 (en) | Printed wiring board, method for manufacturing printed wiring board and package-on-package | |
| JP2004343030A (en) | Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board | |
| US20080036079A1 (en) | Conductive connection structure formed on the surface of circuit board and manufacturing method thereof | |
| US20170033036A1 (en) | Printed wiring board, semiconductor package, and method for manufacturing printed wiring board | |
| US20080185711A1 (en) | Semiconductor package substrate | |
| KR20110064471A (en) | Package substrate and its manufacturing method | |
| JP2011014944A (en) | Method of manufacturing electronic parts packaging structure | |
| US6708398B2 (en) | Substrate for use in package of semiconductor device, semiconductor package using the substrate, and methods for manufacturing the substrate and the semiconductor package | |
| US6455355B1 (en) | Method of mounting an exposed-pad type of semiconductor device over a printed circuit board | |
| JP2016076534A (en) | Printed wiring board with metal post and method of manufacturing the same | |
| US20080290528A1 (en) | Semiconductor package substrate having electrical connecting pads | |
| CN101510515B (en) | Circuit board, manufacturing method thereof and chip packaging structure | |
| KR101131230B1 (en) | A printed circuit board comprising a bump supporiting part and a method of manufacturing the same | |
| JP2010232616A (en) | Semiconductor device, and wiring board | |
| JP6473002B2 (en) | Printed wiring board with bumps | |
| JP4984502B2 (en) | BGA type carrier substrate manufacturing method and BGA type carrier substrate | |
| JPH07226456A (en) | Ic package and its manufacturing method | |
| US20110061907A1 (en) | Printed circuit board and method of manufacturing the same | |
| US9171818B2 (en) | Package structure and the method to manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081022 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090120 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101102 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101215 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110816 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110927 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120403 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120416 |
|
| R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150511 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |