JP4984485B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET.

FIG. 6 is a plan view schematically showing the arrangement of one unit cell of an IGBT in a conventional semiconductor device. In the figure, 51 is a semiconductor chip (hereinafter referred to as a chip), 39 is an emitter electrode, and 40 is a gate pad. A plurality of broken lines indicated by 43 each represents a unit cell. 46 is a pressure | voltage resistant structure.
As shown in FIG. 6, the unit cells 43 are regularly arranged over the entire surface of the chip 51. That is, the unit cells 43 are arranged at the same interval both in the central portion and the outer peripheral portion of the chip 51 in the case of a strite-like arrangement, for example. Such a regular arrangement is the same whether the emitter structure is a planar structure or a trench structure. The same applies to power MOSFETs.
The emitter electrode 39 of the IGBT is formed of a thin Al film of about 5 μm, and the emitter electrode 39 and an external lead-out terminal are connected by an aluminum wire. When the IGBT is turned on and a main current flows in the chip 51, the chip generates heat. The temperature distribution of the chip 51 due to this heat generation is such that the temperature of the outer periphery of the chip 31 with good heat dissipation is low and the temperature at the center of the chip with poor heat dissipation is high. In order to make the temperature in the chip 51 uniform, it has been proposed that the density of the unit cells 43 in the center of the chip 51 is made sparse and the outer peripheral part is made dense (for example, Patent Document 1).

In the IGBT module as shown in FIG. 7 in which the IGBT chip (chip 51) as shown in FIG. 6 is mounted, the electrical wiring to the chip 51 is performed by ultrasonically bonding the aluminum wire 53 to the emitter electrode 39. However, recently, with the aim of improving electrical characteristics and thermal characteristics, a structure in which a heat spreader 60, which is a high thermal conductor, is joined to the emitter electrode 39, or a structure in which a lead frame 63 as shown in FIG. It has been proposed (for example, Patent Document 2). In FIG. 16, 52, 61 and 62 are solders, 54 is an external lead terminal, 55 is an insulating substrate, 56 is a heat sink, 57 is a case, 58 is a gel, and 59 is a circuit pattern formed on the insulating substrate 55. .
JP 2004-363327 A JP-A-2005-116702

However, in Patent Document 1, since there is no high heat conductor such as the heat spreader 60 as shown in FIG. 7 on the emitter electrode 39, the temperature rise of the chip 51 increases from the transient time to the steady time. Further, when a large load is suddenly applied in a short time (msec. Or less) such as a short circuit state, it is difficult to suppress the temperature rise, and the chip 51 may be destroyed due to thermal runaway.
In Patent Document 2, the heat capacity and heat diffusion effect of the heat spreader 60 shown in FIG. 7 can reduce the temperature rise of the chip 51 from the transient time to the steady time. In the case where a large load is applied suddenly, the temperature increase immediately below the heat spreader 60 can be suppressed by the heat capacity of the heat spreader 60, but as shown in FIG. Since there is no contribution of this heat capacity at the part, it is difficult to suppress the temperature rise, and the chip 51 may be destroyed due to thermal runaway. In the figure, 42 is a collector electrode, 44 is a protective film, 47 is an active region, and 49 is a fillet.

In order to prevent this, when the thick emitter electrode 65 in which the Al film of the emitter electrode 39 is thickened to 10 μm or more is formed, as shown in FIG. 10, the patterning at the end of the thick emitter electrode 65 is disturbed. The portion may be fixed so as to overlap with the pressure-resistant structure 46, resulting in a decrease in pressure resistance.
An object of the present invention is to solve the above-described problems and provide a semiconductor device capable of stably suppressing a temperature rise of a chip not only during normal operation but also during a short circuit.

To achieve the above object, a first conductivity type drift layer, a second conductivity type base layer formed on a surface of the drift layer, and a first conductivity type impurity formed in the base layer. A diffusion region; an insulated gate structure provided in contact with a region serving as a channel between the impurity diffusion region and the drift layer; and an electrode electrically connected to both the impurity diffusion region and the base region. In the semiconductor device in which a plurality of unit cells each having the impurity diffusion region, the channel region, and the insulated gate structure are provided, the current density in the outer peripheral portion of the semiconductor device is set smaller than the current density in the central portion.
A first conductivity type drift layer; a second conductivity type base layer formed on a surface of the drift layer; a first conductivity type impurity diffusion region formed in the base layer; and the impurity diffusion. An insulating gate structure provided in contact with a region to be a channel between the region and the drift layer, and an electrode electrically connected to both the impurity diffusion region and the base region, the impurity diffusion region, In a semiconductor device provided with a plurality of unit cells each having a channel region and the insulated gate structure, the interval between adjacent unit cells in the central portion of the semiconductor device is arranged to be narrower than the interval between unit cells in the outer peripheral portion.

A first conductivity type drift layer; a second conductivity type base layer formed on a surface of the drift layer; a first conductivity type impurity diffusion region formed in the base layer; and the impurity diffusion. An insulating gate structure provided in contact with a region to be a channel between the region and the drift layer, and an electrode electrically connected to both the impurity diffusion region and the base region, the impurity diffusion region, In a semiconductor device provided with a plurality of unit cells each having a channel region and the insulated gate structure, the unit cells are arranged at equal intervals in the central portion of the semiconductor device, and the impurity diffusion region is not formed in the outer peripheral portion. The cell is arranged.
Further, it is preferable that a high thermal conductor is fixed or disposed integrally with the electrode on at least the electrode on the central unit cell.

The high thermal conductor may be a heat spreader, a portion in which the central portion of the electrode is selectively thickened, or at least one solder layer.
The electrode and the heat spreader as the high thermal conductor may be fixed with a conductive adhesive.
The conductive adhesive may be solder or metal nanofiller.
The thermal conductivity of the high thermal conductor may be equal to or higher than the thermal conductivity of the semiconductor substrate forming the semiconductor device.
Moreover, the thickness of the electrode on the central portion is preferably 10 μm or more.
In addition, the outer peripheral portion straddles the outer peripheral end of the high thermal conductor from the inner side than the pressure-resistant structure portion formed in the outer peripheral portion of the semiconductor device, and is inside the outer peripheral end of the high thermal conductor and in the vicinity of the outer peripheral end. It should be a crossing point.

According to the present invention, in a semiconductor device in which a high thermal conductor such as a thick emitter electrode having a thickness of 10 μm or more and a heat spreader having a thickness of several hundred μm is fixed on the surface of the semiconductor chip (emitter electrode), the density of the unit cell in the central portion of the semiconductor chip is reduced. By increasing the density and density of the unit cells on the outer periphery, it is possible to stably suppress chip temperature rise not only during normal operation but also when a large current is applied in a short time in a short-circuit state. A highly reliable semiconductor device can be provided.
In addition, by placing a high thermal conductor such as a thick emitter electrode or heat spreader on the part where the density of the unit cells is high and the heat generation density is high, it is stable not only during normal operation but also during short-circuiting. Thus, a rise in the temperature of the chip can be suppressed, and a highly reliable semiconductor device can be provided.

  Embodiments will be described in the following examples.

FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along line XX in FIG. 1 (a). Cross-sectional view of the main part, FIG. 10C is a detailed view of part A of FIG. This semiconductor device is exemplified by a trench gate type IGBT.
n ^- is p base region 2 on the surface of the drift layer 1 is formed, the p base region 2 and the through n ^- trenches 3 reach the drift layer 1 is formed. A gate insulating film 4 is formed on the inner wall of the trench 3, and a gate electrode 5 filled in the trench 3 through the gate insulating film 4 is formed. An n ⁺ emitter region 7 and a p ⁺ base contact region 8 are formed in the surface layer of the p base region 2 sandwiched between the trenches 3. Interlayer insulating film 6 having a contact hole on the surface is formed, and emitter electrode 9 is formed in electrical contact with n ⁺ emitter region 7 and p ⁺ base contact region 8. A channel is formed on the side surface of the trench 3 in the p base region 2 sandwiched between the n ⁺ emitter region 7 and the n ⁻ drift layer 1.

A p ⁺ collector layer 11 is formed on the back surface of the n ⁻ drift layer 1, and a collector electrode 12 that is in electrical contact with the p ⁺ collector layer 11 is formed. The trench 3, the p base region 2, the n ⁺ emitter region 7 and the p ⁺ base contact region 8 are combined into one unit cell 13, and a plurality of unit cells 13 are arranged and protected on the breakdown voltage structure 16 at the outermost periphery. The film 14 is covered, and the trench gate type IGBT chip 15 is formed.
The emitter electrode 9 and the gate pad 10 to which the gate electrode 5 is connected are formed on the surface of the chip 15, and a breakdown voltage structure 16 is formed on the outermost periphery of the chip 15 so as to surround them. The active region 17 of the chip 15 is surrounded by a breakdown voltage structure 16. A heat spreader 20, which is a high thermal conductor (for example, a copper member) having a thermal conductivity of 100 W / m · K or more, is fixed on the emitter electrode 9 with solder 18. In this case, electroless Ni plating is performed on the emitter electrode 9 which is an Al film, and the Ni plating film and the heat spreader 20 are fixed by the solder 18. Here, in FIG. 1B, 100 is the central portion of the chip 15, and 200 is the outer peripheral portion of the chip 15. The outer peripheral portion 200 is located on the inner side of the pressure-resistant structure 16, straddling the outer peripheral end of the heat spreader 20, on the inner side of the outer peripheral end of the heat spreader 20, and in the vicinity of the outer peripheral end (see the arrow in FIG. 1B). Say.

The density of the unit cells 13 in the center portion of the chip 15 is narrowed to increase the density, and the distance between the unit cells 13 located at the locations where the fillets 19 of the solder 18 on the outer peripheral portion are formed is increased. Sparse. As a result, the channel density at the center of the chip 15 becomes dense, the channel density at the outer periphery becomes sparse, the main current flowing through the center of the chip 15 increases, and the main current flowing through the outer periphery decreases. Therefore, the heat generation at the outer peripheral portion is reduced, and the temperature rise at the location 21 that is removed from the heat spreader 20 can be suppressed. In addition, since the heat spreader 20 is disposed at a place where the unit cells 13 generating a large amount of heat are dense, the temperature rise is suppressed and the temperature distribution in the surface of the chip 15 is made uniform.
As shown in FIG. 1B, the outer peripheral portion 200 where the density of the unit cells is sparse is set slightly inside the outer peripheral end of the heat spreader 20, so that the boundary portion between the outer peripheral end of the heat spreader 20 and the fillet 19 of the solder 18. Even immediately below, the density of the unit cells becomes sparse, and heat generation by the main current is suppressed. Therefore, since the thermal stress applied to the boundary portion is reduced, the occurrence of cracks and the like are suppressed, and the reliability of the semiconductor device is improved.

By doing so, not only during normal operation of the IGBT but also in a short circuit, the temperature rise of the chip can be stably suppressed, and chip destruction can be prevented.
Generally, the thermal conductivity when a chip (semiconductor element) is formed on a silicon substrate is almost 100 W / m · K. Therefore, the heat spreader 20 has a thermal conductivity of 100 W / m · K or more. Something (eg, copper, etc.) should be selected. Further, when the thickness of the heat spreader 20 is 0.2 mm or more, the heat dissipation efficiency is particularly improved.
The heat spreader 20 and the emitter electrode 9 are fixed with the solder 18, but metal bonding using a metal nanofiller such as Ag or Cu may be used. The emitter electrode 9 is formed of an Al film of about 5 μm.
By adopting the configuration as described above, it is possible to reduce the main current flowing in the outer peripheral portion, reduce the generated loss, and a large current / high voltage is applied in a very short time of the order of msec or less, particularly during a short circuit. Even in the state, the temperature rise at the outer peripheral portion of the chip 15 to which the high heat conductor such as the heat spreader 20 is not fixed can be suppressed, and the chip 15 can be prevented from being broken.

In the above description, the density of the unit cells 13 is changed between the central portion and the outer peripheral portion. However, the n ⁺ emitter region 7 is not formed in some unit cells 13 located in the outer peripheral portion without changing the interval between the unit cells 13. As a result, the channel density in the outer peripheral portion can be reduced from the central portion.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention. This principal part sectional drawing is a principal part sectional view equivalent to Drawing 1 (b).
The difference from FIG. 1 is that the emitter electrode 9 has a function corresponding to the heat spreader 20, and the thickness of the emitter electrode 9 formed on the dense portion (center portion) of the unit cell 13 is 10 μm or more. The thick emitter electrode 22 is formed. The thickness of the normal emitter electrode 9 at the outer periphery is about 5 μm, and the thickness of the emitter electrode 22 at the center is 10 μm or more, preferably 50 μm or more. Further, it is effective that the area of the thick emitter electrode 22 is 40% or more of the area of the thin emitter electrode 9.
Further, when the area occupied by the thick emitter electrode 22 is reduced, the area occupied by the unit cell 13 having a narrow interval is also reduced accordingly.

As described above, the thick emitter electrode 22 is formed in the central portion as described above. When the entire emitter electrode 22 is a thick emitter electrode, the shape of the outer peripheral end of the thick emitter electrode is disturbed by patterning (etching). This is because the thick emitter electrode 22 partially rides on the breakdown voltage structure 16 without obtaining a street pattern, and the breakdown voltage decreases.
Further, the outer peripheral end of the thick emitter electrode 22 may be formed to be separated from the outer peripheral end of the thin emitter electrode 9 (the inner end of the breakdown voltage structure 16) by about several hundred μm. In this case, naturally, the sparse part of the unit cell 13 needs to be expanded accordingly.

FIG. 3 is a cross-sectional view of a principal part of the semiconductor device according to the third embodiment of the present invention. This principal part sectional view is a principal part sectional view corresponding to FIG.
The difference from FIG. 2 is that a thick solder 24 is formed on the emitter electrode 9 instead of the thick emitter electrode 22. Since the solder 24 is not directly fixed to the emitter electrode 9 which is an Al film, the electrolytic Ni plating film 23 is coated on the emitter electrode 9 and the solder 24 is fixed through the electrolytic Ni plating film 23. At this time, the thickness of the solder 24 is set to 10 μm or more.
In the first to third embodiments, the stripe-shaped unit cells 13 are arranged in parallel. However, in addition to this, as shown in FIG. As shown in FIG. 5, the unit cells themselves may be dot-shaped unit cells 22 instead of stripes.

The gate structure is exemplified by a trench structure, but may be a planar structure.
In the first to third embodiments, the case of the IGBT is described as an example, but a MOSFET may be used.
In the first to third embodiments described above, the semiconductor device such as a vertical IGBT formed using silicon as a substrate has been described. However, a semiconductor device using a substrate such as SiC or GaN may be used.
In the case of semiconductor devices using SiC or GaN as substrates, these substrates are inherently excellent in thermal conductivity. However, by configuring as in the first to third embodiments, similarly, only normal operation is performed. In addition, even when a large current is applied in a short time in a short circuit state, the temperature rise of the chip can be stably suppressed, and the reliability can be improved.

In addition, what is necessary is just to join using metal nano fillers, such as copper, using metals with high heat conductivity, such as copper and aluminum, as a heat spreader. Since an extremely thin bonding layer can be realized by using the metal nanofiller, the thermal resistance can be lowered even with a metal having a lower thermal conductivity than SiC or GaN.
Further, if SiC or GaN is used as a heat spreader, it has a thermal conductivity equivalent to that of a semiconductor substrate, which is advantageous in terms of heat dissipation.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a), (c) is ( Detailed view of part A in b) Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Figure in which unit cells in the outer periphery are orthogonal Diagram of dot unit cell The top view which shows typically arrangement | positioning of 1 unit cell of IGBT in the conventional semiconductor device Cross-sectional view of the main part of an IGBT module having a heat spreader Cross-sectional view of the main part of an IGBT module connected by a lead frame It is a block diagram when the heat spreader adheres on the conventional semiconductor chip, (a) is a principal part top view, The figure (b) is principal part sectional drawing cut | disconnected by the XX line of the figure (a). Diagram showing the disadvantages of using a thick emitter electrode on the entire surface

Explanation of symbols

1 n ⁻ drift layer 2 p base region 3 trench 4 gate insulating film 5 gate electrode 6 interlayer insulating film 7 n ⁺ emitter electrode 8 p ⁺ base contact region 9 emitter electrode 10 gate pad 11 p ⁺ collector layer 12 collector electrode 13 unit cell DESCRIPTION OF SYMBOLS 14 Protective film 15 Chip 16 Withstand voltage structure 17 Active region 18, 24 Solder 19 Fillet 20 Heat spreader 21 Detached part 22 Thick emitter electrode 23 Electrolytic Ni plating film 100 Central part 200 Outer part

Claims (7)

A first conductivity type drift layer; a second conductivity type base layer formed on a surface of the drift layer; a first conductivity type impurity diffusion region formed in the base layer; and the impurity diffusion region; An insulating gate structure provided in contact with a region to be a channel between the drift layers, and an electrode electrically connected to both the impurity diffusion region and the base region, the impurity diffusion region, the channel region In a semiconductor device provided with a plurality of unit cells having the insulated gate structure,
Wherein the current density at the outer peripheral portion of the semiconductor device, the unit cells to be smaller than the current density at the central portion is disposed,
At least a heat conductor is fixed on the electrode on the unit cell arranged in the central part, or is integrated with the electrode on the electrode on the unit cell arranged in the central part. Heat conductor is placed,
The heat conductor is a heat spreader or a solder layer, or a portion where the central portion of the electrode is selectively thickened,
The outer peripheral portion is a region inside a pressure-resistant structure portion formed in the semiconductor device, and an end portion of the heat spreader or the solder layer, or an end portion of a portion where the central portion of the electrode is selectively thickened Located in the area,
A semiconductor device. The semiconductor device according to claim 1 , wherein the electrode and a heat spreader as the heat conductor are fixed with a conductive adhesive. The semiconductor device according to claim 2 , wherein the conductive adhesive is solder or metal nanofiller. The semiconductor device according to claim 1, wherein a thermal conductivity of the thermal conductor is equal to or higher than a thermal conductivity of a semiconductor substrate forming the semiconductor device. The semiconductor device according to any one of claims 1 to 4, wherein a thickness of a portion where the central portion of the electrode is selectively thickened is 10 µm or more. The semiconductor device according to claim 1, wherein the unit cells are arranged such that an interval between adjacent unit cells in a central portion of the semiconductor device is narrower than an interval between unit cells in an outer peripheral portion. The unit cells are arranged in such a manner that the unit cells are arranged at equal intervals in a central portion of the semiconductor device, and unit cells in which the impurity diffusion region is not formed are arranged in an outer peripheral portion. A semiconductor device according to 1.

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