JP4984170B2 - Mounting structure of optical semiconductor element - Google Patents

Description

  The present invention relates to an optical semiconductor device mounting structure, and more particularly to an optical module mounting structure used for optical communication, optical storage, and the like.

  FIG. 6 is a cross-sectional view of a conventional optical semiconductor element mounting structure described in Japanese Patent No. 2871320 “Semiconductor Laser Device” of Patent Document 1 and Japanese Patent Laid-Open No. 6-314857 “Semiconductor Light Emitting Device”. It is a figure and shows the mounting structure of the optical-semiconductor element used for the optical communication etc. of the comparatively short distance called CAN type (airtight sealing type).

An optical element 2 such as a light emitting element (laser diode LD, light emitting diode LED, etc.) or a light receiving element (photodiode PD, etc.) made of a compound semiconductor is mounted on a submount 41 made of ceramic or Si. Are connected to a metal base 44 which is a package housing. The optical element 2 is connected to the lead electrode 46 by a bonding wire 47. The lead electrode 46 is fixed by a metal base 44 and a low melting point glass 45 and hermetically sealed. A metal cap 43 having a lens 42 fixed at the center with low melting glass is disposed on the optical element 2, and the metal cap 43 is connected to the metal base 44 by resistance welding, so that the interior has a nitrogen atmosphere. An airtight sealing structure is formed.
Japanese Patent No. 2871320 JP-A-6-314857

The prior art as described above has the following drawbacks.
(1) The lens 42 is fixed to the center of the metal cap 43 using low melting point glass, and then the lead electrode 46 is fixed to the metal base 44, and further, the metal cap 43 is fixed to the metal base using resistance welding. By fixing to 44, the structure can be hermetically sealed, which takes time and cost.

  (2) Since the lead electrode 46 is used, it is overwhelmingly disadvantageous in terms of cost as compared with electric surface mounting based on a printed circuit board.

  (3) The optical path from the lens 42 fixed to the metal cap 43 to the optical element 2 was long, and the coupling efficiency with the optical fiber was not good.

  The present invention has been made in order to solve such a problem, and by performing hermetic sealing mounting of optical elements, which have required many processes, collectively on a wafer in a semiconductor pre-process, the present invention is inexpensive. It is an object of the present invention to provide a mounting structure for an optical semiconductor element that can realize a simple optical module and can obtain good coupling efficiency with an optical fiber.

The present invention comprises the following technical means in order to solve the above-mentioned problems .
The first technical means includes a first semiconductor substrate on which an electrical functional element is mounted, and a sealing structure that at least surrounds the electrical functional element is formed on the outer periphery using the wiring layer of the electrical functional element. And an optical element is mounted on the front surface facing the first semiconductor substrate or the back surface opposite to the first semiconductor substrate, and having a mirror-image symmetrical shape with the sealing structure of the first semiconductor substrate. A sealing structure having a second semiconductor substrate formed on the outer periphery of the front surface, and a sealing structure having a shape similar to the sealing structure of the first semiconductor substrate on the outer periphery of the back surface; An optical half having a cap substrate in which a sealing structure that is mirror-symmetrical to the sealing structure formed on the back surface side of the semiconductor substrate 2 is formed on the outer periphery of the surface, and a V-shaped groove for introducing an optical fiber is formed on the back surface. Guidance In the element mounting structure, a sealing structure of the first semiconductor substrate and a sealing structure of the front surface of the second semiconductor substrate, and a sealing structure of the back surface of the second semiconductor substrate and a sealing structure of the cap substrate Are bonded using eutectic alloy bonding or surface activated bonding.

According to a second technical means, in the semiconductor element mounting structure according to the first technical means, the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate, or the sealing of the first semiconductor substrate. When the structure and the sealing structure of the front surface of the second semiconductor substrate and the sealing structure of the back surface of the second semiconductor substrate and the sealing structure of the cap substrate are bonded by eutectic alloy bonding, InSn, SnBi , SnZn, SnAu, SnCu, or any eutectic alloy containing any of InSn, SnBi, SnZn, SnAu, SnCu, which is bonded by a eutectic alloy having a eutectic temperature of 300 ° C. or lower. It is characterized by.

According to a third technical means, in the semiconductor element mounting structure according to the first technical means, the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate, or the sealing of the first semiconductor substrate. When the structure and the sealing structure of the front surface of the second semiconductor substrate and the sealing structure of the back surface of the second semiconductor substrate and the sealing structure of the cap substrate are bonded by surface activation bonding, they are bonded to each other. Metals forming each sealing structure are bonded to each other.

According to a fourth technical means, in the optical semiconductor element mounting structure according to any one of the first to third technical means, the semiconductor element substrate or the optical element mounted on the first semiconductor substrate is provided. A microlens is formed at a position on the surface of the cap substrate that serves as an optical path.

According to a fifth technical means, in the optical semiconductor device mounting structure according to any one of the first to fourth technical means, the cap substrate is one of GaAs, InP, InAs, InSb, Si, and Ge, Alternatively, it is made of a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge.

Sixth technical means is the surface mounting bump on the back surface of the cap substrate or the back surface of the second semiconductor substrate in the optical semiconductor element mounting structure according to any one of the first to fifth technical means. Is formed.

According to a seventh technical means, in the optical semiconductor element mounting structure according to the sixth technical means, the bump is one of InSn, SnBi, SnZn, SnAu, SnCu, or InSn, SnBi, SnZn. Of eutectic alloys containing any one of SnAu and SnCu, the eutectic temperature is 300 ° C. or lower.

According to an eighth technical means, in the semiconductor element mounting structure according to any one of the first to seventh technical means, the semiconductor element substrate, or the first semiconductor substrate and the second semiconductor substrate are , GaAs, InP, InAs, InSb, Si, Ge, or a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, Ge.

According to a ninth technical means, in the semiconductor element mounting structure according to any one of the first to eighth technical means, the wiring layer comprises a plurality of wiring layers and insulates the wiring layers. Is made of any one of polyimide, benzocyclobutene (BCB), polysiloxane, parylene, and epoxy resin.

According to the optical semiconductor element mounting structure of the present invention, the following effects can be obtained.
(1) To increase the number of process steps by creating a metal sealing structure by diverting a wiring layer used for wiring of an optical element or an electric functional element on a semiconductor element substrate or first and second semiconductor substrates. The sealing structure that surrounds the optical element and the electric functional element can be manufactured. Further, a deep cavity structure can be produced by increasing the number of wiring layers and laminating the sealing structure in multiple layers.

  (2) Since the process temperature at the time of mounting is kept low at 300 ° C. or lower, even when a compound semiconductor functional element is used, it is possible to mount without impairing the characteristics of the semiconductor functional element.

  (3) Since the optical element and the electric functional element are arranged in a narrow cavity formed by the cap substrate, the semiconductor substrate, and the wiring layer, the optical path between the optical fiber and the optical element can be shortened. Good coupling efficiency with the element can be obtained.

  (4) Furthermore, since a microlens can be manufactured by adding a minimum number of process steps, it is possible to obtain better coupling efficiency between an optical fiber and an optical element.

  Hereinafter, an example of the best embodiment of the optical semiconductor device mounting structure according to the present invention will be described in detail with reference to the drawings.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention relates to an optical semiconductor element mounting structure that can be suitably applied as a hermetically sealed wafer level package technology for a compound semiconductor chip on which an optical element is mounted. Metal sealing that surrounds the optical and electrical functional elements on the outer periphery of the semiconductor element substrate on which the optical and electrical functional elements are mounted and on which two or more multilayer wiring layers are formed. While providing a structure, a cap structure having a V-shaped groove for introducing an optical fiber on the back surface is provided with a sealing structure that is mirror-symmetrical to the sealing structure on the semiconductor element substrate, and on the semiconductor element substrate. The sealing structure and the sealing structure of the cap substrate are opposed to each other and bonded using a eutectic alloy having a eutectic temperature of 300 ° C. or lower, or directly bonded by surface activated bonding.

  That is, the present invention has the following four major features as a hermetically sealed wafer level package mounting structure for an optical module.

  (1) For hermetic sealing, a metal sealing structure surrounding at least an optical element and an electric functional element is produced on the outer peripheral portion of a semiconductor element substrate by diverting a multilayer wiring layer without adding an additional process. As a result, a mounting structure with a deep cavity is realized. A sealing structure having a mirror image shape and a sealing structure of the semiconductor element substrate is also formed on the cap substrate, and hermetic sealing is realized by bonding the sealing structures of both substrates together.

  (2) In order to keep the process temperature at the time of mounting and assembly low, a eutectic temperature of 300 ° C. or lower is used for bonding between the sealing structures of the semiconductor element substrate on which the optical element or the electric functional element is mounted and the cap substrate. Eutectic alloy bonding using an alloy or surface activated bonding that directly bonds the sealing structures is used.

  (3) The cap substrate is provided with a V-shaped groove for introducing an optical fiber, thereby ensuring passive alignment of the optical coupling portion.

  (4) Furthermore, when it is necessary to improve the coupling efficiency between the optical element and the optical fiber, a microlens is disposed on the surface of the cap substrate.

( First reference example )
FIG. 1 is a schematic diagram showing a cross-sectional structure of an optical semiconductor element illustrating a mounting structure of an optical semiconductor element according to a first reference example, and shows a state in which the semiconductor element substrate 1 is to be bonded to a cap substrate 31. Yes. 2 is a perspective view of the mounting structure of the optical semiconductor element illustrated in FIG. 1, and shows a state in which the semiconductor element substrate 1 is to be bonded to the cap substrate 31 as in FIG.

  1 and 2, the semiconductor element substrate 1 is made of any one of GaAs, InP, InAs, InSb, Si, and Ge, or a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge. It has become. On the semiconductor element substrate 1, an epitaxial layer directly grown on the semiconductor element substrate 1 or an epitaxial layer formed by pressure bonding and bonding a thin film grown on a third substrate and peeled off. The optical element 2 and the electric functional element 3 are manufactured using the above.

  On the semiconductor element substrate 1, a multilayer wiring layer is produced for internal connection, interconnection, etc. of the optical element 2 and / or the electric functional element 3. FIG. 1 shows an example of a three-layer wiring layer including a first wiring layer 4, a second wiring layer 6, and a third wiring layer 8. The first wiring layer 4, the second wiring layer 6, and the third wiring layer 8 are made of any one of Au, Cu, Al, W, and Mo, or Au, Cu, Al, W, and Mo. It is made of an alloy containing it.

  Between the first wiring layer 4 and the second wiring layer 6, a first-second wiring interlayer insulating film 10 is provided, and between the second wiring layer 6 and the third wiring layer 8. The second to third wiring interlayer insulating films 11 are inserted into the gate electrode. The first-second wiring interlayer insulating film 10 and the second-third wiring interlayer insulating film 11 are made of polyimide, benzocyclobutene (BCB), polysiloxane, which are organic materials that can be easily thickened. It consists of paralene and epoxy resin.

  The first and second wiring interlayer vias 5 that connect the first wiring layer 4 and the second wiring layer 6, and the second and second wiring layers 6 and 8 that connect the second wiring layer 6 and the third wiring layer 8. The third wiring interlayer via 7 is made of any one of Au, Cu, Al, and W, or an alloy containing any of Au, Cu, Al, and W.

  In the outer peripheral portion on the semiconductor element substrate 1, the first wiring layer 4, the second wiring layer 6, the third wiring layer 8, the first to second wiring interlayer vias 5, and the second to third wirings are provided. A sealing structure 9 is formed in a multilayer (three layers in the case of FIG. 1) for hermetic sealing using the interlayer via 7. As shown in FIGS. 1 and 2, the sealing structure 9 is formed in a square frame shape (ring shape) or the like so as to surround the optical element 2 and the electrical functional element 3 on the semiconductor element substrate 1. The width is about 10 to 200 μm.

  The uppermost wiring layer (third wiring layer 8 in the case of FIG. 1) exposes the wiring metal. However, if necessary, it is oxidized with Au or the like to prevent oxidation of the wiring metal surface. It may be covered with a difficult metal. Further, for the purpose of strengthening the connection with the cap substrate 31, a third wiring layer for connection with the cap substrate 31 side may be disposed at a place other than the sealing structure 9.

  The cap substrate 31 is made of a semiconductor such as GaAs, InP, InAs, InSb, Si, Ge, or a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, Ge. For example, when Si is used as the cap substrate 31, it is desirable to use a high resistance substrate with low high-frequency loss.

  As shown in FIG. 1 and FIG. 2, a sealing structure 34 that is mirror-symmetrical with the sealing structure 9 of the semiconductor element substrate 1 is one of Au, Cu, Al, and W, as shown in FIGS. Alternatively, the surface wiring layer 33 using an alloy containing any of Au, Cu, Al, and W is used. A eutectic alloy metal 32 is deposited on the surface wiring layer 33 forming the sealing structure 34 for eutectic alloy bonding with the semiconductor element substrate 1 side.

  The eutectic alloy metal 32 includes InSn (eutectic temperature of 117 ° C.), SnBi (eutectic temperature of 139 ° C.), SnZn (eutectic temperature of 198 ° C.), SnAu (eutectic temperatures of 217 ° C. and 280 ° C.), SnCu (eutectic crystal). Or a eutectic alloy having any of InSn, SnBi, SnZn, SnAu, and SnCu, and having a eutectic temperature of 300 ° C. or lower. Yes. SnAu (eutectic temperature: 217 ° C., 280 ° C.) may be one described in Japanese Patent No. 3640017 “Lead-free solder bumps and formation method thereof”.

  The front surface wiring layer 33 of the cap substrate 31 is connected to the back surface wiring layer 36 on the back surface side of the cap substrate 31 through the substrate through via 35. Through this backside wiring layer 36, transmission / reception of high-frequency signals from the outside, application of a DC bias, sharing of a ground potential, and the like are performed.

  In addition, bonding bumps 37 are formed on the back wiring layer 36 to enable surface mounting of a printed circuit board or the like. Similarly to the eutectic alloy metal 32, the bump 37 is also InSn (eutectic temperature 117 ° C.), SnBi (eutectic temperature 139 ° C.), SnZn (eutectic temperature 198 ° C.), SnAu (eutectic temperatures 217 ° C., 280 ° C.). , SnCu (eutectic temperature 227 ° C.), or any eutectic alloy containing any one of InSn, SnBi, SnZn, SnAu, SnCu, and the like. It is formed using. SnAu (eutectic temperature: 217 ° C., 280 ° C.) may be one described in Japanese Patent No. 3640017 “Lead-free solder bumps and formation method thereof”.

  Further, as shown in FIGS. 1 and 2, a V-shaped V-shaped groove 39 is provided on the back surface of the cap substrate 31 by utilizing the crystal orientation of the substrate for introducing the optical fiber. Passive alignment is possible. Further, in order to improve the coupling efficiency between the optical fiber and the optical element 2, the surface of the cap substrate 31 serving as an optical path to the optical element 2 is formed with a diameter of 10 to 500 μm by a UV curable resin such as acrylic or epoxy. The micro lens 38 is formed.

  The semiconductor element substrate 1 and the cap substrate 31 are portions of the sealing structure 9 on the semiconductor element substrate 1 side and the sealing structure 34 on the cap substrate 31 side, and the wiring metals forming the respective sealing structures are InSn, Eutectic alloy bonding using eutectic alloy metal 32 having a eutectic temperature of 300 ° C. or lower among any one of SnBi, SnZn, SnAu, SnCu, etc., or a eutectic alloy containing any of these. By doing so, the airtightness around the optical element 2 and the electric functional element 3 is secured.

  Here, the bonding between the semiconductor element substrate 1 and the cap substrate 31 is not performed by using a eutectic alloy as described above, but “low energy bonding by surface activation” (Yuji Suga, Matria, 35 (5), 476 (1996)), and surface activated bonding (SAB) can also be used.

  In the case of surface activation bonding, the surfaces to be bonded to each other of the two substrates to be bonded are etched by irradiating an Ar ion beam or the like in a vacuum, and then activated metals (Au—Au, Cu—Cu). , Al-Al, Au-Cu, etc.) are directly joined. When surface activated bonding is used, it is not necessary to deposit the eutectic alloy metal 32 on the sealing structure 34 of the cap substrate 31, that is, the surface wiring layer 33.

  When surface activated bonding is used, the uppermost wiring layer (third wiring layer 8 in the case of FIG. 1) constituting the sealing structure 9 of the semiconductor element substrate 1 and the sealing structure 34 of the cap substrate 31 are formed. It is desirable to form each material with the surface wiring layer 33 using the same metal material (the same metal material among Au, Cu, Al, W, etc.), and to join the same metal materials.

( First embodiment)
Next, a first embodiment of an optical semiconductor element mounting structure according to the present invention will be described with reference to FIG. FIG. 3 is a schematic diagram showing a cross-sectional structure of an optical semiconductor device illustrating the first embodiment as a mounting structure of the optical semiconductor device according to the present invention.

The optical semiconductor element mounting structure shown in FIG. 3 is the same as that in the first reference example in that the optical element 2 and the electric functional element 3 are respectively formed on separate semiconductor substrates. The semiconductor element mounting structure is different from the semiconductor element mounting structure of the semiconductor element substrate 1 (first semiconductor substrate) on which the electric functional element 3 is mounted, the second semiconductor substrate 21 on which the optical element 2 is mounted, and the cap substrate 31. It has a three-substrate configuration. The mounting structure of the first embodiment is an effective mounting structure when the manufacturing process of the optical element 2 and the electric functional element 3 is not compatible.

The semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21 are any of GaAs, InP, InAs, InSb, Si, and Ge, similar to the semiconductor element substrate 1 in the first reference example . Alternatively, it is made of a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge.

In the case of the mounting structure shown in FIG. 3, the electrical functional element 3 is formed on the semiconductor element substrate 1 (first semiconductor substrate) as in the case of FIG. 1 in the first reference example , and the semiconductor element substrate 1 The upper peripheral portion includes a first wiring layer 4, a second wiring layer 6, a third wiring layer 8, a first to second wiring interlayer via 5, and a second to third wiring interlayer via 7. Is used to form a metal sealing structure 9 for hermetic sealing so as to surround the electrical functional element 3.

The uppermost wiring layer (in the case of FIG. 3, the third wiring layer 8) of the semiconductor element substrate 1 (first semiconductor substrate) is also similar to the case of FIG. 1 in the first reference example . Although the wiring metal is exposed, if necessary, it may be coated with a metal that is difficult to oxidize, such as Au, in order to prevent oxidation of the surface of the wiring metal.

The cap substrate 31 also has the same structure as that of FIG. 1 of the first reference example . The sealing structure 34 using the microlens 38 and the surface wiring layer 33 is formed on the front surface, and the back surface side has the back surface. A wiring layer 36 and a bump 37 are formed, and a V-shaped groove 39 for introducing an optical fiber is formed.

On the other hand, unlike the case of FIG. 1 in the first reference example , the optical element 2 is not on the semiconductor element substrate 1 (first semiconductor substrate) on which the electric functional element 3 is formed, but on the semiconductor element substrate 1 and the cap. It is formed on the back surface of the second semiconductor substrate 21 interposed between the substrate 31 (on the surface facing the cap substrate 31 but not facing the semiconductor element substrate 1).

  Further, a sealing structure 24 having a mirror image symmetry with the sealing structure 9 of the semiconductor element substrate 1 is formed on the outer peripheral portion of the surface of the second semiconductor substrate 21 (the surface facing the semiconductor element substrate 1). . Similar to the sealing structure 9 of the semiconductor element substrate 1 (first semiconductor substrate), the sealing structure 24 of the second semiconductor substrate 21 is either Au, Cu, Al, or W, or Au, Cu, Al, W. It is formed using the surface wiring layer 23 using an alloy containing any of the above. A eutectic alloy metal 22 is deposited on the surface wiring layer 23 forming the sealing structure 24 for eutectic alloy bonding with the semiconductor element substrate 1 (first semiconductor substrate) side.

  The eutectic alloy metal 22 is composed of InSn (eutectic temperature 117 ° C.), SnBi (eutectic temperature 139 ° C.), SnZn (eutectic temperature 198 ° C.), SnAu (eutectic temperatures 217 ° C., 280 ° C.), SnCu (eutectic crystal). Or a eutectic alloy having any of InSn, SnBi, SnZn, SnAu, and SnCu, and having a eutectic temperature of 300 ° C. or lower. Yes. SnAu (eutectic temperature: 217 ° C., 280 ° C.) may be one described in Japanese Patent No. 3640017 “Lead-free solder bumps and formation method thereof”.

  For the purpose of strengthening the connection between the semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21, the sealing structure 9 of the semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate A third wiring layer for connection or a surface wiring layer may be arranged at a place on each substrate other than the sealing structure 24 of 21.

Further, on the outer peripheral portion of the back surface of the second semiconductor substrate 21 (the opposite surface not facing the semiconductor element substrate 1 and facing the cap substrate 31), the semiconductor element substrate 1 (first 1 from the back wiring layer 25 forming a sealing structure having the same shape as that of FIG. 1 of the first reference example (a shape that is mirror-symmetric with the sealing structure 9 of the semiconductor element substrate 1). A back surface wiring layer 25 forming a sealing structure having a mirror image symmetry with the sealing structure 34 on the cap substrate 31 is disposed, and the back surface wiring layer 25 is provided so as to penetrate the second semiconductor substrate 21. It is connected to the surface wiring layer 23 by the through-substrate via 26.
The surface of the second semiconductor substrate 21 on which the optical element 2 is formed is disposed opposite to the semiconductor element substrate 1 (first semiconductor substrate) on which the electrical functional element 3 is formed, and the semiconductor element substrate 1 (first semiconductor substrate) is disposed. The eutectic alloy metal 22 deposited on the surface wiring layer 23 of the second semiconductor substrate 21 is used for the sealing structure 9 on the outer periphery of the substrate) and the sealing structure 24 on the outer periphery of the surface of the second semiconductor substrate 21. Joined by eutectic alloy joining. Furthermore, using the back surface wiring layer 25 on the back surface side of the second semiconductor substrate 21, the second semiconductor substrate 21 formed on the outer periphery of the back surface in the same shape as the semiconductor element substrate 1 (first semiconductor substrate). The sealing structure and the second semiconductor substrate 21 are arranged so as to face the back side, and have the same shape as that of FIG. 1 of the first reference example (a shape that is mirror-symmetric with the sealing structure 9 of the semiconductor element substrate 1), that is, The sealing structure on the back surface side of the semiconductor substrate 21 and the sealing structure 34 on the outer periphery of the cap substrate 31 having a mirror image symmetry are deposited on the surface wiring layer 33 forming the sealing structure 34 of the cap substrate 31. Bonding is performed by eutectic alloy bonding using the crystal alloy metal 32.

Also in the first embodiment, the sealing structures of the semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21 are joined together, and the sealing structures of the second semiconductor substrate 21 and the cap substrate 31 are joined together. The eutectic alloy metals 22 and 32 having a eutectic temperature of 300 ° C. or lower among any one of InSn, SnBi, SnZn, SnAu, SnCu, or a eutectic alloy containing any of these. By using eutectic alloy bonding, it is possible to obtain the same airtightness as in the case of the first reference example with a chip level size.

Here, the bonding between the semiconductor element substrate 1 (first semiconductor substrate) and the front surface side of the second semiconductor substrate 21 and the bonding between the back surface side of the second semiconductor substrate 21 and the cap substrate 31 are performed according to the first reference. As in the case of the example , it is also possible to use surface activated bonding without using eutectic alloy bonding.

  When surface activated bonding is used, bonding between the sealing structure of the semiconductor element substrate 1 (first semiconductor substrate) and the sealing structure of the surface of the second semiconductor substrate 21, and sealing structure of the back surface of the second semiconductor substrate 21 In joining with the sealing structure of the cap substrate 31, metals (Au—Au, Cu—Cu, Al—Al, Au—Cu, etc.) forming the respective sealing structures to be joined together are directly joined, but the sealing to join each other. It is desirable that the metal material forming each structure is made of the same metal material (the same metal material among Au, Cu, Al, W, etc.).

( Second Embodiment)
Next, a second embodiment of the optical semiconductor element mounting structure according to the present invention will be described with reference to FIG. FIG. 4 is a schematic view showing a cross-sectional structure of an optical semiconductor element illustrating the second embodiment as a mounting structure of the optical semiconductor element according to the present invention.

The optical semiconductor element mounting structure shown in FIG. 4 is similar to that of the first embodiment in that the optical element 2 and the electrical functional element 3 are respectively fabricated on separate semiconductor substrates . The semiconductor device mounting structure of FIG. 1 and FIG. 2 in the reference example 1 is different. Therefore, the mounting structure of the second embodiment is also an effective mounting structure when the manufacturing process of the optical element 2 and the electric functional element 3 is not compatible, as in the case of the first embodiment.

The optical semiconductor element mounting structure shown in FIG. 4 is the same as the semiconductor element of FIG. 3 in the first embodiment in that the optical element 2 and the electric functional element 3 are respectively formed on separate semiconductor substrates. The mounting structure is the same as that of the semiconductor device substrate 1, the semiconductor element substrate 1 (first semiconductor substrate) on which the electric functional element 3 is mounted, the second semiconductor substrate 21 on which the optical element 2 is mounted, and the cap substrate 31. Has been.

The semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21 are any of GaAs, InP, InAs, InSb, Si, and Ge, similar to the semiconductor element substrate 1 in the first reference example . Alternatively, it is made of a mixed crystal containing any of GaAs, InP, InAs, InSb, Si, and Ge.

However, in the optical semiconductor element mounting structure shown in FIG. 4, the optical element 2 is not on the back surface of the second semiconductor substrate 21 (the surface facing the cap substrate 31), but on the surface of the second semiconductor substrate 21. The mounting of the semiconductor device of FIG. 3 in the first embodiment in that it is disposed so as to face the electric functional device 3 formed on the semiconductor device substrate 1 (first semiconductor substrate). The structure is different from the structure.

In the second embodiment, since light is incident from the back surface of the optical element 2, a larger opening can be ensured than in the case of front surface incidence.

Also in the second embodiment, the sealing structures of the semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21 are bonded to each other, and the sealing structures of the second semiconductor substrate 21 and the cap substrate 31 are bonded to each other. The eutectic alloy metals 22 and 32 having a eutectic temperature of 300 ° C. or lower among any one of InSn, SnBi, SnZn, SnAu, SnCu, or a eutectic alloy containing any of these. By using eutectic alloy bonding, it is possible to obtain the same airtightness as in the case of the first reference example and the first embodiment at the chip level size.

Here, the bonding between the semiconductor element substrate 1 (first semiconductor substrate) and the front surface side of the second semiconductor substrate 21 and the bonding between the back surface side of the second semiconductor substrate 21 and the cap substrate 31 are performed according to the first reference. As in the case of the example , it is also possible to use surface activated bonding without using eutectic alloy bonding.

  When surface activated bonding is used, bonding between the sealing structure of the semiconductor element substrate 1 (first semiconductor substrate) and the sealing structure of the surface of the second semiconductor substrate 21, and sealing structure of the back surface of the second semiconductor substrate 21 In joining with the sealing structure of the cap substrate 31, metals (Au—Au, Cu—Cu, Al—Al, Au—Cu, etc.) forming the respective sealing structures to be joined together are directly joined, but the sealing to join each other. It is desirable that the metal material forming each structure is made of the same metal material (the same metal material among Au, Cu, Al, W, etc.).

( Second reference example )
Next, the mounting structure of the optical semiconductor element according to the second reference example will be described with reference to FIG. FIG. 5 is a schematic diagram illustrating a cross-sectional structure of an optical semiconductor element illustrating the mounting structure of the optical semiconductor element according to the second reference example .

In the optical semiconductor element mounting structure shown in FIG. 5, the optical element 2 and the electric functional element 3 are respectively formed on separate semiconductor substrates, and the optical element 2 is mounted on the surface of the second semiconductor substrate 21. The semiconductor element mounting structure of FIG. 4 in the second embodiment is that the electric functional element 3 formed on the semiconductor element substrate 1 (first semiconductor substrate) is opposed to the electric functional element 3. The structure is different from the mounting structure of the semiconductor device of FIG. 4 in the second embodiment in that the cap substrate 31 is not provided and the microlens 38 formed on the cap substrate 31 is not provided. It is said that.

As shown in FIG. 5, the present on the back surface of the second semiconductor substrate 21 in the second reference example, the first reference example, Fig. 1 illustrated as a second embodiment, in FIG. 4, the cap An optical fiber introducing V-shaped groove 39 formed on the back side of the substrate 31 is formed using the crystal orientation of the second semiconductor substrate 21 and penetrates through the second semiconductor substrate 21. The back surface wiring layer 25 connected to the front surface wiring layer 23 by the provided through-substrate via 26 is the back surface wiring layer 36 of the cap substrate 31 in FIGS. 1 and 4 illustrated as the first reference example and the second embodiment. It is formed in the same shape.

Through this backside wiring layer 25, transmission / reception of high-frequency signals from the outside, application of a DC bias, sharing of a ground potential, and the like are performed. On the back surface wiring layer 25, as in the case of the back surface wiring layer 36 of the cap substrate 31 in FIGS. 1 and 4 illustrated as the first reference example and the second embodiment, bonding bumps 37 are formed. Formed, enabling surface mounting of printed circuit boards and the like.

As in the case of the cap substrate 31 in FIG. 1 exemplified as the first reference example , the bump 37 is made of InSn (eutectic temperature 117 ° C.), SnBi (eutectic temperature 139 ° C.), SnZn (eutectic temperature 198 ° C.), Of any one of SnAu (eutectic temperature 217 ° C., 280 ° C.), SnCu (eutectic temperature 227 ° C.), etc., or among eutectic alloys containing any of InSn, SnBi, SnZn, SnAu, SnCu, It is formed using a eutectic alloy having a crystallization temperature of 300 ° C. or lower. SnAu (eutectic temperature: 217 ° C., 280 ° C.) may be one described in Japanese Patent No. 3640017 “Lead-free solder bumps and formation method thereof”.

In the second reference example , since the light is incident from the back surface of the optical element 2, a larger opening can be secured than in the case of the front surface incidence. However, good coupling efficiency between the optical fiber and the optical element 2 can be obtained.

Also in the second reference example , the bonding between the sealing structures of the semiconductor element substrate 1 (first semiconductor substrate) and the second semiconductor substrate 21 is any of InSn, SnBi, SnZn, SnAu, SnCu, and the like. Among them, among eutectic alloys containing any of these, the eutectic alloy metal 22 having a eutectic temperature of 300 ° C. or lower is used to join the eutectic alloy to obtain a chip-level size . It is possible to obtain the same airtightness as in the case of the first reference example, the first embodiment, and the second reference example .

Here, the bonding between the surface of the semiconductor element substrate 1 (first semiconductor substrate) and the surface of the second semiconductor substrate 21 is the same as in the case of the first reference example , and surface activation is performed without using bonding with a eutectic alloy. It is also possible to use chemical bonding.

  When surface activated bonding is used, in the bonding of the sealing structure of the semiconductor element substrate 1 (first semiconductor substrate) and the sealing structure of the surface of the second semiconductor substrate 21, the metals forming the respective sealing structures bonded to each other (Au—Au, Cu—Cu, Al—Al, Au—Cu, etc.) are directly joined, but the metal materials forming the respective sealing structures to be joined together are the same metal materials (Au, Cu, Al, W, etc.) Of these, the same metal material is desirable.

(Operational effect of the present invention)
As described above, the use of the optical semiconductor element mounting structure of the present invention produces the following operational effects.

  (1) To increase the number of process steps by creating a metal sealing structure by diverting a wiring layer used for wiring of an optical element or an electric functional element on a semiconductor element substrate or first and second semiconductor substrates. The sealing structure that surrounds the optical element and the electric functional element can be manufactured. Further, a deep cavity structure can be produced by increasing the number of wiring layers and laminating the sealing structure in multiple layers.

  (2) Since the process temperature at the time of mounting is kept low at 300 ° C. or lower, even when a compound semiconductor functional element is used, it is possible to mount without impairing the characteristics of the semiconductor functional element.

  (3) Since the optical element and the electric functional element are arranged in a narrow cavity formed by the cap substrate, the semiconductor substrate, and the wiring layer, the optical path between the optical fiber and the optical element can be shortened. Good coupling efficiency with the element can be obtained.

  (4) Furthermore, since a microlens can be produced on the cap substrate (by using a UV curable resin such as acrylic or epoxy) with a minimum number of process steps, the optical fiber and the optical element can be further reduced. Good coupling efficiency can be obtained.

It is a schematic diagram which shows the cross-section of the optical semiconductor element which illustrates the mounting structure of the optical semiconductor element which concerns on a 1st reference example . It is a perspective view of the mounting structure of the optical semiconductor element illustrated in FIG. 1 is a schematic diagram illustrating a cross-sectional structure of an optical semiconductor element illustrating a first embodiment as a mounting structure of an optical semiconductor element according to the present invention. FIG. 6 is a schematic diagram showing a cross-sectional structure of an optical semiconductor element illustrating a second embodiment as an optical semiconductor element mounting structure according to the present invention. It is a schematic diagram which shows the cross-section of the optical semiconductor element which illustrates the mounting structure of the optical semiconductor element which concerns on a 2nd reference example . It is a schematic diagram which shows the cross-section of the optical semiconductor element mounting of a prior art example.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor element board | substrate (1st semiconductor substrate), 2 ... Optical element (light reception or light emitting element), 3 ... Electric functional element, 4 ... 1st wiring layer, 5 ... 1st-2nd wiring interlayer via, 6 ... 2nd wiring layer, 7 ... 2nd-3rd wiring interlayer via, 8 ... 3rd wiring layer, 9 ... Sealing structure, 10 ... 1st-2nd wiring interlayer insulation film, 11 ... 2nd -Third wiring interlayer insulating film, 21 ... second semiconductor substrate, 22 ... eutectic alloy metal (second semiconductor substrate eutectic alloy metal), 23 ... surface wiring layer (second semiconductor substrate surface wiring layer) , 24 ... sealing structure (second semiconductor substrate sealing structure), 25 ... backside wiring layer (second semiconductor substrate backside wiring layer), 26 ... substrate through via (second semiconductor substrate through via), 31 ... cap substrate 32 ... Eutectic alloy metal, 33 ... Surface wiring layer (wiring layer on the cap substrate), 34 ... Sealing Structure (sealing structure on cap substrate), 35 ... Substrate through via (cap substrate through via), 36 ... Back wiring layer (cap substrate back wiring layer), 37 ... Bump, 38 ... Micro lens, 39 ... V-shaped groove (light Fiber guide groove), 41 ... submount, 42 ... lens, 43 ... metal cap, 44 ... metal base, 45 ... low melting glass, 46 ... lead electrode, 47 ... bonding wire.

Claims (9)

  An electrical functional element is mounted, and a first semiconductor substrate having a sealing structure that surrounds at least the electrical functional element is formed on the outer periphery using a wiring layer of the electrical functional element, and an optical element is provided The first semiconductor substrate is mounted on the surface facing the first semiconductor substrate or on the back surface opposite to the first semiconductor substrate, and the sealing structure having a mirror image shape with respect to the sealing structure of the first semiconductor substrate is an outer peripheral portion of the surface. And a second semiconductor substrate in which a sealing structure having the same shape as the sealing structure of the first semiconductor substrate is formed on the outer periphery of the back surface, and the back surface side of the second semiconductor substrate. An optical semiconductor device mounting structure having a cap substrate having a V-groove for introducing an optical fiber formed on the back surface is produced on the outer peripheral portion of the front surface, and a sealing structure having a mirror image symmetry with the sealing structure formed on A sealing structure of the first semiconductor substrate and a sealing structure of the front surface of the second semiconductor substrate, and a sealing structure of the back surface of the second semiconductor substrate and a sealing structure of the cap substrate. A mounting structure of an optical semiconductor element, characterized in that bonding is performed using crystal alloy bonding or surface activated bonding. 2. The semiconductor element mounting structure according to claim 1 , wherein the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate, or the sealing structure of the first semiconductor substrate and the surface of the second semiconductor substrate. When the sealing structure of the back surface of the second semiconductor substrate and the sealing structure of the cap substrate are bonded by eutectic alloy bonding, any one of InSn, SnBi, SnZn, SnAu, SnCu Of these, or a eutectic alloy containing any one of InSn, SnBi, SnZn, SnAu, and SnCu, the semiconductor element mounting structure is bonded by a eutectic alloy having a eutectic temperature of 300 ° C. or lower. 2. The semiconductor element mounting structure according to claim 1 , wherein the sealing structure of the semiconductor element substrate and the sealing structure of the cap substrate, or the sealing structure of the first semiconductor substrate and the surface of the second semiconductor substrate. When the sealing structure of the back surface of the second semiconductor substrate and the sealing structure of the cap substrate are bonded by surface activated bonding, the metals forming the sealing structures bonded to each other are bonded to each other. A mounting structure of a semiconductor element, wherein: 4. The optical semiconductor element mounting structure according to claim 1 , wherein the surface of the cap substrate is an optical path to the optical element mounted on the semiconductor element substrate or the first semiconductor substrate. 5. A mounting structure of an optical semiconductor element, wherein a microlens is formed. 5. The optical semiconductor device mounting structure according to claim 1 , wherein the cap substrate is one of GaAs, InP, InAs, InSb, Si, and Ge, or GaAs, InP, InAs, InSb, and Si. A structure for mounting an optical semiconductor element comprising a mixed crystal containing any one of Ge and Ge. 6. The optical semiconductor element mounting structure according to claim 1 , wherein bumps for surface mounting are formed on the back surface of the cap substrate or the back surface of the second semiconductor substrate. Semiconductor element mounting structure. 7. The optical semiconductor device mounting structure according to claim 6 , wherein the bump includes any one of InSn, SnBi, SnZn, SnAu, SnCu, or any one of InSn, SnBi, SnZn, SnAu, SnCu. An optical semiconductor element mounting structure comprising a eutectic alloy having a eutectic temperature of 300 ° C. or lower among crystal alloys. 8. The semiconductor element mounting structure according to claim 1 , wherein the semiconductor element substrate or the first semiconductor substrate and the second semiconductor substrate are made of GaAs, InP, InAs, InSb, Si, A mounting structure of an optical semiconductor element comprising a mixed crystal containing any one of Ge, or any of GaAs, InP, InAs, InSb, Si, and Ge. 9. The semiconductor element mounting structure according to claim 1 , wherein the wiring layer includes a plurality of wiring layers, and the wiring interlayer insulating film that insulates the wiring layers is made of polyimide, benzocyclobutene (BCB). ), Polysiloxane, parylene, or epoxy resin, a semiconductor device mounting structure.

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