JP4983359B2 - Imaging apparatus and imaging method - Google Patents

Description

  The present invention relates to an imaging apparatus and an imaging method including a solid-state imaging device that outputs signal charges for one horizontal line in a predetermined arrangement order different from the arrangement order of pixels on a photosensitive surface.

  Conventionally, a CCD is often used as an image pickup device in an image pickup apparatus such as a digital camera. In such a CCD, by normally transferring the charge signals of pixels on the same line arranged in the pixel arrangement order to the horizontal transfer path one line at a time, sweeping it out using one horizontal synchronization signal, and repeating it The information of all pixels is output in a state where the pixel arrangement order is maintained.

  In addition, as a technique for reading an image pickup signal from the CCD, for example, a color filter of an adjacent color in the vertical direction is arranged for the purpose of shortening the processing time of the image pickup signal output from the CCD at the time of moving image shooting. A method of reading out signal charges of a plurality of pixels by adding (mixing) them in the CCD and a CCD that enables this are known (see, for example, Patent Document 1 below).

JP-A-9-18792

  By the way, in recent years, in order to enable a series of processing based on pixel data read out by pixel addition to be performed at high speed, the signal charge of each pixel on the same horizontal line added inside the CCD is photosensitive. A CCD having a specific structure that is driven in a sweeping manner while maintaining the actual arrangement order on the horizontal line of the surface has been considered.

  However, in the CCD having the above specific structure, when the signal charges of all the pixels are read without being added, it is necessary to sweep out the signal charges of each pixel on the same horizontal line at a plurality of horizontal synchronization timings. As a result, the image signal for one horizontal line output from the CCD is composed of signal charges in an arrangement order different from the actual pixel arrangement, and various image processing is performed on the read image signal. There was a problem that the data processing at the time became complicated.

  The present invention has been made in view of such a conventional problem, and is a case where a solid-state imaging device that outputs signal charges for one horizontal line in a predetermined arrangement order different from the arrangement order of pixels on the photosensitive surface is used. However, an object of the present invention is to provide an imaging apparatus and an imaging method capable of efficiently performing various image processing on an imaging signal.

In order to solve the above-mentioned problem, in the imaging apparatus according to the first aspect of the present invention, pixels made of photoelectric conversion elements are two-dimensionally arranged, and signal charges of these pixels are set to a predetermined number for each horizontal line. A solid-state imaging device that is grouped as a unit and outputs the signal charges of each group in units of the predetermined number in a predetermined arrangement order divided into a plurality of divided line signals, and from the solid-state imaging device, the predetermined charge conversion means for converting a signal charge of the picture element which in the sorted Ru are sequentially output to the pixel data, storage means for storing the pixel data converted by the converting means, the pixel data converted by said converting means said A write address used when stored in the storage means, and each pixel data having the predetermined arrangement order is moved forward in the same arrangement order as the arrangement order on the photosensitive surface of the solid-state imaging device. A write address for storing in the memory means, based on the group order on a horizontal line in the output order of the division line signals, group to which each pixel data is included the corresponding pixels each pixel data corresponding It is characterized by comprising: an address acquisition means for acquiring; and a storage control means for storing the pixel data converted by the conversion means in the storage means in accordance with the write address acquired by the address acquisition means.

Further, in the imaging apparatus according to the second aspect of the present invention, the solid-state imaging device, and outputs the signal charges of the pixels in the horizontal lines each at a predetermined arrangement order, and the converting means, the solid converting the predetermined arrangement order in the signal charges of the picture element that will be output for every horizontal line from the element successive pixel data, the storage means stores one horizontal line pixel data converted by said converting means The address acquisition means acquires the write address of pixel data for one horizontal line converted by the conversion means.

In the image pickup apparatus according to the third aspect of the present invention, the address acquisition unit is a prescribed offset position corresponding to both the arbitrary output rank and the arbitrary group rank, and each pixel Offset position storage means for storing offset data indicating the position of each pixel corresponding to the data in the group, first count means for counting the output order, and repeating the group order in units of a predetermined number of groups A second counting means for counting, a base address generating means for generating a base address corresponding to the number of repetitions of the counting of the group order by the second counting means, which serves as a reference for the writing address of each pixel data; a position indicated by offset data stored in the offset position storage means, said first counting means And the pixel position corresponding to each pixel data and the offset position corresponding to the output rank counted by the second counting means, the offset position corresponding to the group order counted by the second counting means, and the base address generated by the base address generating means. Adding means for adding a group head position, which is a position within the horizontal line of the head pixel of the group, wherein the storage control means adds the pixel data converted by the conversion means to the addition means of the address acquisition means According to the write address which is the addition result of the above, it is stored in the storage means.

In the image pickup apparatus according to the fourth aspect of the present invention, the driving mode of the solid-state image sensor is a pixel addition mode for reading out the signal charges of a plurality of pixels, or the signal charges of all the pixels. Drive mode setting means for setting to an all-pixel readout mode for reading without adding, and drive mode determination means for determining the drive mode of the solid-state imaging device set by the drive mode setting means, the address acquisition Means for storing the pixel data converted by the conversion means in the storage means when the drive mode determination means determines that the drive mode of the solid-state imaging device is the all-pixel read mode; Each pixel data having the predetermined arrangement order is the same as the arrangement order on the photosensitive surface of the solid-state imaging device. In and acquires the write address for storing in the storage means.

In the image pickup apparatus according to the fifth aspect of the invention, the address acquisition unit is configured to convert the addressing unit when the drive mode determination unit determines that the drive mode of the solid-state image sensor is the pixel addition mode. A write address used when the pixel data converted by the storage means is stored in the storage means, and a write address for storing each pixel data in the storage means in the order converted by the conversion means It is characterized by acquiring.

The image pickup apparatus according to a sixth aspect of the present invention further includes shooting mode setting means for setting a still image shooting mode as a shooting mode, and the drive mode setting means is configured to take a still image by the shooting mode setting means. When the mode is set and the still image shooting mode is not the high-sensitivity still image shooting mode, the drive mode of the solid-state imaging device is set to the all-pixel reading mode.

Further, in the imaging apparatus according to the invention of claim 7, further comprising a photographing mode setting means for setting at least either one of a photographing mode dynamic image capturing mode or high-sensitivity still image shooting mode, the The drive mode setting means sets the drive mode of the solid-state image sensor to the pixel addition mode when set to at least one of the moving image shooting mode and the high-sensitivity still image shooting mode by the shooting mode setting means. It is characterized by.

In the imaging method according to the eighth aspect of the present invention, pixels composed of photoelectric conversion elements are two-dimensionally arranged, and signal charges of these pixels are grouped in units of a predetermined number for each horizontal line. An imaging method in an imaging apparatus including a solid-state imaging device that outputs signal charges of each group in units of the predetermined number in a predetermined arrangement order divided into a plurality of divided line signals, a step of converting a signal charge of the field element from the solid-state imaging device Ru are output in the predetermined arrangement order sequential pixel data, a write address for the converted pixel data, each having a predetermined arrangement order pixel data, a write address for storing a sequence order and the same arrangement order in the light-sensitive surface of the solid-state imaging device, and an output order of the division line signals which each pixel data corresponding to each pixel data And characterized in that it but includes a step of acquiring, based on the group position on the corresponding on the horizontal line in the group that contains pixels, the converted pixel data, and a step of storing in the memory means in accordance with the write address obtained To do.

  According to the present invention, various image processing for an imaging signal can be performed even in a configuration using a solid-state imaging device that outputs signal charges for one horizontal line in a predetermined arrangement order different from the arrangement order of pixels on the photosensitive surface. Can be performed efficiently.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This embodiment has a recording mode for shooting and a playback mode for playing back recorded images as basic operation modes, and a still image shooting mode and a moving image for shooting still images as lower modes of the recording mode. The present invention relates to a digital camera having a moving image shooting mode for shooting, and further having two types of modes, a normal shooting mode and a high-sensitivity shooting mode, as a lower mode of the still image shooting mode.

  Here, the normal shooting mode among the still image shooting modes is a highly versatile shooting mode used under a general shooting condition. In addition, the high-sensitivity shooting mode is a shooting mode that performs high-sensitivity shooting by adding pixels, ensuring exposure when shooting a dark subject, preventing camera shake, preventing subject shake when shooting a fast-moving subject, etc. This is a shooting mode prepared for the purpose. The normal shooting mode and the high-sensitivity shooting mode can be manually selected by the user, and the high-sensitivity shooting mode is automatically set according to the shooting situation.

  FIG. 1 is a block diagram showing the main part of the digital camera of this embodiment. The digital camera has a CCD 1 that is a solid-state imaging device having the specific structure described above, and a drive circuit 2 for driving the CCD 1. The CCD 1 has a pixel addition mode for internally adding and reading out signal charges of a plurality of pixels (n × m pixels) adjacent in the vertical and horizontal directions as a readout mode (drive mode) of the imaging signal, and signal charges of all the pixels. Are read out as they are, and an all-pixel readout mode is provided. The CCD 1 is driven based on a drive signal corresponding to the read mode supplied from the drive circuit 2 under the control of the CPU 11, and photoelectrically converts the light image of the subject formed on the light receiving surface via an optical system (not shown). Output as an imaging signal.

  The output of the CCD 1 is subjected to noise removal by a CDS (Correlated Double Sampling) 3 and then output to the signal processing unit 4, and is output by the A / D converter 5 (conversion means) in the signal processing unit 4. After conversion to pixel data, the converted pixel data is temporarily stored in the line buffer 7 via the data distribution circuit 6. The line buffer 7 is a storage unit of the present invention, and the line buffer 7 has a storage capacity corresponding to the pixel data for one line of the CCD 1.

  The data distribution circuit 6 is storage control means of the present invention, and sends pixel data input from the A / D converter 5 from the address generation circuit 8 which is address acquisition means of the present invention when the CCD 1 is driven. The data is stored in a predetermined address position of the line buffer 7 according to the written address.

  The pixel data stored in the line buffer 7 is sequentially sent to the image processing circuit 9, and interpolation processing for interpolating color information for each pixel or YUV conversion every time pixel data for a predetermined number of lines is prepared in the image processing circuit 9. Are sequentially stored in the DRAM 10.

  Each block described above is controlled by the CPU 11 that controls the entire digital camera. The CPU 11 adjusts the charge accumulation time (exposure time) of the CCD 1 according to the program required for controlling each block, for example, the brightness of the subject. The AE control program and various data necessary for various control operations are stored in a program memory 12 which is a rewritable nonvolatile memory such as an EEPROM or a flash memory. The program memory 12 stores a program for causing the CPU 11 to function as drive mode setting means and drive mode determination means of the present invention.

  Although not shown in FIG. 1, the digital camera is a liquid crystal that displays buttons and buttons used by the user to operate the digital camera and a recorded image, and also displays a through image in a shooting standby state and functions as an electronic viewfinder. A monitor, a predetermined image memory for recording captured still images and moving images, and the like are provided.

  On the other hand, the CCD 1 has the specific structure described above, and when driving in the pixel addition mode, the signal charge of each pixel on the same horizontal line after addition in the CCD 1 is obtained at one horizontal synchronization timing. While driving in the all-pixel readout mode, the signal charge of each pixel on the same line is divided into a plurality of divided line signals that are output with a plurality of horizontal synchronization timings as one cycle and output. Is.

  For this reason, when driven in the pixel addition mode, the signal charge of each pixel after addition is output from the CCD 1 in the order corresponding to the order of the pixels on the photosensitive surface of the CCD 1, but is driven in the all-pixel readout mode. In some cases, signal charges of all pixels not added are output as shown in FIG. FIG. 6A shows, for the sake of convenience, that the pixel size of the CCD 1 is vertical n pixels and horizontal 16 pixels, and the position of each pixel on the same line and the signal of each pixel output at each horizontal synchronization timing. FIG. 5B is a diagram showing the relationship with the charge, and FIG. 5B is a diagram showing the output order of the signal charge of each pixel on the same line.

  As shown in FIG. 6A, the signal charges of all the pixels of the CCD 1 are divided and output as divided line signals with four horizontal synchronization timings as one cycle for each line. At that time, the signal charge of each pixel on the same line is divided line signal only from the charge of the pixel at a predetermined position of each pixel group, with the number of pixel groups corresponding to the number of divisions (four times) as a unit. Are output in order. That is, when the CCD 1 is driven in the all-pixel readout mode, as shown in FIG. 6B, at each horizontal synchronization timing, a predetermined arrangement order different from the pixel arrangement order on the photosensitive surface of the CCD 1 is obtained. The imaging signal consisting of the signal charges is output. Actually, since the number of horizontal pixels of the CCD 1 is 16 or more, the number of pixel groups is also a number corresponding to that (number of horizontal pixels / 4), and one divided line signal has the same number of pixels as the number of pixel groups. Consists of signal charges.

  Then, the address generation circuit 8 described above outputs pixel data for one line digitized in an order different from the actual pixel arrangement while being output in order from the CCD 1 divided into four divided line signals as described above. As shown in FIG. 5 (d), the data distribution circuit 6 stores the horizontal line dividing write address to be stored in the line buffer 7 in the rearranged order of the actual pixels and the pixel addition. The pixel data after the addition for one line digitized in the order corresponding to the spatial pixel arrangement on the photosensitive surface of the CCD 1 while being output from the CCD 1 at the time of horizontal synchronization at the time of driving in the mode, The data distribution circuit 6 generates a normal write address to be stored in the line buffer 7 while maintaining the output order from the CCD 1. You have me.

  FIG. 2 is a block diagram showing details of the address generation circuit 8. The address generation circuit 8 includes a line division number register 81, an offset position register 82, a pixel group counter 83, a line counter 84, a base address generation circuit 85, an offset position selection circuit 86, a first multiplier 87, and a second multiplication. And an adder 89, a pixel counter 90, a pixel addition mode register 91, and a line buffer write address selection circuit 92.

  The line division number register 81 is a register for holding a line division number (“4”) that is a parameter indicating how many times the pixel data for one line in the CCD 1 is output at the horizontal synchronization timing. Set by CPU11. The line division number is stored in the program memory 12.

  The pixel group counter 83 is a counter for discriminating which group (numbered group) of the pixel groups the pixel data digitized by the A / D converter 5 belongs to. (Second counting means of the present invention). The pixel group counter 83 increments the count value every time pixel data is input according to the reference clock, and the count value is “0” to “3” corresponding to the number of pixels constituting the pixel group (here, four pixels). If the count value reaches “3”, the next count value is returned to “0” and the increment is repeated.

  Since the actual number of horizontal pixels of the CCD 1 is 16 pixels or more, the pixel data digitized by the A / D converter 5 is not shown in FIG. 6A. Also in the case of the group,..., The count value of the pixel group counter 83 is “0”.

  The line counter 84 is a counter (first counting means of the present invention) for specifying which divided line (the nth line in FIG. 6) in the current reading is in the cycle. The line counter 84 increments the count value every time pixel data is input for one divided line according to the reference clock, and the count value is “0” to “3”, similar to the pixel group counter 83, When the count value reaches “3”, the next count value is returned to “0” and the increment is repeated.

  The offset position register 82 is a register (offset position storage means of the present invention) that holds offset data 100 for knowing where the input pixel data is the pixel data of each pixel group. . As shown in FIG. 3, the offset data 100 is table data indicating offset positions corresponding to the value of the pixel group counter 83 (pixel group counter value) and the value of the line counter 84 (line counter value). Are stored in the program memory 12 and set by the CPU 11.

  The base address generation circuit 85 is a base address generation unit of the present invention that generates a base address that serves as a reference for a write address. Is the square value of the number of line divisions ("4") set in the line division number register 81 output from the multiplier 87, and the number of pixels in the pixel group ("4") x one cycle of line division The base address value held by itself is incremented with a value ("16") corresponding to the number ("4") as a unit, and is output.

  The offset position selection circuit 86 selects an offset position corresponding to the line counter value and the pixel group counter value from the offset data held in the offset position register 82.

  The second multiplier 88 multiplies the line division number ("4") held in the line division number register 81 by the count value ("0" to "3") of the pixel group counter 83, and inputs it. The head position of the pixel group to which the pixel of the pixel data that has been assigned (the pixel position at the left end of each pixel group in FIG. 6A) is calculated.

  The adder 89 is an adding means of the present invention, and includes the base address generated by the base address generation circuit 85 described above, the start position of the pixel group calculated by the second multiplier 88, and the offset position selection circuit 86. By adding the selected offset position, the digitized pixel data write address, which is used when the CCD 1 is driven in the all-pixel read mode, is used for the horizontal line dividing write address described above. a is generated and output to the line buffer write address selection circuit 92.

  On the other hand, the pixel counter 90 is a simple counter that increments the count value every time pixel data is input to the signal processing unit 4 according to the reference clock. What is the horizontal line dividing write address a output from the adder 89? Separately, the above-described normal write address b used when the CCD 1 is driven in the pixel addition mode is generated and output to the line buffer write address selection circuit 92. The pixel addition mode register 91 is a register that stores a value indicating the type of drive mode of the CCD 1 that is currently set, and the value is appropriately rewritten by the CPU 11.

  The line buffer write address selection circuit 92 is a circuit that selects a write address to be output to the data distribution circuit 6 according to the type of drive mode of the CCD 1 indicated by the value stored in the pixel addition mode register 91. The horizontal line dividing write address a output from the adder 89 while the drive mode is the all-pixel read mode, and the normal output from the pixel counter 90 while the drive mode is the pixel addition mode. It operates to output the write address b.

  FIG. 4 shows the address generation circuit 8 when pixel data for one line (16 pixels here) of the CCD 1 shown in FIG. 6A is read while the CCD 1 is driven in the all-pixel reading mode. 6 is a timing chart showing the operation of each part and the horizontal line dividing write address and normal write address generated inside the address generation circuit 8 at that time.

  As shown in the figure, while the pixel data is input at the reference timing, the value of the line counter 84 changes from “0” to “3” every time the dividing line changes (here, every time four pixels are input). repeat. On the other hand, during the readout period of each divided line, every time pixel data is input, the value of the pixel group counter 83 repeatedly changes from “0” to “3” and is calculated by the second multiplier 88. The start position of the pixel group repeats the change of “0”, “4”, “8”, “12”. The base address output from the base address generation circuit 85 is always “0” because the number of images read on each division line is four pixels (one group) here. Actually, since the number of images read out in each divided line is 4 pixels or more, the base address is reset to “0” in the pixel group counter 83 within the readout period of the same divided line. Each time it changes, it changes to “0”, “16”, “32”,.

  Further, at the beginning of reading, in the data reading period a of the pixels R1, G4, R5, and G8 of the first line of the divided lines, the offset position selected by the offset position selection circuit 86 every time the pixel data is digitized. Changes in the order of “0”, “3”, “0”, “3”, thereby generating a horizontal line dividing write address a (“base address” + “pixel group start position” generated by the adder 89. "+" Offset position ") changes in the order of" 0 "," 7 "," 8 "," 15 ".

  In the data read period b of the pixels R2, G3, R6, and G7 on the first line, the offset position changes in the order of “2”, “1”, “2”, and “1”, so that the horizontal line The division write address a changes in the order of “2”, “5”, “10”, “13”. Thereafter, the horizontal line dividing write address “a” changes to “1”, “6”, “9”, “14” in the data read period c of the pixel of the third line, and the pixel data of the fourth line. In the read period d, it changes to “3”, “4”, “11”, “12”.

  On the other hand, in parallel with the above, the pixel counter 90 repeats simple increments every time pixel data is input to the signal processing unit 4 in all readout periods a to d, so that the normal write address b is “1”, It changes as “2”, “3”, “4”,..., But as described above, in the all-pixel read mode, the line buffer write address selection circuit 92 selects the horizontal line division write address a. Therefore, the horizontal line dividing write address a is output from the address generation circuit 8 to the data distribution circuit 6 as a final write address.

  FIG. 5 is a transition diagram showing a change in the storage state of the pixel data in the line buffer 7 during that time. FIG. 5A shows the state at the end of the readout period “a” of the first line, FIG. FIG. 4D shows a state at each end point from the reading period b of the second line to the reading period d of the fourth line.

  That is, even if the imaging signal output from the CCD 1 in the all-pixel readout mode is an imaging signal generated from signal charges in an order different from the actual pixel arrangement as shown in FIG. During conversion to data, each image data can be sequentially stored in the line buffer 7 in the same order as the actual pixel arrangement for each line of pixel data.

  Therefore, the image processing circuit 9 can sequentially input the image data for each line constituting the Bayer data via the line buffer 7, and can perform image processing such as interpolation processing and YUV conversion even in the all-pixel reading mode. It can be done efficiently.

  Next, the processing procedure executed by the CPU 11 after the power is turned on in the above digital camera will be described with reference to the flowchart of FIG.

  The CPU 11 confirms the current operation mode (basic operation mode) after starting the operation when the digital camera is powered on (step S1). The operation mode immediately after the power is turned on may be, for example, a predetermined operation mode or a recording mode setting / playback mode setting key provided independently and having a power-on function. For example, the operation mode corresponds to the key used for the power-on operation.

  When the operation mode is the playback mode (“playback” in step S1), the process proceeds to a process of displaying an arbitrary recorded image (step S2). When the operation mode is the recording mode (“record” in step S1), the CCD 1 is driven in the pixel addition mode, the normal write address is generated (output) in the address generation circuit 8 and the through image is displayed. Each starts (steps S3 to S5).

  After that, when a through image is displayed, that is, in the shooting standby state, if recording is instructed by pressing the recording button (YES in step S6), the CCD 1 is driven in the pixel addition mode based on the frame rate at the time of moving image recording (step S6). S7), normal address generation (step S8) by the address generation circuit 8 is started. Thus, the signal charge data of each pixel added inside the CCD 1 is accumulated in the line buffer 7 in the order of output from the CCD 1 for each line. Then, the image data is sent to the image processing circuit 9 line by line via the line buffer 7, where predetermined image processing is performed, and then a frame image based on the image data stored in the DRAM 10 is recorded in a predetermined image memory ( In step S9), a through image is displayed based on the image data (step S10).

  Thereafter, the processes in steps S7 to S10 are repeated until the recording is completed, for example, until the recording button is pressed again, until the specified total recording time elapses, or until there is no free space in the predetermined image memory ( NO in step S11). When the recording is completed (YES in step S11), the process returns to step S3 and waits for a shooting instruction.

  When there is a still image shooting instruction by pressing the shutter key in the shooting standby state (YES in step S12), first, it is determined whether or not the high-sensitivity shooting mode is set as the still image shooting mode at that time. Confirm (step S13). Here, as described above, the high-sensitivity shooting mode is set manually by the mode selection by the user, or automatically set by the CPU 11 according to the shooting situation.

  Although not shown, the automatic setting of the high-sensitivity shooting mode is performed based on the luminance information of the through image displayed immediately before the normal shooting mode is set. For example, it is automatically set when the subject is very dark and appropriate exposure cannot be obtained even by AE control, or when exposure time by AE control is longer than a predetermined time and there is a concern about camera shake or subject shake. Is done.

  If the still image shooting mode is the high-sensitivity shooting mode (YES in step S13), the CCD 1 is driven in the pixel addition mode to acquire a still image for recording (step S14), and the address generation circuit 8 is caused to generate a normal write address (step S15). Thus, the signal charge data of each pixel added inside the CCD 1 is accumulated in the line buffer 7 in the order of output from the CCD 1 for each line. Then, the image data is sent to the image processing circuit 9 line by line via the line buffer 7, where predetermined image processing is performed, and then a still image based on the image data stored in the DRAM 10 is recorded in a predetermined image memory ( Step S16). Thereafter, the process returns to step S3 and waits for a shooting instruction.

  If the still image shooting mode is not the high-sensitivity shooting mode but the normal shooting mode (NO in step S13), the CCD 1 is driven in the all-pixel reading mode to acquire a still image for recording (step S13). In step S17, the address generation circuit 8 generates a horizontal line dividing write address (step S18). As a result, the signal charge data of all the pixels of the CCD 1 is accumulated in the line buffer 7 so as to be in an order corresponding to the actual pixel arrangement on the photosensitive surface for each line. Then, the image data is sent to the image processing circuit 9 line by line via the line buffer 7, where predetermined image processing is performed, and then a still image based on the image data stored in the DRAM 10 is recorded in a predetermined image memory ( Step S19). Thereafter, the process returns to step S3 and waits for a shooting instruction.

  Here, in the present embodiment described above, when the CCD 1 is driven in the all-pixel readout mode, the signal charges of the pixels in one line are output as four horizontal synchronization timings as one cycle. Although the case where the specification is such that four pixels are handled as one pixel group has been described, when another CCD having a specification in which the number of division lines and the number of pixels in the pixel group match but the number is different is described above. If the configuration of the address generation circuit 8 is changed as follows, it can be dealt with.

  That is, the line division number and the offset data 100, which are parameters set in the line division number register 81 and the offset position register 82, are changed, and the maximum count values of the pixel group counter 83 and the line counter 84 are changed. . That is, even if the basic configuration is not changed, other CCDs can be easily accommodated with a slight change.

  Further, the specific configuration of the address generation circuit 8 is not limited to that shown in FIG. 2, and as described above, while the image pickup signal output from the CCD 1 is sequentially converted into pixel data, 1 As long as the pixel data for each line can be stored in the line buffer 7 in a state where they are rearranged in the same order as the actual pixel arrangement, the configuration may be changed to another configuration.

  Here, another embodiment of the present invention will be described. In the above-described embodiment, while the imaging signal output from the CCD 1 is sequentially converted into pixel data when driven in the all-pixel readout mode, the converted pixel data for one line is rearranged in the same order as the actual pixel arrangement. Although what is stored in the line buffer 7 in the above state has been described, the following may be performed separately. That is, the line buffer 7 temporarily stores the pixel data for one line in the conversion order, and when the pixel data for one line is prepared, it is read out in the same order (arrangement order) as the actual pixel arrangement. At the same time, the image processing circuit 9 may be input while rearranging. Also in the other embodiments, even if the imaging signal output from the CCD 1 in the all-pixel readout mode is an imaging signal generated from a signal charge in a different order from the actual pixel arrangement, the all-pixel readout mode The image processing such as interpolation processing and YUV conversion can be performed efficiently.

  As for a specific configuration in that case, for example, the above-described data distribution circuit 6 (FIG. 1) is eliminated, and pixel data for one line is stored in the line buffer 7 between the line buffer 7 and the image processing circuit 9. Is stored, a reading circuit (reading means) for selectively reading out pixel data stored at a predetermined address position from the line buffer 7 is provided. Further, instead of the address generation circuit 8, a horizontal line dividing read address for reading out the pixel data for one line temporarily stored in the line buffer 7 in the same order (arrangement order) as the actual pixel arrangement is provided. A first read address generation circuit that sequentially generates, and a second read address generation circuit that sequentially generates a normal read address for reading the pixel data for one line temporarily stored in the line buffer 7 in that order. When the drive mode of the CCD 1 is the all-pixel read mode, the horizontal line dividing read address generated by the first read address generation circuit is used. When the drive mode of the CCD 1 is the pixel addition mode, Select each normal read address generated by the second read address generation circuit Wherein the one provided another address generating circuit including a read address selection circuit for supplying a readout circuit.

  At this time, the other address generation circuit may have an arbitrary configuration, but the read address to be sequentially supplied to the read circuit is common to all lines, and the horizontal line dividing read address is: Each context changes in the same pattern with a 4-pixel group as one cycle, and the address increases by "16" every cycle. Therefore, as the first read address generation circuit, for example, a register for sequentially storing basic read addresses for 16 pixels, a circuit for sequentially reading the basic read addresses, and every time the number of read pixels reaches 16 pixels, The circuit includes a circuit for generating a base address (“0”, “16”, “32”,...) That increases by 16 ”, a circuit for adding the basic read address and the base address, and the like. The result of addition with the base address may be generated as the horizontal line dividing read address.

  In the above description, the case where the write address supplied to the data distribution circuit 6 and the read address supplied to the read circuit are generated using a dedicated circuit has been described. It is also possible to generate or acquire a read-in address or a read address, and to supply the data to the data distribution circuit 6 or the read circuit.

  In the present embodiment, as described above, for example, when the brightness of the subject is very dark and appropriate exposure cannot be obtained even by AE control, or the exposure time by AE control becomes longer than a predetermined time, The digital camera is described in which the high-sensitivity shooting mode is automatically set as the still image shooting mode when there is a concern about camera shake or subject shake, but the digital camera is not equipped with any sensor for camera shake detection such as a gyro sensor. For example, when the shutter key is pressed, it is determined whether or not camera shake is detected by the sensor. When camera shake is detected, the still image shooting mode is automatically set to the high sensitivity shooting mode. It is good also as a structure to set.

  In the above description, the case where the present invention is applied to a digital camera has been described. However, the signal charges of all pixels are divided into a plurality of divided line signals for each horizontal line (a plurality of horizontal synchronization timings are defined as one cycle). The present invention can be applied to other imaging devices such as a digital video camera, a mobile phone terminal with a camera, a PDA with a camera, etc., as long as it has a CCD having a specific structure to be output.

It is a block diagram which shows the principal part of the digital camera which concerns on this invention. It is the block diagram which showed the detail of the address generation circuit. It is a conceptual diagram which shows the offset data hold | maintained at an offset position register. 5 is a timing chart showing the operation of the address generation circuit. 6 is a schematic diagram showing a change in the storage state of pixel data in the line buffer 7. FIG. It is the model which showed the operation | movement content of CCD in all pixel readout mode. It is the flowchart which showed the processing procedure of CPU after power activation.

Explanation of symbols

1 CCD
4 Signal Processing Unit 5 A / D Converter 6 Data Distribution Circuit 7 Line Buffer 8 Address Generation Circuit 9 Image Processing Circuit 11 CPU
81 Line division number register 82 Offset position register 83 Pixel group counter 84 Line counter 85 Base address generation circuit 86 Offset position selection circuit 87 First multiplier 88 Second multiplier 89 Adder 90 Pixel counter 91 Pixel addition mode register 92 Line buffer write address selection circuit 100 Offset data

Claims (8)

The pixels composed of photoelectric conversion elements are two-dimensionally arranged, and the signal charges of these pixels are grouped in units of a predetermined number for each horizontal line, and the signal charges of each group in units of the predetermined number are A solid-state imaging device that outputs a predetermined arrangement order divided into a plurality of divided line signals ;
Conversion means for converting the predetermined arrangement order in the signal charges of the picture element that will be output from the solid-state imaging device sequentially to the pixel data,
Storage means for storing the pixel data converted by the conversion means;
A write address used when the pixel data converted by the conversion unit is stored in the storage unit, and the pixel data having the predetermined arrangement order are arranged on the photosensitive surface of the solid-state imaging device. Write addresses to be stored in the storage means in the same arrangement order as the output order of the divided line signal corresponding to each pixel data and the horizontal line in the group including the pixel corresponding to each pixel data Address acquisition means for acquiring based on the group ranking in
An image pickup apparatus comprising: storage control means for storing the pixel data converted by the conversion means in the storage means in accordance with a write address acquired by the address acquisition means. The solid-state imaging device outputs the signal charges of the pixels in the horizontal lines each at a predetermined arrangement order,
Said converting means converts said predetermined arrangement order in the signal charges of the picture element that will be output for every horizontal line from the solid-sequential pixel data,
The storage means stores pixel data for one horizontal line converted by the conversion means,
The imaging apparatus according to claim 1, wherein the address acquisition unit acquires the write address of pixel data for one horizontal line converted by the conversion unit. The address acquisition means includes
Offset position storage means for storing offset data indicating prescribed offset positions corresponding to both the arbitrary output rank and the arbitrary group rank, each pixel data indicating the position in the group of each corresponding pixel When,
First counting means for counting the output rank;
Second counting means for repeatedly counting the group rank in units of a predetermined number of groups;
Base address generating means for generating a base address corresponding to the number of repetitions of counting of the group rank by the second counting means, which serves as a reference for the writing address of each pixel data;
An offset position corresponding to the output rank counted by the first count means and the group rank counted by the second count means, the position indicated by the offset data stored in the offset position storage means ; Addition means for adding the base address generated by the base address generation means and the group head position, which is the position within the horizontal line of the head pixel of the group including the pixel corresponding to each pixel data,
3. The imaging according to claim 2 , wherein the storage control unit stores the pixel data converted by the conversion unit in the storage unit according to a write address that is a result of addition by the addition unit of the address acquisition unit. apparatus. The drive mode of the solid-state imaging device is set to a pixel addition mode for reading in a state where signal charges of a plurality of pixels are added, or a drive mode for reading all pixels without adding signal charges of all pixels. Setting means;
Drive mode determination means for determining the drive mode of the solid-state imaging device set by the drive mode setting means,
When the drive mode determination unit determines that the drive mode of the solid-state imaging device is the all-pixel readout mode, the address acquisition unit is configured to store the pixel data converted by the conversion unit in the storage unit. A write address used to store each pixel data having the predetermined arrangement order in the storage means in the same arrangement order as the arrangement order on the photosensitive surface of the solid-state image sensor. imaging device according to any one of claims 1 to 3, characterized in that. The address acquisition unit is used when the pixel data converted by the conversion unit is stored in the storage unit when the drive mode determination unit determines that the drive mode of the solid-state imaging device is the pixel addition mode. The imaging apparatus according to claim 4 , further comprising: a write address for storing the pixel data in the storage unit in the order converted by the conversion unit. A shooting mode setting means for setting a still image shooting mode as a shooting mode is provided.
The drive mode setting means sets the drive mode of the solid-state imaging device to the all-pixel readout mode when the still image shooting mode is set by the shooting mode setting means and the still image shooting mode is not a high-sensitivity still image shooting mode. The imaging device according to claim 4 or 5, wherein Includes a photographing mode setting means for setting at least either one of a photographing mode dynamic image capturing mode or high-sensitivity still image shooting mode,
The drive mode setting unit sets the drive mode of the solid-state imaging device to the pixel addition mode when the shooting mode setting unit sets at least one of the moving image shooting mode and the high-sensitivity still image shooting mode. The imaging apparatus according to claim 4 or 5, wherein The pixels composed of photoelectric conversion elements are two-dimensionally arranged, and the signal charges of these pixels are grouped in units of a predetermined number for each horizontal line, and the signal charges of each group in units of the predetermined number are An imaging method in an imaging apparatus including a solid-state imaging device that outputs a plurality of divided line signals divided in a predetermined arrangement order,
A step of converting the signal charges of picture element that will be output at the predetermined sorted sequential pixel data from the solid-
Write address for the converted pixel data, the write address for storing each pixel data having the predetermined arrangement order in the same arrangement order as the arrangement order on the photosensitive surface of the solid-state imaging device , Obtaining based on the output order of the divided line signal corresponding to each pixel data and the group order on the horizontal line in the group including the pixel corresponding to each pixel data ;
And storing the converted pixel data in a storage unit in accordance with the acquired write address.

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