JP4973255B2 - Radio frame time synchronizer - Google Patents

Description

  The present invention relates to a radio frame time synchronization apparatus, and more particularly to a radio frame time synchronization apparatus with a simplified circuit configuration.

  In recent years, an enormous number of wireless signals are flying in the air, but each signal must not interfere. Furthermore, since the frequency that can be used as signal radio waves is limited and is a limited resource, it is necessary to use it as effectively as possible. Multiplexing is one method for effectively using radio waves. Here, multiplexing is a method of exchanging a plurality of signals with one radio wave.

  As a representative example of multiplexing, there is frequency division multiplexing (FDM: Frequency Division Multiplexing). FDM is a method of arranging a plurality of signals on a frequency axis. FM stereo radio broadcasting in which right channel and left channel signals are transmitted on one radio wave is also a kind of FDM.

  OFDM is called Orthogonal Frequency Division Multiplexing and is considered to be one of FDMs in principle. The fundamental difference between normal FDM and OFDM lies in how the frequencies overlap. In FDM, interference occurs when the spectrum of each signal overlaps, so it is necessary to separate the frequency intervals to some extent. On the other hand, OFDM narrows the frequency interval of each signal multiplexed up to the point where the spectrum overlaps at first glance.

  In OFDM modulation, the modulation signal is converted into parallel data and subjected to I-FFT (Inverse Fast Fourier Transform). The inverse Fourier transform converts frequency domain data into time domain data. Putting modulation signal data in the I-FFT means that the original data (time series data) composed of 1 and 0 is regarded as a signal (spectrum) in which the spectrum is arranged in the same form as the original data on the frequency axis. This is considered to be an operation for converting this into a time series.

  In a radio communication system using OFDM, a time position of a radio frame is obtained with respect to a signal received by a receiving device, thereby determining a window position of a fast Fourier transform (FFT), and in a frequency domain. So that demodulation can be performed accurately.

  As an example, consider a radio frame as shown in FIG. In the illustrated radio frame, one radio frame (10 ms cycle) is composed of 20 subframes, and one symbol at the head of each subframe is a pilot channel (CH), followed by a control channel or data channel of 6 symbols. It consists of 7 symbols. One symbol includes a GI (Guard Interval) length M samples and an effective symbol length N samples.

  Further, when the scrambling code length is one radio frame (10 ms) and the scrambling code is known on the receiving side, the replica of the transmission pilot signal is different for each subframe. Next, a method for synchronizing time with respect to a radio frame will be described. FIG. 6 is a diagram illustrating a conventional configuration example of a radio frame synchronization apparatus. As shown in the figure, this apparatus comprises three stages of a symbol head position detection circuit 10, a radio frame head detection circuit 20, and an FFT timing synchronization circuit 30.

  In the symbol head position detection circuit 10, 11 is an N sample delay for delaying received data by N samples, 2 is a correlator that performs correlation by receiving received data and N sample delay 1, and 3 is an output of the correlator 2. A plurality of in-phase adders 4 for performing in-phase addition are peak detectors for detecting a maximum peak from a plurality of outputs of the in-phase adder 3. Here, the correlation length of the correlator 2 is M samples, and the correlation width of the in-phase adder 3 is N + M samples.

  In the radio frame head detection circuit 20, 21 is a pilot replica at the head of the radio frame, 22 is a plurality of correlators that correlate received data and the pilot replica 21, and 23 receives the outputs of these correlators 22 and performs in-phase addition. A plurality of in-phase adders 24 are peak detectors that receive the output of the in-phase adder 23 and detect the maximum peak from the plurality of outputs.

In the FFT timing synchronization circuit 30, 31 is a pilot replica at the head of a subframe, 32 is a plurality of correlators that perform correlation based on received data and the output of the pilot replica 31, and 33 is a correlation of the correlators 32. A plurality of in-phase adders 34 that receive the output and perform in-phase addition are peak detectors 34 that receive the output of the in-phase adder 33 and detect the maximum peak value from the plurality of outputs. The correlation length of the correlator 22 is N samples, and the correlation width of these correlators 22 is 2M samples. The operation of the apparatus configured as described above will be described as follows.
(Detection of symbol head)
Consider a method of time synchronization for radio frames. First, consider detecting the beginning of a symbol. The data of the GI portion of each symbol is a copy of the data corresponding to the GI length from the end of each valid symbol data (Cyclic Prefix). Utilizing this, the correlator 2 auto-correlates the received data delayed by the effective symbol length N samples by the N sample delay 1 and the input data over the M sample length (GI length).

  The correlation processing is performed starting from each sample having a width of M + N samples (symbol length), and a total of M + N correlation values of the respective points are obtained. A similar process is performed for each symbol in the subframe, and the in-phase adder 3 performs in-phase addition on the samples corresponding to the M + N sample period from the first obtained M + N starting points (inter-symbol in-phase addition). The peak detector 4 detects the peak of the M + N correlation values finally obtained, and sets the sample position with the highest correlation value as the head position of the symbol.

FIG. 7 is an explanatory diagram of the symbol head detection operation. (A) is input data, (b) is input data delayed by N samples, (c) is a correlation window width, and (d) is a correlation result. The correlation between the input data (a) and the input data (b) delayed by N samples is taken based on the correlation window width M + N. As a result, a correlation result as shown in (d) is obtained. When this correlation result is plotted with the time axis as the horizontal axis and the correlation value as the vertical axis, the correlation result as shown on the right of FIG. 7 is obtained. The maximum value (peak value) of the spectrum of this correlation value is the symbol head.
(Detection of start of radio frame)
Next, a method for detecting the start of a radio frame will be described. The correlator 22 performs a correlation operation between the transmission pilot signal replica at the head of the radio frame and the received signal with the correlation width of 2M samples centering on the symbol head position obtained previously. Here, the correlation length is N samples. Since this is performed at the head position of each symbol in one radio frame, the obtained correlation value is 2M samples × 7 symbols × 20 subframes. These are added in-phase by a subsequent in-phase adder 23. Then, the peak of the 2M × 7 × 20 correlation values finally obtained is detected, and the sample position with the highest correlation value is detected by the peak detection unit 24 and set as the radio frame head position.

FIG. 8 is an explanatory diagram of the radio frame head detection operation. Assume that there is one radio frame (10 ms) as shown in the figure. The correlation width of the obtained symbol head position is set to 2M, and correlation with the radio frame head pilot replica is taken. The in-phase adder 23 that continues the correlation in this way performs in-phase addition of the number of 2M samples × 7 symbols × 20 subframes. In response to the output of the in-phase adder 23, the subsequent peak detector 24 obtains the maximum peak and sets it as the radio frame head position.
(Operation of timing synchronization)
Finally, the operation of the FFT timing synchronization circuit 30 will be described. The timing synchronization circuit 30 is for detecting the FFT window position with higher accuracy than the detection of the head of the radio frame. The received signal and the transmission pilot signal replica at the beginning of the subframe (for each subframe) with a correlation width of 2M samples centered on each sample position of the subframe period by the correlator 32, starting from the radio frame head position obtained previously. (Different) correlation calculation. The correlation calculation result is obtained by in-phase addition of the correlation values of the respective subframes by the subsequent in-phase adder 33, the result of the in-phase adder 33 being received by the peak detector 34, and the peak detection result being the start position of the FFT window. And

  FIG. 9 is an explanatory diagram of the operation of the timing synchronization unit. The correlator 32 takes a correlation between the pilot symbol of the input data and the transmission pilot replica with reference to the head of the radio frame. The output of the correlator 32 is in-phase added by the in-phase adder 33. The outputs of these in-phase adders 33 enter a peak detector 34, and the peak detector 34 detects the peak. This peak value is the starting position of the FFT window.

  A series of operations will be described. First, a symbol head position by GI correlation is detected, and a wireless frame head is detected using the detected symbol head position as a base point. Thereafter, an accurate FFT window position is detected by the high-accuracy timing synchronization circuit 30 with the detected radio frame as a starting point.

  The timing synchronization circuit continues to operate and follows the FFT timing variation with high accuracy. Also, the GI correlation → radio frame head detection circuit continues to operate, and updates the radio frame head position notified to the timing synchronization circuit 30.

  As a conventional apparatus of this type, a cross-correlation detection processing unit that detects a cross-correlation value of a received signal, a synchronous addition unit that synchronously adds the cross-correlation value at a predetermined interval, and a reception power of the received signal are calculated. A reception power calculation unit; an autocorrelation power calculation unit that calculates autocorrelation power of the received signal; a threshold calculation unit that calculates a synchronization addition threshold according to the reception power; and a peak timing of the value obtained by synchronization addition A symbol for detecting the timing of the peak as a symbol timing in response to the determination that the autocorrelation power is equal to or less than a value obtained by multiplying the received power by a predetermined coefficient and the value obtained by the synchronous addition is equal to or greater than the synchronous addition threshold A technique including a timing detection unit is known (see, for example, Patent Document 1).

In addition, a correlator that calculates the correlation between the signal generated by the synchronization symbol generator and the OFDM signal, a correlation calculator that calculates the correlation amount from the calculated correlation, and an integration that integrates the calculated correlation amount in the guard period. A timing determiner that determines symbol timing from the integrated correlation amount, an FFT window generator that outputs an operation timing of Fourier transform from the determined symbol timing, and transmission based on an output signal of the FFT window generator A technique is known that includes a demodulator that extracts a signal of an effective symbol period from a symbol (see, for example, Patent Document 2).
JP 2005-318512 A (paragraphs 0014 to 0023, FIGS. 3 and 4) JP 2001-69119 A (paragraphs 0051 to 0062, FIGS. 1 to 7)

  In the conventional system described above, timing detection is performed in three stages, and a correlator is used at each stage. Since the correlator is configured by a multiplier, such a configuration has a problem that the circuit scale increases.

  The present invention has been made in view of such problems, and an object thereof is to provide a radio frame time synchronization apparatus that does not increase the circuit scale.

(1) The invention according to claim 1 is a correlation calculation unit that receives a received data and performs a correlation calculation, a symbol head position detection circuit that receives an output from the correlation calculation unit and outputs symbol head information, and the correlation An output from the calculation unit is connected to the FFT timing synchronization circuit that outputs radio frame and subframe head information based on the output of the symbol head position detection circuit and the correlation calculation unit, and detects the radio frame head. A radio frame time synchronization apparatus configured to include a radio frame head detection circuit , wherein buffering of data in a collision section with the FFT timing synchronization circuit is performed using a common memory .
(2) The invention according to claim 2 is characterized in that GI correlation is performed in an unused section of a correlator of the FFT timing synchronization circuit.
(3) The invention described in claim 3 is characterized in that GI correlation is performed using an unused section of the correlator of the FFT timing synchronization circuit and a section outside the correlation range in the radio frame head detection .

(1) According to the first aspect of the present invention, the correlation processing used in the processing circuit composed of three stages, ie, the symbol start position detection of the radio frame, the detection of the radio frame position, and the detection of the start of the radio frame. It is possible to provide a radio frame time synchronization apparatus that does not increase the circuit scale. Further, by buffering data in the collision section with the FFT timing synchronization circuit using a common memory, hardware can be reduced.
(2) According to the invention described in claim 2, the processing can be made more efficient by performing the GI correlation using the unused period of the correlator of the FFT timing synchronization circuit.
(3) According to the invention described in claim 3, the correlation is performed using the unused period of the correlator of the FFT timing synchronization circuit and the section outside the correlation range in the detection of the start of the radio frame, thereby improving the processing efficiency. Can be planned .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The same components as those in FIG. 6 are denoted by the same reference numerals. In the figure, 10 'is a symbol head position detection unit, 20' is a radio frame head detection unit, and 30 'is an FFT timing synchronization unit. These circuits commonly use a correlation calculation unit 100 described later in the calculation.

  In the symbol head position detection circuit 10 ′, 3 is a plurality of in-phase adders that receive the output from the correlation calculation unit 100 and performs in-phase addition, and 4 is a peak detection that receives the output of the in-phase adder 3 and detects a peak value. It is a vessel. Symbol head information is output from the peak detector 4.

  In the radio frame head detection circuit 20 ′, reference numeral 23 denotes an in-phase adder that receives the output of the correlation calculation unit 100 and performs in-phase addition, and 24 denotes a peak detector that receives the outputs of the plurality of in-phase adders 23 and detects a peak value. It is. In the FFT timing synchronization circuit 30 ′, 33 is an in-phase adder that receives the output of the correlation calculation unit 100 and performs in-phase addition, and 34 is a peak detector that receives the output of the in-phase adder 33 and detects a peak position. Symbol head position detection circuit 10 'outputs symbol head information, radio frame head detection circuit 20' outputs radio frame head information, and FFT timing synchronization circuit 30 'outputs radio frame and subframe head information. Is done.

  In the correlation calculation unit 100, 41 is a data storage memory that receives and stores received data, 1 is an N sample delay that receives the output of the data storage memory 41 and delays it by N samples, and 42 is the start of a radio frame or subframe. It is a pilot replica. 43 is a first selector that selects either one of the received data or the output from the data storage memory 41, and 44 is a second selector that receives either the N sample delay 1 or the pilot replica 42 and selects either one. Selector. These selectors 43 and 44 are adapted to switch their outputs in response to a control signal from a correlation processing control unit 40 described later.

  Reference numeral 45 denotes a plurality of correlators that receive the outputs of the first and second selectors and perform correlation calculations. These correlators 45 also receive control signals from the correlation processing control unit 40. Reference numeral 46 denotes a saving unit that holds an intermediate result when the correlation calculation needs to be canceled during the correlation calculation by the correlator 45. The correlation calculation stop signal is instructed by the correlation processing control unit 40. When there is no reason for stopping the correlation calculation, the correlation calculation process is performed again according to an instruction from the correlation processing control unit 40. An output selection unit 47 receives the outputs of the plurality of correlators 45 and determines the output destination. The saving unit 46 and the output selection unit 47 receive a control signal from the correlation processing control unit 40.

  40 is a correlation processing control for receiving the symbol head information output from the symbol head position detection circuit 10 'and the radio frame head information output from the radio frame head detection circuit 20' and outputting the various control signals described above. Part. As the correlation processing control unit 40, for example, a microcomputer is used.

  The data storage memory 41 in the figure stores data at the time of collision. As described above, it can be shared at the time of GI correlation and the detection of the start of a radio frame. The input data and the data stored in the memory are selected by an instruction from the control unit and input to the correlator. The memory data is also supplied to an N-sample delay circuit for autocorrelation, and is input to a correlator by selection with a pilot replica. When switching the input to the correlator, the control unit supports the correlation length and saves the intermediate result of the manual calculation. When the calculation of the correlation length is completed, the output destination of the result is selected and output from symbol head detection, radio frame head detection, and timing synchronization. The operation of the apparatus configured as described above will be described as follows.

  FIG. 2 is an explanatory diagram of the correlator operation of the timing synchronization circuit 30 '. The correlation processing in the timing synchronization circuit 30 'is performed only at the pilot symbol position in one frame (referenced to the detected radio frame head). Therefore, as shown in the figure, the correlation processing is not performed in the section other than the section of N sample length with respect to the number of samples (M + N) × 7 in one frame. Therefore, the period Tm during which the correlator does not operate is expressed by the following equation.

Tm = M (width) × [(M + N) × 7−N] (long) Between samples. During this time, the correlator 45 is not operating.
Next, it is considered that GI correlation for symbol head detection is performed in a section where the correlation processing of FIG. 2 is not performed. Since GI correlation is autocorrelation with a signal delayed by N samples, even if the correlation width is M + N samples, only one correlator is required. Therefore, as shown in FIG. 3, the data of the portion colliding with the correlation processing of the timing synchronization processing is buffered in the temporary data storage memory 41, and the correlator (width) opened after the timing synchronization correlation processing is completed is used. By performing the correlation calculation, it is possible to process within one frame. FIG. 3 is a diagram showing an operation when the correlator is shared for timing synchronization and symbol head detection.

  FIG. 3 is a diagram showing an operation when the correlator is shared for timing synchronization and symbol head detection. The correlation between the pilot symbol and the correlation width symbol is taken. At this time, if a data collision occurs, the data in the collision section is buffered in the data storage memory 41. A shows the GI correlation of the buffered data.

  Similarly, consider performing pilot correlation processing when detecting the start of a radio frame. Buffering the data in the collision section is the same as in GI correlation (the buffer memory can be shared), but in the case of radio frame head detection, a correlator corresponding to the correlation width is required.

  Here, considering the correlation processing for one symbol at the time of detecting the head of the radio frame, if the correlation length is N symbols, the correlation processing is not performed between M samples. Therefore, if the condition that a total of 7 M samples ≧ N samples (correlation length) of M samples per symbol is satisfied, it is possible to process within one frame.

  FIG. 4 is a diagram showing an operation at the time of correlator sharing for timing synchronization and detection of a radio frame head. Data in the collision period is buffered in the data storage memory 41. Then, the GI correlation of the buffered data is taken. In the second half of the frame, pilot correlation is performed.

  Even if the previous condition of 7M samples ≧ N samples (correlation length) is not satisfied, if there is no problem in the accuracy of radio frame head detection and response speed, processing is performed every other radio frame. It suffices if processing is completed within the radio frame.

  As described above in detail, according to the present invention, the processing circuit configured by the three steps of detecting the start of the radio frame, detecting the position of the start of the symbol, detecting the position of the radio frame, and detecting the start of the radio frame. The correlation processing unit to be used can be configured to be used in common in the three stages, and a radio frame time synchronization apparatus that does not increase the circuit scale can be provided.

Further, the processing can be made more efficient by performing the GI correlation using the unused period of the correlator of the FFT timing synchronization circuit.
Further, by performing correlation using the unused period of the correlator of the FFT timing synchronization circuit and the section outside the correlation range in the radio frame head detection, it is possible to improve the processing efficiency.

Furthermore, hardware can be reduced by buffering data in the collision section with the FFT timing synchronization circuit using a common memory.
As described above, according to the present invention, the GI correlation and the pilot correlation for detecting the start of the radio frame are performed by using the section in which the correlator is not used in the timing synchronization process, so that the correlator is shared. The circuit scale can be reduced.

It is a block diagram which shows one embodiment of this invention. It is explanatory drawing of the correlator operation | movement of a timing synchronization circuit. It is a figure which shows the operation | movement at the time of correlator sharing of a timing synchronization and a symbol head detection. It is a figure which shows the correlator shared operation | movement of a timing synchronization and a radio | wireless frame head detection. It is a figure which shows the structural example of a radio | wireless frame. It is a figure which shows the example of a conventional structure of a radio | wireless frame synchronizing apparatus. It is explanatory drawing of a symbol head detection operation | movement. It is explanatory drawing of a radio | wireless frame head detection operation | movement. It is operation | movement explanatory drawing of a timing synchronizer.

Explanation of symbols

1 N sample delay 3 In-phase adder 4 Peak detector 10 ′ Symbol head position detection circuit 20 ′ Radio frame head detector 23 In-phase adder 24 Peak detector 30 ′ FFT timing synchronization circuit 33 In-phase adder 34 Peak detector 40 Correlation Processing control unit 41 Data storage memory 42 Pilot replica 43 Selector 44 Selector 45 Correlator 46 Save memory 47 Output head selection unit

Claims (3)

A correlation calculation unit that receives the received data and performs a correlation calculation;
A symbol head position detection circuit that receives the output from the correlation calculation section and outputs symbol head information;
An FFT timing synchronization circuit that receives an output from the correlation calculation unit and outputs radio frame and subframe head information based on the output of the symbol head position detection circuit ;
A radio frame head detection circuit connected to the correlation calculation unit and detecting a radio frame head;
In a radio frame time synchronization apparatus configured with
A radio frame time synchronizer for buffering data of a collision section with the FFT timing synchronizer using a common memory .   The radio frame time synchronization apparatus according to claim 1, wherein GI correlation is performed in an unused section of a correlator of the FFT timing synchronization circuit. 2. The radio frame time synchronization apparatus according to claim 1, wherein GI correlation is performed using an unused section of the correlator of the FFT timing synchronization circuit and a section outside the correlation range in radio frame head detection.

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