JP4972924B2 - Solid-state imaging device, manufacturing method thereof, and camera - Google Patents

Description

  The present invention relates to a solid-state imaging device, a manufacturing method thereof, and a camera, and more particularly to a solid-state imaging device having an optical waveguide, a manufacturing method thereof, and a camera.

  In a solid-state imaging device, a waveguide structure is known as means for increasing the light collection efficiency (see, for example, Patent Documents 1 and 2). The waveguide optically connects the on-chip lens and the light receiving part (photodiode part). Utilizing the fact that the transparent film, which is the core material inside the waveguide, has a higher refractive index than the surrounding insulating film, which is the cladding, it has an incident angle greater than the critical angle at the interface between the transparent film and the insulating film. The light is totally reflected, and the light collection efficiency to the light receiving part is increased.

In the formation of the waveguide, after the opening of the waveguide is formed in the interlayer insulating film, the inside of the opening is filled with a transparent film. In the case of a MOS type solid-state imaging device, after all wiring layers are formed, an opening of a waveguide is formed in the interlayer insulating film.
Japanese Patent Laid-Open No. 11-121725 Japanese Patent Laid-Open No. 10-326885

  However, the pixel area is reduced toward an increase in the number of pixels of the image sensor, and accordingly, the opening area of the waveguide is reduced. In particular, in a CMOS sensor having a multilayer wiring structure, the wiring density increases with miniaturization, and therefore it is necessary to provide a margin to prevent contact with the wiring. As a result, there is a problem that the aperture diameter needs to be reduced and the light collection sensitivity is lowered.

  Further, for example, in a solid-state imaging device having a multilayer wiring structure, the opening of the waveguide to be formed becomes deep. As a result, the aspect ratio of the opening is increased, and the embedding property of the transparent film serving as the core material into the waveguide opening is deteriorated. There is a concern about the deterioration and dispersion of the light collecting property.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state imaging device and a camera with improved light collecting properties.
Another object of the present invention is to provide a method for manufacturing a solid-state imaging device capable of improving the embedding property of a transparent film in an opening of a waveguide.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a light receiving unit formed on a substrate, a conductive layer formed on an upper layer of the substrate, the conductive layer and the substrate, and the light receiving unit. An interlayer insulating film having a waveguide opening thereon, and a transparent film formed by being embedded in the opening of the interlayer insulating film, and at least one surface of the conductive layer around the light receiving portion. An etching stopper film is formed on the portion.

  In order to achieve the above object, a method of manufacturing a solid-state imaging device according to the present invention includes a step of forming a light receiving portion on a substrate, a step of forming an interlayer insulating film and a conductive layer on the substrate, and a step on the light receiving portion. Removing the interlayer insulating film to form a waveguide opening; and embedding a transparent film in the opening; and forming the interlayer insulating film and the conductive layer, An etching stopper film is formed on a part of the surface of the conductive layer around the light receiving portion.

  In order to achieve the above object, a camera of the present invention includes a solid-state imaging device, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device. The solid-state imaging device includes a light receiving portion formed on a substrate, a conductive layer formed on an upper layer of the substrate, the conductive layer and the substrate, and an opening portion of a waveguide on the light receiving portion. And an etching stopper film formed on at least a part of the surface of the conductive layer around the light receiving portion. The interlayer insulating film has a transparent film formed in the opening of the interlayer insulating film. Has been.

  In the present invention, the etching stopper film is formed on a part of the surface of the conductive layer around the light receiving portion. This prevents the conductive layer from being exposed when the opening of the waveguide is formed. As a result, since it is not necessary to provide a space between the surrounding conductive layer and the opening of the waveguide, the diameter of the opening can be increased.

ADVANTAGE OF THE INVENTION According to this invention, the solid-state imaging device and camera which improved condensing property are realizable.
According to the method for manufacturing a solid-state imaging device of the present invention, the embedding property of the transparent film into the opening of the waveguide can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating an example of a configuration of an amplification type solid-state imaging device according to the present embodiment. In the present embodiment, for example, a MOS image sensor will be described as an example.

  The solid-state imaging device 10 includes a unit pixel 11 including a photodiode that is a photoelectric conversion element, a pixel array unit (imaging unit) 12 in which the pixels 11 are two-dimensionally arranged in a matrix, a vertical selection circuit 13, It has a column circuit 14 that is a signal processing circuit, a horizontal selection circuit 15, a horizontal signal line 16, an output circuit 17, and a timing generator (TG) 18.

  In the pixel array unit 12, a vertical signal line 121 is arranged for each column with respect to a matrix-like pixel arrangement. A specific circuit configuration of the unit pixel 11 will be described later.

  The vertical selection circuit 13 is configured by a shift register or the like. The vertical selection circuit 13 sequentially outputs control signals such as a transfer signal for driving the transfer transistor of the pixel 11 and a reset signal for driving the reset transistor in units of rows, thereby causing each pixel 11 in the pixel array unit 12 to be in units of rows. Select drive.

  The column circuit 14 is a signal processing circuit arranged for each pixel in the column direction of the pixel array unit 12, that is, for each vertical signal line 121. The column circuit 14 includes, for example, an S / H (sample hold) circuit and a CDS (Correlated Double Sampling) circuit.

  The horizontal selection circuit 15 is configured by a shift register or the like, and sequentially selects the signal of each pixel 11 output through the column circuit 14 and outputs it to the horizontal signal line 16. In FIG. 1, the horizontal selection switch is not shown for simplification of the drawing. The horizontal selection switch is sequentially turned on / off by the horizontal selection circuit 15 in units of columns.

  The signals of the unit pixels 11 that are sequentially output from the column circuit 14 for each column by the selection drive by the horizontal selection circuit 15 are supplied to the output circuit 17 through the horizontal signal line 16, and the output circuit 17 performs signal processing such as amplification. After being applied, it is output outside the device.

  The timing generator 18 generates various timing signals, and performs drive control of the vertical selection circuit 13, the column circuit 14, the horizontal selection circuit 15 and the like based on these various timing signals.

(Pixel circuit)
FIG. 2 shows a circuit diagram of the unit pixel 11A as an example of the circuit configuration of the unit pixel 11. As shown in FIG.

  The unit pixel 11A includes three transistors (active elements), for example, a transfer transistor 112, a reset transistor 113, and an amplification transistor 114 in addition to a photoelectric conversion element, for example, a photodiode 111. Here, for example, n-channel MOS transistors are used as the transistors 112 to 114.

  The transfer transistor 112 is connected between the cathode of the photodiode 111 and an FD (floating diffusion) portion 116. By applying a transfer pulse φTRG to the gate of the transfer transistor 112, photoelectric conversion is performed by the photodiode 111, and signal charges (here, electrons) accumulated therein are transferred to the FD unit 116.

  The reset transistor 113 has a drain connected to the selected power supply SELVDD and a source connected to the FD unit 116. Prior to the transfer of signal charges from the photodiode 111 to the FD unit 116, the potential of the FD unit 116 is reset by applying a reset pulse φRST to the gate. The selected power supply SELVDD is a power supply that selectively takes a VDD level and a GND level as a power supply voltage.

  The amplification transistor 114 constitutes a source follower circuit in which a gate is connected to the FD unit 116, a drain is connected to the selection power supply SELVDD, and a source is connected to the vertical signal line 121. The amplification transistor 114 outputs the potential of the FD unit 116 after resetting by the reset transistor 113 to the vertical signal line 121 as a reset level, and further, the potential of the FD unit 116 after transferring the signal charge by the transfer transistor 112 is set to the signal level. To the vertical signal line 121.

  FIG. 3 shows a circuit diagram of the unit pixel 11B as another example of the circuit configuration of the unit pixel 11. As shown in FIG.

  The unit pixel 11B is a pixel circuit having four transistors, for example, a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115 in addition to a photoelectric conversion element, for example, a photodiode 111. Here, for example, n-channel MOS transistors are used as the transistors 112 to 115.

  The transfer transistor 112 is connected between the cathode of the photodiode 111 and an FD (floating diffusion) portion 116. By applying a transfer pulse φTRG to the gate of the transfer transistor 112, photoelectric conversion is performed by the photodiode 111, and signal charges (here, electrons) accumulated therein are transferred to the FD unit 116.

  The reset transistor 113 has a drain connected to the power supply VDD and a source connected to the FD unit 116. Prior to the transfer of the signal charge from the photodiode 111 to the FD unit 116, the potential of the FD unit 116 is reset by applying a reset pulse φRST to the gate of the reset transistor 113.

  The selection transistor 115 has, for example, a drain connected to the power supply VDD and a source connected to the drain of the amplification transistor 114. The selection transistor 115 is turned on when a selection pulse φSEL is applied to its gate, and the pixel 11B is selected by supplying the power supply VDD to the amplification transistor 114. The selection transistor 115 may be configured to be connected between the source of the amplification transistor 114 and the vertical signal line 121.

  The amplification transistor 114 forms a source follower circuit in which a gate is connected to the FD unit 116, a drain is connected to the source of the selection transistor 115, and a source is connected to the vertical signal line 121. The amplification transistor 114 outputs the potential of the FD unit 116 after resetting by the reset transistor 113 to the vertical signal line 121 as a reset level, and further, the potential of the FD unit 116 after transferring the signal charge by the transfer transistor 112 is set to the signal level. To the vertical signal line 121.

  In the unit transistor 11A having the three-transistor configuration and the unit pixel 11B having the four-transistor configuration, the signal charge obtained by photoelectric conversion by the photodiode 111 is transferred to the FD unit 116 by the transfer transistor 112, and the signal of the FD unit 116 is transmitted. An analog operation is performed in which a potential corresponding to the electric charge is amplified by the amplification transistor 114 and output to the vertical signal line 121.

  FIG. 4 is a cross-sectional view of the solid-state imaging device according to the present embodiment.

  An element isolation insulating film 21 that partitions an active region is formed on a semiconductor substrate 20 made of silicon. A p-type well is formed in the active region of the semiconductor substrate 20, and a light receiving portion 22 mainly composed of an n-type region is formed in the p-type well. The light receiving unit 22 corresponds to the photodiode 111 in FIGS. 2 and 3. A p-type region (not shown) is formed on the surface layer of the light receiving unit 22. Although not shown, the source region and the drain region of various transistors 112 to 115 are formed in the semiconductor substrate 20.

  A gate electrode 24 is formed on the semiconductor substrate 20 via a gate insulating film 23 made of, for example, silicon oxide. The gate electrode 24 is the gate of the transfer transistor 112. Note that gate electrodes of other transistors 113, 114, and 115 (see FIGS. 2 and 3) are formed in a region not shown. The gate electrode is made of polysilicon, for example.

  An insulating film 25 made of, for example, silicon oxide is formed on the gate electrode 24 and the gate insulating film 23. An etching stopper film 26 made of, for example, silicon nitride is formed on the insulating film 25 in the light receiving unit 22. A first interlayer insulating film 31 is formed so as to cover the etching stopper film 26 and various transistors. The first interlayer insulating film 31 is made of, for example, silicon oxide.

  In the first interlayer insulating film 31, a first plug P1 connected to the source region or drain region of the transistor is formed. The first plug P1 is made of, for example, tungsten. On the first interlayer insulating film 31, a first wiring layer M1 connected to the first plug P1 is formed. The first wiring layer M1 is, for example, an aluminum wiring. An etching stopper film 40 made of, for example, silicon nitride is formed on the surface of the first wiring layer M1.

  On the first wiring layer M1, a second interlayer insulating film 32 made of, for example, silicon oxide is formed. In the second interlayer insulating film 32, a second plug P2 connected to the first wiring layer M1 is formed.

  On the second interlayer insulating film 32, a second wiring layer M2 is formed. The second wiring layer M2 is, for example, an aluminum wiring. A third interlayer insulating film 33 made of, for example, silicon oxide is formed on the second wiring layer M2.

  By removing the interlayer insulating films 31 to 33 located on the light receiving portion 22, an opening 50 of the waveguide is formed. The etching stopper film 26 in the opening 50 is removed. A transparent film 51 is embedded in the opening 50. The transparent film 51 is made of a material having a higher refractive index than the surrounding interlayer insulating films (refractive index n = 1.43 in the case of silicon oxide) 31-33. The transparent film 51 is made of silicon nitride (refractive index n = 2.0 in the case of a silicon nitride film formed by a plasma CVD method) or polyimide resin (refractive index n = 1.7). The transparent film 51 does not have to be a single material, and may be a laminated film of a silicon nitride film and a polyimide resin, for example.

  On the third interlayer insulating film 33, a passivation film 61 made of, for example, silicon nitride, a planarizing film 62, a color filter 63, and an on-chip lens 64 are sequentially formed. In the above-described example, the example of the two-layer wiring has been described, but the wiring of three or more layers may be used.

  In the solid-state imaging device according to the above-described embodiment, the etching stopper film 40 is formed on the surface of one of the wiring layers, particularly on the side surface and the upper surface of the wiring layer. For example, as shown in the plan view of FIG. 5, when the wiring layer closest to the light receiving unit 22 is the first wiring layer M1, the etching stopper film 40 is formed on the side surface and the upper surface of the first wiring layer M1. It is formed. FIG. 4 shows an example in which the etching stopper film 40 is formed only on the surface of the first wiring layer M1. Alternatively, as shown in the plan view of FIG. 6, when both the first wiring layer M1 and the second wiring layer M2 are close to the light receiving unit 22, the first wiring layer M1 and the second wiring layer M2 An etching stopper film 40 is formed on the surface.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS. In the present embodiment, an example in which the first wiring layer M1 has the highest wiring density and is disposed close to the light receiving unit 22 will be described.

  As shown in FIG. 7A, after the element isolation insulating film 21 is formed on the semiconductor substrate 20 by, for example, the STI technique, n-type impurities are ion-implanted into the semiconductor substrate 20 to form the light receiving portion 22. Subsequently, a gate insulating film 23 made of silicon oxide is formed on the semiconductor substrate 20 by a thermal oxidation method. Subsequently, polysilicon is deposited on the gate insulating film 23 by CVD, and the polysilicon film is etched using a resist mask to form the gate electrode 24.

  Next, as shown in FIG. 7B, silicon oxide is deposited on the entire surface of the semiconductor substrate 20 by a CVD method to form an insulating film 25. Subsequently, a silicon nitride film is deposited on the insulating film 25 by a CVD method, and the silicon nitride film is patterned to form an etching stopper film 26 only on the light receiving portion 22. The film thickness of the etching stopper film 26 is, for example, 20 nm.

  Next, as shown in FIG. 8A, a first interlayer insulating film 31 made of, for example, silicon oxide is formed on the entire surface of the semiconductor substrate 20.

  Next, as shown in FIG. 8B, a contact hole is formed in the first interlayer insulating film 31 by etching using a resist mask, and a conductive material is buried in the contact hole, whereby the first plug P1 is formed. Form. The conductive material is, for example, tungsten.

  Next, as shown in FIG. 9A, an aluminum film is deposited on the first interlayer insulating film 31 by sputtering, and the aluminum film is patterned to form the first wiring layer M1.

  Next, as shown in FIG. 9B, a silicon nitride film is deposited on the first wiring layer M1 and the first interlayer insulating film 31 by a plasma CVD method, and the silicon nitride film is patterned to form an etching stopper. A film 40 is formed. By this patterning, the silicon nitride film on the light receiving portion 22 and other than the surface of the first wiring layer M1 is removed. The film thickness of the etching stopper film 40 is, for example, 50 nm.

  Next, as shown in FIG. 10A, a second interlayer insulating film 32 made of, for example, silicon oxide is formed on the first wiring layer M <b> 1 and the first interlayer insulating film 31.

  Next, as shown in FIG. 10B, a contact hole is formed in the second interlayer insulating film 32 by etching using a resist mask, and a conductive material is buried in the contact hole, whereby the second plug P2 is formed. Form. The conductive material is, for example, tungsten.

  Next, as shown in FIG. 11A, on the second wiring layer M2 and the second interlayer insulating film 32, a third interlayer insulating film 33 made of, for example, silicon oxide is formed.

  Next, as shown in FIG. 11B, a resist mask 70 having a pattern of the opening of the waveguide is formed on the third interlayer insulating film 33 by lithography. Subsequently, the interlayer insulating films 31 to 33 are etched using the resist mask 70 to form the opening 50 of the waveguide. At this time, since the first wiring layer M1 closest to the light receiving unit 22 is protected by the etching stopper film 40, the first wiring layer M1 is prevented from being exposed or etched. Etching is stopped by the etching stopper film 26 on the light receiving portion 22.

  Next, as shown in FIG. 12A, the etching stopper film 26 exposed in the opening 50 is removed. Since the thickness of the etching stopper film 40 is larger than that of the etching stopper film 26, the first wiring layer M1 is not exposed. The etching stopper film 26 may be left. Thereafter, the resist mask 70 is removed.

  Next, as shown in FIG. 12B, a transparent film 51 is deposited in the opening 50 and on the third interlayer insulating film 33, and unnecessary on the third interlayer insulating film 33 by the CMP method or the etch back method. Remove the transparent film. As the transparent film 51, a material having a higher refractive index than that of the interlayer insulating films 31 to 33 is used. In the deposition of the transparent film 51, for example, a polyimide resin is deposited or a silicon nitride film is deposited by a plasma CVD method. Alternatively, after depositing a silicon nitride film covering the inner wall of the opening 50 by plasma CVD, polyimide resin may be embedded.

  As the subsequent steps, the passivation film 61, the planarization film 62, the color filter 63, and the on-chip lens 64 are formed on the third interlayer insulating film 33 and the transparent film 51, thereby completing the solid-state imaging device.

  The effects of the solid-state imaging device and the manufacturing method thereof according to the present embodiment will be described.

  In this embodiment, the etching stopper film 40 is formed on the surface of the wiring layer closest to the light receiving unit 22. As a result, the wiring layer can be prevented from being exposed when the opening 50 of the waveguide is formed. Conventionally, in consideration of lithography accuracy of the resist mask 70 for forming the opening 50 and variations in wiring dimensions, it has been necessary to secure a predetermined amount of margin with respect to the closest wiring. As a result, it is necessary to reduce the diameter of the opening 50. On the other hand, in this embodiment, since the wiring layer is protected by the etching stopper film 40, the margin can be eliminated or reduced. In addition, as shown in FIG. 4, when the opening 50 overlapped with the wiring layer is formed, the diameter of the opening 50 can be made larger than the conventional one.

  Since the diameter of the opening 50 can be increased, that is, the diameter of the waveguide constituted by the transparent film 51 can be increased, the light collection sensitivity can be improved. Moreover, since the diameter of the opening part 50 can be enlarged, the aspect ratio of the opening part 50 can be made low and the embedding property of the transparent film 51 in the opening part 50 can be improved.

  FIG. 13 is a schematic configuration diagram of a camera in which the above-described solid-state imaging device is used.

  The camera 100 includes the solid-state imaging device 10 described above, an optical system 101, and a signal processing circuit 102. The camera of the present invention includes a camera module in which the solid-state imaging device 10, the optical system 101, and the signal processing circuit 102 are modularized.

  The optical system 101 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 10. Thereby, in the light receiving unit 22 of the solid-state imaging device 10, incident light is converted into a signal charge corresponding to the amount of incident light.

  The signal processing circuit 102 performs various signal processing on the output signal of the solid-state imaging device 10 and outputs it as a video signal.

  According to the camera including the solid-state imaging device according to the above-described embodiment, it is possible to realize a camera with improved sensitivity.

(Second Embodiment)
FIG. 14 is a cross-sectional view of the solid-state imaging device according to the second embodiment. In this embodiment, an example in which a wiring layer is formed by a damascene process will be described.

  The structure from the semiconductor substrate 20 to the first interlayer insulating film 31 is the same as in the first embodiment. On the first interlayer insulating film 31, a second interlayer insulating film 32 made of, for example, silicon oxide is formed. A conductive material is embedded in the wiring groove formed in the second interlayer insulating film 32, whereby the first wiring layer M1 connected to the first plug P1 is formed. The first wiring layer M1 is, for example, a copper wiring. An etching stopper film 40 made of, for example, silicon nitride is formed on the surface of the first wiring layer M1.

  A third interlayer insulating film 33 is formed on the first wiring layer M 1 and the second interlayer insulating film 32. In the third interlayer insulating film 33, a second plug P2 connected to the first wiring layer M1 is formed.

  A fourth interlayer insulating film 34 is formed on the third interlayer insulating film 33. By burying a conductive material in the wiring groove formed in the fourth interlayer insulating film 34, the second wiring layer M2 connected to the second plug P2 is formed. The second wiring layer M2 is, for example, a copper wiring. In the present embodiment, an example of a dual damascene structure in which the second plug P2 and the second wiring layer M2 are simultaneously formed is shown.

  By removing the interlayer insulating films 31 to 34 located on the light receiving portion 22, an opening 50 of the waveguide is formed. The etching stopper film 26 in the opening 50 is removed. A transparent film 51 is embedded in the opening 50. The transparent film 51 is made of a material having a higher refractive index than the surrounding interlayer insulating films (refractive index n = 1.43 in the case of silicon oxide) 31-34. The transparent film 51 is made of silicon nitride (refractive index n = 2.0 in the case of a silicon nitride film formed by a plasma CVD method) or polyimide resin (refractive index n = 1.7). The transparent film 51 does not have to be a single material, and may be a laminated film of a silicon nitride film and a polyimide resin, for example.

  On the fourth interlayer insulating film 34, a passivation film 61 made of, for example, silicon nitride, a planarizing film 62, a color filter 63, and an on-chip lens 64 are sequentially formed. In the above-described example, the example of the two-layer wiring has been described, but the wiring of three or more layers may be used.

  In the solid-state imaging device according to the present embodiment, the etching stopper film 40 is formed on the surface of one of the wiring layers. In this embodiment, since the wiring layer is formed by the damascene process, the etching stopper film 40 that protects the wiring layer covers the entire surface of the wiring layer. As described in the first embodiment, the etching stopper film 40 may be formed on the surface of the second wiring layer M2.

  Next, a method for manufacturing the solid-state imaging device will be described with reference to FIGS.

  Similarly to the first embodiment, the structure shown in FIG. 15A is reached through the steps shown in FIGS.

  Next, as shown in FIG. 15B, a second interlayer insulating film 32 made of, for example, silicon oxide is formed on the first interlayer insulating film 31.

  Next, as shown in FIG. 16A, a resist mask is formed on the second interlayer insulating film 32, the second interlayer insulating film 32 is etched, and a wiring groove 32 a is formed in the second interlayer insulating film 32. To do. Thereafter, the resist mask is removed.

  Next, as shown in FIG. 16B, a first etching stopper film 40a is formed on the inner wall of the wiring groove 32a, and the first wiring layer M1 is embedded in the wiring groove 32a. For example, a silicon nitride film is formed on the entire surface by plasma CVD, and after patterning the silicon nitride film, a copper film is formed by plating, and an excess copper film on the second interlayer insulating film 32 is removed by CMP. . In patterning the silicon nitride film, the portion of the first plug P1 and the silicon nitride film on the second interlayer insulating film 32 are removed. The first etching stopper film 40a may be formed on at least the side wall of the first wiring layer M1. For this reason, for example, after depositing a silicon nitride film, the entire surface may be etched back to form the first etching stopper film 40a only on the side wall of the wiring trench 32a.

  Next, as shown in FIG. 17A, a silicon nitride film is deposited on the entire surface by plasma CVD, and the silicon nitride film is patterned to form a second etching stopper film 40b on the first wiring layer M1. To do. As a result, the etching stopper film 40 including the first etching stopper film 40a and the second etching stopper film 40b is formed on the surface of the first wiring layer M1.

  Next, as shown in FIG. 17B, a third interlayer insulating film 33 and a fourth interlayer insulating film 34 are formed on the first wiring layer M <b> 1 and the second interlayer insulating film 32. The third interlayer insulating film 33 and the fourth interlayer insulating film 34 may be formed of a single silicon oxide film. Alternatively, the material may be changed between the third interlayer insulating film 33 and the fourth interlayer insulating film 34.

  Next, as shown in FIG. 18A, a wiring groove 34 a is formed in the fourth interlayer insulating film 34 and a connection hole 33 a is formed in the third interlayer insulating film 33 by using a lithography technique and an etching technique. The connection hole 33a is formed so as to expose the first wiring layer M1.

  Next, as shown in FIG. 18B, a conductive material such as copper is deposited on the entire surface, and unnecessary conductive material on the fourth interlayer insulating film 34 is removed by CMP. As a result, the second plug P2 is formed in the connection hole 33a, and the second wiring layer M2 is formed in the wiring groove 34a.

  In subsequent steps, similar to the first embodiment, the interlayer insulating films 31 to 34 are etched to form the opening 50 of the waveguide, and the etching stopper film 26 exposed in the opening 50 is removed. Subsequently, the opening 50 is filled with the transparent film 51, and the passivation film 61, the planarizing film 62, the color filter 63, and the on-chip lens 64 are formed, thereby completing the solid-state imaging device.

  In the second embodiment, the etching stopper film 40 is formed on the surface of the wiring layer closest to the light receiving unit 22 among the wiring layers formed by the damascene process. As a result, the wiring layer can be prevented from being exposed when the opening 50 of the waveguide is formed. As a result, for the same reason as in the first embodiment, the diameter of the waveguide constituted by the transparent film 51 can be increased, so that the light collection sensitivity can be improved. Moreover, since the diameter of the opening part 50 can be enlarged, the aspect ratio of the opening part 50 can be made low and the embedding property of the transparent film 51 in the opening part 50 can be improved.

The present invention is not limited to the description of the above embodiment.
For example, the etching stopper film may be formed only on the wiring around the light receiving unit 22 in the wiring layer of the same layer. An etching stopper film may be formed on a plurality of wiring layers. The etching stopper film 40 may be made of a material different from that of the etching stopper film 26. In the present embodiment, the MOS type solid-state imaging device has been described as an example. However, the present invention may be a CCD (Charge Coupled Device) type solid-state imaging device. In this case, the conductive layer of the present invention corresponds to the light shielding film of the CCD solid-state imaging device. The effect of the present invention can be achieved by forming an etching stopper film on the surface of the light shielding film of the CCD solid-state imaging device.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows an example of a structure of the solid-state imaging device which concerns on 1st and 2nd embodiment. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is a circuit diagram which shows the other example of the circuit structure of a unit pixel. It is sectional drawing of the solid-state imaging device which concerns on 1st Embodiment. It is a top view which shows an example of the pattern of a wiring layer. It is a top view which shows the other example of the pattern of a wiring layer. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 1st Embodiment. It is a block diagram which shows schematic structure of the camera with which the solid-state imaging device which concerns on 1st and 2nd embodiment is applied. It is sectional drawing of the solid-state imaging device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device 11, 11A, 11B ... Unit pixel, 12 ... Pixel array part, 13 ... Vertical selection circuit, 14 ... Column circuit, 15 ... Horizontal selection circuit, 16 ... Horizontal signal line, 17 ... Output circuit, 18 DESCRIPTION OF SYMBOLS ... Timing generator (TG), 20 ... Semiconductor substrate, 21 ... Element isolation insulating film, 22 ... Light receiving part, 23 ... Gate insulating film, 24 ... Gate electrode, 25 ... Insulating film, 26 ... Etching stopper film, 31 ... 1st Interlayer insulating film 32 ... second interlayer insulating film 32a ... wiring groove 33 ... third interlayer insulating film 33a ... connection hole 34 ... fourth interlayer insulating film 34a ... wiring groove 40 ... etching stopper film 40a ... first etching stopper film, 40b ... second etching stopper film, 50 ... opening, 51 ... transparent film, 61 ... passivation film, 62 ... flattening film, 63 ... color filter, 64 ... 70: resist mask, 100 ... camera, 101 ... optical system, 102 ... signal processing circuit, M1 ... first wiring layer, M2 ... second wiring layer, M3 ... third wiring layer, P1 ... first plug , P2 ... Second plug

Claims (5)

A light receiving portion formed on the substrate;
A conductive layer formed on an upper layer of the substrate;
An interlayer insulating film that covers the conductive layer and the substrate and has a waveguide opening on the light receiving portion;
A transparent film embedded in the opening of the interlayer insulating film,
An etching stopper film is formed on the side surface and upper surface of the conductive layer around the opening ,
The opening of the waveguide overlaps the conductive layer on which the etching stopper film is formed . Solid-state imaging device. The conductive layer is a wiring composed of a plurality of layers,
The solid-state imaging device according to claim 1, wherein the etching stopper film is formed on a part of the surface of the wiring around the light receiving portion. The solid-state imaging device according to claim 1, wherein the transparent film has a higher refractive index than the interlayer insulating film. Forming a light receiving portion on the substrate;
Forming an interlayer insulating film and a conductive layer on the substrate;
Removing the interlayer insulating film on the light receiving portion to form an opening of the waveguide;
Embedding a transparent film in the opening, and
In the step of forming the interlayer insulating film and the conductive layer, an etching stopper film is formed on a side surface and an upper surface of the conductive layer around the opening ,
In the step of forming the opening of the waveguide, the opening is formed so as to overlap the conductive layer on which the etching stopper film is formed . A solid-state imaging device;
An optical system for guiding incident light to the imaging unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A light receiving portion formed on the substrate;
A conductive layer formed on an upper layer of the substrate;
An interlayer insulating film that covers the conductive layer and the substrate and has a waveguide opening on the light receiving portion;
A transparent film embedded in the opening of the interlayer insulating film,
An etching stopper film is formed on the side surface and upper surface of the conductive layer around the opening ,
The opening of the waveguide overlaps the conductive layer on which the etching stopper film is formed .

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