JP4972887B2 - Semiconductor device and semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor integrated circuit device, and more particularly to a semiconductor device and a semiconductor integrated circuit device used in a power supply system including a high voltage switching element and an IC that controls driving thereof.

Conventionally, a switching power supply system using a semiconductor device has been proposed as shown in FIG. 4 (see Patent Document 1).
FIG. 4 is a main part circuit diagram of the switching power supply system.

  In this switching power supply system 100, the power supplied from the power supply 101 of about AC100V to 240V and rectified by the rectifier 103 via the fuse 102 is first charged in the power supply capacitor 104, smoothed by the power supply capacitor 104, and transformed into the transformer 105. Is supplied to one end of the primary winding 106. The other end of the primary winding 106 is connected to a drain terminal 122 of a MOSFET 121 as a high voltage switching transistor of the switching power supply control unit 120. When the MOSFET 121 is switched at a frequency of about 100 kHz, high frequency power is supplied to the primary winding 106 of the transformer 105. Part of the chopped high-frequency power is rectified by the diode 107 and charged in the output capacitor 108, and DC power smoothed by the output capacitor 108 is output from the output terminal 109.

  In the switching power supply control unit 120, the power smoothed by the power supply capacitor 104 is charged to the smoothing capacitor 110 through the starting power input terminal 123, the junction field effect transistor (JFET) 124, and the Vcc terminal 125. . Here, when the voltage of the smoothing capacitor 110 rises, the JFET 124 is turned off. Then, the starting power is supplied from the smoothing capacitor 110 to the power supply circuit unit 127 of the control IC 126 of the switching power supply control unit 120 via the Vcc terminal 125.

  The control circuit unit 128 of the control IC 126 uses the starting power stored in the power circuit unit 127 as a power source, and controls the switching of the MOSFET 121 based on a predetermined on / off command. As described above, power is supplied to the primary winding 106 of the transformer 105 by switching the MOSFET 121 at a predetermined frequency. When switching is started in this way and a voltage is generated in the secondary winding 111 of the transformer 105, a part of the power generated in the secondary winding 111 is rectified by the diode 112 and smoothed by the smoothing capacitor 110. , And supplied to the power supply circuit unit 127 via the Vcc terminal 125. The control circuit unit 128 continuously operates with this power.

  As described above, in the switching power supply system 100, the control IC 126 that controls the switching of the MOSFET 121 is a dedicated IC that controls the individual MOSFET 121, and the JFET 124 is used as a starting power supply element of the control IC 126. ing. Conventionally, the JFET 124, the MOSFET 121, and the control IC 126 constituting the switching power supply control unit 120 are individually connected to the outside. However, in recent years, these are integrated on the same semiconductor chip to constitute a semiconductor integrated circuit device. However, the number of parts of the switching power supply system is reduced and the configuration is simplified.

  By the way, as described above, in the switching power supply system 100, the starting power of the control circuit unit 128 of the MOSFET 121 is obtained by rectifying and smoothing the input signal of about AC100V to 240V from the power supply 101 and supplying the JFET 124 from the starting power input terminal 123. Via the power supply circuit unit 127 of the control IC 126. For this reason, the JFET 124 needs to have a breakdown voltage of about 450 V. In order to realize such a breakdown voltage and monolithic, for example, a normally-on lateral JFET is used as the JFET 124.

  FIG. 5 is a schematic plan view of an essential part of an example of a JFET, and FIG. 6 is an enlarged schematic view of a portion F in FIG. 7 is a schematic cross-sectional view of the main part of FIG. 6, wherein (A) is a GG cross-sectional view and (B) is a HH cross-sectional view.

In the JFET 124 shown in FIGS. 5 to 7, a p-type substrate 124a is formed with a p-type well region 124b, an n-type drift region 124c, an n ⁺ -type source region 124d, and an n ⁺ -type drain region 124e. The n ⁺ type source region 124d and the n ⁺ type drain region 124e are formed with an n type drift region 124c interposed therebetween. An n ⁺ -type source contact region 124f and an n ⁺ -type drain contact region 124g are formed in the n ⁺ -type source region 124d and the n ⁺ -type drain region 124e, respectively. 124i is pulled out. The element surface is appropriately protected using an insulating film 124j or the like. 5 and 6, the source wiring 124h, the drain wiring 124i, and the insulating film 124j are not shown.

  In such a JFET 124, the source wiring 124h is connected to the power supply circuit unit 127 shown in FIG. 4, and the drain wiring 124i is connected to the starting power input terminal 123 shown in FIG. The p-type well region 124b corresponds to a gate region and is always grounded.

When an input signal is supplied to the n ⁺ -type drain region 124e through the drain wiring 124i, a drain current flows toward the n ⁺ -type source region 124d, and power is supplied to the power supply circuit unit 127 through the source wiring 124h. Is done. Thereafter, when the activation circuit in the power supply circuit unit 127 rises to a certain voltage, the control IC 126 is activated, and the MOSFET 121 is driven by the control circuit unit 128. As a result, in JFET 124, n ⁺ -type source region 124d is biased to a positive potential. When the n ⁺ -type source region 124d is biased to a positive potential, the channel width W is reduced due to the spread of the depletion layer 124k at the pn junction shown by the dotted line in FIG. 6, and the drain current is reduced. Note that the channel width W is controlled by utilizing the difference in the extent of the depletion layer 124k due to the difference in impurity concentration between the n-type drift region 124c and the n ⁺ -type source region 124d, and by controlling the impurity concentration. Can do.

When a certain drain voltage is applied to the n ⁺ -type drain region 124e, the drain current continues to decrease as the potential of the n ⁺ -type source region 124d rises, and when the channel is cut off, the drain current hardly flows. Therefore, the power supply from the JFET 124 to the power supply circuit unit 127 is almost stopped. Normally, the drain current flowing in the JFET 124 is necessary only when the control IC 126 is activated, and becomes an extra power consumption component after the activation. Therefore, the power consumption of the switching power supply system 100 can be reduced by cutting off the channel and reducing the drain current except when starting up.
JP-A-11-289044

  However, in the JFET 124 shown in FIGS. 4 to 7, the simplest method is to reduce the impurity concentration of the n-type drift region 124c in order to increase the breakdown voltage. If the impurity concentration of the n-type drift region 124c is lowered, the overhang of the depletion layer 124k is increased and the channel width W is narrowed, and the drain current flows through this narrow channel, so that the on-resistance is increased.

  Further, since the temperature coefficient of the on-resistance is positive, for example, the on-resistance increases under a high temperature condition, and the amount of power supplied to the smoothing capacitor 110 decreases. As a result, inconveniences such as the power supply circuit unit 127 being unable to start up and the time required for starting up increase, and the use conditions of the switching power supply system 100 are greatly affected.

  On the other hand, if the on-resistance is low and the power supply amount from the JFET 124 to the smoothing capacitor 110 is also sufficient, it is possible to start up even when the voltage of the input signal is low. It becomes possible to expand the range. Further, since it is possible to charge in a short time until the start-up voltage condition of the power supply circuit unit 127, the capacity of the external smoothing capacitor 110 can be reduced, which is advantageous for downsizing of the switching power supply system 100.

Therefore, the JFET 124 provided on the upstream side of the power supply circuit unit 127 needs to have a low on-resistance in order to obtain a high power supply amount.
In order to reduce the on-resistance of the JFET 124, a method of increasing the concentration of the region most contributing to the on-resistance, that is, the n-type drift region 124c is conceivable. However, since there is a trade-off relationship between on-resistance and breakdown voltage, there is a limit to increasing the concentration in order to reduce the on-resistance without sacrificing the breakdown voltage.

As another means for reducing the on-resistance, a method of widening the channel width W can be considered. However, when the n ⁺ -type drain region 124e of the JFET 124 is used as an input terminal, there is a drawback that the wider the channel width W, the weaker the surge voltage due to static electricity or the like. Furthermore, as the channel width W becomes wider, the cutoff voltage necessary for turning off the drain current increases, and the cutoff voltage of the JFET 124 exceeds the withstand voltage of other integrated devices. Can occur. From this point of view, there is still a limit to increasing the channel width W in order to reduce the on-resistance.

The present invention has been made in view of these points, and an object thereof is to provide a semiconductor device having a high breakdown voltage and a low on-resistance.
Another object of the present invention is to provide a semiconductor integrated circuit device using such a semiconductor device.

In the present invention, in order to solve the above problem, a first conductivity type substrate and a second conductivity type drain provided on the substrate and having a rectangular shape with rounded corners at four corners in plan view. A region, a drift region of a second conductivity type provided on the substrate and surrounding the drain region, and a straight line provided on the substrate and excluding the rounded corners of the drain region across the drift region A plurality of second-conductivity-type first source regions provided facing the respective long-side portions, and linear portions excluding the rounded corners of the drain region across the drift region A plurality of source regions each having a second conductivity type second source region provided opposite to each of the short sides; and a gate region provided on the substrate and joined to the drift region and the plurality of source regions. The first A region where the channel is formed between the drain region and the plurality of source regions, and the region facing the rounded corners of the drain region with the drift region interposed therebetween, , A junction between the drift region and the well region, a spread of a depletion layer formed at the junction between the well region and the drift region, and each of the well region and the plurality of source regions The width of each channel is controlled by the spread of the depletion layer formed at the junction, and the junction between the drift region and each of the plurality of source regions includes the well region and each of the plurality of source regions. A semiconductor device is provided which is located on the drain region side of the junction .

According to such a semiconductor device, the channel formed between the drain region and the plurality of source regions is disposed so as to surround the drain region in a substantially elliptical shape, and more channels are efficiently formed on the substrate. Can be placed. Further, by forming more channels, it is possible to achieve a low on-resistance without increasing the channel width while ensuring an appropriate breakdown voltage.

The present invention also includes a first semiconductor device, a control circuit to which activation power is supplied by the first semiconductor device, and a second semiconductor device whose operation is controlled by the control circuit. Is provided on the substrate, a first conductivity type substrate, a drain region of a second conductivity type that is provided on the substrate and has a rectangular shape with corners rounded at four corners in plan view, A second conductivity type drift region that surrounds the drain region, and a straight long side portion provided on the substrate and excluding the rounded corners of the drain region across the drift region. And a plurality of second conductivity type first source regions provided opposite to each of the straight short sides excluding the rounded corners of the drain region across the drift region. Second conductivity type A plurality of source regions each having a second source region; and a first conductivity type well region which is provided on the substrate and is joined to the drift region and the plurality of source regions and serves as a gate region. A channel is formed between each of the source regions and the plurality of source regions, and a region facing the rounded corner of the drain region across the drift region is a junction between the drift region and the well region. And the spread of the depletion layer formed at the junction between the well region and the drift region and the spread of the depletion layer formed at the junction between the well region and each of the plurality of source regions. The width of each channel is controlled, and a junction between the drift region and each of the plurality of source regions is formed in each of the well region and the plurality of source regions. The semiconductor integrated circuit device, characterized in that in the drain region side than the junction portion is provided.

  According to such a semiconductor integrated circuit device, the channel formed between the drain region and the plurality of source regions is arranged so as to surround the drain region in a substantially elliptical shape, while ensuring an appropriate breakdown voltage, Since semiconductor devices having a low on-resistance without increasing the width are integrated, higher performance can be achieved.

In the present invention, the channel formed between the drain region and a plurality of source regions of the semiconductor device, Ru is disposed so as to surround the drain region in a substantially elliptical shape. As a result, more channels can be efficiently arranged, and a low on-resistance can be achieved without increasing the channel width while ensuring a breakdown voltage.

  When such a semiconductor device is applied to a switching power supply system and used for starting power supply to an IC that controls a switching element, a high power supply capability can be obtained by securing a withstand voltage and a low on-resistance. Thus, it is possible to achieve a wide range of stable operating conditions and downsizing of external parts.

  Further, by integrating such a semiconductor device together with another semiconductor device, for example, a control IC for a switching element used in a switching power supply system, a high-performance semiconductor integrated circuit device can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a schematic plan view of an essential part of an example of a semiconductor device, and FIG. 2 is an enlarged schematic view of a C part in FIG. 3 is a schematic cross-sectional view of the main part of FIG. 2, wherein (A) is a DD cross-sectional view and (B) is an EE cross-sectional view.

The semiconductor device 1 shown in FIG. 1 has a structure in which a plurality of n ⁺ -type source regions 5 are formed so that a channel is arranged in a substantially elliptical shape around the n ⁺ -type drain region 6 when viewed from above. ing. n ⁺ -type drain region 6 is generally planar shape has a shape in which the corners of the rectangle rounded, the n ⁺ -type source region 5, n ⁺ -type drain region 6 as viewed from the plane linearly Are formed so as to face each other, except for rounded corners.

In other words, a channel is formed side by side in a region between the linear portion of the n ⁺ -type drain region 6 and each n ⁺ -type source region 5, and the n ⁺ -type drain region 6 is rounded. A channel is not formed in a region corresponding to the corner portion. Here, a region in which channels are formed side by side is referred to as a channel region 1a, and a region in which no channel is formed is referred to as a breakdown voltage region 1b.

As shown in FIGS. 2 and 3, the channel region 1 a includes a p-type substrate 2, a p-type well region 3, an n-type drift region 4, a plurality of n ⁺ -type source regions 5, and an n ⁺ -type drain region 6. Is formed. Each n ⁺ type source region 5 and n ⁺ type drain region 6 are formed with an n type drift region 4 interposed therebetween. Each n ⁺ -type source region 5 has an n ⁺ -type source contact region 7 formed therein, and each n ⁺ -type drain region 6 has n ⁺ -type drain contact regions 8 corresponding to the number of channels. . A source wiring 7a and a drain wiring 8a are led out from the n ⁺ type source contact region 7 and the n ⁺ type drain contact region 8, respectively. The element surface is appropriately protected using an insulating film 9 or the like. In FIGS. 1 and 2, the source wiring 7a, the drain wiring 8a, and the insulating film 9 are not shown.

  Further, as shown in FIG. 1, the breakdown voltage region 1 b is ensured to have a high breakdown voltage of, for example, 500 V or more mainly by a pn junction between the p-type well region 3 and the n-type drift region 4.

  As described above, in the semiconductor device 1, the number of channels is greatly increased as compared with the prior art by forming a plurality of channels side by side in the channel region 1a. Therefore, even if the channel width W is not changed conventionally, by increasing the number of channels, it is possible to obtain substantially the same effect as the on-resistance when the channel width is widened. As a result, it is possible to configure the semiconductor device 1 having a channel width advantageous for the surge voltage and a low on-resistance. From the current-voltage characteristics of the JFET, since the current changes exponentially in the vicinity of the cutoff voltage, the increase in the cutoff voltage with the increase in the number of channels is negligible.

In order to increase the number of channels and effectively use the device configuration area, here, as described above, a plurality of n ⁺ -type source regions 5 are formed so as to surround the n ⁺ -type drain region 6 in a substantially elliptical shape. Deploy. The advantage of arranging the plurality of channels in a substantially elliptical shape in this way is that a wide region in which the current path formed in the n-type drift region 4 can be formed linearly can be secured.

  As described above, in the semiconductor device 1, a plurality of channels are arranged efficiently in the channel region 1a, and the channel is not arranged in the withstand voltage region 1b. It is possible to achieve both resistance and high breakdown voltage.

The semiconductor device 1 having the configuration shown in FIGS. 1 to 3 can be formed by the following procedure, for example.
First, the p-type well region 3 is selectively formed on the surface layer of the p-type substrate 2. A general p-type impurity can be used as the impurity of the p-type well region 3, and the impurity concentration is set to 8 × 10 ¹⁶ / cm ³ , for example.

Next, the n-type drift region 4 is formed in a state where a part of the p-type well region 3 is inserted inside. A general n-type impurity can be used as the impurity of the n-type drift region 4, and the impurity concentration thereof is set to 3 × 10 ¹⁵ / cm ³ , for example. At this time, the n-type drift region 4 is formed in a state where a part of the n-type drift region 4 enters the p-type well region 3 at a plurality of locations.

Next, an n ⁺ type source region 5 is formed at each location where the n type drift region 4 enters the p type well region 3, and the central region of the p type substrate 2 is opposed to each n ⁺ type source region 5. A substantially rectangular n ⁺ -type drain region 6 having a planar shape with rounded corners is formed. A general n-type impurity can be used as the impurity of each of the n ⁺ -type source region 5 and the n ⁺ -type drain region 6, and the impurity concentration is higher than that of the n-type drift region 4, for example, 8 × 10 ¹⁵ / cm ³ .

Then, the n ⁺ -type source contact region 7 is formed on the surface layer of the n ⁺ -type source region 5, in correspondence with each n ⁺ -type source region 5 in the surface layer of the n ⁺ -type drain region 6 n ⁺ -type drain contact Region 8 is formed. Then, a source wiring 7a and a drain wiring 8a are formed, and the entire surface of the element is covered with an insulating film 9 or the like. Thereby, the basic structure of the semiconductor device 1 is completed.

  The semiconductor device 1 as described above can be used as, for example, the JFET 124 of the switching power supply system 100 that can be realized by the circuit configuration as shown in FIG. Hereinafter, for convenience, description will be given with reference to FIG.

  The switching power supply system 100 includes, for example, a MOSFET 121 as a high breakdown voltage switching transistor, a control IC 126 that is a control circuit for controlling the driving of the MOSFET 121, and a JFET 124 that mainly supplies power to the control IC 126 when the system is started up. The switching power supply control unit 120 is integrated as a semiconductor integrated circuit device.

  In this switching power supply system 100, the input signal supplied from the power supply 101 is rectified and smoothed, and then supplied to the transformer 105 having one end connected to the drain terminal 122 of the MOSFET 121. Is supplied, and this electric power is rectified and smoothed to output DC power to the outside. At this time, the driving of the MOSFET 121 is on / off controlled by the control circuit unit 128 using the starting power stored in the power circuit unit 127 of the control IC 126 as a power source. The startup power is supplied to the power supply circuit unit 127 using the JFET 124, and the rectified and smoothed power supplied from the power supply 101 is supplied to the power supply circuit unit 127 via the JFET 124.

  For example, when the drain wiring of the JFET 124 is connected to the power supply 101 side and the source wiring is connected to the power supply circuit unit 127 side, the smoothing capacitor 110 is connected in parallel to the JFET 124 on the source wiring side. The JFET 124 is turned off by increasing the voltage of the smoothing capacitor 110. Then, after the JFET 124 is turned off, power is supplied from the smoothing capacitor 110 to the power supply circuit unit 127. The smoothing capacitor 110 is supplied with a part of the power generated in the transformer 105 by the switching of the MOSFET 121. As a result, power is continuously supplied from the JFET 124 or the smoothing capacitor 110 to the power supply circuit unit 127 of the control IC 126.

When the semiconductor device 1 as shown in FIGS. 1 to 3 is used for the JFET 124 of the switching power supply system 100 as described above, each source wiring 7 a connected to each n ⁺ type source region 5 of the semiconductor device 1 is, for example, The power supply circuit unit 127 of the control IC 126 of the MOSFET 121 that constitutes the switching power supply control unit 120 is combined into one appropriately. On the other hand, each drain wiring 8a connected to the n ⁺ -type drain region 6 of the semiconductor device 1 is, for example, appropriately combined into one, and an activation power input that supplies power from the power supply 101 to the switching power supply control unit 120. Connected to terminal 123. The p-type well region 3 of the semiconductor device 1 corresponds to a gate region and is always grounded.

When an input signal is supplied to the n ⁺ -type drain region 6 via each drain wiring 8a, a drain current flows from the n ⁺ -type drain region 6 toward each n ⁺ -type source region 5, and this flows into each source wiring 7a. The power is supplied to the power supply circuit portion 127 of the control IC 126 of the MOSFET 121.

Thereafter, when the activation circuit in the power supply circuit unit 127 rises to a certain voltage, the control IC 126 of the MOSFET 121 is activated to drive the MOSFET 121. In the semiconductor device 1, a part of the power generated by driving the MOSFET 121 is supplied to the smoothing capacitor 110 connected to the source wiring 7 a side. As a result, the n ⁺ -type source regions 5 are simultaneously biased to a positive potential. It becomes like this.

When each n ⁺ -type source region 5 is biased to a positive potential, in the channel region 1a of the semiconductor device 1, the channel width W is narrowed due to the spread of the depletion layer 10 as shown by the dotted line in FIG. The drain current decreases. Note that the channel width W of the semiconductor device 1 is based on the fact that the depletion layer 10 in the pn junction portion varies depending on the difference in impurity concentration between the n-type drift region 4 and the n ⁺ -type source region 5. It can be controlled by their impurity concentration.

When a constant voltage is applied to the n ⁺ -type drain region 6, the drain current continues to decrease as the potential of each n ⁺ -type source region 5 rises. When the channel is cut off, the drain current hardly flows, and the semiconductor The power supply from the device 1 to the power supply circuit unit 127 of the control IC 126 of the MOSFET 121 is almost stopped.

  As described above, after the control IC 126 of the MOSFET 121 is activated, the channel of the semiconductor device 1 is cut off, and the power supply from the semiconductor device 1 to the power supply circuit unit 127 of the control IC 126 is stopped, so that an excessive drain current is generated. Thus, the switching power supply system 100 can be reduced in power consumption.

  As described above, the semiconductor device 1 is configured to include the channel region 1a in which a large number of channels are arranged, and the breakdown voltage region 1b that ensures a breakdown voltage without forming channels. By forming a large number of channels in this way, the on-resistance can be reduced without increasing the channel width W, and the power supply capability of the semiconductor device 1 can be increased. In addition, since the region for ensuring the withstand voltage is provided, the on-resistance can be reduced without impairing the withstand voltage.

  Therefore, for example, when this semiconductor device 1 is used for supplying power to the control IC 126 of the MOSFET 121 in the switching power supply system 100 as shown in FIG. 4 described above, it is sufficient even at the time of startup or when the voltage of the input signal is low. Electric power can be supplied, and the range of stable operation conditions of the switching power supply system 100 can be expanded. In addition, since a voltage necessary for startup can be obtained by short-time charging, the capacity of the external capacitor can be reduced, and the switching power supply system 100 can be reduced in size. .

It is a principal part plane schematic diagram of an example of a semiconductor device. It is the C section enlarged schematic diagram of FIG. It is a principal part cross-sectional schematic diagram of FIG. 2, Comprising: (A) is DD sectional drawing, (B) is EE sectional drawing. It is a principal part circuit diagram of a switching power supply system. It is a principal part plane schematic diagram of an example of JFET. It is the F section enlarged schematic diagram of FIG. FIG. 7 is a schematic cross-sectional view of a main part of FIG. 6, where (A) is a GG cross-sectional view and (B) is a HH cross-sectional view.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Channel region 1b Withstand voltage region 2,124a p-type substrate 3,124b p-type well region 4,124c n-type drift region 5,124d n ⁺ -type source region 6,124e n ⁺ -type drain region 7,124f n ⁺ Type source contact region 7a, 124h Source wiring 8, 124g n ⁺ type drain contact region 8a, 124i Drain wiring 9, 124j Insulating film 10, 124k Depletion layer 100 Switching power supply system 101 Power supply 102 Fuse 103 Rectifier 104 Power supply capacitor 105 Transformer 106 1 Secondary winding 107, 112 Diode 108 Output capacitor 109 Output terminal 110 Smoothing capacitor 111 Secondary winding 120 Switching power supply controller 121 MOSFET
122 Drain terminal 123 Start-up power input terminal 124 JFET
125 Vcc terminal 126 IC for control
127 Power circuit part 128 Control circuit part W Channel width

Claims (4)

  A first conductivity type substrate;
  A drain region of a second conductivity type provided on the substrate and having a rectangular shape with corners rounded at the four corners in plan view;
  A drift region of a second conductivity type provided on the substrate and surrounding the drain region;
  A plurality of second-conductivity-type first sources provided on the substrate and opposed to the straight long sides excluding the rounded corners of the drain region across the drift region. And a second source region of the second conductivity type provided opposite to each of the straight short sides excluding the rounded corners of the drain region across the drift region. Source area,
  A well region of a first conductivity type provided on the substrate, joined to the drift region and the plurality of source regions, and serving as a gate region;
  Including
  Channels are formed between the drain region and the plurality of source regions,
  A region facing the rounded corner of the drain region across the drift region is a junction between the drift region and the well region,
  The width of each channel is determined by the spread of the depletion layer formed at the junction between the well region and the drift region and the spread of the depletion layer formed at the junction between the well region and each of the plurality of source regions. Is controlled,
  The junction between the drift region and each of the plurality of source regions is closer to the drain region than the junction between the well region and each of the plurality of source regions.
  A semiconductor device.   The semiconductor device according to claim 1, wherein the drain region and the plurality of source regions have a higher impurity concentration than the drift region.   A first semiconductor device;
  A control circuit to which startup power is supplied by the first semiconductor device;
  A second semiconductor device whose operation is controlled by the control circuit;
  Including
  The first semiconductor device includes:
  A first conductivity type substrate;
  A drain region of a second conductivity type provided on the substrate and having a rectangular shape with corners rounded at the four corners in plan view;
  A drift region of a second conductivity type provided on the substrate and surrounding the drain region;
  A plurality of second-conductivity-type first sources provided on the substrate and opposed to the straight long sides excluding the rounded corners of the drain region across the drift region. And a second source region of the second conductivity type provided opposite to each of the straight short sides excluding the rounded corners of the drain region across the drift region. Source area,
  A well region of a first conductivity type provided on the substrate, joined to the drift region and the plurality of source regions, and serving as a gate region;
  Including
  Channels are formed between the drain region and the plurality of source regions,
  A region facing the rounded corner of the drain region across the drift region is a junction between the drift region and the well region,
  The width of each channel is determined by the spread of the depletion layer formed at the junction between the well region and the drift region and the spread of the depletion layer formed at the junction between the well region and each of the plurality of source regions. Is controlled,
  The junction between the drift region and each of the plurality of source regions is closer to the drain region than the junction between the well region and each of the plurality of source regions.
  A semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 3, wherein the drain region and the plurality of source regions have a higher impurity concentration than the drift region.

Images