JP4963890B2 - 樹脂封止回路装置 - Google Patents
樹脂封止回路装置 Download PDFInfo
- Publication number
- JP4963890B2 JP4963890B2 JP2006207092A JP2006207092A JP4963890B2 JP 4963890 B2 JP4963890 B2 JP 4963890B2 JP 2006207092 A JP2006207092 A JP 2006207092A JP 2006207092 A JP2006207092 A JP 2006207092A JP 4963890 B2 JP4963890 B2 JP 4963890B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- chip electronic
- solder
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 46
- 229910000679 solder Inorganic materials 0.000 claims description 43
- 229920005989 resin Polymers 0.000 claims description 40
- 239000011347 resin Substances 0.000 claims description 40
- 238000002844 melting Methods 0.000 claims description 27
- 230000008018 melting Effects 0.000 claims description 27
- 239000000945 filler Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 description 7
- 238000005304 joining Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Wire Bonding (AREA)
Description
2、12 配線基板
3、13 半導体装置
4、14 チップ電子部品
5、15 外装樹脂
6、16 アンダーフィル
7、17 ランド
8 バンプ
9、19 半田
10 半田の溶融流出
18 ワイヤ
Claims (2)
- 配線基板と、前記配線基板上に実装された半導体装置と、前記半導体装置の周囲に配置されたランドに半田接合された1つ以上のチップ電子部品と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との空間と、前記チップ電子部品の少なくとも一部に接する部分と、に外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、1度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられている
ことを特徴とする樹脂封止回路装置。 - 配線基板と、前記配線基板上のランドに半田接合された1つ以上のチップ電子部品と、前記チップ電子部品の一部の上に実装された半導体装置と、前記半導体装置及び前記チップ電子部品を被覆する外装樹脂と、を有する樹脂封止回路装置において、
前記半導体装置の下面と前記配線基板との間に、外装樹脂よりも低粘度かつ低フィラー充填率である樹脂からなるアンダーフィルが形成されており、
前記アンダーフィルが形成されている部分の前記チップ電子部品の半田接合に、1度目の加熱による溶融温度よりも再度加熱した時の溶融温度が高くなる半田が用いられている
ことを特徴とする樹脂封止回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006207092A JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006207092A JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008016785A JP2008016785A (ja) | 2008-01-24 |
JP4963890B2 true JP4963890B2 (ja) | 2012-06-27 |
Family
ID=39073491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006207092A Expired - Fee Related JP4963890B2 (ja) | 2006-06-30 | 2006-06-30 | 樹脂封止回路装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4963890B2 (ja) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP3763520B2 (ja) * | 2000-12-25 | 2006-04-05 | Tdk株式会社 | はんだ付け用組成物 |
JP2004128288A (ja) * | 2002-10-04 | 2004-04-22 | Renesas Technology Corp | 半導体装置および電子装置 |
JP2004247637A (ja) * | 2003-02-17 | 2004-09-02 | Nec Saitama Ltd | 電子部品の三次元実装構造および方法 |
-
2006
- 2006-06-30 JP JP2006207092A patent/JP4963890B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2008016785A (ja) | 2008-01-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102487020B (zh) | 形成引线上凸块互连的半导体器件和方法 | |
CN100373597C (zh) | 集成电路封装结构及底部填充胶工艺 | |
CN101996902B (zh) | 半导体器件的制造方法 | |
US8039307B2 (en) | Mounted body and method for manufacturing the same | |
TWI419300B (zh) | 內建電子零件之基板及其製造方法 | |
US9258904B2 (en) | Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings | |
US20240145346A1 (en) | Semiconductor device with through-mold via | |
KR20080057156A (ko) | 전자 부품 내장 기판 및 그 제조 방법 | |
EP3301712B1 (en) | Semiconductor package assembley | |
JP2009200067A (ja) | 半導体チップおよび半導体装置 | |
JP4435187B2 (ja) | 積層型半導体装置 | |
JP3847602B2 (ja) | 積層型半導体装置及びその製造方法並びに半導体装置搭載マザーボード及び半導体装置搭載マザーボードの製造方法 | |
JP4963890B2 (ja) | 樹脂封止回路装置 | |
JP4525148B2 (ja) | 半導体装置およびその製造方法 | |
JPH11168116A (ja) | 半導体チップ用電極バンプ | |
KR20110013902A (ko) | 패키지 및 그 제조방법 | |
USRE44500E1 (en) | Semiconductor device and method of forming composite bump-on-lead interconnection | |
JP4561969B2 (ja) | 半導体装置 | |
TWI508243B (zh) | 封裝結構及其製造方法 | |
US20240312856A1 (en) | Electronic component package, circuit module and method for producing electronic component package | |
JP4591715B2 (ja) | 半導体装置の製造方法 | |
JP2010278247A (ja) | 電子部品内蔵モジュール | |
JP2008071792A (ja) | 半導体装置の製造方法 | |
JP2011071378A (ja) | 半導体装置 | |
KR19990034732A (ko) | 금속 입자를 이용한 플립칩 접속 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090630 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120105 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120222 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120316 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120327 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4963890 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150406 Year of fee payment: 3 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |