JP4962421B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a simple configuration and varying the position of a polarity inversion line of a video signal voltage for each frame.

  Conventionally, when driving a liquid crystal panel by applying a voltage, as a method of preventing liquid crystal burn-in, luminance unevenness (crosstalk), and flicker, there has been a method of reversing the polarity of the applied voltage at regular intervals. Are known.

  Specifically, the timing controller uses a polarity control signal (hereinafter referred to as POL signal) for inverting the polarity of the voltage of the video signal (hereinafter referred to as video signal voltage) applied to each pixel of the liquid crystal panel to the source driver. send. The source driver outputs a positive video signal voltage to the liquid crystal panel if the POL signal received at the rising edge of a latch pulse signal (hereinafter referred to as LP signal), which is an output trigger of the video signal, is output to the liquid crystal panel. If the level is Low, a negative video signal voltage is output to the liquid crystal panel.

  In recent years, a one-line inversion method or a two-line inversion method is known as a polarity control method for liquid crystal panels. The 1-line inversion method inverts the polarity of the video signal voltage output for each line, so the power consumption of the source driver increases, and when driving a large screen or a high-definition liquid crystal panel, the source driver generates a large amount of heat. There is a problem of becoming.

  In recent years, in order to improve moving image blur of a liquid crystal panel, a liquid crystal display device of a double speed driving method in which a frame period is driven at 120 Hz has become widespread. When the double speed driving method and the one-line inversion method are combined, there is a problem that the power consumption of the source driver is further increased.

  In contrast, the 2-line inversion method consumes less power than the 1-line inversion method, and can solve the above problems. However, in the 2-line inversion method, when the charging time of the liquid crystal panel is short, a voltage difference is generated between the line whose polarity is inverted due to insufficient charging and the line immediately after this line. In the case of the method, a new problem arises that the horizontal stripes are easily visible on the screen every two lines).

  On the other hand, Patent Document 1 discloses a liquid crystal display device that can change the position of the polarity inversion line for each frame. According to this type of liquid crystal display device, the polarity is not reversed between the same lines for each frame, so that it is possible to prevent the occurrence of horizontal stripes due to insufficient charging.

  However, this type of liquid crystal display device needs to include a circuit set in advance so as to output a video signal voltage having a predetermined pattern for each frame in order to change the position of the polarity inversion line for each frame. . Therefore, in the liquid crystal display device of Patent Document 1, for example, a new problem that a video signal other than the inversion method other than the two-line inversion cannot be generated occurs.

Patent Documents 2 to 4 each disclose a method for driving a liquid crystal panel, but do not disclose a solution to the above problem.
JP 2005-345603 A JP-A-3-167521 JP-A-62-209515 JP 2001-249643 A

  The present invention has been made to solve the above-described problems, and prevents occurrence of flicker and horizontal stripes, and makes the position of the polarity inversion line of the video signal voltage different for each frame with a simple configuration. It is an object of the present invention to provide a liquid crystal display device capable of achieving the above.

The liquid crystal display device according to the present invention in order to achieve the above object, applies the image signal voltage corresponding to the table display data of a plurality of pixels via a plurality of video signal lines corresponding to each of the plurality of pixels A liquid crystal display device , a timing signal for informing a timing for generating a polarity control signal for inverting the polarity of the video signal voltage indicated by positive polarity or negative polarity every N (N ≧ 2) lines , and video A timing controller that outputs a frame timing signal that informs display start timing of a frame, and a polarity control signal output pattern that is an output pattern of the polarity control signal in one frame unit based on the timing signal output by the timing controller a polarity control signal generating means for generating for a negative polarity polarity from positive polarity of the video signal voltage or, So that the position changes from polar to positive polarity becomes discontinuous every frame, on the basis of the said frame timing signal output by the timing controller, said polarity control signal generated by the generating means and said polarity control signal output a pattern, by one line shifted every frame, and the polarity control signal shift means for sequentially outputting a polarity control signal based on the polarity control signal output pattern obtained by the shift, the which are sequentially outputted by said polarity control signal shift means Video signal voltage supply means for supplying the video signal voltage to each of the plurality of video signal lines based on a polarity control signal output .
In the present invention, it is preferable that the timing controller includes the polarity control signal generating means and the polarity control signal shifting means.

  According to the present invention, the video signal voltage supply means supplies, to each of the plurality of video signal lines, the video signal voltage in which the position of the polarity inversion line is different for each frame based on the shifted polarity control signal. . Therefore, since the position of the polarity inversion line can be varied for each frame with a simple configuration, it is possible to prevent the occurrence of flicker and horizontal stripes even when the liquid crystal panel is insufficiently charged.

  Further, by shifting the timing of the polarity control signal, it is possible to easily supply a video signal voltage in which the position of the polarity inversion line is changed for every arbitrary number of lines. Further, since the polarity of the video signal voltage is inverted every N (N ≧ 2) lines, power consumption can be suppressed as compared with the one-line inversion method.

  A liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. As an example of the liquid crystal display device according to the present embodiment, a television (TV) receiver 1 using a liquid crystal panel is shown. FIG. 1 shows a schematic configuration of the TV receiver 1, and FIG. 2 shows a schematic configuration of the liquid crystal display unit 11 of the TV receiver 1.

  The TV receiver 1 includes a liquid crystal display unit 11 that displays video, a speaker 12 that outputs audio, a tuner 13 that is connected to an external antenna and that selects a desired TV broadcast program received by the antenna. A terminal portion 14 provided so as to be exposed to the outside of the housing of the TV receiver 1, a receiving portion 15 for receiving an operation signal transmitted from the remote control device 3 separate from the apparatus main body, and the TV receiver The control part 10 which controls operation | movement of each part of 1 is provided.

  Based on the control by the control unit 10, the TV receiver 1 displays, for example, a TV broadcast program selected by the tuner 13, a video / audio input from an external input device connected to the terminal unit 14, and the like on a liquid crystal display The unit 11 and the speaker 12 can be viewed. The terminal unit 14 is connected to an external device such as a DVD recorder 2 via an HDMI (High-Definition Multimedia Interface) cable or the like.

  The control unit 10 includes a video processing circuit 16 constituted by a CPU, a ROM, a RAM, and other electronic components, an audio processing circuit 17, and the like, and video display data of a program selected by the tuner 13, for example, a terminal unit On the basis of video display data input from the DVD recorder 2 connected to 14, a video signal or the like is supplied to the liquid crystal display unit 11 to display a video.

  As shown in FIG. 2, the liquid crystal display unit 11 includes a liquid crystal panel 111, a source driver 112, a gate driver 113, a plurality of data signal lines (video signal lines) 114, and a plurality of gate signal lines 115. . The source driver 112 and the gate driver 113 are for controlling the liquid crystal panel 111 and are arranged on different sides of the liquid crystal panel 111, respectively. The plurality of data signal lines 114 and the plurality of gate signal lines 115 are arranged around the liquid crystal panel 111.

  The liquid crystal panel 111 includes pixels (not shown) such as TFTs arranged in a matrix in each region where the data signal line 114 and the gate signal line 115 intersect. Each pixel is connected to a data signal line 114 and a gate signal line 115, respectively.

  The source driver 112 supplies to each of the plurality of data signal lines 114 a video signal voltage (hereinafter referred to as a video signal voltage) corresponding to the video display data of each pixel connected to the data signal line 114. Apply. The source driver 112 supplies the video signal voltage as positive polarity or negative polarity based on a polarity control signal (hereinafter referred to as POL signal) for inverting the polarity of the video signal voltage transmitted from the video processing circuit 16. .

  Specifically, the source driver 112 rises a latch pulse signal (a signal for latching video display data for one line of the liquid crystal panel 111; hereinafter referred to as “LP signal”) that is an output trigger of the video signal voltage. Sometimes, when a POL signal higher than a reference level (High level) (hereinafter referred to as a Hi level POL signal) is received, a positive video signal voltage is supplied to the data signal line 114, and the signal level is less than the reference level (Low level). When a POL signal (hereinafter referred to as a Lo level POL signal) is received, a negative video signal voltage is supplied to the data signal line 114. The source driver 112 sets the polarity of the video signal voltage supplied to each of the plurality of data signal lines 114 to N (N ≧ 2) based on the reception pattern of the Hi level POL signal and the Lo level POL signal. Invert line by line. Details will be described later.

  The gate driver 113 supplies an address signal for selectively driving each pixel connected to the gate signal line 115 to the corresponding gate signal line 115.

  Next, the configuration of the video processing circuit 16 will be described with reference to FIGS. FIG. 3 is a block diagram illustrating a schematic configuration of the video processing circuit 16, and FIG. 4 is a block diagram illustrating another example of the schematic configuration of the video processing circuit 16.

  The video processing circuit 16 determines the timing of the POL signal output from the timing controller 161, the N-line inversion POL signal generation circuit (polarity control signal output means) 162 that outputs the POL signal, and the N-line inversion POL signal generation circuit 162. And a shift circuit 163 (polarity control signal shift means) for shifting.

  The timing controller 161 outputs a timing signal for informing the timing for generating the POL signal to the N-line inversion POL signal generation circuit 162, and a frame for informing the shift circuit 163 of the display start timing of the video frame. Output timing signal.

  When the N line inversion POL signal generation circuit 162 receives the timing signal output from the timing controller 161, the N line inversion POL signal generation circuit 162 sets the polarity of the video signal voltage output from the source driver 112 to the shift circuit 163 as N (N ≧ 2). A POL signal for inversion for each line is generated and sequentially output. Each of the POL signals output from the N line inversion POL signal generation circuit 162 corresponds to each line of the liquid crystal panel 111.

  The output pattern of the POL signal sequentially output from the N-line inversion POL signal generation circuit 162 (hereinafter referred to as the POL signal output pattern) is predetermined for each number of polarity lines to be inverted. It is stored in advance in the N line inversion POL signal generation circuit 162.

  Specifically, for example, when the polarity of the video signal voltage is inverted every two lines, the POL signal in the order of “Hi level POL signal, Hi level POL signal, Lo level POL signal, Lo level POL signal”. Or a POL signal output pattern that outputs a POL signal in the order of “Lo level POL signal, Lo level POL signal, Hi level POL signal, Hi level POL signal”. One is stored in the N-line inversion POL signal generation circuit 162.

  The shift circuit 163 has a frame counter 163a for counting and storing the number of displayed frames based on the frame timing signal received from the timing controller 161. The shift circuit 163 shifts the output timing of the POL signal based on the POL signal output pattern output from the N-line inverted POL signal generation circuit 162 for each frame, and then shifts the shifted POL signal to the source driver. 112 are sequentially output. Therefore, the video signal voltage output from the source driver 112 based on the POL signal based on the shifted POL signal output pattern changes the polarity of the video signal voltage from positive polarity to negative polarity, or from negative polarity to positive polarity. The position (hereinafter referred to as polarity inversion line position) is discontinuous for each frame.

  Specifically, for example, when the polarity of the video signal voltage is inverted every two lines, the shift circuit 163 receives the “Hi level POL signal, Hi level POL signal, Lo level from the N line inversion POL signal generation circuit 162. When a POL signal output pattern in the order of “POL signal of POL signal and POL signal of Lo level” is received, the output timing of the POL signal is shifted without shifting the output timing of the POL signal in an arbitrary k-th frame. The POL signal is sequentially output to the source driver 112 in the order of “level POL signal, Lo level POL signal, Lo level POL signal”. In the (k + 1) th frame, the POL signal output pattern is shifted by one line, and the POL is in the order of “Hi level POL signal, Lo level POL signal, Lo level POL signal, Hi level POL signal”. The signals are sequentially output to the source driver 112.

  As shown in FIG. 4, the video processing circuit 16 may include an N-line inversion POL signal generation circuit 162 and a shift circuit 163 in the timing controller 111 and may be a single chip.

  Next, video signal voltage output processing based on the shifted POL signal will be described with reference to the flowchart shown in FIG. Here, it is assumed that the shift circuit 163 has already received the POL signal output pattern from the N-line inversion POL signal generation circuit 162.

  When receiving the frame timing signal from the timing controller 161 (S1), the shift circuit 163 determines the value of the frame counter 163a (S2), and performs a shift process for shifting the POL signal output pattern based on this value. (S3). Details of the shift process will be described later.

  Then, the shift circuit 163 sequentially outputs the POL signal to the source driver 112 based on the POL signal output pattern shifted by the process of S3 (S4). The source driver 112 applies a positive or negative video signal voltage to each of the plurality of data signal lines 114 based on the POL signal output based on the POL signal output pattern shifted by the shift circuit 163. (S5).

  Next, details of the shift processing will be described with reference to the flowchart shown in FIG. Here, the polarity of the video signal voltage is inverted every two lines. The initial value of the counter frame value is 1.

  First, when the value of the frame counter 163a is (4m (m is an integer equal to or greater than zero) +1) (YES in S31), the shift circuit 163 does not shift the received POL signal output pattern (S34).

  On the other hand, when the value of the frame counter 163a is not (4m + 1) (NO at S31), when the value of the frame counter 163a is (4m + 2) (YES at S32), the shift circuit 163 receives the received POL signal output pattern. Is shifted by one line (S35).

  On the other hand, when the value of the frame counter 163a is not (4m + 2) (NO in S32), when the value of the frame counter 163a is (4m + 3) (YES in S33), the shift circuit 163 receives the received POL signal output pattern. Is shifted by two lines (S36).

  On the other hand, when the value of the frame counter 163a is not (4m + 3) (NO in S33), the shift circuit 163 shifts the received POL signal output pattern by three lines (S37).

  Next, the change in polarity of the video signal voltage supplied from the source driver 112 will be described with reference to the graphs shown in FIGS. 7 to 9, the vertical axis indicates the line number in an arbitrary column of the liquid crystal panel 111, and the horizontal axis indicates the frame number. N in the figure is a positive integer.

  FIG. 7 shows changes in polarity when the polarity of the video signal voltage is inverted every two lines. For example, as shown in FIG. 7, the polarity inversion line position to the first positive polarity for each frame is the first line for n frames, the second line for n + 1 frames, and 3 for n + 2 frames. It is the 4th line in the case of n + 3 frames. Then, in the case of n + 4 frames, it becomes the first line, and thereafter, the polarity inversion line position for each frame similarly changes. Accordingly, the polarity is sequentially inverted every two lines, and the polarity inversion line position is different for each frame.

  FIG. 8 shows changes in polarity when the polarity of the video signal voltage is inverted every three lines. For example, as shown in FIG. 8, the polarity inversion line position to the first positive polarity for each frame is the first line for n frames, the second line for n + 1 frames, and 3 for n + 2 frames. It is the 4th line at the time of n + 3 frame, the 5th line at the time of n + 4 frame, and the 6th line at the time of n + 5 frame. Then, in the case of n + 6 frames, it becomes the first line, and thereafter, the polarity inversion line position for each frame similarly changes. Accordingly, the polarity is sequentially inverted every three lines, and the polarity inversion line position is different for each frame.

  FIG. 9 shows changes in polarity when the polarity of the video signal voltage is inverted every four lines. For example, as shown in FIG. 9, the polarity inversion line position to the first positive polarity for each frame is the first line for n frames, the second line for n + 1 frames, and 3 for n + 2 frames. It is the 4th line at the time of n + 3 frame, the 5th line at the time of n + 4 frame, the 6th line at the time of n + 5 frame, the 7th line at the time of n + 6 frame, and the 8th line at the time of n + 7 frame. It is the line eye. Then, in the case of n + 9 frames, it becomes the first line, and thereafter the polarity inversion line position for each frame similarly changes. Therefore, the polarity is sequentially inverted every four lines, and the polarity inversion line position is different for each frame.

  As described above, in the TV receiver 1 according to the present embodiment, the source driver 112 determines the position of the polarity inversion line based on the POL signal output based on the POL signal output pattern shifted by the shift circuit. A video signal voltage varied for each frame is supplied to each of a plurality of data signal lines. For this reason, since the position of the polarity inversion line can be changed for each frame with a simple configuration, it is possible to prevent the occurrence of flicker and horizontal stripes even when the liquid crystal panel 111 is insufficiently charged.

  Further, by shifting the timing of the polarity control signal, the source driver 112 can easily supply a video signal voltage in which the position of the polarity inversion line is changed for each arbitrary number of lines. Further, since the polarity of the video signal voltage is inverted every N (N ≧ 2) lines, power consumption can be suppressed as compared with the one-line inversion method.

  In addition, this invention is not restricted to the structure of the said embodiment, A various deformation | transformation is possible in the range which does not change the meaning of invention.

1 is a block diagram showing a schematic configuration of a TV receiver according to an embodiment of the present invention. The block block diagram of the liquid crystal display part of the said TV receiver. The block diagram which shows schematic structure of the video processing part of the said TV receiver. The block diagram which shows another example of schematic structure of the video processing part of the said TV receiver. The flowchart which shows the procedure of the output process of the video signal voltage in the said TV receiver. The flowchart which shows the procedure of the shift process in the output process of the said video signal voltage. The graph which shows the polarity change of the video signal voltage in the said TV receiver. The graph which shows the polarity change of the video signal voltage in the said TV receiver. The graph which shows the polarity change of the video signal voltage in the said TV receiver.

Explanation of symbols

1 TV receiver (liquid crystal display)
16 Video processing circuit 112 Source driver (video signal voltage supply means)
114 Data signal line (video signal line)
162 N-line inversion POL signal generation circuit (polarity control signal output means)
163 Shift circuit (polarity control signal output means)

Claims (2)

The video signal voltage corresponding to the table display data of a plurality of pixels, a liquid crystal display device to be applied through a plurality of video signal lines corresponding to each of the plurality of pixels,
A timing signal for informing a timing for generating a polarity control signal for inverting the polarity of the video signal voltage indicated by positive polarity or negative polarity for every N (N ≧ 2) lines , and a display start timing of the video frame are informed. A timing controller that outputs a frame timing signal;
Polarity control signal generating means for generating a polarity control signal output pattern which is an output pattern of the polarity control signal in one frame unit based on the timing signal output by the timing controller;
The polarity of the video signal voltage is so positioned that varies negative from positive polarity or negative polarity, to the positive polarity becomes discontinuous every frame, on the basis of said frame timing signal output by said timing controller, A polarity control signal shift that shifts the polarity control signal output pattern generated by the polarity control signal generation means by one line for each frame and sequentially outputs a polarity control signal based on the shifted polarity control signal output pattern Means,
And a video signal voltage supply means for supplying the video signal voltage to each of the plurality of video signal lines based on the polarity control signal output sequentially output by the polarity control signal shift means. Display device. The liquid crystal display device according to claim 1, wherein the timing controller includes the polarity control signal generation unit and the polarity control signal shift unit.

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