JP4956355B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a stack type DRAM capacitor.

  In recent years, along with the high integration of semiconductor integrated circuits, miniaturization of minimum processing dimensions and reduction of memory cells have been progressing. Therefore, the capacitor area in the memory cell has become very small. As the memory cell area decreases, the capacitor capacity (storage capacity; Cs) also decreases. However, the capacitor capacity needs to be a certain value or more in terms of sense sensitivity, soft error, circuit noise, and the like.

  The following two methods have been studied as methods for increasing the capacitor capacity. The first method is to increase the surface area of the capacitor as much as possible by forming the capacitor three-dimensionally. The second method uses an insulating film having a high dielectric constant (so-called high ε film) as the capacitor insulating film.

  However, after the generation of the design rule of 0.15 microns or less (1G bit DRAM generation or later), processing of a storage node electrode (SN electrode) having a complicated three-dimensional shape becomes increasingly difficult. Therefore, as a method of increasing the capacitor capacity, a method of using an insulating film having a high dielectric constant as the capacitor insulating film becomes very important.

A typical example of an insulating film having a high dielectric constant is a (Ba, Sr) TiO ₃ (hereinafter abbreviated as BST) film. In the case of using a BST film, studies have been made to use a Ru film in which an oxide exhibits metal conductivity (RuO ₂ film is conductive) or a laminated film of RuO ₂ film / Ru film as an SN electrode (1995). IEDM Technical Digest, S. Yamamichi et al., P.119-p.122). Hereinafter, a capacitor of the stacked DRAM having such a configuration will be briefly described with reference to FIG.

  First, the element isolation region 102 is formed on the P-type Si substrate 101. Thereafter, a gate insulating film 103a, a gate electrode (poly Si film 103b and WSi film 103c), a SiN film 104, a source / drain diffusion layer 105, a SiN film 106, and an interlayer insulating film 108 are formed.

  Next, poly Si films 107a and 107b are embedded in the SN electrode contact region and the bit line contact region, respectively. Thereafter, interlayer insulating films 109 and 111 are formed, and bit lines 110 and SN contacts are formed.

Next, a TiSi _x film 113, a TiN film 114, a Ru film 115, and a RuO ₂ film 116 are stacked. These laminated films are patterned using a normal lithography method and an RIE method to form an SN electrode. Thereafter, a high dielectric constant insulating film 117 such as a BST film is formed, and an upper electrode 118 (for example, a laminated film of TiN film / Al film) is formed.

  However, when the SN electrode is formed by the above conventional manufacturing method, there are the following problems.

  By forming the SN electrode by using the normal lithography method and the RIE method, the upper corner of the SN electrode becomes a right angle (in some cases, an acute angle). Therefore, the leakage current of the capacitor insulating film increases due to the electric field concentration at the upper corner. Further, since the SN electrode is patterned by the RIE method, the roughness of the side surface of the resist is amplified and transferred to the side surface of the SN electrode. Therefore, the leakage current of the capacitor insulating film increases due to the side surface roughness of the SN electrode.

  Further, since the SN electrode is formed by lithography, the SN electrode is likely to be displaced. Therefore, there is a possibility that a part of the plug is exposed when the capacitor insulating film is formed. Therefore, the metal plug may be oxidized when forming the BST film serving as the capacitor insulating film. When the metal plug is oxidized, there are problems that the electrical connection between the SN electrode and the plug is deteriorated, and that the plug film is easily peeled off due to volume expansion due to oxidation. To solve this problem, proposals have been made to form a barrier metal layer on the plug surface, but the oxidation resistance of the barrier metal material is insufficient, and the number of manufacturing processes for forming the barrier metal layer is increased. There is a problem such as.

  Further, when the SN electrode is formed on the plug and the insulating film, the SN electrode can provide good electrical connection to the plug and good adhesion to the insulating film. It is preferable to use an electrode material. However, it is not easy to form an SN electrode that satisfies these requirements.

  As described above, the conventional stacked DRAM capacitor has several problems due to the structure of the SN electrode and the manufacturing method, and a capacitor that is always satisfactory in terms of the electrical characteristics and reliability of the capacitor has been obtained. There wasn't.

  The present invention has been made to solve the above-described conventional problems, and an object thereof is to provide a semiconductor device having a capacitor excellent in electrical characteristics, reliability, and the like, and a manufacturing method thereof.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor, a capacitor insulating film formed on an upper surface and a side surface of the lower electrode, and an upper electrode formed on the capacitor insulating film. In the semiconductor device having a charge holding capacitor, the side surface of the lower electrode is formed so as to gradually spread downward from above, and the side surface near the bottom of the lower electrode is connected to the capacitor insulating film. Are in contact with different insulating films.

  According to the present invention, since the side surface of the lower electrode (corresponding to the storage node electrode) is formed so as to gradually spread from the upper side to the lower side, the upper corner of the lower electrode has an obtuse angle. Therefore, the electric field concentration at the upper corner can be relaxed, and the leakage current of the capacitor insulating film can be reduced. Moreover, since the coverage (coverage) of the capacitor insulating film can be improved, it is possible to promote the thinning of the capacitor insulating film and increase the capacitance of the capacitor. In addition, since the uniformity of the film thickness of the upper electrode (corresponding to the plate electrode) of the capacitor can be improved, a stable capacitor can be configured. Furthermore, since the side area of the lower electrode can be increased, the capacitor capacity can also be increased.

  In the present invention, the side surface near the bottom of the lower electrode is in contact with an insulating film different from the capacitor insulating film. When the side surface of the lower electrode is formed so as to gradually spread from the upper side to the lower side, the lower corner of the lower electrode becomes an acute angle, and the electric field may concentrate. In the present invention, since the insulating film is in contact with this portion, the leakage current of the capacitor insulating film due to electric field concentration can be suppressed.

  Thus, according to the present invention, the leakage current of the capacitor can be reduced and the capacitor capacity can be increased. Therefore, a stacked DRAM having excellent reliability and characteristics can be obtained.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a base on which a MIS transistor is formed, and a part of the insulating film is removed so that a side surface gradually spreads from top to bottom. A step of forming a hole; a step of embedding a conductive film connected to one of the source and drain of the MIS transistor in the hole and serving as a lower electrode of the capacitor; and removing the insulating film to form at least a side surface of the conductive film The method includes a step of exposing a part, a step of forming a capacitor insulating film on the upper surface and the exposed side surface of the conductive film, and a step of forming an upper electrode of the capacitor on the capacitor insulating film. .

  According to the present invention, since the lower electrode is formed by embedding the conductive film in the hole formed in the insulating film, the side surface of the lower electrode can be formed smoothly. Therefore, it is possible to suppress an increase in the leakage current of the capacitor insulating film due to the side surface roughness of the lower electrode.

  In the invention, the step of removing a part of the insulating film and forming a hole whose side surface gradually widens from the top to the bottom includes, for example, removing a part of the insulating film and the side surface from the top to the bottom. Forming a first hole that gradually widens toward the surface, and forming a second hole that expands the first hole by etching the insulating film in which the first hole is formed. It consists of.

  Thus, by forming the lower electrode in the second hole obtained by enlarging the first hole, the size of the lower electrode can be made larger than the size determined by lithography. Therefore, the surface area of the lower electrode can be increased, and the capacitor capacity can be increased.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor, a capacitor insulating film formed on an upper surface and a side surface of the lower electrode, and an upper electrode formed on the capacitor insulating film. In the semiconductor device having a charge holding capacitor, the side surface near the bottom of the lower electrode is recessed, and the recessed portion is in contact with an insulating film different from the capacitor insulating film. .

  According to the present invention, the insulating film bites into the recessed portion of the side surface near the bottom of the lower electrode from the outside. Therefore, compared with the case where the whole bottom face of a lower electrode is formed on the flat surface, the adhesiveness with the base | substrate of a lower electrode can be improved. Therefore, it is possible to configure a highly reliable stack DRAM.

  In the present invention, the side surface above the recessed portion of the lower electrode may be formed so as to gradually spread from the upper side to the lower side.

  By adopting such a configuration, the leakage current of the capacitor can be reduced and the capacitance of the capacitor can be increased. Therefore, a stacked DRAM having excellent reliability and characteristics can be obtained.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a base on which a MIS transistor is formed, and forming a second insulating film on the first insulating film; Removing a part of the first and second insulating films to form a first hole; and selectively etching the second insulating film with respect to the first insulating film to Forming a second hole in which the upper portion of the hole is enlarged, and embedding a conductive film which is connected to one of the source and drain of the MIS transistor and serves as a lower electrode of the capacitor in the second hole Removing the second insulating film to expose at least a part of the side surface of the conductive film; forming a capacitor insulating film on the upper surface and the exposed side surface of the conductive film; Capacitor top electrode on membrane Characterized in that comprising the step of forming.

  According to the present invention, since the lower electrode is formed by embedding the conductive film in the hole formed in the insulating film, it is possible to suppress an increase in the leakage current of the capacitor insulating film due to the side surface roughness of the lower electrode. Further, since the lower electrode is formed in the second hole obtained by enlarging the first hole, the dimension of the lower electrode can be made larger than the dimension determined by lithography. Therefore, the surface area of the lower electrode can be increased, and the capacitor capacity can be increased.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor via a plug, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. A semiconductor device having a charge retention capacitor, comprising a titanium nitride (TiN) film, a titanium aluminum nitride (TiAlN) film, and a titanium silicon nitride (TiSiN) film between the lower electrode and the plug. Tantalum silicon nitride (TaSiN) film, ruthenium (Ru) film, iridium (Ir) film, laminated film of ruthenium film and ruthenium oxide film (preferably a ruthenium oxide film is formed on the ruthenium film), A laminated film of an iridium film and an iridium oxide film (an iridium oxide film is formed on the iridium film) And these films (titanium nitride film, titanium aluminum nitride film, titanium silicon nitride film, tantalum silicon nitride film, ruthenium film, iridium film, ruthenium film and ruthenium oxide film) Any one of the conductive films selected from the multilayer films of any combination of the multilayer film, the iridium film and the iridium oxide film) is formed in a self-aligned manner with respect to the plug. It is characterized by.

  In the present invention, a conductive film such as titanium aluminum nitride having excellent oxidation resistance is formed between the lower electrode and the plug in a self-aligned manner with respect to the plug. Therefore, when the capacitor insulating film is formed, the exposed portion of the plug can be prevented from being oxidized. Therefore, a stacked DRAM having excellent reliability can be configured.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor via a plug, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. A semiconductor device having a charge retention capacitor, wherein a conductive film obtained by nitriding the plug is formed between the lower electrode and the plug in a self-aligned manner with respect to the plug. And

  Also in the present invention, like the above-described invention, when the capacitor insulating film is formed, it is possible to prevent the exposed portion of the plug from being oxidized. In addition, since the conductive film in which the plug is nitrided is used, a lithography process or the like for forming the conductive film is not necessary, and the manufacturing process can be simplified.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor via a plug, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The lower electrode includes a first conductive portion formed on the plug in a self-aligned manner with respect to the plug, and a side surface of the first conductive portion. Or it consists of the 2nd electroconductive part formed in the side surface and the upper surface, It is characterized by the above-mentioned.

  In the present invention, the first conductive portion is formed in a self-aligned manner with respect to the plug. Therefore, the electrical connection between the lower electrode and the plug can be ensured. Further, when the capacitor insulating film is formed, it is possible to prevent the exposed portion of the plug from being oxidized.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film having a hole on a base on which a MIS transistor is formed, and a plug connected to one of a source or a drain of the MIS transistor in the hole. A step of forming the upper surface of the plug so as to be positioned at an intermediate height of the hole, a step of forming a first conductive film on the plug in the hole, and removing a part of the insulating film. Exposing at least a part of a side surface of the first conductive film, forming a second conductive film on the exposed side surface or the exposed side surface and the top surface of the first conductive film, and the first And a step of forming a capacitor insulating film on a lower electrode of the capacitor constituted by the second conductive film, and a step of forming an upper electrode of the capacitor on the capacitor insulating film.

  The present invention includes a lower electrode connected to one of a source and a drain of a MIS transistor via a plug, a capacitor insulating film formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. The lower electrode is embedded in a hole in which the plug is embedded, and is formed in a self-aligned manner with respect to the plug; and A first component that is formed on the first component and on a region outside the first component and that has a cross-sectional area wider than a cross-sectional area of the first component; The part and the second constituent part are integrally formed of a continuous film.

  According to the present invention, the first component of the lower electrode is formed in a self-aligned manner with respect to the plug. Therefore, the electrical connection between the lower electrode and the plug can be ensured. Further, when the capacitor insulating film is formed, it is possible to prevent the exposed portion of the plug from being oxidized. Moreover, since the 1st structure part and 2nd structure part of a lower electrode are integrally formed by the continuous film, the adhesiveness with the base | substrate of a lower electrode can be improved. Therefore, a stacked DRAM having excellent reliability and characteristics can be obtained.

  In the present invention, the side surface near the bottom of the second component of the lower electrode may be in contact with an insulating film different from the capacitor insulating film.

  In the present invention, the second component of the lower electrode is formed such that the side surface gradually narrows from the upper side to the lower side, or the side surface is formed so as to gradually widen from the upper side to the lower side. It may be.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film having a first hole on a base on which a MIS transistor is formed, and a source of the MIS transistor or a source of the MIS transistor in the first hole. Forming a plug connected to one of the drains so that an upper surface of the plug is positioned at a height in the middle of the first hole; and on the region corresponding to the first hole and the first hole Forming a second insulating film having a second hole on the outer region of the semiconductor substrate, embedding a conductive film on the plug and in the second hole in the first hole, and the second Removing the insulating film to expose at least a part of a side surface of the conductive film; forming a capacitor insulating film on a lower electrode of the capacitor constituted by the conductive film; and a capacitor on the capacitor insulating film Shape the top electrode Characterized in that comprising the step of.

  According to the present invention, by improving the lower electrode and the like of the capacitor, it is possible to reduce the leakage current of the capacitor and increase the capacitance of the capacitor, and to obtain a semiconductor device having excellent reliability and characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 to FIG. 11 are process diagrams sequentially showing the manufacturing process of the stack type DARM according to the first embodiment of the present invention. In each of these drawings, (a) is a plan view of a memory cell portion, (b) is a plan view of a peripheral circuit portion, (c) is a cross-sectional view taken along line AA ′ of (a), and (d) is a cross-sectional view of (a). BB 'sectional drawing, (e) respond | corresponds to CC' sectional drawing of (b).

  The stacked DRAM of this embodiment is basically the same structure as the conventional stacked DRAM except for the structure of the storage node electrode (SN electrode). The difference from the conventional stacked DRAM is that an SN electrode is formed by embedding a conductive film in a groove formed in an insulating film, and the side surface of the SN electrode is forward tapered.

  Here, the case where an N channel MOS transistor is used as the MOS transistor in the memory cell portion and the peripheral circuit portion will be described, but the same applies to the case where a P channel MOS transistor is used.

First, as shown in FIG. 1, a P-type silicon substrate 1 (or N-type silicon substrate) having an impurity concentration of about 5 × 10 ¹⁵ cm ⁻³ and a (100) plane is prepared. Subsequently, a P well is formed in the N channel transistor region, and an N well is formed in the P channel transistor region (not shown). Subsequently, a groove is dug in the silicon substrate 1 using a reactive ion etching (RIE) method. By embedding an insulating film in the groove, an STI (Shallow Trench Isolation) region 2 (a trench depth of about 0.2 μm) is formed.

Next, a silicon oxide film having a thickness of about 60 nm is formed as the gate insulating film 3 of the transistor. A conductive film to be the gate electrode 4 is formed on the gate insulating film 3. This conductive film becomes the word line 4 in the memory cell portion. In this example, the structure of the gate electrode 4, in order to reduce the resistance, a polycide structure (e.g., laminated structure comprising a multilayer film of poly-Si film 4a and WSi ₂ film 4b, the poly-Si film 4a and WSi ₂ film 4b Each film thickness is about 50 nm). In addition, as a gate electrode structure, you may use the structure of only a poly Si film, or the laminated structure which consists of a poly Si film and W film | membrane.

The gate electrode 4 is processed as follows. First, a silicon nitride film (Si ₃ N ₄ film) is formed as a gate cap film 5 on a conductive film to be a gate electrode. This gate cap film 5 serves as an etching stopper for the gate electrode in a later step. Thereafter, a resist pattern (not shown) is formed on the gate cap film 5, and the gate cap film 5 is processed using the resist pattern as a mask. Further, the gate electrode 4 is processed using the processed gate cap film 5 as a mask.

Next, rapid thermal oxidation is performed in an oxygen atmosphere at 1050 ° C. for about 100 seconds by an RTO (Rapid Thermal Oxidation) method to form a so-called post-oxide film (not shown). This step is performed in order to improve the breakdown voltage between the gate electrode 4 and the impurity diffusion layer 6 (formed in a later step). Next, an n ⁻ impurity diffusion layer 6 to be a source / drain is formed by ion implantation using a resist pattern (not shown) and the gate electrode 4 as a mask.

  Next, as a stopper film, a silicon nitride film 7 (for example, a film thickness of about 20 nm) is deposited on the entire surface by the LP-CVD method. Thereafter, a BPSG film is deposited on the entire surface with a thickness of about 500 nm by the CVD method as the interlayer insulating film 8. Thereafter, the interlayer insulating film 8 is polished and planarized by a CMP (Chemical Mechanical Polish) method. At this time, the thickness of the interlayer insulating film 8 on the gate cap film 5 is set to about 100 nm. By this CMP process, almost the entire surface of the substrate is flattened.

In addition to the n ⁻ diffusion layer 6, an n ⁺ diffusion layer may be formed as the source / drain as follows. After forming the n ⁻ diffusion layer 6, a silicon nitride film (for example, a film thickness of about 20 nm) is deposited on the entire surface by LP-CVD. Subsequently, a sidewall film made of a silicon nitride film is formed on the sidewall portion of the gate electrode by RIE. Subsequently, ion implantation is performed on the silicon substrate 1 using the resist mask, the sidewall film, and the gate electrode as a mask to form an n ⁺ source / drain diffusion layer. Thereafter, a silicon nitride film (for example, a film thickness of about 20 nm) is deposited on the entire surface as a stopper film by the LP-CVD method.

  Next, as shown in FIG. 2, a resist 9 is formed on the interlayer insulating film 8. Etching is performed using the resist 9 as a mask to form a contact hole 10 for connecting the impurity diffusion layer 6 to the bit line and the SN electrode.

In this contact hole etching, a high selection ratio RIE method is used such that the etching rate is about 10 or more between the BPSG film used for the interlayer insulating film 8 and the silicon nitride film used as the stopper film 7 (BPSG). The etching rate of the film should be 10 times faster than the silicon nitride film). By using such an etching method, it is possible to prevent a short circuit between the gate electrode 4 and the n ⁺ -type poly-Si film embedded in the contact hole 10 in a later step. Further, by using the stopper film 7 on the gate electrode 4 and the resist film 9 on which the rectangular pattern is formed, the hole pattern can be made rectangular, so that the contact hole area can be increased.

Next, as shown in FIG. 3, an n ⁺ -type poly-Si film doped with phosphorus (P ⁺ ) or arsenic (As ⁺ ) as an impurity is deposited on the entire surface by LP-CVD. Subsequently, an n ⁺ -type poly-Si film is left only in the contact hole by CMP or etch-back to form a poly-Si plug 11. The poly-Si plug 11 is electrically connected to the source / drain diffusion layer and becomes an SN contact 12 and a BL contact 13.

  Next, as shown in FIG. 4, a BPSG film as an interlayer insulating film 14 is deposited on the entire surface by a CVD method with a thickness of about 300 nm. Subsequently, a TEOS oxide film (interlayer insulating film 15) is deposited to a thickness of about 100 nm by a CVD method as an etching stopper during CMP.

  Next, contact holes and trenches are formed in the interlayer insulating films 14 and 15 by using a normal lithography method and an RIE method. A bit line contact 16 and a bit line (BL) 17 are formed by embedding a conductive material in the contact hole and groove. The poly Si plug 11 and the bit line 17 are electrically connected by the bit line contact 16 and the bit line 17. The bit line contact 16 and the bit line 17 are formed by using a so-called dual damascene process.

  For example, a laminated film composed of a W film / TiN film / Ti film is embedded in a linear groove (depth of about 350 nm), and the W film embedded in the groove is etched by about 100 nm. Subsequently, a SiN film is deposited on the entire surface to a thickness of about 300 nm. Further, the SiN film 18 is selectively embedded only on the W film or the like to be the bit line 17 by CMP or CDE (Chemical Dry Etching). At this time, contact holes and grooves are also formed in advance in the contact region of the peripheral circuit portion. In this way, when the bit line contact and the bit line are formed by the dual damascene process, the contact plug 19 that is electrically connected to the source / drain diffusion layer can be formed in the peripheral circuit portion at the same time. .

  Next, as shown in FIG. 5, contact holes reaching the poly-Si plug (SN plug 11a) are formed in the interlayer insulating films 14 and 15 by using a normal lithography method and an RIE method. Subsequently, for example, a laminated film of W film / TiN film / Ti film is deposited on the entire surface. Subsequently, the W film / TiN film / Ti film on the interlayer insulating film 15 is removed by CMP or the like, and the W film / TiN film / Ti film is embedded only in the contact hole (hereinafter, embedded in the contact hole). W film / TiN film / Ti film is abbreviated as W plug). The W plug 20 is electrically connected to the source / drain diffusion layer via the SN plug 11a. When forming the contact hole, a resist (not shown) and the SiN film 18 on the bit line 17 are used as a mask. Thereby, a fine contact hole can be formed in a narrow region between the bit lines. At this stage, as is apparent from the drawing, both the memory cell portion and the peripheral circuit portion are flat. Note that a Ru film or an Ir film may be used as the plug.

  Next, as shown in FIG. 6, a silicon nitride film 21 having a thickness of about 20 nm is deposited on the entire surface. Subsequently, a TEOS oxide film 22 is deposited on the entire surface to a thickness of about 300 nm. Thereafter, a resist 23 in which the SN electrode formation region has a groove pattern is formed, and the TEOS oxide film 22 and the silicon nitride film 21 are etched by the RIE method using the resist 23 as a mask. By this etching, the surface of the W plug 20 embedded in the interlayer insulating films 14 and 15 is exposed.

  At this time, as shown in FIGS. 6C and 6D, etching is performed so that the interlayer insulating films 21 and 22 have a forward tapered shape. In other words, the etching is performed so that the hole pattern of the SiN film 21 is larger than the hole pattern of the resist 23. That is, assuming that the dimension at the bottom surface of the resist 23 is S1, and the dimension at the surface of the interlayer insulating film 15 is S2, S1 <S2. Further, the angle θ of the side surfaces of the interlayer insulating films 21 and 22 is an acute angle (for example, about 80 to 89 degrees). This angle θ is determined in consideration of a short circuit problem between adjacent patterns, SN electrode embedding characteristics, and the like.

  In this etching step, the TEOS oxide film 22 may be etched by the RIE method using the SiN film 21 as a stopper, and then the SiN film 21 may be selectively etched. At this time, the region such as the peripheral circuit portion is covered with a resist 23 as shown in FIG.

  Next, as shown in FIG. 7, after removing the resist 23, a Ru film is deposited to a thickness of about 400 nm on the entire surface by sputtering or CVD. Thereafter, planarization is performed using a CMP method or an etch-back method to form an SN electrode 24 (lower electrode of the capacitor) made of a Ru film. At this time, there is no step between the memory cell portion and the peripheral circuit portion.

Here, the Ru film is used as the material of the SN electrode 24. However, the RuO ₂ film, the Pt film, the Re film, the Os film, the Pd film, the Rh film, the Au film, the Ir film, the IrO ₂ film, and the perovskite crystal structure are used. A held metal oxide film (for example, SRO (SrRuO ₃ ) film) may be used. Moreover, you may use these laminated films. Furthermore, a film in which the grains of these metal films are stuffed with another metal film (for example, Rh or Ir) may be used.

  In addition, since the groove pattern in which the SN electrode is embedded has an inversely tapered shape, a hollow portion may be formed in the SN electrode when the SN electrode is embedded, but the surface of the SN electrode after CMP is performed. It only needs to be flat. Further, the angle of the reverse taper may be adjusted so as to be flat.

Next, as shown in FIG. 8, the peripheral circuit portion and the like are covered with a resist 25, and the TEOS oxide film 22 is selectively removed using a wet etching solution such as NH ₄ F solution. At this time, the etching can be stopped by the SiN film 21 under the TEOS oxide film 22. At this time, the height of the surface of the SN electrode 24 in the memory cell portion and the height of the surface of the TEOS oxide film 22 other than the memory cell portion are aligned. Therefore, the step between the memory cell region and the region other than the memory cell region can be almost eliminated. In the manufacturing process of a DRAM having a stack structure, it is important to reduce the level difference.

  Further, the angle (θ2) of the upper corner of the SN electrode 24 is an obtuse angle, and the angle (θ1) of the lower corner is an acute angle. Therefore, the electric field concentration at the upper corner of the SN electrode 24 is relaxed, and the breakdown voltage degradation of the capacitor insulating film can be suppressed. Further, the lower corner of the SN electrode 24 is covered with the silicon nitride film 21. Therefore, the electric field concentration at the lower corner can be alleviated, and the breakdown voltage degradation of the capacitor insulating film can be suppressed.

  Further, the side surface of the SN electrode 24 is a transfer of the side surface of the groove obtained by etching the TEOS oxide film 22. Therefore, the smooth etching surface of the TEOS oxide film 22 is transferred to the SN electrode, and the side surface of the SN electrode can be smoothed. When the SN electrode is formed by etching a metal material, it is difficult to obtain a smooth side surface of the SN electrode because it is difficult to control the etching surface. In this example, since the side surface of the SN electrode can be smoothed, electric field concentration due to the roughness of the side surface of the SN electrode can be suppressed. Therefore, an increase in leakage current of the capacitor insulating film can be suppressed.

  Next, as shown in FIG. 9, a BST film 26 to be a capacitor insulating film is deposited to a thickness of about 20 nm on the entire surface by a CVD method. Subsequently, on this BST film 26, a Ru film to be the upper electrode (plate electrode 27) of the capacitor is deposited on the entire surface with a film thickness of about 40 nm by the CVD method. Further, a TiN film or the like to be the cap film 28 is formed on the Ru film with a thickness of about 50 nm by a sputtering method. Thereafter, the plate electrode 27 and the cap film 28 are patterned using a normal lithography method and an RIE method. At this time, a step d is formed between the memory cell portion and a region where there is no plate electrode such as a peripheral circuit portion.

  In addition to the Ru film, a noble metal film such as a Pt film, a Re film, an Ir film, an Os film, a Pd film, an Rh film, or an Au film can be used as the plate electrode 27. It is also possible to use a metal oxide film of these noble metals. Furthermore, a perovskite type metal oxide film such as SRO can be used. Moreover, it is also possible to use these laminated films.

  Next, as shown in FIG. 10, an interlayer insulating film 29 such as a plasma TEOS oxide film is deposited on the entire surface with a film thickness of about 400 nm by the CVD method, and then the entire surface is planarized by the CMP method. Thereby, a step between the memory cell portion and the peripheral circuit portion can be eliminated.

  Next, as shown in FIG. 11, a contact hole is opened in a desired region to form a metal wiring 30. Thereafter, a plurality of layers of contacts and metal wirings are formed as necessary. Thereafter, a passivation film, a pad contact, etc. are formed to complete the DRAM.

  The feature of this embodiment is that the SN electrode is formed in a forward tapered shape. As shown in FIGS. 12 and 13, if the angle θ1 of the lower side surfaces of the TEOS film 22 and the SiN film 21 is a right angle (θ1 = 90 degrees) or an obtuse angle (θ1> 90 degrees), the upper part of the SN electrode 24 The corner angle θ2 is a right angle (θ2 = 90 degrees) or an acute angle (θ2 <90 degrees). Therefore, the electric field concentrates on the upper corner of the SN electrode 24.

  As described above, in the present embodiment, various effects as described below can be achieved.

  Since the outer peripheral length of the bottom of the SN electrode can be increased, the side area of the SN electrode can be increased. Therefore, the storage capacity (Cs) can be increased, and a stable operation of the DRAM can be realized. In addition, the coverage of the capacitor dielectric film of the high dielectric film can be improved. Therefore, the capacitor insulating film can be thinned, so that the storage capacity can be further increased.

  The SN electrode formation method is not a method of processing the electrode film by the RIE method, but a method of forming the electrode film by embedding it in a groove formed in the insulating film. Therefore, the side surface of the SN electrode can be smoothed, and the leakage current of the capacitor insulating film can be reduced.

  Furthermore, since the angle of the upper corner of the SN electrode can be larger than 90 degrees, the electric field concentration can be relaxed, and the leakage current of the capacitor insulating film can be reduced.

(Embodiment 2)
FIG. 14 is a diagram showing a schematic configuration of a memory cell portion of a stack type DARM according to the second embodiment of the present invention. FIG. 14A and FIG. 14B correspond to FIG. 6C and FIG. 8C of the first embodiment, respectively. The difference from the first embodiment is the difference in the structure of the SN electrode.

  In the present embodiment, after the step of FIG. 6 of the first embodiment, the TEOS film 22 and the SiN film 21 are isotropically etched using a CDE method or a wet etching method. By this isotropic etching, the hole pattern expands in the lateral direction, so that the surface area of the SN electrode 24 can be increased. For example, the diameter of the hole pattern is W1 (for example, 0.2 μm) in the first embodiment, but can be expanded to W2 (for example, 0.3 μm) in the present embodiment. Thereby, an SN electrode having a size larger than that determined by lithography can be obtained. Therefore, the storage capacity of the capacitor can be increased.

(Embodiment 3)
FIG. 15 is a diagram showing a schematic configuration of a memory cell portion of a stacked DARM according to the third embodiment of the present invention. FIGS. 15A and 15B correspond to FIGS. 6C and 8C of the first embodiment, respectively. This embodiment is also different from the first embodiment in the structure of the SN electrode.

  In the present embodiment, the side surfaces of the TEOS film 22 and the SiN film 21 have a reverse tapered parabolic shape. This parabolic etching shape can be realized by combining the RIE method and the CDE method. These methods may be combined with a wet etching method or the like.

  In this embodiment, since the side surface of the SN electrode 24 is parabolic, the surface area of the SN electrode can be increased. For example, the diameter of the hole pattern can be increased from W3 (for example, 0.2 μm) to W4 (for example, 0.3 μm). Moreover, since the side surface of the SN electrode is parabolic, the surface area of the SN electrode can be further increased as compared to the second embodiment. As a result, an SN electrode having a size larger than that determined by lithography can be obtained, and the storage capacity can be increased. Further, the upper corner of the SN electrode can be made gentle, and an increase in leakage current due to electric field concentration can be reduced.

(Embodiment 4)
FIG. 16 is a diagram illustrating main manufacturing steps of the memory cell portion of the stacked DARM according to the fourth embodiment of the present invention. FIGS. 16A, 16B, and 16C correspond to FIGS. 6C, 8C, and 11C of the first embodiment, respectively. The structure of the silicon nitride film 21 is different from the above-described embodiments.

  After processing the TEOS film 22 and the SiN film 21 in the process of FIG. 6, in the second embodiment, the TEOS film 22 and the SiN film 21 are etched together in order to enlarge the area of the SN electrode 24. However, the simultaneous etching of the oxide insulating film 22 and the nitride insulating film 21 is not actually easy to control.

  Therefore, in the present embodiment, only the TEOS film 22 is etched by a desired amount by a wet etching method or a CDE method using a diluted HF solution.

  Also in the present embodiment, the same effect as that of the second embodiment can be obtained in terms of enlargement of the SN electrode 24. As a result, an SN electrode having a size larger than that determined by lithography can be obtained, and the storage capacity can be increased. The side surface near the bottom of the SN electrode is recessed, and the silicon nitride film 21 is in contact with the recessed portion. That is, the silicon nitride film 21 is formed so as to bite under the bottom surface of the SN electrode 24. Therefore, the adhesion between the SN electrode and the base can be improved.

  In addition, in the example of FIG. 16, the side surface of the SN electrode has a forward taper shape, but it may be configured as shown in FIGS. 17 (a) and 17 (b). Such a configuration is obtained as follows. First, the side surfaces of the TEOS film 22 and the SiN film 21 are processed so as not to be tapered. Thereafter, only the TEOS film 22 is retracted by a desired amount (for example, 0.05 μm on one side) by wet etching using a diluted HF solution or CDE. Since the wet etching method can precisely control the etching amount, it is possible to precisely control the retraction amount of the TEOS film 22.

  In each of the above embodiments, a TiN film, a TiSiN film, a TiAlN film, or a TaSiN film may be formed as a barrier metal layer between the W plug 20 and the SN electrode 24. Further, a Ru film, an Ir film, an Nb film, a Ti film, or the like may be used as the barrier metal layer. Further, a silicide film of these metals may be used, or a nitride film (for example, a WN film) of a plug film may be used. Further, a Ru film or an Ir film may be used as the barrier metal layer. Further, a Ru or Ir conductive oxide film may be used. The barrier metal layer is embedded in the groove where the plug is formed.

(Embodiment 5)
18 to 23 are process diagrams sequentially showing the manufacturing process of the stack type DARM according to the fifth embodiment of the present invention. Since the steps up to the middle of the present embodiment are the same as those of the first embodiment already described, the first embodiment is referred to the steps up to the middle (step of FIG. 5). The subsequent steps will be described. Note that the plan view ((b) of each drawing) and the cross-sectional view ((e) of each drawing) of the peripheral circuit portion shown in the first embodiment are omitted, and in this embodiment, the memory cell portion is omitted. FIG. 4A is a plan view ((a) of each figure), an AA ′ sectional view (c) of each figure (a), and a BB ′ sectional view (d) of each figure (a).

  The stacked DRAM of this embodiment is characterized by a connection structure between the SN electrode and the metal plug. In this embodiment, a conductive and oxidation-resistant barrier metal layer is formed in a self-aligned manner with respect to the upper surface of the metal plug. The SN electrode and the metal plug layer are electrically connected through this barrier metal layer.

  Although the case where an N channel MOS transistor is used for the memory cell will be described here, the same applies to the case where a P channel MOS transistor is used.

  After the step of FIG. 5 of the first embodiment, as shown in FIG. 18, WN (tungsten nitride) having a thickness of about 5 nm to 10 nm is formed on the exposed surface of the W plug 20 in the interlayer insulating film 15 and the SiN film 18. Ride) film is formed as the barrier metal layer 31. The barrier metal layer 31 is obtained, for example, by nitriding the exposed surface of the W plug 20 in a plasma atmosphere using an RTA apparatus and a processing temperature of 500 ° C. and using ammonia gas.

The barrier metal layer 31 can also be formed as follows. The exposed surface of the W plug 20 is etched by about 10 nm using RIE or CDE to form a recess. Thereafter, oxidation resistance that is not oxidized even in an oxygen atmosphere of about 500 ° C. such as TiN (titanium nitride) film, TiAlN (titanium aluminum nitride) film, TiSiN (titanium silicon nitride) film, or TaSiN (tantalum silicon nitride). Deposit a film. Instead of forming an oxidation resistant film, a metal film such as an Ir film or an Ru film in which the oxide exhibits metal conductivity (RuO ₂ film is conductive) may be deposited. Thereafter, an unnecessary conductive film (the oxidation-resistant film, Ir film, or Ru film) is removed by using a CMP method, an RIE method, a CDE method, or the like, and only the W plug surface exposed in the recess is removed. The conductive film is left behind. A barrier metal layer 31 is formed by the remaining conductive film.

  Next, as shown in FIG. 19, a silicon nitride film 21 having a thickness of about 20 nm is deposited on the entire surface. Further, a TEOS oxide film 22 is deposited on the silicon nitride film 21 to a thickness of about 300 nm. Next, a resist 23 having an SN electrode formation region as an opening pattern is formed. Using this resist 23 as a mask, the TEOS film 22 and the silicon nitride film 21 are etched by the RIE method to expose the surface of the barrier metal layer 31.

  In this etching step, the TEOS oxide film 22 may be etched by the RIE method using the SiN film 21 as a stopper, and then the SiN film 21 may be selectively etched. At this time, if the region such as the peripheral circuit portion is covered with the resist 23, it is not etched.

Next, as shown in FIG. 20, a Ru film or RuO ₂ film (which may be a laminated film thereof) is deposited on the entire surface with a film thickness of about 400 nm by a sputtering method or a CVD method as an SN electrode material. Thereafter, planarization is performed using, for example, a CMP method or an etch back method, and the SN electrode 24 is formed.

In addition, as a material for the SN electrode, a Pt film, a Re film, an Os film, a Pd film, an Rh film, an Au film, an Ir film, or an IrO ₂ film can be used. Further, a metal oxide film having a perovskite crystal structure (for example, an SRO (SrRuO ₃ ) film, a CaRuO ₃ film) or the like can also be used as a material for the SN electrode. Alternatively, a film in which the grain of each metal film is stuffed with another metal film (for example, Rh or Ir) may be used.

Next, as shown in FIG. 21, the TEOS film 22 is selectively removed using a wet etching solution such as NH ₄ F solution. At this time, the etching can be stopped by the SiN film 21 under the TEOS oxide film 22. Further, a region where the TEOS film 22 is not desired to be removed, such as the peripheral circuit portion, is protected by covering it with a resist. By this etching treatment, the height of the surface of the SN electrode 24 in the memory cell portion and the height of the surface of the TEOS oxide film 22 other than the memory cell portion can be made uniform. Therefore, the step between the memory cell region and the region other than the memory cell region can be almost eliminated.

  Further, the side surface of the SN electrode 24 is a transfer of the side surface of the groove obtained by etching the TEOS oxide film 22. Therefore, the smooth etching surface of the TEOS oxide film 22 is transferred to the SN electrode, and the side surface of the SN electrode can be smoothed. When the SN electrode is formed by etching a metal material, it is difficult to obtain a smooth side surface of the SN electrode because it is difficult to control the etching morphology. In this example, since the side surface of the SN electrode can be smoothed, electric field concentration due to the roughness of the side surface of the SN electrode can be suppressed. Therefore, an increase in leakage current of the capacitor insulating film can be suppressed.

  Next, as shown in FIG. 22, a BST film 26 to be a capacitor insulating film is deposited on the entire surface with a film thickness of about 20 nm by a CVD method. Subsequently, on this BST film 26, a Ru film to be the upper electrode (plate electrode 27) of the capacitor is deposited on the entire surface with a film thickness of about 50 nm by the CVD method. Further, on this Ru film, a TiN or W film to be the cap film 28 is formed with a film thickness of about 50 nm by sputtering. Thereafter, the plate electrode 27 and the cap film 28 are patterned using a normal lithography method and an RIE method.

  In addition to the Ru film, a noble metal film such as a Pt film, a Re film, an Ir film, an Os film, a Pd film, an Rh film, or an Au film can be used as the plate electrode 27. It is also possible to use a metal oxide film of these noble metals. Furthermore, a perovskite-type metal oxide film such as SRO or CRO can be used.

  Next, as shown in FIG. 23, an interlayer insulating film 29 such as a plasma TEOS oxide film is deposited on the entire surface to a thickness of about 400 nm by a CVD method. Subsequently, the entire surface is planarized by the CMP method. Thereby, a step between the memory cell portion and the peripheral circuit portion can be eliminated.

  Next, a contact hole is opened in a desired region, and a metal wiring 30 is formed. Thereafter, a plurality of layers of contacts and metal wirings are formed as necessary. Thereafter, a passivation film, a pad contact, etc. are formed to complete the DRAM.

  Thus, in this embodiment, the barrier metal layer is formed on the surface of the metal plug in a self-aligned manner with respect to the metal plug. In particular, by using titanium aluminum nitride (TiAlN) or titanium silicon nitride (TiSiN) having excellent oxidation resistance as the barrier metal layer, an excellent effect can be obtained. That is, the surface of the metal plug can be prevented from being oxidized in a high temperature (about 500 ° C.) process in an oxygen atmosphere when forming the BST film. Therefore, a good electrical connection can be obtained between the plug and the SN electrode. In addition, it is possible to prevent the plug film from being easily peeled off due to volume expansion due to oxidation of the metal film.

In the present embodiment, the SN electrode can be formed under formation conditions using oxygen. Therefore, when metal oxides such as RuO _x, SrRuO _3, IrO _{x, and} CaRuO ₃ that are effective in improving the reliability of BST films and the like are used as SN electrodes, the film formation conditions for forming these metal oxides The width can be increased and the yield can be improved.

  In addition, when the capacitor insulating film such as BST is formed, restrictions on the oxygen partial pressure and the film forming temperature are eased. Therefore, it is possible to optimize the film formation conditions and the crystallization annealing conditions of the BST film, and improve the characteristics of the BST film.

In this embodiment, when an SN electrode (Ru, RuO _x, SrRuO _3, IrO _x, CaRuO _3, etc.) is formed, the underlying SiO ₂ film is also surface-treated at the same time. Therefore, the incubation time for forming the SN electrode film by the CVD method is uniform, and a uniform SN electrode film can be formed on the entire surface.

  Furthermore, the process can be simplified by forming the barrier metal layer only on the upper surface of the metal plug in a self-aligning manner, in particular, nitriding the plug material to form the barrier metal layer.

(Embodiment 6)
FIG. 24 is a diagram showing a schematic configuration of a stacked DARM memory cell according to the sixth embodiment.

  The difference from the fifth embodiment is the difference in the structure of the SN electrode. That is, in the fifth embodiment, the SN electrode is formed in a box shape, but in this embodiment, the SN electrode is formed on the side surface and the bottom surface of the groove. Hereinafter, a manufacturing process for obtaining such a structure will be described.

After forming the groove and removing the resist in the step of FIG. 19 of the fifth embodiment, a Ru film or RuO ₂ film to be an SN electrode is deposited by sputtering or CVD. The film thickness is about 30 to 40 nm on the side surface of the groove. Thereafter, planarization is performed using a CMP method or an etching method in a state where the bottom of the groove is covered with an SOG film or a resist so as not to be etched. By this planarization treatment, the SN electrode 24 can be selectively formed on the side surface and the bottom surface of the SN electrode groove.

  In the present embodiment, since the SN electrode is selectively formed on the side surface and the bottom surface of the groove, the flatness between the memory cell portion and the peripheral circuit portion can be improved. Further, since the silicon oxide film such as TEOS is in contact with the side surface of the SN electrode, the adhesion of the SN electrode can be improved.

(Embodiment 7)
FIG. 25 is a diagram showing a schematic configuration of a stacked DARM memory cell according to the seventh embodiment. This embodiment also differs from the fifth embodiment in the structure of the SN electrode.

  In this embodiment, after forming the SN electrode 24 in the sixth embodiment (FIG. 24), the interlayer insulating film 22 is removed by wet etching using a hydrofluoric acid-based diluted solution or the like. This wet etching stops at the silicon nitride film 21, and the SN electrode 24 is formed in a cylindrical shape.

  In the present embodiment, both the inner wall and the outer wall of the cylindrical SN electrode can be used as the capacitor electrode. Therefore, the height of the SN electrode can be reduced. A cylindrical SN electrode has been proposed so far, but this embodiment has a feature that the material of the barrier metal layer 31 having good adhesion to the material used for the SN electrode 24 can be selected.

In the fifth, sixth and seventh embodiments, the BST film is used as the capacitor insulating film. However, any insulating film having a high dielectric constant may be used, and a PZT film, STO (SrTiO ₃ ) film, BTO ( It is also possible to use a BaTiO ₃ ) film, a Ta ₂ O ₅ film, or the like.

(Embodiment 8)
26 to 29 are process diagrams showing manufacturing processes of the stack type DARM according to the eighth embodiment.

First, as shown in FIG. 26A, a (100) plane P-type silicon substrate 41 (or N-type silicon substrate) having an impurity concentration of about 5 × 10 ¹⁵ cm ⁻³ is prepared. Subsequently, a P well is formed in the N channel transistor region, and an N well is formed in the P channel transistor region (not shown). Subsequently, a trench is dug in the silicon substrate 41 by using the RIE method. By embedding an insulating film in the trench, an STI region 42 (trench depth of about 0.2 μm) is formed.

Next, a silicon oxide film having a thickness of about 60 nm is formed as the gate insulating film 43 of the transistor, and a conductive film to be a gate electrode is formed on the gate insulating film 43. This conductive film becomes a word line in the memory cell portion. In this example, the structure of the gate electrode, in order to reduce the resistance, a polycide structure (e.g., laminated structure comprising a multilayer film of poly-Si film 44 and WSi ₂ film 45, film of a poly Si film 44 and WSi ₂ film 45 Each thickness is about 50 nm). In addition, as a gate electrode structure, you may use the structure of only a poly Si film, or the laminated structure which consists of a poly Si film and W film | membrane.

The gate electrode is processed as follows. First, a silicon nitride film (Si ₃ N ₄ film) is formed as a gate cap film 46 on the conductive film to be a gate electrode. This gate cap film 46 serves as an etching stopper for the gate electrode in a later step. Thereafter, a resist pattern (not shown) is formed on the gate cap film 46, and the gate cap film 46 is processed using the resist pattern as a mask. Further, the gate electrode is processed using the processed gate cap film 46 as a mask.

Next, rapid thermal oxidation is performed in an oxygen atmosphere at 1050 ° C. for about 100 seconds by an RTO (Rapid Thermal Oxidation) method to form a so-called post-oxide film (not shown). This step is performed in order to improve the breakdown voltage between the gate electrode and the impurity diffusion layer (formed in a later step). Next, an n ⁻ impurity diffusion layer 48 to be a source / drain is formed by ion implantation using a resist pattern (not shown), the gate electrode 45 and the cap film 46 as a mask.

  Next, a silicon nitride film 47 (for example, a film thickness of about 20 nm) is deposited on the entire surface by LP-CVD. Subsequently, a sidewall film made of the silicon nitride film 47 is formed on the sidewall portion of the gate electrode by RIE. Thereafter, a silicon nitride film (for example, a film thickness of about 20 nm, not shown) is deposited on the entire surface by the LP-CVD method. Further, a BPSG film is deposited as an interlayer insulating film 49 to a thickness of about 500 nm by the CVD method. Thereafter, the interlayer insulating film 49 is polished and planarized by CMP (Chemical Mechanical Polish). At this time, the thickness of the interlayer insulating film 49 on the gate cap film 46 is set to about 100 nm. By this CMP process, almost the entire surface of the substrate is flattened.

In addition to the n ⁻ diffusion layer 48, an n ⁺ diffusion layer may be formed as the source / drain. In this case, after the sidewall film 47 is formed, ions are implanted into the silicon substrate using the resist mask, the sidewall film, and the gate electrode as a mask to form n ⁺ source / drain diffusion layers.

  Next, a resist (not shown) is formed on the interlayer insulating film 49, and etching is performed using the resist as a mask to form a contact hole for connecting the impurity diffusion layer 48 to the bit line and the SN electrode. .

In this contact hole etching, a high selectivity RIE method is used such that the etching rate is about 10 or more between the BPSG film used for the interlayer insulating film 49 and the silicon nitride film serving as the stopper film (BPSG film). The etching rate is made to be 10 times faster than that of the silicon nitride film). By using such an etching method, it is possible to prevent a short circuit between the gate electrode 45 and the n ⁺ -type poly-Si film embedded in the contact hole in a later step.

Next, an n ⁺ type poly-Si film doped with phosphorus (P ⁺ ) or arsenic (As ⁺ ) as an impurity is deposited on the entire surface by LP-CVD. Subsequently, an n ⁺ -type poly-Si film is left only in the contact hole by a CMP method or an etch-back method, and a poly-Si plug 50 is formed. The poly-Si plug 50 is electrically connected to the source / drain diffusion layer and becomes an SN contact and a BL contact.

  Next, an interlayer insulating film 51 is deposited on the entire surface with a thickness of about 100 nm by a CVD method. Subsequently, contact holes and grooves are formed in the interlayer insulating film 51 by using a normal lithography method and an RIE method. A bit line contact and a bit line (not shown) are formed by embedding a conductive material in the contact hole and groove. Thereby, the poly Si plug (BL contact) and the bit line are electrically connected. In this process, a so-called dual damascene process is used to embed a W film or the like in a groove or the like.

  Thereafter, a silicon nitride film 53 is deposited on the entire surface of about 50 nm as an etching stopper film. After this etching stopper film is planarized, an interlayer insulating film made of TEOS film 54 is deposited to a thickness of about 150 nm. The interlayer insulating film 54 only needs to be selectively wet-etched with respect to the silicon nitride film 53 serving as an etching stopper film, and a material other than the TEOS film (for example, a BPSG film or an SOG film) may be used. Good.

  Next, the interlayer insulating film 54, the etching stopper film 53, and the interlayer insulating film 51 are etched using RIE or the like, thereby opening a contact hole reaching the poly Si plug 50. Thereafter, a tungsten film 52 is deposited on the entire surface by CVD or the like. Although an example of the W film is shown here, a Ru film or an Ir film may be used.

  Next, as shown in FIG. 26B, the tungsten film on the interlayer insulating film 54 is removed by CMP, and the tungsten film 52 is left only in the contact holes.

  Next, as shown in FIG. 27C, the tungsten film in the contact hole is selectively etched (recessed) using the RIE method or the like to form a tungsten plug 52.

  Next, as shown in FIG. 27D, a ruthenium (Ru) film 55 is deposited on the entire surface by CVD. A sputtering method, a plating method, or the like may be used instead of the CVD method. Thereafter, the ruthenium film on the interlayer insulating film 54 is removed by using the CMP method, and a part of the ruthenium film is left only on the contact hole to form the first SN electrode 55.

Next, as shown in FIG. 28E, the interlayer insulating film 54 on the etching stopper film 53 is selectively etched using a solution such as NH ₄ F solution. At this time, the etching stopper film 53 made of a silicon nitride film functions as a wet etching stopper film.

  Next, as shown in FIG. 28F, a ruthenium film 56 to be the second SN electrode is deposited on the entire surface by using the CVD method. A sputtering method, a plating method, or the like may be used instead of the CVD method.

  Next, as shown in FIG. 29G, the ruthenium film 56 is etched using the RIE method, and the ruthenium film 56 is left only on the sidewall of the first SN electrode 55. Thereby, the second SN electrode 56 is formed on the side wall of the first SN electrode 55.

Next, as shown in FIG. 29H, a (Ba, Sr) TiO ₃ film (BST film 57) is deposited on the entire surface by a CVD method as a capacitor insulating film. Subsequently, a ruthenium film is deposited on the entire surface as a plate electrode 58 by about 50 nm. Thereafter, the BST film 57 and the ruthenium film 58 are processed using the RIE method.

As the capacitor insulating film 57, a high dielectric film such as Ta ₂ O ₅ can be used in addition to a perovskite type high dielectric constant film typified by BST. Further, as the capacitor insulating film 57, a ferroelectric film such as (Pb, Zn) TiO ₃ may be used, and further Si oxide, Al oxide (Al ₂ O ₃ ), Si nitride or the like is used. May be.

  Through the above steps, the first SN electrode 55, the second SN electrode 56, the capacitor insulating film 57, and the PL electrode 58 form a DRAM capacitor.

  As described above, according to the present embodiment, when the SN electrodes 55 and 56 are processed, the first SN electrode 55 is formed in a self-aligned manner with respect to the tungsten plug 52 without using the photolithography method. The Therefore, the electrical connection between the SN electrode and the plug can be ensured.

  Further, since the SN electrode 55 is formed in a self-aligned manner with respect to the tungsten plug 52, it is possible to reliably prevent the plug material from being exposed. Therefore, it is possible to prevent the plug from being oxidized when the capacitor insulating film is formed. In addition, contact between the plug material and the capacitor insulating film and contact between the plug material and the PL electrode can be prevented.

  In addition, since an optical lithography method is not used for processing the SN electrode, a capacitor can be manufactured with a smaller number of processes than in the past.

  Furthermore, since the upper corner of the SN electrode is not acute, electric field concentration at the upper corner can be suppressed, and the leakage current of the capacitor insulating film can be suppressed.

The first and second SN electrodes include a Ti film, a TiN film, a TiAlN film, a W film, a WN _x film, a SrRuO ₃ film, a Ru film, a Pt film, a Re film, an Ir film, an Os film, and a Pd film. Rh film and Au film can be used. Alternatively, an oxide conductor of these metals or a conductor containing a minute amount of oxygen in these metals may be used.

  In addition, the first SN electrode material and the second SN electrode material may be made different by using these electrode materials. For example, as the first SN electrode material, a material capable of obtaining normal electrical connection with the plug material is used, and as the second SN electrode material, a material having excellent adhesion to the etching stopper film is used. Like that.

  Even if the first SN electrode material and the second SN electrode material are the same, the first SN electrode and the second SN can be changed by changing the film formation method or the film formation conditions (for example, temperature and atmosphere). You may make it change a crystal structure, a composition, etc. with an electrode.

  FIGS. 30A and 30B show a modified example of the present embodiment and are sectional views showing a schematic configuration in the vicinity of the SN electrode portion.

  In the example shown in FIGS. 26 to 29, the contact surface between the plug 52 and the first SN electrode 55 is located below the etching stopper film 53, but the plug 52 and the first SN electrode 55 The contact surface may be in the contact hole in which the plug 52 is formed. For example, the contact surface between the plug 52 and the first SN electrode 55 may be above the etching stopper film 53 as shown in FIG. 30A, and the contact surface between the etching stopper film 53 and the first SN electrode 55 as shown in FIG. You may make it become the same height. The height position of the contact surface between the plug 52 and the first SN electrode 55 can be adjusted by changing the etching amount in the recess processing of the plug material.

  Thus, since the height position of the contact surface between the plug 52 and the first SN electrode 55 has a degree of freedom, the process margin can be widened. Further, when an expensive material typified by a noble metal material is used for the first SN electrode 55, the total volume of the first SN electrode can be reduced by using the structure as shown in FIG. .

  Further, as shown in FIG. 31, the second SN electrode 5 may cover the side surface and the upper surface of the first SN electrode 55. Such a structure is effective when the oxide of the constituent material of the first SN electrode 55 is an insulator. In this case, as the constituent material of the second SN electrode 56, a material whose oxide exhibits conductivity is used. With such a structure, since the first SN electrode can be prevented from being oxidized during the formation of the capacitor insulating film, a highly reliable capacitor can be manufactured.

  Further, as shown in FIG. 32, by changing the width x of the second SN electrode 56 and the distance y from the upper surface of the first SN electrode 55 to the etching stopper film 53, the area of the charge storage region of the capacitor can be reduced. Can be changed.

  Note that the etching stopper film 53 is not necessarily provided, and can be omitted to further reduce the number of steps.

(Embodiment 9)
33 to 34 are process diagrams showing a manufacturing process of the stack type DARM according to the ninth embodiment of the present invention. The process up to the middle is the same as the process of FIG. 28 (e) described in the eighth embodiment, and FIG. 33 (a) corresponds to FIG. 28 (e).

  After the step of FIG. 33A, as shown in FIG. 33B, a silicon oxide film such as a TEOS film 59 is deposited on the entire surface by a CVD method. Thereafter, a trench is formed in the TEOS film 59 by using an optical lithography method, an RIE method, or the like.

Next, as shown in FIG. 34C, a Ru film is deposited on the entire surface using the CVD method, and the Ru film on the TEOS film 59 is removed using the CMP method. Thereafter, the second SN electrode 60 is formed by selectively etching the TEOS film 59 using a solution such as NH ₄ F solution.

  Next, as shown in FIG. 34D, a BST film is deposited on the entire surface as a capacitor insulating film 57 by the CVD method. Further, a Ru film is deposited on the capacitor insulating film 57 as the PL electrode 58. Then, a capacitor cell is formed by processing these films using the RIE method.

  Also in this embodiment, the same effect as that in the eighth embodiment can be obtained. Furthermore, in the present embodiment, there is an advantage that the second SN electrode can be processed into a desired shape.

(Embodiment 10)
35 to 36 are process diagrams showing a manufacturing process of the stack type DARM according to the tenth embodiment of the present invention. The process up to the middle is the same as the process up to FIG. 27C described in the eighth embodiment.

  After the step of FIG. 27 (c), as shown in FIG. 35 (a), the TEOS film 61 (corresponding to the TEOS film 54 of FIG. 26 (c)) is processed into a shape corresponding to the second SN electrode. To form grooves. Subsequently, a Ru film 62 to be an SN electrode is deposited on the entire surface by a CVD method.

  Next, as shown in FIG. 35B, the excess Ru film 62 is removed by CMP to form an SN electrode.

  Next, as shown in FIG. 36C, the TEOS film 61 on the etching stopper film 53 is removed using an appropriate etching solution.

  Next, as shown in FIG. 36D, a BST film is deposited on the entire surface as a capacitor insulating film 57 by the CVD method. Further, a Ru film is deposited on the capacitor insulating film 57 as the PL electrode 58. Then, a capacitor cell is formed by processing these films using the RIE method.

  As described above, according to the present embodiment, the lower component of the SN electrode 62 is formed in a self-aligned manner with respect to the plug 52, so that the electrical connection between the SN electrode and the plug can be ensured. Further, since the lower part of the SN electrode is formed in a self-aligned manner with respect to the plug, it is possible to prevent the plug material from being exposed and to prevent the plug from being oxidized when the capacitor insulating film is formed. be able to.

  Furthermore, in this embodiment, the SN electrode 62 is integrally embedded as a continuous film in the contact hole in which the plug 52 is formed and in the groove of the TEOS film 61, so that the strength of the SN electrode can be improved.

(Embodiment 11)
37 to 39 are process diagrams showing a manufacturing process of the stack type DARM according to the eleventh embodiment of the present invention. The process up to the middle of FIG. 37A is the same as the middle of the process shown in FIG. 26A of the eighth embodiment.

  After the poly Si plug 50 and the like are formed by the same process as in the eighth embodiment, a BPSG film as an interlayer insulating film 71 is deposited on the entire surface by the CVD method to a thickness of about 300 nm by the CVD method. Subsequently, a silicon nitride film (interlayer insulating film 72) is deposited to a thickness of about 50 nm by a CVD method as an etching stopper during CMP.

  Next, contact holes and grooves (not shown) are formed in the interlayer insulating films 71 and 72 by using a normal lithography method and an RIE method. By burying a conductive material in the contact holes and grooves, bit line contacts and bit lines are formed. The poly Si plug 50 (BL plug) and the bit line are electrically connected from the bit line contact and the bit line. In forming the bit line contact and the bit line, a so-called dual damascene process is used, and a W film or the like is embedded in a line-shaped groove (depth of about 350 nm).

  Next, the W film or the like buried in the trench is etched by about 100 nm, for example. Subsequently, a SiN film is deposited on the entire surface to a thickness of about 300 nm. Further, a SiN film (not shown) is selectively buried only on the W film or the like that becomes the bit line by CMP or CDE.

  Next, a contact hole reaching the poly Si plug 50 (SN plug) is formed in the interlayer insulating films 71 and 72 by using a normal lithography method and an RIE method. Subsequently, for example, a laminated film of W film / TiN film / Ti film is deposited on the entire surface. Subsequently, the W film / TiN film / Ti film on the interlayer insulating film 72 is removed by CMP or the like, and the W film / TiN film / Ti film is embedded only in the contact hole (hereinafter, embedded in the contact hole). W film / TiN film / Ti film is abbreviated as W plug). The W plug 73 is electrically connected to the source / drain diffusion layer via the SN plug 50. At this stage, the memory cell portion is flat.

  Next, as shown in FIG. 37B, a silicon nitride film 74 having a thickness of about 20 nm is deposited on the entire surface. Further, a TEOS oxide film 75 having a thickness of about 300 nm is deposited on the silicon nitride film 74.

  Next, as shown in FIG. 37C, the silicon nitride film 74 and the TEOS oxide film 75 are etched using a resist (not shown) in which the region for forming the SN electrode has a hole pattern as a mask. The surface of the plug 73 is exposed.

  Next, as shown in FIG. 38D, the exposed upper region of the W plug 73 is etched by about 100 nm, and the surface of the W plug 73 is retracted (recess process).

  Next, as shown in FIG. 38E, a Ru film 76 serving as an SN electrode material is deposited with a film thickness of about 400 nm by sputtering or CVD.

  Next, as shown in FIG. 38F, a planarization process is performed by a CMP method or an etch back method to form an SN electrode 76.

Here, the Ru film is used as the material of the SN electrode 76. However, the RuO ₂ film, Pt film, Re film, Os film, Pd film, Rh film, Au film, Ir film, IrO ₂ film, and perovskite crystal structure are used. A held metal oxide film (for example, SRO (SrRuO ₃ ) film) may be used. Alternatively, a film in which the grains of these metal films are stuffed with another metal film (for example, Rh or Ir) may be used.

Next, as shown in FIG. 39G, the peripheral circuit portion and the like are covered with a resist (not shown), and the TEOS oxide film 75 is selectively removed using a wet etching solution such as NH ₄ F solution. At this time, the etching can be stopped by the SiN film 74 under the TEOS oxide film 75. By this etching process, the height of the surface of the SN electrode 76 in the memory cell portion and the height of the surface of the TEOS oxide film 75 other than the memory cell portion can be made uniform. Therefore, the step between the memory cell region and the region other than the memory cell region can be almost eliminated.

  The side surface of the SN electrode 76 is obtained by transferring the side surface of the groove obtained by etching the TEOS oxide film 75. Therefore, the smooth etching surface of the TEOS oxide film 75 is transferred to the SN electrode, and the side surface of the SN electrode can be smoothed. When the SN electrode is formed by etching a metal material, it is difficult to obtain a smooth side surface of the SN electrode because it is difficult to control the etching surface. In this example, since the side surface of the SN electrode can be smoothed, electric field concentration due to the roughness of the side surface of the SN electrode can be suppressed. Therefore, an increase in leakage current of the capacitor insulating film can be suppressed.

  Next, as shown in FIG. 39H, a BST film 77 to be a capacitor insulating film is deposited to a thickness of about 20 nm on the entire surface by a CVD method. Subsequently, an SRO film 78 to be an upper electrode (plate electrode) of the capacitor is deposited on the entire surface of the BST film 77 with a film thickness of about 40 nm by the CVD method. Further, a TiN film or the like (not shown) serving as a cap film is formed on the SRO film 78 with a film thickness of about 50 nm by a sputtering method. Thereafter, the plate electrode 78 and the cap film are patterned using a normal lithography method and an RIE method.

  In addition to the SRO film, a noble metal film such as a Ru film, Pt film, Re film, Ir film, Os film, Pd film, Rh film, or Au film can be used as the plate electrode 78. It is also possible to use a metal oxide film of these noble metals. Further, a perovskite metal oxide film can be used.

  Thereafter, although not shown, an interlayer insulating film such as a plasma TEOS oxide film is deposited on the entire surface with a thickness of about 400 nm by a CVD method. Further, the entire surface is flattened by the CMP method. Thereby, a step between the memory cell portion and the peripheral circuit portion can be eliminated. Further, a contact hole is opened in a desired region, and a metal wiring is formed. Thereafter, a plurality of layers of contacts and metal wirings are formed as necessary. Thereafter, a passivation film, a pad contact, etc. are formed to complete the DRAM.

  Also in this embodiment, the same effect as that in the tenth embodiment can be obtained. Further, in the present embodiment, since the insulating film is in contact with the side surface near the bottom of the upper component part of the SN electrode, electric field concentration in this part can be suppressed, and the leakage current of the capacitor can be reduced.

Embodiment 12
FIG. 40 is a process diagram showing a manufacturing process of the stack type DARM according to the twelfth embodiment of the present invention. The basic manufacturing process is similar to that of the eleventh embodiment shown in FIGS.

  In the eleventh embodiment, in the step of FIG. 37 (c), holes such as SN electrodes are formed substantially vertically. In the present embodiment, as shown in FIG. 40 (a), the side surface of the hole is tapered forward by appropriately selecting the RIE condition. Subsequent steps are the same as those in the eleventh embodiment. That is, the surface of the W plug 73 is retracted by recess etching (FIG. 40B), and then the SN electrode 76 is formed (FIG. 40C).

  In this embodiment, the surface area of the SN electrode can be increased while avoiding short-circuiting between the SN electrodes by making the side surface of the SN electrode reversely tapered.

(Embodiment 13)
FIG. 41 is a process diagram showing a manufacturing process of the stack type DARM according to the thirteenth embodiment of the present invention. The basic manufacturing process is similar to that of the eleventh embodiment shown in FIGS.

  In the eleventh embodiment, in the step of FIG. 37 (c), holes such as SN electrodes are formed substantially vertically. In this embodiment, as shown to Fig.41 (a), the side surface of a hole is made into a reverse taper. The inversely tapered shape can be obtained by, for example, combining the RIE method and the CDE method (and may further combine a wet etching method). Subsequent steps are the same as those in the eleventh embodiment. That is, the surface of the W plug 73 is retracted by recess etching (FIG. 41B), and then the SN electrode 76 is formed (FIG. 41C).

  In this embodiment, the surface area of the SN electrode can be increased by making the side surface of the SN electrode forwardly tapered. In addition, the side surface near the bottom of the upper part of the SN electrode has an acute angle, but since this portion is in contact with the insulating film, electric field concentration in this portion can be suppressed.

(Embodiment 14)
FIG. 42 is a process diagram showing manufacturing processes of the stack type DARM according to the fourteenth embodiment of the present invention. The basic manufacturing process is similar to that of the eleventh embodiment shown in FIGS.

  In the present embodiment, the TEOS oxide film 75 is directly formed on the silicon nitride film 72. Thereafter, in the step of retracting the surface of the W plug 73 by recess etching, the surface of the silicon nitride film 72 is also retracted (FIG. 42A). Subsequent steps are the same as those in the eleventh embodiment, and the SN electrode 76 is formed (FIG. 42B).

  Also in this embodiment, since the insulating film is in contact with the side surface in the vicinity of the bottom of the upper component part of the SN electrode, the electric field concentration in this part can be suppressed.

(Embodiment 15)
FIG. 43 is a process diagram showing a manufacturing process of the stack type DARM according to the fifteenth embodiment of the present invention. The basic manufacturing process is similar to that of the eleventh embodiment shown in FIGS.

  Also in this embodiment, the TEOS oxide film 75 is formed directly on the silicon nitride film 72 as in the fourteenth embodiment. Thereafter, in the step of recessing the surface of the W plug 73 by recess etching, all exposed portions of the silicon nitride film 72 are removed (FIG. 43A). The subsequent steps are the same as those in the eleventh embodiment, and the first SN electrode 76 is formed (FIG. 43B).

  Also in this embodiment, since the insulating film is in contact with the side surface in the vicinity of the bottom of the upper component part of the SN electrode, the electric field concentration in this part can be suppressed.

  In the eighth to fifteenth embodiments, a TiN film, a TiSiN film, a TiAlN film, or a TaSiN film may be formed as a barrier metal layer between the plug and the SN electrode. Further, a W film, an Nb film, a Ti film, or the like may be used as the barrier metal layer. Further, a silicide film or a nitride film (for example, a WN film) of these metals may be formed. Further, a Ru film may be used as the barrier metal layer. The barrier metal layer is embedded in the groove where the plug is formed.

In each of the above embodiments, the BST film is used as the capacitor insulating film. However, any insulating film having a high dielectric constant may be used. For example, a PZT film, an STO film, a Ta ₂ O ₅ film, or the like may be used. An epitaxial BST film can also be used as the BST film.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these embodiment, In the range which does not deviate from the meaning, it can change and implement variously.

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The figure shown about the main manufacturing processes about 15th Embodiment of this invention. The figure shown about the capacitor of the conventional stack structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 41 ... Silicon substrate 2, 42 ... Element isolation region 3, 43 ... Gate insulating film 4a, 44 ... Polysilicon film 4b, 45 ... WSi film 5, 46 ... Cap layer 6, 48 ... Source / drain diffused layer 7, 47, 74 ... SiN film 8, 14, 15, 29, 49, 51, 71, 72 ... Interlayer insulating film 9, 23, 25 ... Resist 10 ... Contact hole 11, 50 ... Poly Si plug 12 ... SN contact 13 ... BL Contact 16 ... Bit line contact 17 ... Bit line 18, 21, 53 ... SiN film 19 ... Contact plug 20, 52, 73 ... W plug 22, 54, 59, 61, 75 ... TEOS film 24, 55, 56, 60, 62, 76 ... SN electrode 26, 57, 77 ... BST film 27, 58, 78 ... Plate electrode 28 ... Cap film 30 ... Metal wiring 31 ... Plastic Gcap layer

Claims (1)

  A step of forming an insulating film having a hole on the base on which the MIS transistor is formed; a tungsten plug connected to one of a source or a drain of the MIS transistor in the hole; and an upper surface of the tungsten plug having the hole Forming the first conductive film on the tungsten plug in the hole, removing a part of the insulating film and forming the first conductive film; Exposing a part of the side surface and leaving a part of the first conductive film in the insulating film; and exposing the side surface of the first conductive film or the second conductive film on the exposed side surface and the upper surface. Forming a capacitor insulating film on the lower electrode of the capacitor constituted by the first and second conductive films, and an upper electrode of the capacitor on the capacitor insulating film The method of manufacturing a semiconductor device characterized by comprising a step of forming.

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