JP4955725B2 - Binary circuit - Google Patents

Description

  The present invention relates to a binarization circuit that binarizes an input signal that changes with time.

  2. Description of the Related Art A binarization circuit that binarizes an input signal that changes with time, such as an electric signal generated by a change in a magnetic field due to a difference in unevenness on the surface of a magnetic body during rotation of the magnetic body, is known. In such a binarization circuit, an input signal is measured, and a peak voltage and a bottom voltage of the measured input signal are detected using a hold circuit such as a peak hold circuit and a bottom hold circuit. Then, an intermediate value between the peak voltage and the bottom voltage of the input signal is obtained, and the input signal is binarized using the intermediate value as a threshold voltage. In order to binarize the input signal accurately, a technique for accurately detecting both the peak voltage and the bottom voltage of the input signal is required.

In the input signal, a voltage that changes in a long cycle may be superimposed on a voltage that changes in a short cycle.
FIG. 19A illustrates an input signal measured when a voltage that changes in a long period tends to decrease. In this case, it is necessary to detect the peak voltage of the input signal that changes in a short cycle.
FIG. 19B illustrates an input signal measured when a voltage that changes in a long cycle tends to increase. Even in this case, it is necessary to detect the bottom voltage of the input signal that changes in a short cycle.
In the case of FIG. 19A, when a simple peak hold circuit is used, the peak voltage Vp ′ indicated by the broken line is not detected, and the peak voltage of the input signal that changes in a short cycle cannot be detected. In the case of FIG. 19B, when a simple bottom hold circuit is used, the bottom voltage Vb ′ indicated by the broken line is not detected, and the bottom voltage of the input signal that changes in a short cycle cannot be detected.

Patent Document 1 discloses a circuit that accurately detects both the peak voltage of each input signal and the bottom voltage of each input signal.
The peak hold circuit of Patent Document 1 includes a first storage circuit, and increases the stored value of the first storage circuit when the voltage at the input terminal is higher than the stored value of the first storage circuit. The first memory circuit decreases the stored value in synchronization with the input of the clock signal input from the outside. The bottom hold circuit of Patent Document 1 includes a second memory circuit, and reduces the stored value of the second memory circuit when the voltage at the input terminal is lower than the stored value of the second memory circuit. The second memory circuit increases the stored value in synchronization with the input of the clock signal input from the outside.

In the technique of Patent Document 1, the memory values of the first memory circuit and the second memory circuit are changed based on a clock signal input from the outside. That is, as shown by a solid line in FIG. 19A, when the voltage that changes in the long cycle tends to decrease, the stored value of the first memory circuit is decreased to change the peak of the input voltage that changes in the short cycle. Prepare for the voltage drop. As a result, the voltage held by the peak hold circuit can be reduced in accordance with the drop in the peak voltage.
Similarly, as shown by the solid line in FIG. 19B, when the voltage that changes in the long cycle is on the rise, the stored value of the second memory circuit is increased to reduce the input voltage that changes in the short cycle. Prepare for rising bottom voltage. As a result, the voltage held by the bottom hold circuit can be increased as the bottom voltage increases.

JP 2007-178498 A

  In the input signal, an operation period in which the input signal changes over a threshold voltage within a predetermined period and a stop period in which the input signal does not change over a threshold voltage may be repeated over a predetermined period. When such an input signal is input to the binarization circuit, during the operation period, the input signal changes beyond the threshold voltage within a predetermined period, and the output signal is inverted. In the stop period, the input signal does not change beyond the threshold voltage over a predetermined period, and the output signal does not invert. Therefore, it seems that the detection target state can be detected. Furthermore, it seems that it is possible to detect that the input signal is in the stop period because the output signal is not inverted during the predetermined period.

  In the binarization circuit of Patent Document 1, when the stop period is longer than the time until the peak voltage and the input signal become the same potential due to the decrease in the peak voltage, the peak voltage and the input signal match in the stop period. Similarly, when the stop period is longer than the time until the bottom voltage and the input signal become the same potential due to the rise of the bottom voltage, the bottom voltage and the input signal match in the stop period. When the peak voltage, the bottom voltage, and the input signal match, the threshold voltage and the input signal match, and the output voltage of the binarization circuit becomes unstable. For example, when noise that swings to the low voltage side is superimposed on the input signal, the input signal falls below the threshold voltage, and the output signal of the binarization circuit is inverted. Further, when noise that swings to the high voltage side is superimposed on the input signal, the input signal rises above the threshold voltage, and the output signal of the binarization circuit is inverted. Furthermore, there are cases where the binarized signal at the first edge immediately after re-rotation cannot be detected. As described above, there is a problem that the output signal of the binarization circuit is erroneously inverted or lost, and the detection target state cannot be detected correctly. Further, in this case, the stop period cannot be detected based on the output signal of the binarization circuit.

  The present invention solves the above problems. That is, an object of the present invention is to provide a technique capable of correctly detecting the detection target state based on the output signal of the binarization circuit and accurately detecting the operation period and the stop period of the input signal.

The present invention is embodied in a binarization circuit that binarizes an input signal that changes with time. This binarization circuit includes a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit.
The peak hold circuit includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit. The peak hold circuit executes a process of increasing the storage value of the first storage circuit while the voltage of the input signal is higher than the storage value of the first storage circuit. Further, when the stop determination signal from the stop determination circuit is turned on, the stored value of the first memory circuit follows the change of the input signal while the voltage of the input signal is lower than the stored value of the first memory circuit. Execute processing to change

  The bottom hold circuit includes a second memory circuit, and outputs the stored value of the second memory circuit to the binarization determination circuit. The bottom hold circuit executes a process of decreasing the stored value of the second storage circuit while the voltage of the input signal is lower than the stored value of the second storage circuit. Further, when the stop determination signal from the stop determination circuit is turned on, the stored value of the second storage circuit follows the change of the input signal while the voltage of the input signal is higher than the stored value of the first storage circuit. Execute processing to change

The binarization determination circuit outputs an output signal obtained by binarizing the input signal to the output terminal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit.
The stop determination circuit outputs a stop determination signal that is turned off when the output signal is inverted within a predetermined period and turned on when the output signal is not inverted over a predetermined period to the peak hold circuit and the bottom hold circuit.

  In the above binarization circuit, during the operation period in which the stop determination signal is turned off, the stored value of the first storage circuit of the peak hold circuit is increased while the voltage of the input signal is higher than the stored value of the first storage circuit. Further, while the voltage of the input signal is lower than the stored value of the second storage circuit, the stored value of the second storage circuit of the bottom hold circuit is decreased. Thus, during the operation period, the peak value of the voltage of the input signal can be stored in the peak hold circuit in the first storage circuit, and the bottom value of the voltage of the input signal is stored in the bottom hold circuit in the second storage circuit. can do.

In the peak hold circuit and the bottom hold circuit, each stored value changes following the change of the input signal during the stop period in which the stop determination signal is turned on.
According to this binarization circuit, the input signal is prevented from changing beyond the threshold during the stop period. As a result, inversion of the output signal of the binarization circuit during the stop period is suppressed, and the detection target state can be detected correctly. Furthermore, the operation period and the stop period can be detected with high accuracy based on the output signal of the binarization circuit.

The binarization circuit of the present invention can be expressed as follows. The binarization circuit of the present invention includes an input terminal for inputting an input signal, an output terminal for outputting an output signal, a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit. Yes.
The peak hold circuit is connected to the input terminal, the stop determination circuit, and the binarization determination circuit. The peak hold circuit includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit and executes at least the following three processes.
(1) When the stop determination signal from the stop determination circuit is turned off, the storage value of the first storage circuit is increased while the voltage of the input signal is higher than the storage value of the first storage circuit.
(2) When the stop determination signal from the stop determination circuit is turned on and the stored value of the first storage circuit is lower than the voltage of the input signal, the stored value of the first storage circuit is increased.
(3) When the stop determination signal from the stop determination circuit is turned on and the stored value of the first memory circuit is higher than the voltage of the input signal, the stored value of the first memory circuit is changed following the change of the input signal. Let

The bottom hold circuit is connected to the input terminal, the stop determination circuit, and the binarization determination circuit. The bottom hold circuit includes a second storage circuit, and outputs the stored value of the second storage circuit to the binarization determination circuit and executes at least the following three processes.
(1) When the stop determination signal from the stop determination circuit is turned off, the storage value of the second storage circuit is decreased while the voltage of the input signal is lower than the storage value of the second storage circuit.
(2) When the stop determination signal from the stop determination circuit is turned on and the stored value of the second storage circuit is higher than the voltage of the input signal, the stored value of the second storage circuit is decreased.
(3) When the stop determination signal from the stop determination circuit is turned on and the stored value of the second memory circuit is lower than the voltage of the input signal, the stored value of the second memory circuit is changed following the change of the input signal. Let

  The binarization determination circuit is connected to an input terminal, an output terminal, a peak hold circuit, and a bottom hold circuit. The binarization determination circuit executes a process of outputting an output signal obtained by binarizing the input signal to the output terminal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit.

  The stop determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit. The stop determination circuit outputs a stop determination signal that is turned off when the output signal is inverted within a predetermined period and turned on when the output signal is not inverted over a predetermined period to the peak hold circuit and the bottom hold circuit.

  In the above stop determination circuit, the stop determination signal is turned off in the operation period in which the output signal is inverted within the predetermined period, and the stop determination signal is turned on in the stop period in which the output signal is not inverted over the predetermined period. In the above binarization circuit, a state in which the storage value of the first storage circuit is higher than the input signal and the storage value of the second storage circuit is lower than the input signal during the stop period in which the stop determination signal is on is formed. At the same time, the memory value of the first memory circuit and the memory value of the second memory circuit are changed following the input signal.

  According to the above binarization circuit, the threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit can be changed following the input signal during the stop period. Therefore, inversion of the output signal of the binarization circuit during the stop period is suppressed, and the detection target state can be detected correctly.

The binarization circuit preferably includes an input signal detection circuit. The input signal detection circuit is connected to the input terminal, the peak hold circuit, and the bottom hold circuit. The input signal detection circuit includes a third memory circuit, which is turned on when the stored value of the third memory circuit is higher than the voltage of the input signal, and the stored value of the third memory circuit is lower than the voltage of the input signal. In this case, the detection signal to be turned off is output to the peak hold circuit and the bottom hold circuit. Further, the stored value of the third storage circuit is changed following the change of the input signal.
Further, in the above binarization circuit, the first memory circuit, the second memory circuit, and the third memory circuit include means for storing the digitized voltage. That is, the third memory circuit digitizes the input signal and stores it in the third memory circuit. Similarly, the first memory circuit digitizes the peak value of the input signal and stores it in the first memory circuit. The second memory circuit digitizes the bottom value of the input signal and stores it in the second memory circuit.

  According to the above binarization circuit, the stored values of the first to third storage circuits are digitized. Therefore, when the stored value is changed, the digitized stored value may be changed. There is no need to change the analog voltage, and the time required for processing can be shortened. In general, a circuit for storing a digital value can be formed smaller than a circuit for storing an analog voltage. Therefore, the binarization circuit can be reduced in size.

The binarization circuit preferably includes a first clock terminal and a second clock terminal. The first clock terminal receives the first clock signal and is connected to the peak hold circuit, the bottom hold circuit, and the input signal detection circuit. The second clock terminal receives the second clock signal and is connected to the peak hold circuit, the bottom hold circuit, and the input signal detection circuit. The first memory circuit, the second memory circuit, and the third memory circuit increase or decrease each stored value based on the first clock signal when increasing or decreasing each stored value. Is changed following the change of the input signal, each stored value is changed based on the second clock signal.
According to the binarization circuit described above, in the first memory circuit, the second memory circuit, and the third memory circuit, the change speed when increasing or decreasing each stored value, and the change of each input value for each stored value It is possible to set separately the changing speed when changing following. Thereby, the change speed can be set according to each situation, and the storage value of the first storage circuit and the storage value of the second storage circuit can be made to accurately follow the input signal.

The present invention is also embodied in the following binarization circuit. The second binarization circuit of the present invention includes a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit.
The peak hold circuit includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit. The peak hold circuit executes a process of increasing the storage value of the first storage circuit while the voltage of the input signal is higher than the storage value of the first storage circuit. Further, when the stop determination signal from the stop determination circuit is turned on, the stored value of the first memory circuit follows the change of the input signal while the voltage of the input signal is lower than the stored value of the first memory circuit. Execute processing to change

  The bottom hold circuit includes a second memory circuit, and outputs the stored value of the second memory circuit to the binarization determination circuit. The bottom hold circuit executes a process of decreasing the stored value of the second storage circuit while the voltage of the input signal is lower than the stored value of the second storage circuit. Further, when the stop determination signal from the stop determination circuit is turned on, the stored value of the second storage circuit follows the change of the input signal while the voltage of the input signal is higher than the stored value of the first storage circuit. Execute processing to change

The binarization determination circuit outputs an output signal obtained by binarizing the input signal to the output terminal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit.
The stop determination circuit outputs a stop determination signal that is turned off when the output signal is inverted within a predetermined period and turned on when the output signal is not inverted over a predetermined period to the peak hold circuit and the bottom hold circuit.

Further, in the above binarization circuit, before the peak hold circuit and the bottom hold circuit change their stored values in accordance with the change of the input signal during the stop period, the stored values of the first storage circuit and A process of making either one of the stored values of the two storage circuits substantially coincide with the voltage of the input signal is executed.
According to this binarization circuit, when the peak hold circuit and the bottom hold circuit change the stored values during the stop period, either the stored value of the first storage circuit or the stored value of the second storage circuit To detect changes in the input signal. As a result, the processing performed by the binarization circuit during the stop period can be simplified. Further, it is not necessary to prepare a circuit for detecting a change in the input signal. For this reason, the circuit configuration can be simplified.

The second binarization circuit of the present invention can be expressed as follows. The second binarization circuit of the present invention includes an input terminal for inputting an input signal, an output terminal for outputting an output signal, a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit. It has.
The peak hold circuit is connected to the input terminal, the output terminal, the stop determination circuit, and the binarization determination circuit. The peak hold circuit includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit and executes at least the following three processes.
(1) The stored value of the first memory circuit is increased while the voltage of the input signal is higher than the stored value of the first memory circuit.
(2) When the stop determination signal from the stop determination circuit transits from OFF to ON and the output signal from the binarization determination circuit at that time is high, the stored value of the first storage circuit is decreased, and the first After the storage value of the storage circuit is made lower than the voltage of the input signal, the storage value of the first storage circuit is changed following the change of the input signal.
(3) When the stop determination signal from the stop determination circuit transits from OFF to ON and the output signal from the binarization determination circuit at that time is low, the stored value of the second storage circuit of the bottom hold circuit is input After making it higher than the voltage of the signal, the memory value of the first memory circuit is changed following the change of the memory value of the second memory circuit.
Here, “output signal is high” indicates a state in which the voltage of the input signal is higher than a threshold value in a binarization determination circuit described later, and “output signal is low” indicates binarization determination described later. In the circuit, the voltage of the input signal is lower than the threshold value.

The bottom hold circuit is connected to the input terminal, the output terminal, the stop determination circuit, and the binarization determination circuit. The bottom hold circuit includes a second storage circuit, and outputs the stored value of the second storage circuit to the binarization determination circuit and executes at least the following three processes.
(1) The stored value of the second memory circuit is decreased while the voltage of the input signal is lower than the stored value of the second memory circuit.
(2) When the stop determination signal from the stop determination circuit transits from OFF to ON and the output signal from the binarization determination circuit at that time is high, the stored value of the first storage circuit of the peak hold circuit is input After making it lower than the voltage of the signal, the stored value of the second storage circuit is changed following the change of the stored value of the first storage circuit.
(3) When the stop determination signal from the stop determination circuit transits from off to on and the output signal from the binarization determination circuit at that time is low, the stored value of the second storage circuit is increased, and the second After the storage value of the storage circuit is made higher than the voltage of the input signal, the storage value of the second storage circuit is changed following the change of the input signal.

  The binarization determination circuit is connected to an input terminal, an output terminal, a peak hold circuit, and a bottom hold circuit. The binarization determination circuit executes a process of outputting an output signal obtained by binarizing the input signal to the output terminal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit.

  The stop determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit. The stop determination circuit outputs a stop determination signal that is turned off when the output signal is inverted within a predetermined period and turned on when the output signal is not inverted over a predetermined period to the peak hold circuit and the bottom hold circuit.

In the stop determination circuit, the storage value of the first storage circuit and the storage value of the second storage circuit are changed following the input signal in the stop period in which the stop determination signal is turned on.
According to the above binarization circuit, the threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit can be changed following the input signal. As a result, inversion of the output signal of the binarization circuit during the stop period is suppressed, and the detection target state can be detected correctly. Furthermore, the operation period and stop period of the input signal can be accurately detected based on the output signal of the binarization circuit.

In the above binarization circuit, the following processing is executed prior to changing the storage value of the first storage circuit and the storage value of the second storage circuit following the input signal during the stop period.
(1) When the output signal from the binarization circuit is high, that is, when the voltage of the input signal is higher than the threshold value, the storage value of the first storage circuit is decreased, and the storage value of the first storage circuit and the input signal The voltages of are substantially the same.
(2) When the output signal from the binarization circuit is low, that is, when the voltage of the input signal is lower than the threshold value, the storage value of the second storage circuit is increased, and the storage value of the second storage circuit and the input signal The voltages of are substantially the same.

In the above binarization circuit, when the voltage of the input signal is higher than the threshold value, the storage value of the first storage circuit is made to substantially match the voltage of the input signal. Accordingly, when the storage value of the first storage circuit and the storage value of the second storage circuit are changed following the input signal during the stop period, a change in the input signal can be detected by the storage value of the first storage circuit. For this reason, the process performed by the binarization circuit during the stop period of the input signal can be simplified. Further, it is not necessary to prepare a circuit for detecting a change in the input signal, and therefore the circuit can be simplified.
Similarly, when the input signal is lower than the threshold value, the stored value of the second storage circuit is made to substantially match the voltage of the input signal. Accordingly, when the storage value of the first storage circuit and the storage value of the second storage circuit are changed following the input signal during the stop period, a change in the input signal can be detected by the storage value of the second storage circuit. For this reason, the process performed by the binarization circuit during the stop period of the input signal can be simplified. Further, it is not necessary to prepare a circuit for detecting a change in the input signal, and therefore the circuit can be simplified.

The binarization circuit preferably includes a first voltage determination circuit and a second voltage determination circuit. The first voltage determination circuit is connected to the output terminal, the peak hold circuit, and the stop determination circuit. The first voltage determination circuit is inverted immediately after the stop determination signal is turned on, when the output value from the binarization circuit is high and the stored value of the first storage circuit becomes lower than the voltage of the input signal. A peak hold value coincidence signal is output to the peak hold circuit. The second voltage determination circuit is connected to the output terminal, the bottom hold circuit, and the stop determination circuit. The second voltage determination circuit is inverted immediately after the stop determination signal is turned on, when the output value from the binarization circuit is high and the stored value of the second storage circuit becomes higher than the voltage of the input signal. A bottom hold value coincidence signal is output to the bottom hold circuit.
According to the binarization circuit described above, the timing at which the stored value of the first storage circuit substantially matches the input signal can be accurately detected using the peak hold value match signal. In addition, the timing at which the stored value of the second storage circuit substantially matches the input signal can be accurately detected using the bottom hold value match signal.

The binarization circuit preferably includes a first clock terminal and a second clock terminal. The first clock terminal receives the first clock signal and is connected to the peak hold circuit and the bottom hold circuit. The second clock terminal receives the second clock signal and is connected to the peak hold circuit and the bottom hold circuit. The first memory circuit and the second memory circuit increase or decrease each stored value based on the first clock signal when increasing or decreasing each stored value, and change each stored value to an input signal. Each of the stored values is changed based on the second clock signal.
According to the above binarization circuit, in the first memory circuit and the second memory circuit, the rate of change when each stored value is increased or decreased, and each stored value changes following the change of the input signal. It is possible to set the change speed when making it different. Thereby, the change speed can be set according to each situation, and the storage value of the first storage circuit and the storage value of the second storage circuit can be made to accurately follow the input signal.

The two binarization circuits preferably include a third clock terminal. The third clock terminal receives the third clock signal and is connected to the stop determination circuit. The stop determination circuit determines the predetermined period based on the period of the third clock signal.
According to the above binarization circuit, the predetermined period for determining whether or not the output signal is inverted can be set using the third clock signal input from the outside.

  According to the present invention, the inversion of the output signal of the binarization circuit during the stop period of the input signal is suppressed. Thereby, the state of the detection target can be detected correctly. Furthermore, the operation period and stop period of the input signal can be detected with high accuracy.

A circuit diagram of the binarization circuit 10 is shown. A circuit diagram of the input signal detection circuit 130 is shown. A circuit diagram of the peak hold circuit 30 is shown. A circuit diagram of the bottom hold circuit 40 is shown. The flowchart of the binarization circuit 10 is shown. The flowchart of the binarization circuit 10 is shown. A circuit diagram of the binarization determination circuit 120 is shown. 6 is a diagram for explaining the operation of a binarization determination circuit 120. FIG. A circuit diagram of the stop determination circuit 140 is shown. FIG. 6 is a diagram for explaining the effect of the binarization circuit 10. A circuit diagram of the binarization circuit 210 is shown. A circuit diagram of the peak hold circuit 230 is shown. A circuit diagram of the bottom hold circuit 240 is shown. The flowchart of the binarization circuit 210 is shown. A circuit diagram of the stop / voltage determination circuit 340 is shown. A circuit diagram of the control signal generation circuit 330 is shown. It is a figure explaining the inversion operation | movement of the peak flag signal Fp and the bottom flag signal Fb. It is a figure explaining the effect of the binarization circuit. It is a figure explaining the problem of a prior art.

The main features of the embodiments described below are first organized.
(Feature 1) The peak hold circuit includes a comparator, a peak counter control circuit, a peak counter, and a D / A conversion circuit.
(Feature 2) The bottom hold circuit includes a comparator, a bottom counter control circuit, a bottom counter, and a D / A conversion circuit.
(Feature 3) The input signal detection circuit includes a comparator, an input counter control circuit, an input counter, and a D / A conversion circuit.
(Feature 4) The determination clock signal is formed by dividing the basic clock signal.
(Feature 5) The temperature compensation clock signal is formed by dividing the basic clock signal.
(Feature 6) The frequency of the temperature compensation clock signal is higher than the frequency of the determination clock signal.
(Feature 7) The frequency of the input signal is set to be lower than the frequency of the basic clock signal and higher than the frequency of the determination clock signal.

  FIG. 1 shows a binarization circuit 10. The binarization circuit 10 includes an input terminal 20, a basic clock terminal 22 (corresponding to a first clock terminal), a determination clock terminal 23 (corresponding to a third clock terminal), a reset terminal 24, and a temperature compensation clock terminal 25 (first compensation terminal). A binary output terminal 26 (corresponding to an output terminal), a delay output terminal 28, a peak hold circuit 30, a bottom hold circuit 40, a binarization determination circuit 120, and an input signal detection circuit 130. A stop determination circuit 140 is provided.

The input terminal 20 is connected to the peak hold circuit 30, the bottom hold circuit 40, and the binarization determination circuit 120, and an input signal is input from an external circuit (not shown) such as a magnetic sensor.
The basic clock terminal 22 is connected to the peak hold circuit 30, the bottom hold circuit 40, the input signal detection circuit 130, and the stop determination circuit 140, and the basic clock signal Cl1 is input from an external circuit.
The determination clock terminal 23 is connected to the stop determination circuit 140, and the determination clock signal Cl3 is input from an external circuit. The determination clock signal Cl3 is formed by dividing the basic clock signal Cl1, and its frequency is set lower than the frequency of the input signal.
The reset terminal 24 is connected to the peak hold circuit 30, the bottom hold circuit 40, the input signal detection circuit 130, and the stop determination circuit 140, and a reset signal is input from an external circuit.
The temperature compensation clock terminal 25 is connected to the peak hold circuit 30, the bottom hold circuit 40, and the input signal detection circuit 130, and the temperature compensation clock signal Cl2 is inputted from an external circuit. The temperature compensation clock signal Cl2 is formed by dividing the basic clock signal Cl1. The frequency of the temperature compensation clock signal Cl2 is set higher than the frequency of the determination clock signal Cl3, and is set lower than the frequency of the input signal.

  The input signal detection circuit 130 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the temperature compensation clock terminal 25, the peak hold circuit 30, the bottom hold circuit 40, and the stop determination circuit 140. FIG. 2 shows a specific configuration of the input signal detection circuit 130. The input signal detection circuit 130 includes a comparator 131, an input counter control circuit 132, an input counter circuit 133, and a D / A conversion circuit 134. A non-inverting input terminal 131 a of the comparator 131 is connected to the input terminal 20. The inverting input terminal 131 b of the comparator 131 is connected to the output terminal 134 a of the D / A conversion circuit 134. The output terminal 131 c of the comparator 131 is connected to the input unit 132 a of the input counter control circuit 132, and is connected to the peak hold circuit 30 and the bottom hold circuit 40. In addition to the output terminal 131 c of the comparator 131, the basic clock terminal 22, the temperature compensation clock terminal 25, and the stop determination circuit 140 are connected to the input unit 132 a of the input counter control circuit 132. The output unit 132b of the input counter control circuit 132 is connected to the UP terminal 133b and the DOWN terminal 133c of the input counter circuit 133. A reset (RES) input terminal 133 a of the input counter circuit 133 is connected to the reset terminal 24. The input counter circuit 133 is connected to the D / A conversion circuit 134. The output terminal 134 a of the D / A conversion circuit 134 is connected to the inverting input terminal 131 b of the comparator 131.

In the comparator 131, when the voltage Vin (that is, the voltage of the input signal) input to the non-inverting input terminal 131a is higher than the stored value V3 of the input signal detection circuit 130 input to the inverting input terminal 131b, the output terminal 131c. The voltage of becomes high. On the other hand, when the voltage Vin is lower than the stored value V3, the voltage of the output terminal 131c becomes low.
The input counter circuit 133 includes a digitized input counter value Din, and increases or decreases the input counter value Din according to signals input from the reset terminal 24 and the input counter control circuit 132. That is, the input counter circuit 133 corresponds to the third storage circuit, and the input counter value Din stored in the input counter circuit 133 corresponds to the storage value of the third storage circuit. When a signal is input to the UP input terminal 133b, the input counter circuit 133 increases the input counter value Din of the input counter circuit 133 by a first predetermined value in accordance with this signal. When a signal is input to the DOWN input terminal 133c, the input counter value Din of the input counter circuit 133 is decreased by a second predetermined value in accordance with this signal. The input signal detection circuit 130 resets the input counter value Din to an initial value when a reset signal is input from the reset terminal 24.

Based on the stop determination signal input from the stop determination circuit 140, the input signal detection circuit 130 controls the input counter value Din as follows.
(1) When the Stop Determination Signal is Off As shown in FIG. 5A, the input counter value Din of the input counter circuit 133 is controlled based on the voltage Vcomin input from the comparator 131. When voltage Vcomin is high (that is, voltage Vin is higher than stored value V3) (YES in S10), input counter value Din is set to a first predetermined value (here, “1” in synchronization with the rise of basic clock signal Cl1). )) Is increased (S12). When the voltage Vcomin is low (NO in S10), the input counter value Din is decreased by a second predetermined value (here, “1”) in synchronization with the rising of the basic clock signal Cl1 (S14).
(2) When the Stop Determination Signal is On As shown in FIG. 6A, the input counter value Din of the input counter circuit 133 is controlled based on the voltage Vcomin. When the voltage Vcomin is high (YES in S40 (1) YES), if the temperature compensation clock signal Cl2 falls (YES in S40 (2) YES), the input counter value Din is synchronized with the rise of the basic clock signal Cl1. Is increased by a first predetermined value, and a peak counter value Dp of the peak hold circuit 30 and a bottom counter value Db of the bottom hold circuit 40 to be described later are increased by a first predetermined value (S42). When the voltage Vcomin is low (NO in S40 (1) NO), if the temperature compensation clock signal Cl2 falls (YES in S40 (2)), the input counter is synchronized with the rising of the basic clock signal Cl1. The value Din is decreased by a second predetermined value, and a peak counter value Dp of the peak hold circuit 30 and a bottom counter value Db of the bottom hold circuit 40 described later are decreased by a second predetermined value (S44).
With the above processing, the voltage Vin of the input signal is stored in the storage value V3 of the input signal detection circuit 130.

The input signal detection circuit 130 controls the input counter value Din of the input signal detection circuit 130 in synchronization with the basic clock signal Cl1 during the operation period when the stop determination signal is turned off, and the temperature during the stop period when the stop determination signal is turned on. The input counter value Din of the input signal detection circuit 130 is controlled in synchronization with the rise of the basic clock signal Cl1 at the fall timing of the compensation clock signal Cl2. As a result, the change in the voltage Vin of the input signal during the operation period can be stored in the stored value V3 of the input signal detection circuit 130 with high accuracy. Further, during the stop period in which the stop determination signal is turned on, the peak counter value Dp and the bottom counter value Db are also changed at the falling timing of the temperature compensation clock signal Cl2, similarly to the change of the stored value V3 of the input signal detection circuit 130. Thus, temperature compensation can be performed during the stop period in which the stop determination signal is turned on.
The input signal detection circuit 130 stores the stored value V3 as an input counter value Din that is a digital value. As a result, the time required for processing the stored value V3 can be shortened, and the input signal detection circuit 130 can be reduced in size and formed.

  The peak hold circuit 30 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the temperature compensation clock terminal 25, the binarization determination circuit 120, the input signal detection circuit 130, and the stop determination circuit 140. FIG. 3 shows a specific configuration of the peak hold circuit 30. The peak hold circuit 30 includes a comparator 31, a peak counter control circuit 32, a peak counter circuit 33, and a D / A conversion circuit 34. A non-inverting input terminal 31 a of the comparator 31 is connected to the input terminal 20. The inverting input terminal 31 b of the comparator 31 is connected to the output terminal 34 a of the D / A conversion circuit 34. The output terminal 31 c of the comparator 31 is connected to the input unit 32 a of the peak counter control circuit 32. In addition to the output terminal 31 c of the comparator 31, the input unit 32 a of the peak counter control circuit 32 includes a basic clock terminal 22, a temperature compensation clock terminal 25, a binarization determination circuit 120, an input signal detection circuit 130, and a stop determination. A circuit 140 is connected. The output section 32b of the peak counter control circuit 32 is connected to the UP terminal 33b, the first DOWN terminal 33c, and the second DOWN terminal 33d of the peak counter circuit 33. A reset (RES) input terminal 33 a of the peak counter circuit 33 is connected to the reset terminal 24. The peak counter circuit 33 is connected to the D / A conversion circuit 34. The output terminal 34 a of the D / A conversion circuit 34 is connected to the inverting input terminal 31 b of the comparator 31 and is also connected to the binarization determination circuit 120.

In the comparator 31, when the voltage Vin (that is, the voltage of the input signal) input to the non-inverting input terminal 31a is higher than the stored value V1 of the peak hold circuit 30 input to the inverting input terminal 31b, the output terminal 31c The voltage goes high. On the other hand, when the voltage Vin is lower than the stored value V1, the voltage of the output terminal 31c becomes low.
The peak counter circuit 33 has a digitized peak counter value Dp, and increases or decreases the peak counter value Dp according to signals input from the reset terminal 24 and the peak counter control circuit 32. That is, the peak counter circuit 33 corresponds to the first storage circuit, and the peak counter value Dp stored in the peak counter circuit 33 corresponds to the storage value of the first storage circuit. When a signal is input to the UP input terminal 33b, the peak counter circuit 33 increases the peak counter value Dp of the peak counter circuit 33 by a first predetermined value in accordance with this signal. When a signal is input to the first DOWN input terminal 33c, the peak counter value Dp of the peak counter circuit 33 is decreased by a second predetermined value in accordance with this signal. When a signal is input to the second DOWN input terminal 33d, the peak counter value Dp of the peak counter circuit 33 is decreased by a third predetermined value in accordance with this signal. The peak hold circuit 30 resets the peak counter value Dp to the initial value when a reset signal is input from the reset terminal 24.

The peak hold circuit 30 controls the peak counter value Dp as follows based on the stop determination signal input from the stop determination circuit 140.
(1) When the Stop Determination Signal is Off As shown in FIG. 5B, the peak counter is based on the voltage Vcomp input from the comparator 31 and the peak hold value decrease signal Vθ1 input from the binarization determination circuit 120. The peak counter value Dp of the circuit 33 is controlled. When voltage Vcomp is high (that is, voltage Vin is higher than stored value V1) (YES in S20 (1) YES), peak counter value Dp is increased by a first predetermined value in synchronization with the rise of basic clock signal Cl1. (S22). When the voltage Vcomp is low and the peak hold value decrease signal Vθ1 is inverted from low to high ((1) NO (2) YES in S20), the peak counter is synchronized with the rising edge of the basic clock signal Cl1. The value Dp is decreased by a third predetermined value (here, “m”) (S24).
(2) When the Stop Determination Signal is On As shown in FIGS. 6A and 6B, the peak counter value Dp of the peak counter circuit 33 is controlled based on the voltages Vcomin and Vcomp input from the comparators 31 and 131. To do. As described above with reference to FIG. 6A, when the voltage Vcomin is high, the peak counter value Dp is set to the first value in synchronization with the rise of the basic clock signal Cl1 at the fall timing of the temperature compensation clock signal Cl2. Increase by a predetermined value. When the voltage Vcomin is low, the peak counter value Dp is decreased by a second predetermined value in synchronization with the rising of the basic clock signal Cl1 at the falling timing of the temperature compensation clock signal Cl2. In addition, if the voltage Vcomp is high (YES in S50 (1) YES) and the temperature compensation clock signal Cl2 does not fall (NO in S50 (2)), it is synchronized with the rising edge of the basic clock signal Cl1. Then, the peak counter value Dp is increased by the first predetermined value (S52).
In the peak hold circuit 30 of this embodiment, when the voltage Vin of the input signal becomes higher than the stored value V1 of the peak hold circuit 30 even during the stop period in which the stop determination signal is on, the basic clock signal Cl1 is used. In synchronization, the stored value V1 is made to follow the voltage Vin of the input signal.

The peak hold circuit 30 decreases the peak counter value Dp of the peak counter circuit 33 at the rising timing of the peak hold value decrease signal Vθ1 from the binarization determination circuit 120 during the operation period in which the stop determination signal is turned off. Therefore, even if the input signal voltage Vin includes a short-cycle fluctuation component as well as a long-cycle fluctuation component, the peak voltage of the input signal voltage Vin gradually decreases even when the peak voltage of the input signal voltage Vin slowly decreases. The voltage can be stored in the peak hold circuit 30. Further, during the stop period in which the stop determination signal is turned on, a state in which the stored value V1 of the peak hold circuit 30 is higher than the voltage Vin of the input signal is formed, and the basic clock signal Cl1 is generated at the falling timing of the temperature compensation clock signal Cl2. The stored value V1 of the peak hold circuit 30 is made to follow the voltage Vin of the input signal in synchronization with the rising edge of the input signal. As a result, the stored value V1 of the peak hold circuit 30 and the voltage Vin of the input signal can be kept at a constant potential difference.
The peak hold circuit 30 stores the stored value V1 as a peak counter value Dp that is a digital value. As a result, the time required for processing the stored value V1 can be shortened, and the peak hold circuit 30 can be reduced in size.

  The bottom hold circuit 40 is connected to the input terminal 20, the basic clock terminal 22, the reset terminal 24, the temperature compensation clock terminal 25, the binarization determination circuit 120, the input signal detection circuit 130, and the stop determination circuit 140. FIG. 4 shows a specific configuration of the bottom hold circuit 40. The bottom hold circuit 40 includes a comparator 41, a bottom counter control circuit 42, a bottom counter circuit 43, and a D / A conversion circuit 44. An inverting input terminal 41 b of the comparator 41 is connected to the input terminal 20. The non-inverting input terminal 41 a of the comparator 41 is connected to the output terminal 44 a of the D / A conversion circuit 44. The output terminal 41 c of the comparator 41 is connected to the input part 42 a of the bottom counter control circuit 42. In addition to the output terminal 41c of the comparator 41, the input unit 42a of the bottom counter control circuit 42 includes a basic clock terminal 22, a temperature compensation clock terminal 25, a binarization determination circuit 120, an input signal detection circuit 130, and a stop determination. A circuit 140 is connected. The output part 42b of the bottom counter control circuit 42 is connected to the DOWN terminal 43b, the first UP terminal 43c, and the second UP terminal 43d of the bottom counter circuit 43. A reset (RES) input terminal 43 a of the bottom counter circuit 43 is connected to the reset terminal 24. The bottom counter circuit 43 is connected to the D / A conversion circuit 44. The output terminal 44 a of the D / A conversion circuit 44 is connected to the non-inverting input terminal 41 a of the comparator 41 and also connected to the binarization determination circuit 120.

  In the comparator 41, when the voltage Vin (that is, the voltage of the input signal) input to the inverting input terminal 41b is lower than the stored value V2 of the bottom hold circuit 40 input to the non-inverting input terminal 41a, the output terminal 41c The voltage goes high. On the other hand, when the voltage Vin is higher than the stored value V2, the voltage of the output terminal 41c becomes low. The bottom counter circuit 43 includes a digitized bottom counter value Db, and increases or decreases the bottom counter value Db according to signals input from the reset terminal 24 and the bottom counter control circuit 42. That is, the bottom counter circuit 43 corresponds to the second storage circuit, and the bottom counter value Db stored in the bottom counter circuit 43 corresponds to the storage value of the second storage circuit. In the bottom counter circuit 43, when a signal is input to the DOWN input terminal 43b, the bottom counter value Db of the bottom counter circuit 43 is decreased by a first predetermined value in accordance with this signal. When a signal is input to the first UP input terminal 43c, the bottom counter value Db of the bottom counter circuit 43 is increased by a second predetermined value in accordance with this signal. When a signal is input to the second UP input terminal 43d, the bottom counter value Db of the bottom counter circuit 43 is increased by a third predetermined value in accordance with this signal. In the bottom hold circuit 40, when a reset signal is input from the reset terminal 24, the bottom counter value Db is reset to an initial value.

The bottom hold circuit 40 controls the bottom counter value Db as follows based on the stop determination signal input from the stop determination circuit 140.
(1) When the Stop Determination Signal is Off As shown in FIG. 5C, the bottom counter is based on the voltage Vcomb input from the comparator 41 and the bottom hold value increase signal Vθ2 input from the binarization determination circuit 120. The bottom counter value Db of the circuit 43 is controlled. When voltage Vcomb is high (that is, voltage Vin is lower than stored value V2) (YES in S30 (1) YES), bottom counter value Db is decreased by a first predetermined value in synchronization with the rise of basic clock signal Cl1. (S32). When voltage Vcomb is low and bottom hold value increase signal Vθ2 is inverted from low to high ((1) NO (2) YES in S30), the bottom counter is synchronized with the rising of basic clock signal Cl1. The value Db is increased by a third predetermined value (S34).
(2) When the Stop Determination Signal is On As shown in FIGS. 6A and 6C, the bottom counter value Db of the bottom counter circuit 43 is controlled based on the voltages Vcomin and Vcomb input from the comparators 41 and 131. To do. As described above with reference to FIG. 6A, when the voltage Vcomin is high, the bottom counter value Db is set to the first counter in synchronization with the rise of the basic clock signal Cl1 at the fall timing of the temperature compensation clock signal Cl2. Increase by a predetermined value. When the voltage Vcomin is low, the bottom counter value Db is decreased by a second predetermined value in synchronization with the rising of the basic clock signal Cl1 at the falling timing of the temperature compensation clock signal Cl2. In addition, when the voltage Vcomb is high (YES in S60 (1) YES) and the temperature compensation clock signal Cl2 does not fall (NO in S60 (2)), it is synchronized with the rise of the basic clock signal Cl1. Then, the bottom counter value Db is decreased by the first predetermined value (S62).
In the bottom hold circuit 40 of the present embodiment, when the voltage Vin of the input signal becomes lower than the stored value V2 of the bottom hold circuit 40 even in the stop period in which the stop determination signal is turned on, the bottom hold circuit 40 is synchronized with the basic clock signal Cl1. Thus, the stored value V2 is made to follow the voltage Vin of the input signal.

The bottom hold circuit 40 increases the bottom counter value Db of the bottom counter circuit 43 based on the bottom hold value increase signal Vθ2 from the binarization determination circuit 120 during the operation period in which the stop determination signal is turned off. Therefore, even if the input signal voltage Vin includes a short cycle fluctuation component and a long cycle fluctuation component, the bottom voltage of the input signal voltage Vin gradually increases even if the bottom voltage of the input signal voltage Vin increases slowly. The voltage can be stored in the bottom hold circuit 40. In addition, during the stop period in which the stop determination signal is turned on, a state in which the stored value V2 of the bottom hold circuit 40 is lower than the voltage Vin of the input signal is formed, and the basic clock signal Cl1 is generated at the falling timing of the temperature compensation clock signal Cl2. The stored value V2 of the bottom hold circuit 40 is made to follow the voltage Vin of the input signal in synchronization with the rising edge of the input signal. As a result, the stored value V2 of the bottom hold circuit 40 and the voltage Vin of the input signal can be maintained at a constant potential difference.
The bottom hold circuit 40 stores the stored value V2 as a bottom counter value Db that is a digital value. As a result, the time required for processing the stored value V2 can be shortened, and the bottom hold circuit 40 can be reduced in size.

The binarization determination circuit 120 is connected to the input terminal 20, the binarization output terminal 26, the delay output terminal 28, the peak hold circuit 30, and the bottom hold circuit 40. FIG. 7 shows a specific configuration of the binarization determination circuit 120. The binarization determination circuit 120 includes a threshold value calculation circuit 50, a first comparison circuit 60, a second comparison circuit 70, a first selection circuit 80, a second selection circuit 90, a third selection circuit 100, and a fourth selection circuit 110. ing. A specific structure and function of the binarization determination circuit 120 will be described with reference to FIG.

A specific configuration of the threshold value calculation circuit 50 is shown on the left side of FIG. In the threshold calculation circuit 50, four resistors R1 to R4 are connected in series in this order between a connection terminal 51 to the peak hold circuit 30 and a connection terminal 55 to the bottom hold circuit 40. A first connection terminal 52 is formed between the resistor R1 and the resistor R2. A second connection terminal 53 is formed between the resistor R2 and the resistor R3. A third connection terminal 54 is formed between the resistors R3 and R4.
The resistance values of the resistors R1 to R4 are the same. Therefore, the voltage of each connection terminal 52, 53, 54 is adjusted to the following value.
Vref = (stored value V1−stored value V2) × (1/2) + stored value V1
Vu = (stored value V1−stored value V2) × (3/4) + stored value V1
Vd = (stored value V1−stored value V2) × (1/4) + stored value V1
The voltage Vref of the second connection terminal 53 is an average value of the stored value V1 of the peak hold circuit 30 and the stored value V2 of the bottom hold circuit 40, and is used as the intermediate threshold value Vref. The voltage Vu of the first connection terminal 52 is an average value of the stored value V1 and the intermediate threshold value Vref, and is used as the high-side offset threshold value Vu. The voltage Vd of the third connection terminal 54 is an average value of the intermediate threshold value Vref and the stored value V2, and is used as the low-side offset threshold value Vd.

  The first comparison circuit 60 includes a first transistor S1, a second transistor S2, a first comparator 61, and a NOT circuit 62. The high-side offset threshold value Vu is input to one terminal of the first transistor S1, and the other terminal is connected to the inverting input terminal 61a of the first comparator 61. The output terminal 62b of the NOT circuit 62 is connected to the gate electrode G1 of the first transistor S1. The intermediate threshold value Vref is input to one terminal of the second transistor S 2, and the other terminal is connected to the inverting input terminal 61 a of the first comparator 61. The output terminal 61c of the first comparator 61 is connected to the gate electrode G2 of the second transistor S2. The non-inverting input terminal 61 b of the first comparator 61 is connected to the input terminal 20. The output terminal 61c of the first comparator 61 is connected to the gate electrode G2 of the second transistor S2, and is connected to the input terminal 62a of the NOT circuit 62, the second selection circuit 90, and the third selection circuit 100. The output terminal 62b of the NOT circuit 62 is connected to the gate electrode G1 of the first transistor S1 and to the first selection circuit 80.

  The second comparison circuit 70 includes a third transistor S3, a fourth transistor S4, a second comparator 71, and a NOT circuit 72. The intermediate threshold value Vref is input to one terminal of the third transistor S 3, and the other terminal is connected to the inverting input terminal 71 a of the second comparator 71. The output terminal 72b of the NOT circuit 72 is connected to the gate electrode G3 of the third transistor S3. The low-side offset threshold value Vd is input to one terminal of the fourth transistor S4, and the other terminal is connected to the inverting input terminal 71a of the second comparator 71. The output terminal 71c of the second comparator 71 is connected to the gate electrode G4 of the fourth transistor S4. A non-inverting input terminal 71 b of the second comparator 71 is connected to the input terminal 20. The output terminal 71c of the second comparator 71 is connected to the gate electrode G4 of the fourth transistor S4 and to the input terminal 72a of the NOT circuit 72 and the first selection circuit 80. An output terminal 72b of the NOT circuit 72 is connected to the gate electrode G3 of the third transistor S3 and to the second selection circuit 90 and the fourth selection circuit 110.

  The operation of the first comparison circuit 60 and the second comparison circuit 70 will be described with reference to FIG. FIG. 8A shows a change in the voltage Vin of the input signal input to the input terminal 20, and FIG. 8A will be described using an input signal having a constant peak voltage and bottom voltage. When the peak voltage and the bottom voltage are constant, the high-side offset threshold value Vu, the intermediate threshold value Vref, and the low-side offset threshold value Vd are also constant. FIG. 8B shows the output voltage that the first comparison circuit 60 outputs to the first selection circuit 80. FIG. 8C shows the output voltage that the second comparison circuit 70 outputs to the second selection circuit 90 and the fourth selection circuit 110. FIG. 8D shows a binarized signal that is the first output signal that the first selection circuit 80 outputs to the binarized output terminal 26. FIG. 8E shows a delayed binary signal that is the second output signal output from the second selection circuit 90 to the delayed output terminal 28.

The operation of the first comparison circuit 60 will be described. The first transistor S1 and the second transistor S2 shown in FIG. 7 are both n-type transistors and are turned on when a high voltage is applied to the gate electrode. Until the voltage Vin of the input signal exceeds the high-side offset threshold Vu (t12), the first transistor S1 is on and the second transistor S2 is off. The high-side offset threshold value Vu is input to the inverting input terminal 61a of the first comparator 61, and a high signal is output to the first selection circuit 80 as shown in FIG. 8B.
When the voltage Vin of the input signal exceeds the high-side offset threshold Vu (t12), the voltage at the output terminal 61c of the first comparator 61 is switched to high. As a result, the second transistor S2 is turned on. Further, the voltage at the output terminal 62b of the NOT circuit 62 is switched to low. As a result, the first transistor S1 is turned off. As a result, the voltage at the inverting input terminal 61a of the first comparator 61 is switched to the intermediate threshold value Vref, and the signal output to the first selection circuit 80 is switched to low as shown in FIG. 8B.
Next, when the voltage Vin of the input signal falls below the intermediate threshold value Vref (t13), the voltage at the output terminal 61c of the first comparator 61 is switched to low. As a result, the second transistor S2 is turned off. Further, the voltage at the output terminal 62b of the NOT circuit 62 is switched to high. As a result, the first transistor S1 is turned on. As a result, the voltage at the inverting input terminal 61a of the first comparator 61 is switched to the high-side offset threshold Vu, and the signal output to the first selection circuit 80 is switched to high as shown in FIG. 8B. . Thereafter, this operation is repeated.
In the first comparison circuit 60, the voltage input to the inverting input terminal 61a of the first comparator 61 is switched between the high-side offset threshold value Vu and the intermediate threshold value Vref using the first transistor S1 and the second transistor S2. As a result, a signal that is inverted when the voltage Vin of the input signal falls below the intermediate threshold Vref and when it exceeds the high-side offset threshold Vu is output.

Next, the operation of the second comparison circuit 70 will be described. The third transistor S3 and the fourth transistor S4 shown in FIG. 7 are both n-type transistors and are turned on when a high voltage is applied to the gate electrode. Until the voltage Vin of the input signal exceeds the intermediate threshold value Vref (t11), the third transistor S3 is on and the fourth transistor S4 is off. The intermediate threshold value Vref is inputted to the inverting input terminal 71a of the second comparator 71, and a high signal is outputted to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG. 8C.
When the voltage Vin of the input signal exceeds the intermediate threshold value Vref (t11), the voltage at the output terminal 71c of the second comparator 71 is switched to high. As a result, the fourth transistor S4 is turned on. Further, the voltage at the output terminal 72b of the NOT circuit 72 is switched to low. As a result, the third transistor S3 is turned off. As a result, the voltage at the inverting input terminal 71a of the second comparator 71 is switched to the low-side offset threshold value Vd, and is output to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG. 8C. The signal switches to low.
Next, when the voltage Vin of the input signal falls below the low-side offset threshold Vd (t14), the voltage at the output terminal 71c of the second comparator 71 is switched to low. As a result, the fourth transistor S4 is turned off. Further, the voltage at the output terminal 72b of the NOT circuit 72 is switched to high. As a result, the third transistor S3 is turned on. As a result, the voltage at the inverting input terminal 71a of the second comparator 71 is switched to the intermediate threshold value Vref, and the signals output to the second selection circuit 90 and the fourth selection circuit 110 as shown in FIG. Switch to high. Thereafter, this operation is repeated.
In the second comparison circuit 70, the voltage input to the inverting input terminal 71a of the second comparator 71 is switched between the intermediate threshold value Vref and the low-side offset threshold value Vd using the third transistor S3 and the fourth transistor S4. As a result, a signal that is inverted when the voltage Vin of the input signal falls below the low-side offset threshold Vd and when it exceeds the intermediate threshold Vref is output.

The first selection circuit 80 includes a flip-flop circuit 81. The flip-flop circuit 81 has a set terminal 81S, a reset terminal 81R, and an output terminal 81Q. In the flip-flop circuit 81, when the set terminal 81S rises from low to high, the voltage at the output terminal 81Q goes high, and when the reset terminal 81R rises from low to high, the voltage at the output terminal 81Q goes low. It becomes.
A set terminal 81S of the flip-flop circuit 81 is connected to the second comparison circuit 70, and a signal obtained by inverting the signal shown in FIG. The reset terminal 81R of the flip-flop circuit 81 is connected to the first comparison circuit 60, and the signal shown in FIG. The output terminal 81Q of the flip-flop circuit 81 is connected to the binarized output terminal 26. Due to the input / output signal characteristics of the flip-flop circuit described above, from the binarized output terminal 26, as shown in FIG. 8D, when the voltage Vin of the input signal falls below the intermediate threshold Vref (t11). A binary signal that is inverted when the intermediate threshold Vref is exceeded (t13) is output.

The second selection circuit 90 includes a flip-flop circuit 91. The flip-flop circuit 91 has the same terminal and input / output characteristics as the flip-flop circuit 81, and a duplicate description is omitted.
The set terminal 91S of the flip-flop circuit 91 is connected to the first comparison circuit 60, and a signal obtained by inverting the signal shown in FIG. The reset terminal 91R of the flip-flop circuit 91 is connected to the second comparison circuit 70, and the signal shown in FIG. The output terminal 91Q of the flip-flop circuit 91 is connected to the delayed output terminal 28. Due to the input / output signal characteristics of the flip-flop circuit described above, when the voltage Vin of the input signal exceeds the high-side offset threshold Vu from the second output terminal 28 as shown in FIG. 8E (t12). When the value falls below the low-side offset threshold Vd (t14), a delayed binary signal is output.

The third selection circuit 100 includes a rising edge detection circuit 101. A signal obtained by inverting the signal shown in FIG. 8B is input to the input terminal 101 a of the rise detection circuit 101, and the output terminal 101 b of the rise detection circuit 101 is connected to the peak hold circuit 30. The rise detection circuit 101 outputs the peak hold value decrease signal Vθ1 from the output terminal 101b when the signal input from the input terminal 101a rises from low to high.
The fourth selection circuit 110 includes a falling detection circuit 111. A signal shown in FIG. 8C is input to the input terminal 111 a of the fall detection circuit 111, and the output terminal 111 b of the fall detection circuit 111 is connected to the bottom hold circuit 40. The falling detection circuit 111 outputs a bottom hold value increase signal Vθ2 from the output terminal 111b when the signal input from the input terminal 111a falls from high to low.
In the above description, the first comparison circuit 60 is directly connected to the third selection circuit 100, and the second comparison circuit 70 is directly connected to the fourth selection circuit 110. Instead, the first comparison circuit 60 and the second comparison circuit 70 may be connected to the third selection circuit 100 and the fourth selection circuit 110 via the second selection circuit 90.

The stop determination circuit 140 is connected to the basic clock terminal 22, the determination clock terminal 23, the reset terminal 24, the binarized output terminal 26, the peak hold circuit 30, the bottom hold circuit 40, and the input signal detection circuit 130.
A specific configuration of the stop determination circuit 140 is shown in FIG. The stop determination circuit 140 includes NOT circuits 141 to 148, D flip-flop circuits 151 to 162 with a reset function, D flip-flop circuits 163 to 166 with a set function, SR flip-flop circuit 167, AND circuits 171 to 180, an OR circuit 181, 182 and NAND circuits 191 to 194. The D flip-flop circuit with a reset function has a data terminal D, a clock terminal CK, a reset terminal R, an output terminal Q, and an inverted output terminal QB. The D flip-flop circuit with a reset function reads the value of the data terminal D and outputs it to the output terminal Q when the clock terminal CK rises from low to high. Further, the inverted value is output to the inverted output terminal QB. When the reset terminal R goes low, the output terminal Q goes low and the inverted output terminal QB goes high. The D flip-flop circuit with a set function has a data terminal D, a clock terminal CK, a set terminal S, an output terminal Q, and an inverted output terminal QB. The D flip-flop circuit with set function reads the value of the data terminal D and outputs it to the output terminal Q when the clock terminal CK rises from low to high. Further, the inverted value is output to the inverted output terminal QB. When the set terminal S goes low, the output terminal Q goes high and the inverted output terminal QB goes low. The SR flip-flop circuit 167 has a set terminal S, a reset terminal R, and an output terminal Q. The SR flip-flop circuit 167 sets the output terminal Q to high when the set terminal S rises from low to high. When the reset terminal R rises from low to high, the output terminal Q is set to low.

  The stop determination circuit 140 receives a binarized signal and a determination clock signal Cl3. The stop determination circuit 140 uses the binarized signal and the determination clock signal Cl3 to turn off when the binarized signal is inverted over the half cycle of the determination clock signal Cl3 and turns off when not inverted. Generate a signal. The stop determination signal is output to the peak hold circuit 30, the bottom hold circuit 40, and the input signal detection circuit 130. The peak hold circuit 30 detects that the input signal is inverted when the stop determination signal is turned off. That is, it is detected that it is an operation period in which the input signal is inverted. The peak hold circuit 30 detects that the input signal is not inverted when the stop determination signal is turned on. That is, it is detected that the input signal is in a stop period that is not inverted. The same applies to the bottom hold circuit 40 and the input signal detection circuit 130.

FIG. 10 shows the result of binarizing the input signal using the binarization circuit 10 of this embodiment. FIG. 10 shows output signals VoutA and VoutB obtained by binarizing two input signals VinA and VinB using two binarization circuits. VpA indicates the peak voltage of the input signal VinA, and VbA indicates the bottom voltage of the input signal VinA. VpB indicates the peak voltage of the input signal VinB, and VbB indicates the bottom voltage of the input signal VinB. Further, T1 indicates an operation period, and T2 indicates a stop period. In FIG. 10, the ambient temperature decreases from Temp1 to Temp2 during the stop period T2.
According to the binarization circuit 10 of the present embodiment, the potential difference between the voltage VpA (similarly, the same as in B) and the input signal VinA is kept constant during the stop period T2 when the stop determination signal is turned on. The potential difference between the voltage VbA and the input signal VinA is also kept constant. Therefore, the potential difference between the threshold value (intermediate threshold value Vref, high-side offset threshold value Vu, high-side offset threshold value Vu) calculated from the voltage VbA and the voltage VpA and the input signal VinA is also kept constant, and the output signal VoutA is inverted during the stop period. It is suppressed.
Further, according to the binarization circuit 10 of the present embodiment, the potential difference among the voltage VpA, the input signal VinA, and the voltage VbA can be kept constant during the stop period T2, and after the transition from the stop period T2 to the operation period T1. Even in the initial period of the operation period T1, the input signal VinA can be accurately binarized.

  FIG. 11 shows the binarization circuit 210. The binarization circuit 210 includes an input terminal 20, a basic clock terminal 22, a determination clock terminal 23, a reset terminal 24, a temperature compensation clock terminal 25, a binarization output terminal 26, a delay output terminal 28, a peak hold circuit 230, and a bottom hold. A circuit 240, a binarization determination circuit 120, a control signal generation circuit 330, and a stop / voltage determination circuit 340 are provided.

  The input terminal 20 is connected to the peak hold circuit 230, the bottom hold circuit 240, and the binarization determination circuit 120. The basic clock terminal 22 is connected to the peak hold circuit 230, the bottom hold circuit 240, the control signal generation circuit 330, and the stop / voltage determination circuit 340. The determination clock terminal 23 is connected to the stop / voltage determination circuit 340. The reset terminal 24 is connected to the peak hold circuit 230, the bottom hold circuit 240, the control signal generation circuit 330, and the stop / voltage determination circuit 340. The temperature compensation clock terminal 25 is connected to the peak hold circuit 230, the bottom hold circuit 240, and the control signal generation circuit 330. Signals input from the respective terminals are the same as those in the binarization circuit 10, and redundant description is omitted.

  The peak hold circuit 230 includes an input terminal 20, a basic clock terminal 22, a reset terminal 24, a temperature compensation clock terminal 25, a binarization output terminal 26, a bottom hold circuit 240, a binarization determination circuit 120, and a control signal generation circuit 330. The stop / voltage determination circuit 340 is connected. FIG. 12 shows a specific configuration of the peak hold circuit 230. An output terminal 231 c of the comparator 231 is connected to the bottom hold circuit 240, the control signal generation circuit 330, and the stop / voltage determination circuit 340. The binarized output terminal 26, the bottom hold circuit 240, the control signal generation circuit 330, and the stop / voltage determination circuit 340 are connected to the input unit 232 a of the peak count control circuit 232. Other connections are the same as those of the peak hold circuit 30 shown in FIG.

  The bottom hold circuit 240 includes an input terminal 20, a basic clock terminal 22, a reset terminal 24, a temperature compensation clock terminal 25, a binarized output terminal 26, a peak hold circuit 230, a binarization determination circuit 120, and a control signal generation circuit 330. The stop / voltage determination circuit 340 is connected. FIG. 13 shows a specific configuration of the bottom hold circuit 240. An output terminal 241 c of the comparator 241 is connected to the peak hold circuit 230, the control signal generation circuit 330, and the stop / voltage determination circuit 340. The binarized output terminal 26, the peak hold circuit 230, the control signal generation circuit 330, and the stop / voltage determination circuit 340 are connected to the input unit 242a of the bottom count control circuit 242. Other connections are the same as those of the bottom hold circuit 40 shown in FIG.

The peak hold circuit 230 and the bottom hold circuit 240 are based on the stop determination signal input from the stop / voltage determination circuit 340 and the binarized signal Vout output from the binarized output terminal 26, and the peak counter value Dp and the bottom hold circuit 240. The counter value Db is controlled as follows. Note that the control when the stop determination signal is OFF is the same as in the case of the peak hold circuit 30 and the bottom hold circuit 40, and redundant description is omitted.
In the binarization circuit 210 of the present embodiment, when the stop determination signal is turned on, first, an initial operation shown in FIG. In the initial operation, the peak hold value coincidence signal Vpcl and the bottom hold value coincidence signal Vbcl input from the stop / voltage determination circuit 340 are set to high (S70), and the binarized signal Vout is monitored (S72). When the binarized signal Vout is high (YES in S72), the process proceeds to step S80. When the binarized signal Vout is low (NO in S72), the process proceeds to step S90.

  In step S80, the peak hold circuit 230 monitors the voltage Vcomp input from the comparator 231. If the voltage Vcomp is high (that is, the voltage Vin is higher than the stored value V1) (YES in S80), step S84 is performed. Migrate to When the voltage Vcomp is low (NO in S80), the peak counter value Dp stored in the peak hold circuit 230 is decreased by a second predetermined value in synchronization with the rising of the basic clock signal Cl1 (S82). By repeating step S80 and step S82, the stored value V1 decreases, and the voltage Vin and the stored value V1 substantially coincide with each other in a state where the voltage Vin is higher than the stored value V1. In step S84, the peak hold value coincidence signal Vpcl and the peak flag signal Fp input from the control signal generation circuit 330 are set to low (S84, S86), and the temperature compensation operation shown in FIG. And migrate.

In the temperature compensation operation shown in FIG. 14B, the peak counter value Dp and the bottom counter value Db are controlled based on the voltage Vcomp input from the comparator 231 and the peak flag signal Fp.
When the voltage Vcomp is high (that is, the voltage Vin is higher than the stored value V1) ((1) YES in S1000), the basic clock signal at the timing of the fall of the temperature compensation clock signal Cl2 ((3) YES in S100). In synchronization with the rise of Cl1, the peak counter value Dp is increased by a first predetermined value, the bottom counter value Db is increased by a second predetermined value, and the peak flag signal Fp is set to low (S102). When the voltage Vcomp is high and the temperature compensation clock signal Cl2 does not fall (NO in S100 (3) NO), the peak counter value Dp is set to the first predetermined value in synchronization with the rise of the basic clock signal Cl1. Is increased only by S104.
Further, when the voltage Vcomp is low (NO in S100 (1)), when the peak flag signal Fp is high (YES in (2) in S100), the temperature compensation clock signal Cl2 falls (in S100 (3) ) At the timing of (YES), the bottom counter value Db is increased by the second predetermined value in synchronization with the rising of the basic clock signal Cl1, and the peak flag signal Fp is set to low (S106). Further, when the peak flag signal Fp is low ((2) NO in S100), the peak is synchronized with the rising edge of the basic clock signal Cl1 at the timing of the falling edge of the temperature compensation clock signal Cl2 ((3) YES in S100). The counter value Dp is decreased by the second predetermined value, and the bottom counter value Db is decreased by the first predetermined value (S108).
By the processing of Step S100 to Step S108, the stored value V1 and the stored value V2 can be changed following the voltage Vin during the stop period in which the stop determination signal is turned on, and the stored value V1, the stored value V2, and the voltage Vin. Can be maintained at a constant potential difference.

  In the above-described control, a process for substantially matching the voltage Vin and the stored value V1 is performed for the initial operation, and a process for changing the stored value V1 following the voltage Vin is performed for the temperature compensation operation. Prior to making the stored value V1 follow the voltage Vin, if the voltage Vin and the stored value V1 are substantially matched, when the stored value V1 and the stored value V2 are made to follow the voltage Vin, the stored value V1 is changed to the voltage Vin. Can be set equal. Therefore, the processing in the peak hold circuit 230 can be simplified. Further, since the voltage Vin and the stored value V1 are substantially matched in the peak hold circuit 230, a circuit for storing the voltage Vin separately from the peak hold circuit 230 (for example, the input signal detection circuit 130 of the binarization circuit 10). ) Is not necessary. Therefore, the configuration of the binarization circuit 210 can be simplified.

  In step S90, the bottom hold circuit 240 monitors the voltage Vcomb input from the comparator 241. If the voltage Vcomb is high (that is, the voltage Vin is lower than the stored value V2) (YES in S90), step S94 is performed. Migrate to When the voltage Vcomb is low (NO in S90), the bottom counter value Db stored in the bottom hold circuit 240 is increased by the second predetermined value in synchronization with the rising of the basic clock signal Cl1 (S92). By repeating step S90 and step S92, the stored value V2 increases, and the voltage Vin and the stored value V1 substantially coincide with each other when the voltage Vin is lower than the stored value V2. In step S94, the bottom hold value coincidence signal Vbcl and the bottom flag signal Fb input from the control signal generation circuit 330 are set to low (S94, S96), and the temperature compensation operation shown in FIG. And migrate.

In the temperature compensation operation shown in FIG. 14C, the peak counter value Dp and the bottom counter value Db are controlled based on the voltage Vcomb input from the comparator 241 and the bottom flag signal Fb.
When voltage Vcomb is high (that is, voltage Vin is lower than stored value V2) (YES in S110 (1) YES), the basic clock is generated at the timing of the fall of temperature compensation clock signal Cl2 (YES in S110 (3)). In synchronization with the rise of the signal Cl1, the peak counter value Dp is decreased by a second predetermined value, the bottom counter value Db is decreased by a first predetermined value, and the bottom flag signal Fb is set to low (S112). If the temperature compensation clock signal Cl2 does not fall (NO in S110 (3) NO), the bottom counter value Db is decreased by the first predetermined value in synchronization with the rise of the basic clock signal Cl1 (S114).
Further, when the voltage Vcomb is low (NO in S110 (1) NO), if the bottom flag signal Fb is high (YES in S110 (2) YES), the temperature compensation clock signal Cl2 falls (in S110 (3) ) At the timing of YES), the peak counter value Dp is decreased by the second predetermined value in synchronization with the rising of the basic clock signal Cl1, and the bottom flag signal Fb is set to low (S116). When the bottom flag signal Fb is low ((2) NO in S110), the peak is synchronized with the rising of the basic clock signal Cl1 at the timing of the falling of the temperature compensation clock signal Cl2 ((3) YES in S100). The counter value Dp is increased by the first predetermined value, and the bottom counter value Db is increased by the second predetermined value (S118).
Through the processing in steps S110 to S118, the stored value V1 and the stored value V2 can be changed following the voltage Vin during the stop period in which the stop determination signal is turned on, and the stored value V1, the stored value V2, and the voltage Vin. Can be maintained at a constant potential difference.

  In the above-described control, a process for substantially matching the voltage Vin and the stored value V2 is performed for the initial operation, and a process for changing the stored value V2 following the voltage Vin is performed for the temperature compensation operation. Prior to making the stored value V2 follow the voltage Vin, if the voltage Vin and the stored value V2 are substantially matched, the stored value V2 is set equal to the voltage Vin when the stored value V2 is made to follow the voltage Vin. Can do. Therefore, the processing in the bottom hold circuit 240 can be simplified. Further, since the voltage Vin and the stored value V2 are substantially matched in the bottom hold circuit 240, a circuit that stores the voltage Vin separately from the bottom hold circuit 240 (for example, the input signal detection circuit 130 of the binarization circuit 10). ) Is not necessary. Therefore, the configuration of the binarization circuit 210 can be simplified.

The binarization determination circuit 120 is connected to the input terminal 20, the binarization output terminal 26, the delay output terminal 28, the peak hold circuit 230, and the bottom hold circuit 240. The binarization determination circuit 120 is the same as the binarization determination circuit 120 of the binarization circuit 10 shown in FIG.

The stop / voltage determination circuit 340 is connected to the basic clock terminal 22, the determination clock terminal 23, the reset terminal 24, the binarized output terminal 26, the peak hold circuit 230, the bottom hold circuit 240, and the control signal generation circuit 330.
A specific configuration of the stop / voltage determination circuit 340 is shown in FIG. The stop / voltage determination circuit 340 includes a NOT circuit 341, AND circuits 171 and 172, and SR flip-flop circuits 168 to 169 in addition to the stop determination circuit 140 of the binarization circuit 10 shown in FIG. Thus, in addition to the processing executed by the stop determination circuit 140, the following processing is further executed.
The stop / voltage determination circuit 340 receives the voltage Vcomp from the peak hold circuit 230. The stop / voltage determination circuit 340 outputs a peak hold value coincidence signal Vpcl that goes low when the voltage Vcomp goes high during the period when the binarized signal Vout is high during the stop period. When the peak hold value coincidence signal Vpcl is used, the timing at which the stored value V1 and the voltage Vin substantially coincide in the stop period can be detected with high accuracy.
The stop / voltage determination circuit 340 receives the voltage Vcomb from the bottom hold circuit 240. The stop / voltage determination circuit 340 outputs a bottom hold value coincidence signal Vbcl that goes low when the voltage Vcomb goes high during the period when the binarized signal Vout is low during the stop period. By using the bottom hold value coincidence signal Vbcl, it is possible to accurately detect the timing at which the stored value V2 and the voltage Vin substantially coincide in the stop period.

The control signal generation circuit 330 is connected to the basic clock terminal 22, the reset terminal 24, the temperature compensation clock terminal 25, the peak hold circuit 230, the bottom hold circuit 240, and the stop / voltage determination circuit 340.
A specific structure of the control signal generation circuit 330 is shown in FIG. The control signal generation circuit 330 includes NOT circuits 351 to 355, SR flip-flop circuits 361 and 362, AND circuits 371 to 376, NAND circuits 381 to 384, D flip-flop circuits 391 to 394 with a reset function, and D flip-flops with a set function. Implemented by circuits 395-398.

The control signal generation circuit 330 receives the stop determination signal, the peak hold value match signal Vpcl, and the bottom hold value match signal Vbcl from the stop / voltage determination circuit 340. The voltage Vcomp is input from the peak hold circuit 230 and the voltage Vcomb is input from the bottom hold circuit 240. The control signal generation circuit 330 outputs the peak flag signal Fp and the bottom flag signal Fb using the above signals.
As shown in FIG. 17, the peak flag signal Fp falls in synchronization with the fall of the peak hold value coincidence signal Vpcl during the stop period in which the stop determination signal is turned on. Thereafter, the peak flag signal Fp rises in synchronization with the rise of the signal from the output terminal 231c of the comparator 231 of the peak hold circuit 230, and falls in synchronization with the fall of the temperature compensation clock signal Cl2. The bottom flag signal Fb falls in synchronization with the fall of the bottom hold value match signal Vbcl during the stop period in which the stop determination signal is turned on. Thereafter, the bottom flag signal Fb rises in synchronization with the rise of the signal from the output terminal 241c of the comparator 241 of the bottom hold circuit 240, and falls in synchronization with the fall of the temperature compensation clock signal Cl2.

FIG. 18 shows the result of binarizing the input signal using the binarization circuit 210 of this embodiment.
Also in the binarization circuit 210 of the present embodiment, the potential difference between the threshold value calculated from the voltage VbA and the voltage VpA and the input signal VinA is kept constant, and the output signal VoutA is prevented from being inverted during the stop period. Further, according to the binarization circuit 10 of the present embodiment, the potential difference among the voltage VpA, the input signal VinA, and the voltage VbA can be kept constant during the stop period T2, and after the transition from the stop period T2 to the operation period T1. Even in the initial period of the operation period T1, the input signal VinA can be accurately binarized.
Further, in the binarization circuit 210, at least one of the stored value V1 and the stored value V2 is substantially matched with the voltage Vin before the stored value V1 and the stored value V2 are changed following the voltage Vin. Thereby, the processing in the peak hold circuit 230 and the bottom hold circuit 240 included in the binarization circuit 210 can be simplified. In addition, since at least one of the stored value V1 and the stored value V2 is substantially matched with the voltage Vin, a circuit for storing the voltage Vin separately from the peak hold circuit 230 and the bottom hold circuit 240 (for example, a binarization circuit) There is no need to prepare ten input signal detection circuits 130). Therefore, the configuration of the binarization circuit 210 can be simplified.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10, 210 Binary circuit 20 Input terminal 22 Basic clock terminal 23 Determination clock terminal 24 Reset terminal 25 Temperature compensation clock terminal 26 Binary output terminal 28 Delay output terminals 30, 230 Peak hold circuits 31, 231 Comparator 32, 232 Peak Counter control circuit 33, 233 Peak counter circuit 34, 244 D / A conversion circuit 40, 240 Bottom hold circuit 41, 241 Comparator 42, 242 Bottom counter control circuit 43, 243 Bottom counter circuit 44, 244 D / A conversion circuit 50 Threshold value Arithmetic circuit 60 First comparison circuit 70 Second comparison circuit 80 First selection circuit 90 Second selection circuit 100 Third selection circuit 110 Fourth selection circuit 120 Binary decision circuit 130 Input signal detection circuit 131 Comparator 132 Input counter control circuit 133 entering Counter circuit 134 D / A conversion circuit 140 Stop determination circuit 330 Control signal generation circuit 340 Stop / voltage determination circuit Cl1 Basic clock signal Cl2 Temperature compensation clock signal Cl3 Determination clock signal Db Bottom counter value Din Input counter value Dp Peak counter value Fb Bottom Flag signal Fp Peak flag signal V1 Peak hold circuit stored value V2 Bottom hold circuit stored value V3 Input signal detection circuit stored value Vbcl Bottom hold value match signal Vpcl Peak hold value match signal Vθ1 Peak hold value decrease signal Vθ2 Bottom hold value Increase signal T1 Operation period T2 Stop period

Claims (9)

A binarization circuit that binarizes an input signal that varies with time,
It has a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit.
The peak hold circuit includes a first memory circuit, and outputs the stored value of the first memory circuit to the binarization determination circuit. The peak hold circuit receives the first value while the voltage of the input signal is higher than the stored value of the first memory circuit. When the memory value of one memory circuit is increased and the stop determination signal from the stop determination circuit is turned on, the change in the input signal is followed while the voltage of the input signal is lower than the memory value of the first memory circuit. A process for changing the stored value of the first storage circuit is executed,
The bottom hold circuit includes a second memory circuit, and outputs the stored value of the second memory circuit to the binarization determination circuit. The bottom hold circuit is configured to output the second signal while the voltage of the input signal is lower than the stored value of the second memory circuit. 2 When the stored value of the memory circuit is decreased and the stop determination signal from the stop determination circuit is turned on, the change in the input signal is followed while the voltage of the input signal is higher than the stored value of the first memory circuit. Executing a process of changing the stored value of the second storage circuit;
The binarization determination circuit outputs an output signal obtained by binarizing the input signal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit to the output terminal,
The stop determination circuit is turned off when the output signal is inverted within a predetermined period and is turned off when the output signal is not inverted over a predetermined period, and is binarized to output a stop determination signal to the peak hold circuit and the bottom hold circuit circuit. A binarization circuit that binarizes an input signal that varies with time,
An input terminal for inputting an input signal, an output terminal for outputting an output signal, a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit are provided.
The peak hold circuit is connected to the input terminal, the stop determination circuit, and the binarization determination circuit, includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit. 1) When the stop determination signal from the stop determination circuit is turned off, the memory value of the first memory circuit is increased while the voltage of the input signal is higher than the memory value of the first memory circuit. When the stop determination signal from the circuit is turned on and the stored value of the first storage circuit is lower than the voltage of the input signal, the stored value of the first storage circuit is increased, and (3) the stop determination signal from the stop determination circuit Is turned on, and when the stored value of the first memory circuit is higher than the voltage of the input signal, a process of changing the stored value of the first memory circuit following the change of the input signal is executed,
The bottom hold circuit is connected to the input terminal, the stop determination circuit, and the binarization determination circuit, includes a second storage circuit, and outputs the stored value of the second storage circuit to the binarization determination circuit. 1) When the stop determination signal from the stop determination circuit is turned off, the stored value of the second storage circuit is decreased while the voltage of the input signal is lower than the stored value of the second storage circuit, and (2) the stop determination is performed. When the stop determination signal from the circuit is turned on and the stored value of the second storage circuit is higher than the voltage of the input signal, the stored value of the second storage circuit is decreased, and (3) the stop determination signal from the stop determination circuit Is turned on, and when the stored value of the second memory circuit is lower than the voltage of the input signal, a process of changing the stored value of the second memory circuit following the change of the input signal is executed,
The binarization determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit, and is input based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit. Output the binarized output signal to the output terminal,
The stop determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit, and is turned off when the output signal is inverted within a predetermined period, and when the output signal is not inverted over the predetermined period. The binarization circuit according to claim 1, wherein a stop determination signal to be turned on is output to a peak hold circuit and a bottom hold circuit. It has an input signal detection circuit,
The input signal detection circuit is connected to the input terminal, the peak hold circuit, and the bottom hold circuit, includes a third memory circuit, and turns on when the stored value of the third memory circuit is higher than the voltage of the input signal. When the stored value of the 3 memory circuit is lower than the voltage of the input signal, a detection signal that is turned off is output to the peak hold circuit and the bottom hold circuit, and the stored value of the 3rd memory circuit is tracked following the change of the input signal. The process to change is executed,
3. The binarization circuit according to claim 1, wherein each of the first memory circuit, the second memory circuit, and the third memory circuit includes a unit that stores a digitized voltage. A first clock terminal for inputting a first clock signal and connected to a peak hold circuit, a bottom hold circuit, and an input signal detection circuit;
A second clock signal is input, and a second clock terminal connected to the peak hold circuit, the bottom hold circuit, and the input signal detection circuit is provided.
The first memory circuit, the second memory circuit, and the third memory circuit increase or decrease each stored value based on the first clock signal when increasing or decreasing each stored value. 4. The binarization circuit according to claim 3, wherein each of the stored values is changed based on the second clock signal when the signal is changed following the change of the input signal. 5. A binarization circuit that binarizes an input signal that varies with time,
It has a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit.
The peak hold circuit includes a first memory circuit, and outputs the stored value of the first memory circuit to the binarization determination circuit. The peak hold circuit receives the first value while the voltage of the input signal is higher than the stored value of the first memory circuit. When the memory value of one memory circuit is increased and the stop determination signal from the stop determination circuit is turned on, the change in the input signal is followed while the voltage of the input signal is lower than the memory value of the first memory circuit. A process for changing the stored value of the first storage circuit is executed,
The bottom hold circuit includes a second memory circuit, and outputs the stored value of the second memory circuit to the binarization determination circuit. The bottom hold circuit is configured to output the second signal while the voltage of the input signal is lower than the stored value of the second memory circuit. 2 When the stored value of the memory circuit is decreased and the stop determination signal from the stop determination circuit is turned on, the change in the input signal is followed while the voltage of the input signal is higher than the stored value of the first memory circuit. Executing a process of changing the stored value of the second storage circuit;
The binarization determination circuit outputs an output signal obtained by binarizing the input signal based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit to the output terminal,
The stop determination circuit outputs a stop determination signal that is turned off when the output signal is inverted within a predetermined period and turned on when the output signal is not inverted over a predetermined period to the peak hold circuit and the bottom hold circuit,
In the peak hold circuit and the bottom hold circuit, when the stop determination signal from the stop determination circuit is turned on, the stored value of the first storage circuit is changed prior to changing each stored value following the change of the input signal. One of the stored values of the second storage circuit and the voltage of the input signal are made to substantially coincide with the voltage of the input signal. A binarization circuit that binarizes an input signal that varies with time,
An input terminal for inputting an input signal, an output terminal for outputting an output signal, a stop determination circuit, a peak hold circuit, a bottom hold circuit, and a binarization determination circuit are provided.
The peak hold circuit is connected to the input terminal, the output terminal, the stop determination circuit, and the binarization determination circuit. The peak hold circuit includes a first storage circuit, and outputs the stored value of the first storage circuit to the binarization determination circuit. (1) The memory value of the first memory circuit is increased while the voltage of the input signal is higher than the memory value of the first memory circuit, and (2) the stop determination signal from the stop determination circuit is turned on. When the output signal from the value determination circuit is high, the memory value of the first memory circuit is decreased, the memory value of the first memory circuit is made lower than the voltage of the input signal, and the change in the input signal is followed. (3) When the stop determination signal from the stop determination circuit is turned on and the output signal from the binarization determination circuit is low, the second value of the bottom hold circuit is changed. After the storage value of the storage circuit is made higher than the voltage of the input signal, And executes the processing of changing the stored value of the first memory circuit following the change of the value stored in the circuit,
The bottom hold circuit is connected to the input terminal, the output terminal, the stop determination circuit, and the binarization determination circuit, includes a second memory circuit, and outputs the stored value of the second memory circuit to the binarization determination circuit. (1) The stored value of the second storage circuit is decreased while the voltage of the input signal is lower than the stored value of the second storage circuit, and (2) the stop determination signal from the stop determination circuit is turned on. When the output signal from the value determination circuit is high, the memory value of the first memory circuit of the peak hold circuit is made lower than the voltage of the input signal, and then the change of the memory value of the first memory circuit is followed. (3) When the stop determination signal from the stop determination circuit is turned on and the output signal from the binarization determination circuit is low, the storage value of the second storage circuit is changed. Increase the memory value of the second memory circuit higher than the voltage of the input signal To, and executes the processing of changing the stored value of the second storage circuit to follow a change in the input signal,
The binarization determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit, and is input based on a threshold value calculated from the storage value of the first storage circuit and the storage value of the second storage circuit. Output the binarized output signal to the output terminal,
The stop determination circuit is connected to the input terminal, the output terminal, the peak hold circuit, and the bottom hold circuit, and is turned off when the output signal is inverted within a predetermined period, and when the output signal is not inverted over the predetermined period. 6. The binarization circuit according to claim 5, wherein a stop determination signal to be turned on is output to a peak hold circuit and a bottom hold circuit. A first voltage determination circuit and a second voltage determination circuit;
The first voltage determination circuit is connected to the output terminal, the peak hold circuit, and the stop determination circuit, and is inverted when the stop determination signal is turned on and the stored value of the first storage circuit becomes lower than the voltage of the input signal. Output a peak hold value match signal to the peak hold circuit,
The second voltage determination circuit is connected to the output terminal, the bottom hold circuit, and the stop determination circuit, and is inverted when the stop determination signal is turned on and becomes higher than the stored value of the second storage circuit and the voltage of the input signal. 7. The binarization circuit according to claim 5, wherein a bottom hold value coincidence signal is output to the bottom hold circuit. A first clock terminal for inputting a first clock signal and connected to a peak hold circuit and a bottom hold circuit;
A second clock signal is input, and a second clock terminal connected to the peak hold circuit and the bottom hold circuit is provided.
The first memory circuit and the second memory circuit increase or decrease each stored value based on the first clock signal when increasing or decreasing each stored value, and change each stored value to an input signal. 8. The binarization circuit according to claim 7, wherein each of the stored values is changed on the basis of the second clock signal when the change is made in accordance with the second clock signal. 9. A third clock signal is input, and a third clock terminal connected to the stop determination circuit is provided.
The binarization circuit according to claim 1, wherein the stop determination circuit determines a predetermined period based on a cycle of the third clock signal.

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