JP4951486B2 - Information processing apparatus and information processing method - Google Patents

Description

  The present invention relates to an information processing apparatus composed of a plurality of computer components, and more particularly to an information processing method in the case where real-time information and non-real-time information are mixed.

  As a method of configuring a plurality of computers, there are a method of connecting computers with a backplane, or a method of directly connecting computers via a connector (PC / 104-Plus or the like) provided in an individual computer. Communication between each computer is performed by a signal on a bus between computers according to a predetermined protocol.

  On these computers, an operating system (hereinafter referred to as an OS) generally operates and manages computer resources on the computers. In these OSs, there are mainly two types of classification depending on the difference in functions provided by the computer. That is, a real-time OS and a non-real-time OS (hereinafter referred to as a general-purpose OS). The former is mainly for the purpose of controlling the device, and the tasks on the OS are set with priorities and scheduled so as to guarantee time constraints inherent to the tasks. Accordingly, a high priority is generally set for a task that needs to operate in a short cycle. Conversely, a task with a low priority may not be scheduled for a long time. On the other hand, since the latter is a general purpose, the priority is set so that each task is executed on average even though there are some differences in static priority among tasks.

  In a system composed of a plurality of computers, a real-time OS may operate on a certain computer, and a general-purpose OS may operate on another computer. In a computer on which a real-time OS operates, a control command for controlling an external device is transmitted from another computer constituting the same system or another computer connected via a network.

JP 2000-132209 A

  A computer connected to the network sends a packet that requires a real-time property, such as a control command, via the network. The computer that operates the general-purpose OS receives this packet and transfers it to the computer that operates the real-time OS. May be transferred. In this case, the communication delay of the control command to the task operating on the real-time OS must be long enough to guarantee time constraints.

  However, due to fluctuations in the packet protocol processing in the general-purpose OS and the start timing of the protocol processing task, there arises a problem that the imposed time constraint cannot be guaranteed in the actual control command in the computer on which the real-time OS operates.

  In Patent Document 1, the processing time related to PLC data communication using a noise error signal is reduced by performing parallel processing of determination processing of the head code and generation of sum check code determination data of received data during DMAC transfer. ing. However, in the processing of computer components, if real-time processing and non-real-time processing are mixed, there is a problem that the time limit required for real-time processing cannot be observed.

  An object of the present invention is to provide an information processing apparatus and an information processing method capable of transferring to a computer component corresponding to a case where it is determined that real-time processing is necessary in view of the above-described problems of the prior art.

  The present invention relates to an information processing apparatus composed of a plurality of computer components, wherein the plurality of computer components are coupled by a communication bus including an interrupt signal line, and the computer component receives the information when receiving information from the outside. Determining means for determining whether or not a predetermined time constraint is present, and transfer means for transferring information by asserting an interrupt signal line to another corresponding computer component immediately when it is determined that the predetermined time constraint is determined It is characterized by having.

  The determination unit determines whether the packet received from the data input unit is a packet to be transferred to another computer component immediately. If it is determined that the packet should be transferred to another computer component immediately, the transmission unit has This is a real-time transfer determination unit that transfers a packet to a queue having a high priority among the queues. In addition, the transfer means transmits a packet input to a queue having a high priority to another computer component preferentially, and a packet received by the real-time transfer determination unit immediately transfers the packet to another computer component. It consists of a transmission means (interrupt signal line) for transmitting that it is determined that the packet is a packet to the computer component that is the transmission destination of the packet.

  The other computer component to which the information is transferred receives the information by asserting the interrupt signal line, and preferentially processes the information.

  In the information processing method of the present invention, in an information processing apparatus composed of a plurality of computer components, the computer components are connected by a communication bus including an interrupt signal line. If the determined information has a predetermined time constraint, and if it is determined that it has the predetermined time constraint, the interrupt signal line to another corresponding computer component is immediately asserted to transfer the information. Features.

  The operation of the present invention will be described. In order to solve the above problems, the present invention determines whether or not the packet is to be transferred in real time by hardware on a computer that has received the packet. If it is necessary to transfer in real time, the protocol processing is omitted, the packet is immediately transferred to the target computer, and an interrupt signal indicating real-time transfer is notified at the same time. In this way, even when a packet requiring real-time property is received on a computer on which a general-purpose OS operates, the packet can be transferred to the target computer in real time.

  Further, the effect of the present invention can be confirmed by measuring the difference between the time point when the computer has a time measuring function and it is determined whether or not to transfer the packet in real time and the time point when the packet is transferred.

  In addition, information related to packets transferred in real time (transmission source address, reception time, determination time, transfer time, transmission destination computer, etc.) can be recorded and displayed to check the operation status of the present invention. it can.

  An information processing system that consists of multiple computers and can be transferred in real time to a computer running a real-time OS even when a communication packet is received by a computer running a general-purpose OS can be provided, ensuring real-time constraints reliably There is an effect.

  According to the best mode of the present invention, in an information processing apparatus composed of a plurality of computer components, the computer component (104) includes a data input unit (113) and one or a plurality of queues for which priority setting is possible. And a transmission unit (116) that preferentially transmits a packet input to a queue having a high priority to another computer component, and a packet that is received from the data input unit is to be immediately transferred to another computer component. A real-time transfer determination unit (114) for transmitting a packet to a queue having a higher priority among the queues of the communication unit when it is determined that the transfer should be immediately transferred to another computer component And the real-time transfer determination unit immediately sends the packet received from the data input unit to another computer component. That it has determined that the packet should be forwarded to preparative (104), and a transmitting means for transmitting to the computer component is a destination of the packet (118,126). In addition, the computer component that is the transmission destination receives the packet received by the determination of the real-time transfer determination unit by the transmission unit in the queue with the high priority.

  The real-time transfer determination unit includes a determination criterion storage unit (122) for storing a determination criterion for determining whether a packet received from the data input unit is a packet to be immediately transferred to another computer component, and the determination A determination criterion setting unit (121) for setting a determination criterion in the reference storage unit is provided.

  Hereinafter, a plurality of embodiments will be described in detail with reference to the drawings.

  FIG. 2 shows an example of an information processing apparatus composed of computer components. The information processing apparatus 102 is connected to the information processing apparatus 100 via the network 101 and is also connected to the control apparatus 103. The information processing apparatus 100 transmits a control command for controlling the control apparatus 103 to the information processing apparatus 102 via the network 101 and collects operation information of the control apparatus 103.

  FIG. 3 is an external view of the information processing apparatus. The information processing apparatus 102 includes a plurality of computer components 104a to 104e.

  FIG. 1 is a configuration diagram of computer components to which the present invention is applied. The CPU 110 transfers the program from the nonvolatile storage medium 112 to the RAM 111 and executes it. Examples of the execution processing program include a program for communicating with the OS and the network 101, and a program for communicating with the other computer components 104b to 104e to be connected. The RAM 111 is a temporary storage area for the operation of the CPU 110, and stores the OS, application programs, information on the execution tasks being executed, etc. transferred from the nonvolatile storage medium 112. The non-volatile storage medium 112 is an information storage medium, and is used for storing a program for operating the CPU 110 and storing a program execution result.

  The LAN 113 is a transceiver IC that implements a communication function with a network. Examples of communication standards provided by the LAN 113 include Ethernet (trademark of Xerox). The user logic IC 114 is an IC that provides an arbitrary function on hardware. Examples of the user logic IC 114 include FPGA, CPLD, gate array, ASIC, and the like. The bus 115 connects the CPU 110, the RAM 111, the nonvolatile storage medium 112, the LAN 113, the user logic IC 114, and the communication buffer 116, respectively. Examples of the bus 115 include a PCI bus, an ISA bus, a PCI Express bus, and the like.

  The communication buffer 116 is a buffer IC for transmission packets. The communication buffer 116 and the user logic IC 114 may be mounted on the same IC. In that case, the user logic IC 114 and the communication buffer 116 are connected by a bus in the IC. Further, the communication buffer 116 and the LAN 113 may be mounted on the same IC. In that case, the LAN 113 and the communication buffer 116 are connected by a bus in the IC.

  The inter-component communication IC 117 is an IC for communicating with other computer components 104 b to e configuring the information processing apparatus 102, and is connected to the communication buffer 116. Specific examples include a bridge IC for various bus protocols such as a PCI bridge bus and a controller IC for a specific bus protocol. The inter-component communication IC may be included in the CPU 110, and may be included in the user logic IC 114 together with the communication buffer 116.

  The interrupt signal line 126 is asserted by the communication buffer 116 when a packet is transmitted from the high priority queue of the communication buffer 116. When the interrupt signal line 126 is asserted, the signal line 118 is asserted via the user logic IC 114.

  The interrupt signal line 118 is asserted by the user logic IC 114 at a predetermined timing for a predetermined period when a packet transmitted from the inter-component communication IC 117 has a predetermined time constraint. The timing to be asserted is system-dependent, and examples include immediately before a packet is transmitted on the bus, during transmission, and after transmission.

  The inter-component communication bus 119 is a bus for communicating between the components 104. Examples of the bus communication standard for the inter-component communication bus 119 include a PCI bus, a PCI-Express bus, an ISA bus, and the like. Examples of physical connection forms include a PC 104 connector and a card edge connector.

  FIG. 16 shows a packet transmission procedure in the computer component. First, the LAN 113 receives a packet transferred from the outside to another component (S001). Next, the user logic IC 114 receives a packet from the LAN (S002). The user logic IC 114 determines whether the packet has a predetermined time constraint and there is a packet to be transferred immediately (S003). If the packet is to be transferred immediately, the user logic IC 114 transmits the packet to a queue with a high priority in the communication buffer 116. (S004). Next, the communication buffer 116 waits until the output interface can be transmitted (S005). If transmission is possible, the communication buffer 116 transmits a packet to the inter-component communication IC 117, and at the same time asserts the interrupt signal line 126 to the user logic IC 114 (S006). Receiving the assertion of the interrupt signal line 126, the user logic IC 114 asserts the interrupt signal line 118 to other components (S007).

  If the packet is not to be transferred immediately in S003, the user logic IC 114 transmits the packet to the RAM 111 (S008). Thereafter, a transfer process is performed by the OS, and the packet is transmitted to a low priority queue of the communication buffer 116 (S009). Next, the communication buffer 116 waits until the output interface is ready to transmit and there are no packets in the queue with high priority (S010). If transmission is possible, the communication buffer 116 transmits the packet to the inter-component communication IC 117 (S011).

  FIG. 4 is a block diagram of functional units provided by the user logic IC 114. The receiving unit 120 transmits the packet received by the user logic IC 114 to the real-time transfer determination unit 123. The determination criterion setting unit 121 provides a reference setting function for determining whether a packet to be determined is a packet to be transferred immediately. The content of the determination criterion storage unit 122 is changed according to the input content. The determination criterion storage unit 122 stores a criterion for determining whether a packet to be determined is a packet to be transferred immediately. The real-time transfer determination unit 123 determines whether or not the packet to be determined is a packet that should be immediately transferred to the other computer components 104b to 104e according to the determination criterion provided in the determination criterion storage unit 122. The transmission unit 124 transmits the packet to either the RAM 111 or the communication buffer 116 through the bus 115 according to the determination result of the real-time transfer determination unit 123. The receiving unit 120 and the transmitting unit 124 may be a single functional block.

  The real-time transfer control unit 125 controls the real-time transfer determination unit 123. Specific examples of the control include valid / invalid switching of determination by the real-time transfer determination unit 123 and acquisition of the current valid / invalid setting. When the present invention is not used, the determination by the real-time transfer determination unit 123 is invalidated by the real-time transfer control unit 125.

  When the interrupt signal line 126 is asserted, the interrupt signal line assert unit 230 asserts the interrupt signal line 118 according to a predetermined timing. When the interrupt signal line 126 is asserted, the asserted period is different from the asserted timing and the asserted period of the interrupt signal line 118 requested by the reception side, the interrupt signal line asserting unit 230 determines the timing. , Adjust the period.

  FIG. 13 shows a modification of the computer component. When adjustment of the timing and period of assertion is unnecessary, the interrupt signal line 118 is directly connected to the other component 104 from the communication buffer 116 as illustrated.

  A communication packet received on the LAN 113 is transferred to the user logic IC 114 via the bus 115. When the user logic IC 114 receives the communication packet, the user logic IC 114 starts determining whether the packet is to be transferred to another computer component immediately. If the packet is to be transferred immediately, it is transmitted to the communication buffer 116. Otherwise, it is sent to the RAM 111.

  The criteria for determining whether or not to transfer the packet immediately include the contents of the packet, the difference in the input interface on the computer component 104a, the size of the packet, and the like. Specifically, when the destination IP address or source IP address of the IP protocol header on the packet matches a specific IP address, or when the destination MAC address or source MAC address of the Ethernet header is a specific MAC address. Match determination based on address definitions in various communication protocols, such as when they match, when there are multiple external interfaces on the computer component, and packets received from a specific interface, packet size and specific size The case where it determines by the magnitude of is illustrated. Alternatively, a unique protocol may be defined and the determination may be made based on the contents depending on the protocol.

  FIG. 5 shows an example of the data configuration of the criterion storage unit. Each row of the determination criterion table 130 includes a combination of “determination item”, “determination value”, and “destination computer component”. For example, the determination criterion in the first row indicates a destination IP address as a determination item, an IP address of 192.168.0.4 as a determination value, and a computer component at position 0 as a destination computer component. When determining an arbitrary packet, if the transmission destination IP address of the IP header on the packet is 192.168.0.4, it matches the determination criterion of this line.

  It is also possible to define an identifier defined depending on the system as a determination item and a determination value. For example, specific data is embedded in a specific position of a packet.

  As a method of defining the address of the computer component 104, a method of defining at a configuration position in the information processing apparatus 102 in which the computer component 104a is arranged, or a method of using an address definition in a communication bus protocol between the computer components 104a to 104e. A method of using an address definition in a communication protocol constructed on a communication bus protocol between the computer components 104a to 104e is exemplified.

  For example, as a protocol layer of the network layer on the communication bus protocol, there is a method that enables communication by the IP layer and is defined by an IP address. Alternatively, a method of mapping an address space in a communication bus protocol between the computer components 104a to 104e and physical configuration positions of the computer components a to e and defining them by relative positions from the computer components 104 is exemplified. .

  The real-time transfer determination unit 123 collates the packet transmitted from the reception unit 120 with the determination criterion stored in the determination criterion storage unit 122, and determines whether the packet should be transferred immediately. When there are a plurality of determination criteria stored in the determination criterion storage unit 122, it is recommended that the determination criteria be determined in parallel and the logical sum of these results as a determination result instead of collating the determination criteria in order. The

  The setting of the determination criterion to the determination criterion setting unit 121 may be performed by an application on the OS running on the CPU 110, or may be performed by a specific input unit or computer by providing a connector on the computer component 104a. . An example of a graphics user interface (hereinafter referred to as GUI) of the setting screen by the former application is shown in FIG.

  An example of the latter specific input means is shown in FIG. The determination criterion input device 150 may be connected to the computer component 104 by providing a connector, or may be directly provided on the computer component 104. In the judgment item input 151, a judgment item to be input is selected. The determination value input 152 is input with the determination value of the determination item selected by the determination item input 151 using the numeric keypad 154. The transmission destination component 153 sets a transmission destination component in the case where the determination criterion that is being input is met. After inputting the determination item, the determination value, and the transmission destination component, the application determination criterion is input to the determination criterion setting unit 121 by pressing the apply button 155.

  It is also possible to acquire the setting content of the determination criterion storage unit 122 by making a specific input to the determination value 152. For example, it is assumed that an input beginning with “.” Is defined as a command, and a determination criterion entry in the determination criterion storage unit 122 specified by a number to be subsequently input is acquired.

  FIG. 8 shows an example in which the computer 161 and the computer component 104a are connected by communication using RS232C or communication using Ethernet. A determination criterion is set in the determination criterion setting unit 121 by an application operating on the computer 161. The GUI example of the application is the same as that shown in FIG. Specific examples of the computer 161 include a PC (Personal Computer) and a PDA (Personal Digital Assistant).

  When a determination criterion is input by the method illustrated in FIGS. 6, 7, and 8, setting input including an error display can be supported by the physical configuration of the information processing apparatus 102. For example, when the number of computer components constituting the information processing apparatus 102 including the own computer component 104a is 2, the computer component 104b that is not the own computer component 104a is input as the first input candidate of the transmission destination component. . When the number of computer components constituting the information processing apparatus 102 is 1 or when there is no computer component 104 set as a transmission destination, it is displayed that there is an error in the input content. For example, dialog display is performed in FIG. 6, and “E”, which is an error, is displayed on the transmission destination component 153 in FIG.

  9, 10 and 11 show the configuration of the communication buffer. The communication buffer 116 has first-in first-out (FIFO) queues 171a to 171c. As long as there are a plurality of queues, it does not matter. The required number of buffers 173 in the queue 171 is changed according to the application to which the information processing apparatus 102 is applied, and is one or a plurality. The packet 174 input from the input interface 170 is stored from the head buffer 173 in the queue 171 and is output when the output interface 172 can be output according to the communication bus protocol.

  In FIG. 9, there are as many input interfaces 170a to 170c as queues 171a to 171c. On the other hand, in FIG. 10, there is only one input interface 175, and the queues 171a to 171c for storing the packets are selected according to the queue ID included in the packet received by the input interface 175. The peripheral IC that transmits the packet to the communication buffer adds an ID for designating the queue to the packet as necessary. In FIG. 11, there is one input interface 176, but a queue selection signal 177 for selecting the queues 171 a to 171 c is input to the input interface 176. The bus width of the queue selection signal 177 differs depending on the number of queues 171 that can be selected. For example, if the number of queues 171 is four, the bus width is 2 bits. The input interface 176 selects the queues 171a to 171c to transmit the packet according to the state of the queue selection signal 177 asserted when the packet is received.

  These queues 171a to 171c have different priorities, and when the output interface 172 can be transmitted, the packets in the queue with higher priority are preferentially transmitted. At the same time, when a packet is transmitted from the queue 171a having a high priority, the interrupt signal line 126 is asserted.

  A packet that is determined to be transferred immediately by the user logic IC 114 is transmitted to the queue 171 having a high priority in the communication buffer 116. At the same time (when interrupt signal line 126 is asserted), user logic IC 114 asserts signal line 118 of the inter-component bus.

Next, an embodiment of the computer component on the receiving side will be described. FIG. 12 shows a configuration diagram of the computer component on the receiving side. Although the configuration is similar to that of FIG. 1, the control IC 180 and the user logic IC 129 are included.

  The control IC 180 communicates a control command from the CPU 110 to the control device 103, operation information from the control device 103 to the CPU 110, and the like. The control device 103 receives a control command from the CPU 110 through the control IC 180 and operates based on the control command. As a result of the operation, the operation information is transmitted to the CPU 110 through the control IC 180.

  The interrupt signal line 127 is asserted by the user logic IC 129 at a predetermined timing and for a predetermined period when the interrupt signal line 118 is asserted. When the timing at which the interrupt signal line 118 is asserted and the period during which the interrupt signal line 118 is asserted differ from the timing at which the interrupt signal line 127 requested by the reception side is asserted and the period during which it is asserted, the interrupt signal line asserting unit illustrated in FIG. 230 adjusts their timing and period.

  FIG. 15 shows the receiving-side computer component when adjustment of the timing and period of assertion is unnecessary. The interrupt signal line 118 is directly connected to the communication buffer 116. In the reception in this case, the user logic IC 114 can be omitted.

  Returning to FIG. 12, the description will be continued. The signal line 128 is a part of the inter-component communication bus 119 and includes an address bus and a control bus. The interrupt signal line 118 is implemented using a wired OR or OR logic element. When the interrupt signal line 118 is asserted, the user logic IC 129 uses the information on the signal line 128 to determine whether its own computer component is receiving a packet. Alternatively, although the number of signal lines of the inter-component bus is increased, it is also exemplified that the interrupt signal line 118 is prepared so as to be one-to-one between the computer components.

  FIG. 17 shows a packet reception procedure in the computer component 104. First, a packet is received from another component (S020). Next, the user logic IC 129 determines whether the interrupt signal line 118 is asserted (S021). If it is asserted, the user logic IC 129 asserts the queue selection signal 127 to the communication buffer, and the communication buffer 116 receives the packet in the queue having a high priority (S022). Next, the communication buffer 116 waits until the output interface can be transmitted (S023). If transmission is possible, the communication buffer 116 transmits the packet to the RAM 111 (S024). If the interrupt signal line 118 is not asserted in S021, the communication buffer 116 receives the packet in the queue having a low priority (S025). Thereafter, the communication buffer 116 waits until the output interface can be transmitted (S026). If transmission is possible, the communication buffer 116 transmits a packet to the RAM 111 (S024).

  The above-described communication buffer of FIG. 11 shows a configuration of a communication buffer suitable for use on the receiving side. In this case, the queue selection signal 177 is connected to the signal line 118 on the bus between the computer components 104. If the signal line 118 is asserted, the packet is a packet to be preferentially processed, and therefore the packet is transmitted to the queue 171 having a high priority. If the output interface 172 can transmit, the packet is transmitted from the queue 171 having a high priority to the RAM 111. At the same time, an interrupt indicating packet reception is generated in the real-time OS operating on the CPU 110. A control program that operates on the real-time OS controls the control device 103 or acquires operation information in accordance with information and instructions included in the packet.

The RS232C standard, wireless communication, or the like is also exemplified for the external connection with the information processing apparatus 102. Examples of wireless communication standards include IEEE802.11a, IEEE802.11b, IEEE802.11g, IEEE802.11n, Bluetooth (registered trademark) , ZigBee (registered trademark) , UWB, infrared communication, and the like.

  By adopting these configurations, even when the OS operating on the computer component 104a is a general-purpose OS, the communication delay to the control task of the control device 103 operating on the computer components 104b to 104e is reduced, and Communication can be performed with low communication jitter.

  FIG. 18 shows another embodiment of the user logic IC to which the present invention is applied. The reference numerals used in the second embodiment are the same as the functions and elements described in the first embodiment unless otherwise specified. The user logic IC 114 in FIG. 13 includes a communication buffer 116. Specific examples of the communication buffer 116 include those shown in FIGS. 9, 10, and 11. Here, the communication buffer shown in FIG. 9 is described.

  The timekeeping unit 190 has timekeeping means and transmits time information to the processing time recording unit 191. The processing time recording unit 191 is connected to each functional block in the user logic IC 114. When a predetermined process is executed by the receiving unit 120, the determination criterion setting unit 121, the determination criterion storage unit 122, the real-time transfer determination unit 123, the transmission unit 124, the input interface 170, and the output interface 172, the connected signal is asserted. (The transmission path is not shown). The processing time recording unit 191 acquires time information of the time measuring unit at that time, and records predetermined processing of each functional block and time information at the time when the processing is executed.

  Further, the processing time recording unit 191 transmits the recorded information to each IC connected to the bus 115 in response to a request from each IC connected to the bus 115. For example, deleting the recording information transmitted to the bus 115 due to the limitation of the recording capacity is also exemplified.

  An OS application operating on the CPU 110 can check an arbitrary processing time of the user logic IC to which the present invention is applied using these pieces of information. For example, the processing time from “determined as a packet to be transferred immediately” in the real-time transfer determination unit 123 to “transmit packet” in the output interface 172 can be acquired. Further, it is possible to acquire the time from when it is determined that the packet is not to be transferred immediately to the actual transmission. By comparing the two processing times, the processing time shortened by the present invention can be confirmed.

  FIG. 19 shows a GUI example of an application according to the second embodiment. The tab 201 displays information (event generation function unit, generated event, event occurrence time) and number (No.) acquired from the processing time recording unit 191. In the tab 202, any two numbers are selected from the tab 201, an arbitrary label is attached, and an add button is pressed, and the processing time between the two events is displayed.

  According to the second embodiment, the user can confirm an arbitrary processing time according to the present invention and know the shortened time of packet transfer. For example, by operating the present invention on a trial basis and knowing the actual packet transfer processing time, it is possible to easily determine whether or not a predetermined time constraint imposed on the system can be observed. Also, by comparing with the transfer time by software processing, it is possible to evaluate the performance of network processing by software and to identify the bottleneck of the communication path on the component.

  FIG. 20 shows another embodiment of the user logic IC to which the present invention is applied. The reference numerals used in the third embodiment are the same as the functions and elements described in the first and second embodiments unless otherwise specified. The user logic IC 114 includes a communication buffer 116. Specific examples of the communication buffer 116 in FIG. 20 include those shown in FIGS. 9, 10, and 11. Here, the communication buffer shown in FIG. 9 is described.

  The operation status recording unit 210 is connected to each functional block in the user logic IC 114. When a predetermined process is executed by the receiving unit 120, the determination criterion setting unit 121, the determination criterion storage unit 122, the real-time transfer determination unit 123, the transmission unit 124, the input interface 170, and the output interface 172, the connected signal is asserted. (The transmission path is not shown), and the operation status of the packet transfer process in the user logic IC 114 is recorded. When the real-time transfer determination unit 123 determines that the packet is to be transferred immediately, the necessary information is acquired. Specific examples of the information as the operation status include the transmission source address of the packet acquired from the packet, the determination time point of the packet acquired from the time measuring unit 190, the transmission destination component, and the processing time required for the transfer.

  In addition, the operating status recording unit 210 transmits the recorded information to each IC connected to the bus 115 in response to a request from each IC connected to the bus 115. For example, deleting the recording information transmitted to the bus 115 due to the limitation of the recording capacity is also exemplified.

  The OS application running on the CPU 110 can check the operating status of the user logic IC to which the present invention is applied using these pieces of information. An example GUI of this application is shown in FIG.

  In the tab 221, information (a transmission source address, a transmission destination component, a transfer time) and a number (No.) acquired from the operation status recording unit 210 are displayed. When an error occurs in the transfer, it is displayed together with a number indicating a predetermined cause of the error. An example of the cause of the error is that the packet or the transfer destination component that violates the communication protocol is invalid. In the tab 222, predetermined statistical information is displayed based on the information in the tab 221.

  According to the third embodiment, the user can easily check the operation status related to the packet real-time transfer processing. By using this operating status, it can be used for diagnosis whether an error has occurred on the computer component 104 or whether there is a problem in the configuration of the information processing apparatus 102.

The block diagram of the computer component by Example 1 of this invention. 1 is a configuration diagram of an information processing apparatus to which an embodiment of the present invention is applied. 1 is an external view of an information processing apparatus to which an embodiment of the present invention is applied. FIG. 3 is a functional block diagram of a user logic IC according to the first embodiment. 2 is a data configuration diagram of a determination criterion storage unit according to Embodiment 1. FIG. FIG. 3 is a GUI diagram illustrating a determination criterion setting screen according to the first embodiment. The block diagram of the criteria input part by other embodiment. 1 is an external view of an information processing apparatus including a determination criterion input unit. The block diagram of the communication buffer by one Embodiment. The block diagram of the communication buffer by other embodiment. The block diagram of the communication buffer by other embodiment. 1 is a configuration diagram of a computer component on a receiving side according to Embodiment 1. FIG. FIG. 6 is a configuration diagram of a computer component showing a modification of the first embodiment. FIG. 3 is a functional block diagram of a receiving-side user logic IC according to the first embodiment. FIG. 6 is a modified configuration diagram of a receiving computer component according to the first embodiment. The flowchart which showed the transmission procedure of the packet by one Embodiment of this invention. The flowchart which showed the reception procedure of the packet by one Embodiment of this invention. FIG. 9 is a functional block diagram of a user logic IC according to a second embodiment. FIG. 10 is a GUI diagram illustrating a display screen according to the second embodiment. FIG. 10 is a functional block diagram of a user logic IC according to a third embodiment. FIG. 10 is a GUI diagram illustrating a display screen according to the third embodiment.

Explanation of symbols

  100, 102, 160, 161 ... Information processing device, 101 ... Network, 103 ... Control device, 104 ... Computer component, 110 ... CPU, 111 ... RAM, 112 ... Non-volatile storage medium, 113 ... LAN, 114, 129 ... User Logic IC, 115 ... bus, 116 ... communication buffer, 117 ... inter-component communication IC, 118, 126, 127 ... interrupt signal line, 128 ... signal line, 119 ... inter-component communication bus, 120 ... receiving unit, 121 ... criteria Setting unit, 122 ... Determination criterion storage unit, 123 ... Real-time transfer determination unit, 124 ... Transmission unit, 130 ... Determination criterion table, 131 ... Determination criterion entry, 140 ... Determination criterion setting screen, 141 ... Determination criterion item, 142 ... Determination Reference value 150... Judgment reference input device 171... Communication queue 170, 75,176 ... input interface, 172 ... output interface, 177 ... queue selection signal line, 190 ... timing unit, 191 ... processing time recording unit, 210 ... operating status recording unit, 230 ... interrupt signal line asserted section.

Claims (15)

In an information processing apparatus composed of a plurality of computer components,
The computer components are connected by a communication bus that includes interrupt signal lines.
The computer component, when receiving information from the outside, transfer determination means for determining whether the information has a predetermined time constraint;
A processing unit that processes information from the outside according to a determination result of the transfer determination unit;
An inter-component communication unit that transfers information from the outside to another computer component via a communication bus according to the processing of the processing unit;
Wherein the processing unit, first causes transfer of information immediately asserts the interrupt signal line to the corresponding other computer components when the information from the outside in the transfer determination unit determines that a predetermined time constraints And a second processing unit that processes the information to be transferred without asserting the interrupt signal line when it is determined that the information from the outside does not have a predetermined time constraint. An information processing apparatus characterized by that. The information processing apparatus according to claim 1,
An information processing apparatus characterized in that, when another computer component to which the information is transferred receives the information by asserting the interrupt signal line, the information processing device preferentially processes the information. In an information processing apparatus composed of a plurality of computer components,
The computer component is:
A data input section;
A transmission unit that has one or a plurality of queues in which priority setting is possible, and that preferentially transmits packets input to the high priority queue to other computer components;
If the packet received from the data input unit is immediately determined to be a packet to be transferred to another computer component, and if it is determined that the packet should be immediately transferred to another computer component, A real-time transfer determination unit that transfers packets to a queue with high priority,
A means for transmitting to the computer component which is the transmission destination of the packet that the real-time transfer determination unit has determined that the packet received from the data input unit is a packet to be immediately transferred to another computer component;
A processing unit that inputs a packet to a low-priority queue of the transmission unit when it is determined that the packet received from the data input unit is not a packet that should be immediately transferred to another computer component. An information processing apparatus characterized by that.   4. The information processing apparatus according to claim 3, wherein the computer component that is the transmission destination receives a packet received by receiving the determination result of the real-time transfer determination unit by the transmission unit in a queue having a high priority. Information processing apparatus. The information processing apparatus according to claim 4.
The real-time transfer determination unit includes a determination criterion storage unit that stores a determination criterion for determining whether a packet received from the data input unit is a packet to be immediately transferred to another computer component, and the determination criterion storage An information processing apparatus comprising: a determination criterion setting unit that sets a determination criterion to the unit. The information processing apparatus according to claim 5,
An information processing apparatus comprising a connector on a computer component, connected to an external information processing apparatus, and setting the determination criterion in the determination criterion setting unit. The information processing apparatus according to claim 3,
The information processing apparatus, wherein the transmission means is an interrupt signal line on a bus connecting the computer components. The information processing apparatus according to claim 3,
The computer component includes a timekeeping unit capable of timing time information, and a processing time recording unit for recording an occurrence time of an event in each functional unit using a timekeeping function of the timekeeping unit. Information processing device. The information processing apparatus according to claim 8.
An information processing apparatus having display means for acquiring and displaying information from the processing time recording unit. The information processing apparatus according to claim 3,
The computer component, when the real-time transfer determination unit determines that the packet received from the data input unit is a packet to be immediately transferred to another computer component, information relating to the packet received from the data input unit And an operating status recording unit for recording information related to the computer component of the transfer destination. The information processing apparatus according to claim 10.
An information processing apparatus having display means for acquiring and displaying information from the operating status recording unit. In an information processing method of an information processing apparatus composed of a plurality of computer components,
The computer components are connected by a communication bus that includes interrupt signal lines.
The computer component that has received information from the outside determines whether or not the information has a predetermined time constraint. If it is determined that the information has the predetermined time constraint, an interrupt signal line to another corresponding computer component immediately To transfer information ,
When it is determined that the information does not have a predetermined time constraint, the information is transmitted to the other computer component without asserting an interrupt signal line to the other computer component. Method. The information processing method according to claim 12,
An information processing method characterized in that when the other computer component as the transfer destination receives the information by asserting the interrupt signal line, the information is preferentially processed. In an information processing method of an information processing apparatus composed of a plurality of computer components,
A computer component that receives information from the outside includes a real-time transfer determination unit, a communication unit, a communication transmission unit, and a processing unit .
When the real-time transfer determination unit of the computer component determines whether the information received from the outside is a packet that should be transferred to another computer component immediately, and if it is determined that the information should be transferred immediately , the communication Send information to the queue with higher priority among the queues
In the communication transfer unit , the information transmitted to the high priority queue is notified to the computer component of the transmission destination that the information is preferentially transferred ,
If it is determined that the packet is not to be transferred to another computer component immediately, information is input to a queue with a low priority among the queues of the communication unit in the processing unit and is transmitted. Method. The information processing method according to claim 14,
The information processing method characterized in that the information determined to be transferred immediately is real-time information having a time limit for processing.

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