JP4947064B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device such as a gate array, an embedded array, or a standard cell that is designed using various cells according to specifications of a customer. Furthermore, the present invention relates to a method for designing such a semiconductor device.

In a semiconductor device such as a gate array, a layout design is performed by arranging and connecting several cells constituting a circuit block that realizes a desired function. Each cell
An impurity diffusion layer formed in the semiconductor substrate, a gate insulating film and a gate electrode formed on the semiconductor substrate, and at least one wiring layer formed through an interlayer insulating film.

In a semiconductor substrate using a submicron order (particularly, 0.25 μm or less) process, when there are a dense region where cells are densely arranged and a sparse region where cells are not often arranged, The thickness of the layer formed on the semiconductor substrate is biased. In order to eliminate the uneven thickness of the layer, it may be possible to make the thickness of the layer uniform by a CMP (scientific mechanical polishing) process, but the polishing time takes several hours. Therefore, when performing automatic placement and routing using a computer, it is common practice to automatically generate dummy cells in a sparse cell area. The dummy cell includes a wiring pattern or the like (dummy pattern) that is not related to the circuit operation, whereby the thickness of the layer formed on the semiconductor substrate can be made uniform.

In automatic placement and routing that automatically generates dummy cells as described above, dummy pattern generation is used to prevent mask patterns from being placed in areas where circuit blocks are not placed and to prevent analog circuit characteristics from changing due to dummy patterns. Setting of prohibited areas is performed. When the dummy pattern generation prohibition area is set, dummy pattern data overlapping the dummy pattern generation prohibition area is not generated. At that time, even when the outer periphery of the dummy pattern coincides with the outer periphery of the dummy pattern generation prohibition region, that is, when the area of the region where the dummy pattern and the dummy pattern generation prohibition region overlap is zero, the dummy pattern data is It was not generated. Further, even when a part of the dummy pattern overlaps the dummy pattern generation prohibited area, no dummy pattern data was generated. Therefore, there is a problem that the area where the dummy pattern is not arranged becomes wider than necessary, and the thickness of the layer formed on the semiconductor substrate cannot be made sufficiently uniform.

In addition, system LSIs and the like are often designed using large-scale functional blocks called IP blocks. However, if a dummy pattern is placed inside an IP block after placing an IP block that has already been evaluated, the characteristics of an analog circuit included in the IP block may be different from the characteristics at the time of evaluation. On the other hand, if a dummy pattern generation prohibition region is set in the entire IP block, the region where the dummy pattern is not arranged becomes wide, and the thickness of the layer formed on the semiconductor substrate cannot be made sufficiently uniform. there were.

Incidentally, Japanese Patent Application Publication (JP-A) No. 8-6231 (hereinafter referred to as “Patent Document 1”).
In other words, when performing automatic wiring design of multi-layer metal wiring of semiconductor devices, mutual comparison of wiring patterns of each layer of multi-layer metal wiring is performed against all wiring patterns designed to obtain desired device characteristics. When there is the closest approach pattern in the second layer wiring pattern, the first
When the layer wiring pattern interval is defined as a grid between the wiring centers, a dummy pattern is generated when the interval defined by grid / 2 is more than four times the amount defined, and the first layer is compared. A method of manufacturing a semiconductor device characterized by using a photolithography mask combined with a wiring pattern is described.

However, the semiconductor device manufacturing method disclosed in Patent Document 1 generates a dummy pattern efficiently to the minimum necessary without generating a dummy on the entire surface of the grid. It does not take into account the provision of a dummy pattern in the IP block.

Japanese Laid-Open Patent Publication No. 9-115905 (hereinafter also referred to as “Patent Document 2”) describes a method for designing a dummy wiring pattern formed in a lower layer of a semiconductor integrated circuit device having a multilayer wiring structure, and has a predetermined dimension. And a pattern in which a region where the auxiliary pattern group regularly arranged at a predetermined interval is created and a region where the auxiliary pattern group and a wiring pattern formed in the lower layer are extended by a predetermined dimension overlap are erased from the auxiliary pattern And a dummy pattern design method characterized in that it includes a step of forming a group into a dummy wiring pattern.

However, the dummy pattern design method disclosed in Patent Document 2 is to dispose a dummy pattern on a semiconductor integrated circuit device having a multilayer wiring structure without using a virtual grid. It does not take into account the provision of a dummy pattern in the IP block.

Japanese Laid-Open Patent Publication No. 10-256255 (hereinafter also referred to as “Patent Document 3”) takes in layout data of a regular pattern and expands the pattern by an appropriate amount, and the first step and the enlarged step. A second step of generating a reverse pattern of the pattern and slightly expanding the reverse pattern, and a reverse mesh that protrudes from the mesh pattern by superimposing a grid mesh pattern having a predetermined width on the reverse pattern enlarged in the second step A pattern generation method for a semiconductor integrated circuit device, comprising: a third step of forming a dummy pattern and a fourth step of synthesizing the dummy pattern and a regular pattern to create a pattern for chip or reticle exposure. When combining a dummy pattern and a regular pattern in 4 steps, the size of one side of the dummy patterns adjacent to the regular pattern If there is a minute dummy pattern that does not satisfy the minimum allowable width in the design rule, a pattern generation method for a semiconductor integrated circuit device is characterized in that the minute dummy pattern and a regular pattern are connected Is posted.

However, the pattern generation method of the semiconductor integrated circuit device described in Patent Document 3 suppresses pattern omission and pattern peeling by connecting between a small dummy pattern and a regular pattern. It does not take into account the provision of a prohibited area or the placement of a dummy pattern in an IP block.

JP-A-8-6231 JP 9-115905 A JP-A-10-256255

Accordingly, in view of the above points, an object of the present invention is to provide a semiconductor device in which the thickness of a layer formed on a substrate is made closer to uniform by disposing a dummy pattern in a wider area than before. To do. Another object of the present invention is to provide a method for designing such a semiconductor device.

In order to solve the above problems, a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate,
A third circuit block excluding a plurality of circuit blocks formed on the semiconductor substrate, a first region where the plurality of circuit blocks are formed on the semiconductor substrate, and a second region where generation of dummy patterns is prohibited.
And a plurality of dummy patterns including a dummy pattern formed so as to be in contact with a straight line defining a boundary of the second region.

A semiconductor device according to a second aspect of the present invention includes a semiconductor substrate, a functional block formed in a predetermined region of the semiconductor substrate, and a dummy pattern formed in the predetermined region.

Furthermore, a semiconductor device according to a third aspect of the present invention includes a plurality of semiconductor substrates, a functional block formed in a predetermined region of the semiconductor substrate, and a plurality of lines formed across a straight line that defines a boundary of the predetermined region. And a dummy pattern.

A semiconductor device design method according to a first aspect of the present invention is a method for designing a layout of a semiconductor device using a computer, the step (a) of setting a dummy pattern generation prohibition region, and a plurality of circuit blocks A step (b) of arranging and wiring a semiconductor device including:
Step (c) in which dummy cells including a plurality of dummy patterns are arranged in the region where the circuit block is not arranged, and the area of the region where the dummy cells arranged in step (c) overlap with the dummy pattern generation prohibition region is less than zero. And (d) deleting the dummy cell if it is larger.

A semiconductor device design method according to a second aspect of the present invention is a method for designing a layout of a semiconductor device using a computer, the step (a) of setting a dummy pattern generation prohibition region, and a plurality of methods A step (b) of arranging and wiring a semiconductor device including a circuit block;
And (c) disposing dummy cells including a plurality of dummy patterns under the condition that the dummy pattern generation prohibition area may be contacted except for the dummy pattern generation prohibition area in the area where the circuit block is not disposed. It comprises.

Furthermore, a semiconductor device design method according to a third aspect of the present invention is a method for designing a layout of a semiconductor device using a computer, and creates design data for a functional block having dummy cells including a plurality of dummy patterns. Step (a), step (b) for evaluating the functional block based on the design data created in step (a), and using the design data created in step (a) And (c) performing placement and wiring of the semiconductor device.

In addition, a method for designing a semiconductor device according to a fourth aspect of the present invention is a method for designing a layout of a semiconductor device using a computer, including dummy cells formed across a boundary line and including a plurality of dummy patterns. A step (a) of creating design data of the functional block having, a step (b) of deleting a dummy cell portion protruding from the boundary line of the functional block in the design data created in the step (a), and a step (b) Step (c) for evaluating the functional block based on the design data obtained in step (b), and a step for placing and wiring the semiconductor device including the functional block using the design data obtained in step (b). (D) and the incomplete dummy cell in which the part that protrudes from the boundary line of the functional block is deleted is changed to a complete dummy cell. Comprising a step (e) that.

In the method for designing a semiconductor device according to the fourth aspect of the present invention, step (e) includes:
Disposing a complete dummy cell over an incomplete dummy cell, or step (e) may include disposing a dummy cell that compensates for the deleted portion of the incomplete dummy cell.

According to the present invention configured as described above, the thickness of the layer formed on the substrate can be made closer to uniform by disposing the dummy pattern in a wider area than before.

As described above, according to the present invention, the thickness of the layer formed on the substrate can be made closer to uniform by disposing the dummy pattern in a wider area than in the past.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, about the same component, it has shown with the same reference number.
FIG. 1 shows a part of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, the semiconductor device is in a state where a first wiring layer is formed. A plurality of cells 11 constituting a circuit block for realizing a desired function are arranged on a semiconductor substrate 10 (wafer or chip). Each cell 11 includes an impurity diffusion layer formed in the semiconductor substrate, a gate insulating film and a gate electrode formed on the semiconductor substrate, and at least one wiring layer formed through the interlayer insulating film. The

In order to prevent the name of the mask from being put in an area where the circuit block is not arranged and the characteristics of the analog circuit from being changed due to the dummy pattern, the semiconductor substrate 10 includes a dummy pattern generation prohibiting area 20 which prohibits the generation of the dummy pattern. Is set. Multiple cells 1
A plurality of dummy cells 1 except for the area where 1 is arranged and the dummy pattern generation prohibition area 20
2a to 12d are automatically arranged. The dummy cells 12a to 12d include wiring patterns and the like (dummy patterns) that are not related to circuit operation. In this embodiment, the dummy pattern formed in the wiring layer has a square shape with one side of 2 μm and is arranged vertically and horizontally at intervals of 1 μm. Thereby, the thickness of the layer formed on the semiconductor substrate 10 can be made uniform.

The semiconductor device according to the present embodiment is arranged so as to contact not only the dummy patterns of the dummy cells 12a and 12b arranged away from the dummy pattern generation prohibition region 20, but also a straight line that defines the boundary of the dummy pattern generation prohibition region 20. Dummy cells 12c and 1
A 2d dummy pattern is also included. Thereby, a dummy pattern can be arrange | positioned in the area | region wider than before, and the thickness of the layer formed on the semiconductor substrate 10 can be closely approached.

FIG. 2 is a flowchart showing a semiconductor device design method according to the first embodiment of the present invention for designing the layout of the semiconductor device shown in FIG. Such a layout design of a semiconductor device is performed by automatic placement and routing using a computer.

First, in step S11, a dummy pattern generation prohibited area is set. The dummy pattern generation prohibited area is set by, for example, inputting a dummy pattern generation prohibited area frame into a predetermined layer of pattern data used in the placement and routing program.

Next, in step S12, the semiconductor device including a plurality of circuit blocks is arranged and wired except for the dummy pattern generation prohibition region.
Next, in step S13, a plurality of dummy cells are temporarily arranged in an area where the circuit block is not arranged.

Next, in step S14, an AND operation is performed on the dummy pattern generation prohibition area and the temporarily arranged dummy cells, and the area of the overlapping area is obtained.
Next, in step S15, it is checked whether or not the area of the area where the dummy pattern generation prohibited area and the dummy cell overlap is zero. If the area of the overlapping area is not zero, the process proceeds to step S16, and the area of the overlapping area is If it is zero, the process is terminated.

In step S16, the dummy cells whose area overlapping the dummy pattern generation prohibition area is larger than zero are deleted, and the process ends. As a result, the dummy pattern formed so as to be in contact with the straight line that defines the boundary of the dummy pattern generation prohibited area can be left without being deleted.

Next, a semiconductor device design method according to the second embodiment of the present invention for designing the layout of the semiconductor device shown in FIG. 1 will be described. FIG. 3 is a flowchart showing this design method.

First, in step S21, a dummy pattern generation prohibited area is set.
Next, in step S22, a semiconductor device including a plurality of circuit blocks is arranged and wired.

Next, in step S23, a plurality of dummy cells are arranged except for the dummy pattern generation prohibition area in the area where the circuit block is not arranged. At this time, a plurality of dummy cells are arranged under the condition that they may contact the dummy pattern generation prohibited area. As a result, the dummy pattern formed so as to be in contact with the straight line that defines the boundary of the dummy pattern generation prohibited area can be left without being deleted.

Next, a semiconductor device according to a second embodiment of the present invention will be described. FIG. 4 is a diagram showing a part of the semiconductor device according to the second embodiment of the present invention. In FIG. 4, the semiconductor device
The first wiring layer is formed. The semiconductor substrate 10 has an IP block 3
0 is arranged. IP blocks are intellectual property rights.
However, in the field of semiconductor devices, functional blocks of electronic circuits (also called cores)
Point to. More specifically, the IP block is a processor, a DSP (Digital Signal Proceed).
ssor), a functional block including electronic circuits such as a memory and an input / output circuit. In recent years, in order to design a semiconductor device (particularly, a system LSI), such IP block design data is made into a library and reused in-house or purchased from a supplier called an IP provider. It has been broken.

In the IP block 30, a plurality of cells 1 constituting a circuit block for realizing a desired function
1 is arranged. Conventionally, no dummy pattern is arranged in the IP block 30, but in this embodiment, dummy patterns of a plurality of dummy cells 12 a to 12 c are arranged in the IP block 30.

Here, if a dummy pattern is placed inside an IP block after placing an IP block that has already been evaluated, the characteristics of an analog circuit included in the IP block may be different from those at the time of evaluation. Therefore, in this embodiment, the dummy cell 12
The IP blocks that have been evaluated after the dummy patterns a to 12c are arranged are registered in advance, and the semiconductor devices are arranged and wired by using the IP blocks. This
A dummy pattern can be arranged in a wider area than before, and the thickness of the layer formed on the semiconductor substrate 10 can be made close to uniform.

Next, a semiconductor device design method according to the third embodiment of the present invention for designing the layout of the semiconductor device shown in FIG. 4 will be described. FIG. 5 is a flowchart showing this design method.

First, in step S31, design data for an IP block having a dummy cell is created.
Next, in step S32, an IP block having a dummy cell is evaluated. IP
Evaluation of the block includes functional evaluation, characteristic evaluation of an analog circuit, and the like.

Next, in step S33, the design data of the IP block having the dummy cell is registered in the library.
Next, in step S34, placement and wiring of the semiconductor device are performed using the IP block design data registered in the library.

As described above, in this embodiment, design data of an IP block having dummy cells is created in advance, and the IP block is evaluated and registered. If a dummy pattern is placed in an IP block after placing an IP block that does not have a dummy cell, the characteristics of an analog circuit and the like may change. A dummy pattern can be provided in the block. In this embodiment, a plurality of IPs
In addition to arranging blocks, dummy cells may be arranged in regions between a plurality of IP blocks.

Next, a semiconductor device according to a third embodiment of the present invention will be described. FIG. 6 is a diagram showing a part of a semiconductor device according to the third embodiment of the present invention. In FIG. 6, the semiconductor device is
The first wiring layer is formed. The semiconductor substrate 10 has an IP block 4
0 is arranged.

In the IP block 40, a plurality of cells 1 constituting a circuit block that realizes a desired function.
1 is arranged. In the IP block 40, a plurality of dummy cells 12a to 12c are provided.
The dummy patterns of the dummy cells 12d and 12e are arranged across the straight line that defines the boundary of the IP block 40.

Thus, in the semiconductor device according to the present embodiment, the dummy patterns of the dummy cells 12a to 12c are arranged in the IP block 40, and the dummy patterns of the dummy cells 12d and 12e are arranged on the frame of the IP block 40. Compared with the semiconductor device shown in FIG. 4, the thickness of the layer formed on the semiconductor substrate 10 can be made more uniform.

Next, a semiconductor device design method according to the fourth embodiment of the present invention for designing the layout of the semiconductor device shown in FIG. 6 will be described. FIG. 7 is a flowchart showing this design method.

First, in step S41, design data for an IP block having a dummy cell is created. Here, the design data of the IP block in which the dummy cell is arranged is created under the condition that it may be arranged on the frame of the IP block. FIG. 8 is a diagram showing an example of the layout of the IP block 40 created in this way. As shown in FIG. 8, dummy cells 12 a to 12 c are arranged in the IP block 40, and dummy cells 12 f and 12 g are arranged on the frame of the IP block 40.

Next, in step S42, a portion outside the IP block frame of the dummy cell arranged on the IP block frame is deleted. FIG. 9 is a diagram showing incomplete dummy cells in which the dummy cells 12f and 12g arranged on the frame of the IP block 40 are removed from the outside of the frame of the IP block 40.

Next, in step S43, an IP block having an incomplete dummy cell as shown in FIG. 9 is evaluated. In step S44, design data of an IP block having an incomplete dummy cell as shown in FIG. 9 is registered in the library.
Next, in step S45, the semiconductor device is placed and wired using the IP block design data registered in the library.

Next, in step S46, the incomplete dummy cell from which the portion outside the frame of the IP block is deleted is corrected to a complete dummy cell. Here, the correction of the incomplete dummy cell to the complete dummy cell can be performed by placing the complete dummy cell on the incomplete dummy cell. FIG. 10 is a diagram showing a part of the layout of the semiconductor device in which the IP block 40 is arranged and the complete dummy cells 12d and 12e are arranged on the incomplete dummy cells 12f and 12g.

Alternatively, correction of an incomplete dummy cell to a complete dummy cell may be performed by supplementing a dummy cell that compensates for the deleted portion of the incomplete dummy cell. FIG. 11 shows a part of the layout of a semiconductor device in which a complete dummy cell is formed by disposing an IP block 40 and further disposing dummy cells 12h and 12i that compensate for deleted portions of incomplete dummy cells 12f and 12g. FIG.

As described above, according to the method for designing a semiconductor device according to the present embodiment, the dummy cells can be arranged across the straight line that demarcates the boundary of the IP block.

In the present embodiment, a plurality of IP blocks may be arranged, and further dummy cells may be arranged in an area between the plurality of IP blocks. In this case, if the dummy cells arranged in the area between the plurality of IP blocks overlap with the dummy cells arranged on the frame of the IP block, for example, the dummy cells arranged in the area between the plurality of IP blocks are deleted. You should do it.

1 is a plan view showing a part of a semiconductor device according to a first embodiment of the present invention. 3 is a flowchart illustrating a method for designing a semiconductor device according to the first embodiment of the present invention. 6 is a flowchart showing a method for designing a semiconductor device according to a second embodiment of the present invention. It is a top view which shows a part of semiconductor device concerning the 2nd Embodiment of this invention. 7 is a flowchart illustrating a method for designing a semiconductor device according to a third embodiment of the present invention. It is a top view which shows a part of semiconductor device concerning the 3rd Embodiment of this invention. 9 is a flowchart illustrating a method for designing a semiconductor device according to a fourth embodiment of the present invention. It is a figure which shows the layout of the IP block in the middle of preparation with the design method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a figure which shows the layout of the IP block produced by the design method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a figure which shows an example of the layout of the semiconductor device using the IP block produced by the design method of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a figure which shows the other example of the layout of the semiconductor device using the IP block produced by the design method of the semiconductor device which concerns on the 4th Embodiment of this invention.

10 Semiconductor substrate, 11 cells, 12a, 12b, 12c, dummy cell, 20 dummy pattern generation prohibited area, 30, 40 IP block.

Claims (3)

Generate design data including dummy patterns,
Generating a mask based on the design data;
A semiconductor device is manufactured using the mask,
The design data is
Creating design data of a functional block having a dummy cell formed across the boundary line and including a plurality of dummy patterns;
Deleting the portion of the dummy cell that protrudes from the boundary line of the functional block from the complete dummy cell formed as the dummy cell in the design data created in step (a);
A step (c) of evaluating the functional block based on the design data obtained in the step (b);
(D) performing placement and wiring of the semiconductor device including the functional block using the design data obtained in step (b);
A step (e) of correcting an incomplete dummy cell from which a portion protruding from a boundary line of the functional block is deleted to the complete dummy cell;
A method for manufacturing a semiconductor device, characterized by comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein said step (e) includes disposing said complete dummy cell on said incomplete dummy cell.   The method of manufacturing a semiconductor device according to claim 1, wherein the step (e) includes disposing a dummy cell that compensates for the deleted portion of the incomplete dummy cell.

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