JP4944715B2 - Pipeline type ADC - Google Patents

Description

  The present invention relates to a pipeline type ADC (A / D conversion circuit).

  FIG. 17 is a block diagram showing a configuration of a conventional pipeline type ADC. The pipeline type ADC shown in FIG. 17 has a 7-bit configuration in which analog input Ain is A / D converted to output 7-bit output data Dout <6: 0>.

  As shown in FIG. 17, the sample hold unit (S / H) 50 samples the analog input Ain and outputs a sample hold output value SHout to the stage circuit 51.

  The stage circuit 51 executes A / D conversion processing in the first stage based on the sample hold output value SHout, outputs the converted data D1 <1: 0> to the error correction circuit 56, and outputs the remainder output ST1 to the next stage. Output to the circuit 52.

  The stage circuit 52 executes A / D conversion processing in the second stage based on the remainder output ST1, outputs the converted data D2 <1: 0> to the error correction circuit 56, and outputs the remainder output ST2 to the next stage circuit 53. Output to.

  The stage circuit 53 executes A / D conversion processing in the third stage based on the remainder output ST2, outputs the converted data D3 <1: 0> to the error correction circuit 56, and outputs the remainder output ST3 to the next stage circuit 54. Output to.

  The stage circuit 54 performs A / D conversion processing in the fourth stage based on the remainder output ST3, outputs the converted data D4 <1: 0> to the error correction circuit 56, and outputs the remainder output ST4 to the next-stage 3-bit ADC 55. Output to. Each of the stage circuits 51 to 54 described above functions as a 1.5-bit stage circuit.

  The 3-bit ADC 55 is configured as a flash type, and outputs conversion data D5 <2: 0>, which is a 3-bit A / D conversion result, to the error correction circuit 56 based on the remainder output ST4.

  The error correction circuit 56 performs conversion data D1 <1: 0>, conversion data D2 <1: 0>, conversion data D3 <1: 0>, conversion data D4 <1: 0>, and conversion data D5 <2: 0>. The output data Dout <6: 0> is output while performing error correction processing based on the above.

  FIG. 18 is an explanatory diagram schematically showing the internal configuration of the stage circuit 52. FIG. 18 shows a configuration in which the stage circuit 52 is classified by function. As shown in the figure, the stage circuit 52 samples the remainder output ST1 obtained from the stage circuit 51 by the sample hold circuit 21 and A / D converts it by the 2-bit ADC 22 to obtain conversion data D2 <1: 0>. . The converted data D2 <1: 0> is output to an external error correction circuit 56 (not shown) and DA-converted by the 2-bit DAC 23 to be obtained as an output V23.

  Then, the difference between the remainder output ST1 and the output V23 is taken by the analog arithmetic circuit 24, and this difference (ST1-V23) is doubled by the amplifier circuit 25 and then outputted as the remainder output ST2.

  19 and 20 are circuit diagrams showing the actual circuit configuration of the stage circuit 52. FIG. FIG. 19 shows a switching state in the sample mode (Sample Mode), and FIG. 20 shows a switching state in the hold mode (Hold Mode). As shown in the figure, the stage circuit 52 includes comparators 71 and 72, a latch circuit 73a, a multiplexer circuit 73b, a plurality of switches SW1 and SW2, capacitors 74 and 75, and an operational amplifier 76.

  The comparator 71 compares the remainder output ST1 with the reference voltage + Vref / 4 and outputs the comparison result to the latch circuit 73a. The comparator 72 compares the remainder output ST1 with the reference voltage -Vref / 4 and outputs the comparison result to the latch circuit 73a. In the present specification, the reference voltage −Vref / 4 means (Vref−Vref / 4) precisely. Further, the reference voltage + Vref / 4 means (0 + Vref / 4) precisely.

  The latch circuit 73a latches the comparison results of the comparators 71 and 72, and outputs the result as conversion data D2 <1: 0> to the outside (error correction circuit 56).

  The multiplexer circuit 73b outputs a reference voltage Vr obtained by D / A converting the conversion data D2 <1: 0> latched by the latch circuit 73a.

  The output of the multiplexer circuit 73b is connected to the node N12 via the switch SW2. The node N12 is connected to the remainder output ST1 (input section thereof) via the switch SW1.

  In addition, a capacitor 75 having a capacitance value Cs is inserted between the node N12 and the node N13, and the node N13 and the common voltage VCM (input portion thereof) are connected via the switch SW1. Further, the node N13 and the node N14 are connected via the switch SW2. Node N14 and common voltage VCM are connected via switch SW1.

  The operational amplifier 76 has a negative input connected to the node N14 and receives a common voltage VCM at the positive input. The remainder output ST2 is output from the node N15 which is the output of the operational amplifier 76. Node N15 is connected to common voltage VCM via switch SW1.

  The common voltage VCM means a reference voltage at a differential input of a differential amplifier circuit such as the operational amplifier 76 and is generally set to an intermediate potential between the ground level and the power supply voltage Vdd. The common voltage VCM includes a ground level and a power supply voltage Vdd, and can be set to any potential between the ground level and the power supply voltage Vdd.

  Node N15 is also connected to node N11 via switch SW2. The node N11 is connected to the remainder output ST1 through the switch SW1, and a capacitor 74 having a capacitance value Cf is inserted between the node N11 and the node N13.

  As shown in FIG. 19, in the sample mode, the plurality of switches SW1 among the plurality of switches SW1 and the plurality of switches SW2 are all turned on, and the plurality of switches SW2 are all turned off.

  In such a sample mode, the voltage between the terminals of the capacitors 74 and 75 follows the voltage of the output ST1.

  As shown in FIG. 20, in the hold mode, the plurality of switches SW2 among the plurality of switches SW1 and the plurality of switches SW2 are all turned on, and the plurality of switches SW1 are all turned off.

  In such a hold mode, the reference voltage Vr selected by the multiplexer circuit 73b from the comparison result of the comparators 71 and 72 for comparing the remainder output ST1 with a certain threshold value (+ Vref / 4, −Vref / 4), and the above-mentioned Based on the voltage stored in the capacitors 74 and 75 in the sample mode, the arithmetic processing is executed. As a result, a surplus output ST2 can be obtained from the node N15.

  21 and 22 are circuit diagrams showing the operating states of the stage circuit 52 and the stage circuit 53 connected in series with each other. FIG. 21 shows the switching state in the sample mode state, and FIG. 22 shows the switching state in the hold mode state. As shown in the figure, the stage circuit 53 includes comparators 81 and 82, a latch circuit 83a, a multiplexer circuit 83b, a plurality of switches SW1 and SW2, capacitors 84 and 85, and an operational amplifier 86.

  The comparator 81 compares the remainder output ST2 with the reference voltage + Vref / 4, and outputs the comparison result to the latch circuit 83a. The comparator 82 compares the remainder output ST2 with the reference voltage −Vref / 4, and outputs the comparison result to the latch circuit 83a.

  The latch circuit 83a latches the comparison result of the comparators 81 and 82, and outputs the result as conversion data D3 <1: 0> to the outside (the error correction circuit 56).

  The multiplexer circuit 83b outputs a reference voltage Vr obtained by D / A converting the conversion data D3 <1: 0> latched by the latch circuit 83a.

  The output of the multiplexer circuit 83b is connected to the node N22 via the switch SW2. The node N22 is connected to the remainder output ST2 (the input part thereof) via the switch SW1.

  In addition, a capacitor 85 having a capacitance value Cs is inserted between the node N22 and the node N23, and the node N23 and the common voltage VCM (input section thereof) are connected via the switch SW1. Further, the node N23 and the node N24 are connected through the switch SW2. Node N24 and common voltage VCM are connected via switch SW1.

  The operational amplifier 86 has a negative input connected to the node N24 and receives a common voltage VCM at the positive input. The remainder output ST3 is output from the node N25 which is the output of the operational amplifier 86. The node N25 is connected to the common voltage VCM via the switch SW1.

  Node N25 is also connected to node N21 via switch SW2. The node N21 is connected to the remainder output ST2 via the switch SW1, and a capacitor 84 having a capacitance value Cf is interposed between the node N21 and the node N23.

  As shown in FIG. 21, in the hold mode, all of the plurality of switches SW2 among the plurality of switches SW1 and the plurality of switches SW2 of the stage circuit 53 are turned on, and all the plurality of switches SW1 are turned off.

  As shown in FIG. 22, in the sample mode, in the stage circuit 53, the plurality of switches SW1 among the plurality of switches SW1 and the plurality of switches SW2 are all turned on, and the plurality of switches SW2 are all turned off.

  The operation of the stage circuit 53 in the hold mode and the sample mode is performed in the same manner as the stage circuit 52. That is, the stage circuit 53 performs the same operation as the stage circuit 52 except that the conversion target is changed from the remainder output ST1 to the remainder output ST2.

  As described above, between the stage circuits connected in series in the pipeline type ADC, there is an operation characteristic in which one is in the sample mode and the other is necessarily in the hold mode.

  Non-Patent Document 1 discloses a circuit that uses this operational characteristic to share one operational amplifier between two stage circuits connected in series to achieve low power consumption and a small layout area. Has been.

  FIG. 23 is a block diagram showing a configuration of a pipelined ADC having a conventional vertical shared amplifier configuration disclosed in Non-Patent Document 1. In FIG. The pipeline type ADC shown in FIG. 23 has a 7-bit configuration in which analog input Ain is A / D converted to output 7-bit output data Dout <6: 0>.

  As shown in FIG. 23, the sample hold unit 50 samples the analog input Ain and outputs a sample hold output value SHout to the stage circuit 57.

  The stage circuit 57 executes A / D conversion processing in the first and second stages based on the sample hold output value SHout, and sends the conversion data D1 <1: 0> and the conversion data D2 <1: 0> to the error correction circuit 56. At the same time, the remainder output ST12 is output to the next stage circuit 58.

  The stage circuit 58 executes A / D conversion processing in the third and fourth stages based on the remainder output ST12, and outputs the converted data D3 <1: 0> and the converted data D4 <1: 0> to the error correction circuit 56. At the same time, the remainder output ST34 is output to the 3-bit ADC 55.

  The 3-bit ADC 55 is configured as a flash type, and outputs conversion data D5 <2: 0>, which is a 3-bit A / D conversion result, to the error correction circuit 56 based on the remainder output ST34.

  The error correction circuit 56 converts the conversion data D1 <1: 0>, conversion data D2 <1: 0>, conversion data D3 <1: 0>, conversion data D4 <1: 0>, and conversion data D5 <3: 0>. The output data Dout <6: 0> is output while performing error correction processing based on the above.

  FIG. 24 is a circuit diagram showing an actual circuit configuration of the stage circuit 57. As shown in the figure, the stage circuit 57 includes a first stage portion 57a, a second stage portion 57b, and an operational amplifier shared portion 57c.

  In the same figure, the switching state when the first stage unit 57a is in the sample mode (Sample Mode) and the second stage unit 57b is in the hold mode (Hold Mode) is shown.

  The first stage unit 57a includes comparators 61 and 62, a latch circuit 63a, a multiplexer circuit 63b, a plurality of switches SW1 and SW2, and capacitors 64 and 65. These connection configurations are the same as those of the stage circuit 52 shown in FIGS. 21 and 22 (except for the portion corresponding to the operational amplifier 76). The comparators 61 and 62, the latch circuit 63a, the multiplexer circuit 63b, the plurality of switches SW1 and SW2 and the capacitors 64 and 65 of the first stage unit 57a are composed of the comparators 71 and 72, the latch circuit 73a, and the multiplexer circuit 73b of the stage circuit 52. , Corresponding to a plurality of switches SW1, SW2 and capacitors 74, 75. The nodes N41 to N44 of the first stage unit 57a correspond to the nodes N11 to N14 of the stage circuit 52.

  On the other hand, the second stage unit 57b corresponds to the stage circuit 52 having the conventional configuration shown in FIGS. 21 and 22 (excluding the operational amplifier 76).

  The common operational amplifier 77 has a negative input connected to the node N14 of the second stage unit 57b, and receives a common voltage VCM at the positive input. A surplus output ST12 is obtained from the node N15 which is the output section of the shared operational amplifier 77. The node N15 is connected to the node N41 of the first stage unit 57a via the switch SW2, and is connected to the node N11 of the second stage unit 57b via the switch SW2.

  25 and 26 are circuit diagrams schematically showing the operation state of the stage circuit 57. FIG. As shown in these drawings, the first stage AD / DA conversion portion 93 (see FIG. 24) including the comparators 61 and 62, the latch circuit 63a, and the multiplexer circuit 63b in the first stage portion 57a is omitted, and the first stage is omitted. A portion 91 is shown. Similarly, the second stage AD / DA conversion portion 94 (see FIG. 24) including the comparators 71 and 72, the latch circuit 73a, and the multiplexer circuit 73b in the second stage portion 57b is omitted, and is shown as the second stage portion 92. Yes.

  The input voltage Vi to the first stage portion 91 means the sample hold output value SHout, the reference voltage Vr means the output voltage from the multiplexer circuit 63b of the first stage AD / DA conversion portion 93, and the reference voltage Vr (1 ) Means an output voltage from the multiplexer circuit 73b of the second stage AD / DA converter 94.

  25 and 26 show the presence of a capacitor 78 (capacitance value Cp) that is a negative input capacitance of the shared operational amplifier 77. FIG. The capacitor 78 has one electrode connected to the negative input of the common operational amplifier 77 and the other electrode to which a common voltage VCM is applied.

  FIG. 25 shows the first state (when the first stage portion 91 is in the sample mode and the second stage portion 92 is in the hold mode), and FIG. 26 shows the second state (when the first stage portion 91 is in the hold mode). In the mode, the second stage portion 92 is in the sample mode).

  In FIG. 25 showing the first state of the stage circuit 57, the first stage portion 91 is in the sample mode state, and the plurality of switches SW1 among the plurality of switches SW1 and the plurality of switches SW2 are all turned on, and the plurality of switches All SW2 are turned off. On the other hand, the second stage portion 92 is in the hold mode state, and among the plurality of switches SW1 and the plurality of switches SW2, all the plurality of switches SW2 are turned on, and all the plurality of switches SW1 are turned off.

  At this time, the charge Qa on the node N43 side of the capacitors 64 and 65 in the first stage portion 91 is expressed by the following equation (1).

  Further, a potential difference Vx is generated between one electrode and the other electrode of the capacitor 78. That is, the potential of one electrode of the capacitor 78 is the potential difference Vx + the common voltage VCM. Therefore, the potential difference Vx is represented by {Vx = − (Vo / A)}. “A” means the amplification factor of the shared operational amplifier 77, and Vo means the output voltage of the shared operational amplifier 77.

  Due to this potential difference Vx, a charge Qp expressed by the following equation (2) is accumulated in the capacitor 78 of the shared operational amplifier 77.

  Consider the case where the capacitor 78 has accumulated charges and the state changes from the first state (FIG. 25) to the second state (FIG. 26).

  In FIG. 26 showing the second state of the stage circuit 57, the first stage portion 91 is in the hold mode, and the plurality of switches SW2 among the plurality of switches SW1 and the plurality of switches SW2 are all turned on, and the plurality of switches All SW1 are turned off. On the other hand, the second stage portion 92 is in the sample mode, and among the plurality of switches SW1 and the plurality of switches SW2, all the plurality of switches SW1 are turned on and all the plurality of switches SW2 are turned off.

  At this time, the accumulated charge Qb of the capacitor 78 on the node N44 side is expressed by the following equation (3). The potential difference Vx1 means a potential difference on one electrode side of the capacitor 78 in the second state, and has a relationship of {Vx1 = −Vo1 / A} with the output voltage Vo1.

  Since {Qa + Qp = Qb} is established from the law of conservation of charge, the output voltage Vo1 is obtained by the following equation (4).

  Here, when {(Cs + Cf + Cp) / A << Cf}, the formula (4) is simplified to the formula (5).

  The double underline of this equation (5) is output as an offset. In the non-patent document 1, this is described as “Memory Effect”. In addition, this offset tends to increase each time the first state and the second state are repeated.

krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis and Robert G. Renninger, "A 250-mW, 8-b, 52-Msamples / s Parallel-Pipelined A / D Converter with Reduced Number of Amplifers", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 32, NO. 3, MARCH 1997

  FIG. 27 is an explanatory diagram schematically showing an offset increase phenomenon due to the “Memory Effect”. In FIGS. 27A to 27E, the contents of FIGS. 25 and 26 are simplified for convenience of explanation.

  As shown in the figure, the stage circuit 57 in the pipeline type ADC alternately repeats the first state and the second state. In other words, the stage circuit 57 operates in the order of (a) to (e), and among (a) to (e), the stage circuit 57 is in the first state at the time of (a), (c) and (e), In the case of (b) and (d), the second state is entered. Hereinafter, the operation of the stage circuit 57 will be described with reference to FIG.

  First, as shown in FIG. 27A, the first stage portion 91 of the stage circuit 57 is in the sample mode, the second stage portion 92 is in the hold mode, and the output voltage Vo is obtained from the shared operational amplifier 77. The reference voltage Vr (0) means the reference voltage Vr of the second stage AD / DA conversion portion 94. At this time, the output voltage Vo is obtained.

  Next, as shown in (b) of FIG. 27, the first stage portion 91 of the stage circuit 57 is in the hold mode and the second stage portion 92 is in the sample mode. An output voltage Vo1 is obtained. The reference voltage Vr (1) means the reference voltage Vr of the first stage AD / DA conversion portion 93. In the equation (6), it means a potential difference Vx1 (= −Vo1 / A).

  Thereafter, as shown in (c) of FIG. 27, the first stage portion 91 of the stage circuit 57 is in the sample mode, the second stage portion 92 is in the hold mode, and the output shown in the following equation (7) from the common operational amplifier 77. A voltage Vo2 is obtained. The reference voltage Vr (2) means the reference voltage Vr of the second stage AD / DA conversion portion 94. Further, in the equation (7), it means the potential difference Vx2 (= −Vo2 / A), and the hatched portion means a portion that can be ignored as an equation.

  Next, as shown in (d) of FIG. 27, the first stage portion 91 of the stage circuit 57 is in the hold mode and the second stage portion 92 is in the sample mode. An output voltage Vo2 is obtained. The reference voltage Vr (3) means the reference voltage Vr of the first stage AD / DA conversion part 93. In the equation (8), it means the potential difference Vx3 (= −Vo3 / A), and the hatched portion means a portion that can be ignored as an equation.

  Further, as shown in FIG. 27 (e), the first stage portion 91 of the stage circuit 57 is in the sample mode, the second stage portion 92 is in the hold mode, and the output shown in the following equation (9) from the common operational amplifier 77. A voltage Vo4 is obtained. The reference voltage Vr (4) means the reference voltage Vr of the second stage AD / DA conversion portion 94. In Equation (9), it means the potential difference Vx4 (= Vo4 / A), and the shaded portion means a portion that can be ignored as an equation.

  As described above, when a pipelined ADC having a shared amplifier configuration is configured, the offset (the double underlined portion of Expressions (6) to (9)) increases each time the stage circuit 57 serving as the component repeats the operation. A phenomenon occurs. For this reason, there existed a problem that AD conversion precision will deteriorate.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a pipeline type ADC having low power consumption and a small layout area and having high A / D conversion accuracy.

  According to one embodiment of the present invention, the pipeline type ADC shares a shared amplifier between the first and second stage portions. A first reset means is provided in the first stage portion, and initializes the potential of the first negative input of the shared amplifier to a reset voltage in the sample mode of the first stage portion. Further, the pipeline type ADC is provided in the second stage portion, and includes a second reset means for initializing the potential of the second negative input of the shared amplification unit to a reset voltage in the sample mode of the second stage portion. Have.

  According to this embodiment, the pipeline type ADC shares the common amplifier between the first and second stage portions, thereby reducing the power consumption and the layout area.

  In addition, each of the first and second stage portions has first and second reset means for initializing the potentials of the first and second negative inputs of the shared amplifier to a reset voltage for each sample mode. . For this reason, the pipeline type ADC can exhibit high A / D conversion accuracy.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of a pipelined ADC having a vertical shared amplifier configuration according to Embodiment 1 of the present invention. The pipeline type ADC shown in FIG. 1 has a 7-bit configuration in which analog input Ain is A / D converted to output 7-bit output data Dout <6: 0>.

  As shown in FIG. 1, the sample hold unit 10 samples the analog input Ain and outputs a sample hold output value SHout to the stage circuit 1.

  The stage circuit 1 executes A / D conversion processing (partial A / D conversion processing) in the conversion ranges for the first and second stages based on the sample hold output value SHout, and conversion data D1 <1: 0. > And conversion data D2 <1: 0> are output to the error correction circuit 6, and the remainder output ST12 is output to the next stage circuit 2. The conversion data D1 <1: 0> is obtained from the first stage portion of the stage circuit 1, and the conversion data D2 <1: 0> is obtained from the second stage portion of the stage circuit 1.

  The stage circuit 2 executes A / D conversion processing in the conversion ranges for the third and fourth stages based on the remainder output ST12, and converts the conversion data D3 <1: 0> and the conversion data D4 <1: 0> into an error correction circuit. 6 and the remainder output ST34 is output to the 3-bit DAC 5. The conversion data D3 <1: 0> is obtained from the third stage portion of the stage circuit 2, and the conversion data D4 <1: 0> is obtained from the fourth stage portion of the stage circuit 2.

  The 3-bit DAC 5 is configured as a flash type, and outputs conversion data D5 <2: 0>, which is a 3-bit A / D conversion result, to the error correction circuit 6 based on the remainder output ST34.

  The error correction circuit 6 performs conversion data D1 <1: 0>, conversion data D2 <1: 0>, conversion data D3 <1: 0>, conversion data D4 <1: 0>, and conversion data D5 <3: 0>. The output data Dout <6: 0> is output while performing error correction processing based on the above.

  2 and 3 are circuit diagrams schematically showing the operation state of the stage circuit 1. FIG. As shown in these drawings, the stage circuit 1 mainly includes a first stage portion 11, a second stage portion 12, a shared operational amplifier 37, and capacitors 38 and 48.

  FIG. 2 shows a switching state when the first stage portion 11 is in the sample mode (Sample Mode) and in the second stage portion 57b hold mode (Hold Mode).

  The first stage portion 11 includes a plurality of switches SW1, SW2, SWa and capacitors 34, 35. The switch SWa is provided between the node N3 and the common voltage VCM. These connection configurations are the same as those of the first stage portion 91 shown in FIG. The capacitors 34 and 35 of the first stage portion 11 correspond to the capacitors 64 and 65 of the first stage portion 91, and the nodes N1 to N3 of the first stage portion 11 correspond to the nodes N41 to N43 of the first stage portion 91.

  The switch SWa between the node N3 and the common voltage VCM corresponds to the switch SW1 between the node N43 and the common voltage VCM. The switch SWa is turned on / off at the same timing as the switch SW1.

  Further, the input voltage Vi (input related voltage) means the sample hold output value SHout obtained from the sample hold unit 10, and the reference voltage Vr has the same configuration as that of the first stage AD / DA conversion part 93 shown in FIG. It means the reference voltage Vr output from the first stage AD / DA conversion part.

  The second stage portion 12 includes a plurality of switches SW1, SW2, SWb and capacitors 44, 45. These connection configurations are the same as those of the second stage portion 92 shown in FIG. The capacitors 44 and 45 of the second stage portion 12 correspond to the capacitors 74 and 75 of the second stage portion 92, and the nodes N 6 to N 8 of the second stage portion 12 correspond to the nodes N 11 to N 13 of the second stage portion 92.

  The node N8 of the second stage portion 12 is connected to the common voltage VCM via the switch SWb. The switch SWb is turned on / off at the same timing as the switch SW1.

  Further, the reference voltage Vr (0) means the reference voltage Vr output from the second stage AD / DA conversion part configured similarly to the second stage AD / DA conversion part 94 shown in FIG.

  Further, the node N3 of the first stage portion 11 is connected to the node N4, and this node N4 is connected to the first negative input (first amplification input section) of the shared operational amplifier 37. Similarly, the node N8 of the second stage portion 12 is connected to the node N9, and this node N9 is connected to the second negative input (second amplification input section) of the shared operational amplifier 37.

  A capacitor 38 (capacitance value Cp1) that is an input capacitance of the shared operational amplifier 37 exists between the node N4 and the common voltage VCM, and similarly, a capacitor 48 (capacitance value Cp2) that is an input capacitance between the node N9 and the common voltage VCM. Exists.

  The common operational amplifier 37 (common amplification unit) has a four-input one-output configuration. The potential difference between the first negative input and the first positive input (first and second amplification input units) and the second negative input and second The potential difference between the positive inputs (third and fourth amplification input units) is amplified, and the output voltage Vo is output from the node N10. The common voltage VCM is applied to the first and second positive inputs of the shared operational amplifier 37 as the first and second comparison voltages.

  2 shows the first state (when the first stage portion 11 is in the sample mode and the second stage portion 12 is in the hold mode), and FIG. 3 shows the second state (when the first stage portion 11 is in the hold mode). In the mode, the second stage portion 12 is in the sample mode.

  In FIG. 2 showing the first state of the stage circuit 1, the first stage portion 11 is in the sample mode, and all of the plurality of switches SW1 and the switch SWa among the plurality of switches SW1, the plurality of switches SW2, and the switch SWa are turned on. Thus, the plurality of switches SW2 are all turned off. On the other hand, the second stage portion 12 is in the hold mode, and among the plurality of switches SW1, the plurality of switches SW2, and the switch SWa, all the plurality of switches SW2 are turned on, and all the plurality of switches SW1 and the switch SWa are turned off. Become.

  At this time, the charge Qa on the node N3 side of the capacitors 34 and 35 in the first stage portion 11 is expressed by the above-described equation (1). Thus, the first stage portion 11 samples the input voltage Vi.

  At this time, the common voltage VCM is applied to the node N4 (node N3) of the first stage portion 11 by the switch SWa in the on state. As a result, there is no potential difference between one electrode and the other electrode of the capacitor 38, and the charge of the capacitor 38 is reset to “0”. That is, the charge Qp represented by the above-described equation (2) is not accumulated in the capacitor 38. Then, consider a case where the state changes from the first state (FIG. 2) to the second state (FIG. 3).

  In addition to the above, the first stage portion 11 performs A / D conversion processing (first partial A / D) of the conversion range (first range) of the first stage portion with respect to the input voltage Vi in the sample mode. D conversion processing) is executed to obtain 2-bit conversion data D1 <1: 0> (first conversion data).

  In the hold mode, the second stage portion 12 has a voltage related to the potential difference between the sampled remainder output ST1 and the reference voltage Vr (0) obtained by D / A converting the conversion data D2 <1: 0> (second output). Is output to the second negative input of the shared operational amplifier 37 via the node N8.

  In FIG. 3 showing the second state of the stage circuit 1, the first stage portion 11 is in the hold mode, and the plurality of switches SW1, the plurality of switches SW2, and the plurality of switches SW2 among the switches SWa are all turned on. All the switches SW1 and the switch SWa are turned off. On the other hand, the second stage portion 12 is in the sample mode, and all the plurality of switches SW1 and the switch SWb among the plurality of switches SW1 and the plurality of switches SW2 are turned on, and all the plurality of switches SW2 are turned off.

  At this time, the accumulated charge Qb of the capacitor 38 on the node N4 side is expressed by the above-described equation (3). The potential difference Vx1 means a potential difference on the one electrode side of the capacitor 38 in the second state, and has a relationship of {Vx1 = −Vo1 / A} with the output voltage Vo1.

  Since {Qa = Qb} is established from the law of conservation of charge, the output voltage Vo1 is obtained by the following equation (10).

  As described above, the first stage portion 11 has the potential difference Vx1 (the first difference between the input voltage Vi and the reference voltage Vr (1) obtained by D / A converting the conversion data D1 <1: 0> in the hold mode. (Stage output voltage) is output from the node N3 (first stage output unit).

  At this time, as shown in Expression (10), there is no offset in the output voltage Vo1 obtained from the stage circuit 1. The same applies to the stage circuit 2. Therefore, the “Memory Effect” does not occur in the pipeline type ADC of the first embodiment.

  As a result, in the ADC of the first embodiment, the common operational amplifier 37 is shared between the first stage portion 11 and the second stage portion 12, thereby reducing power consumption and reducing the layout area and increasing the A / D conversion accuracy can be exhibited.

  In addition to the above, the second stage portion 12 samples the output voltage Vo1 of the shared operational amplifier 37 as a remainder output ST1 in the sample mode, and also converts the second stage portion to a conversion range (second range) with respect to the remainder output ST1. ) A / D conversion processing (second partial A / D conversion processing) is executed to obtain 2-bit conversion data conversion data D2 <1: 0> (second conversion data).

  Of course, the stage circuit 2 performs the same configuration and operation as the stage circuit 1. However, the corresponding portion of the first stage portion 11 outputs the remainder output ST3 with the remainder output ST2 as the input voltage Vi, and the equivalent portion of the second stage portion 12 receives the remainder output ST3 and outputs the remainder output ST4.

  As described above, the stage circuit 1 (2) constituting the pipeline type ADC according to the first embodiment shares the common amplifier between the first stage portion 11 and the second stage portion 12, so that the ADC as a whole can be realized. Low power consumption and a small layout area can be achieved.

  In addition, in the stage circuit 1, the first stage portion 11 and the second stage portion 12 are initially set to the common voltage VCM, which is a reset voltage, at the node N4 (node N3) and the node N9 (node N8) in the sample mode, respectively. First and second resetting means (switches SWa and SWb) are provided.

  For this reason, since the potentials of the node N4 and the node N9 are always reset to the common voltage VCM every time the first stage portion 11 and the second stage portion 12 are in the sample mode, the “Memory Effect” occurs as described above. Absent.

  Therefore, in the hold mode of each of the first stage portion 11 and the second stage portion 12, the potentials of the node N4 and the node N9 in the previous sample mode do not affect the operation of the shared operational amplifier 37.

  As a result, the pipeline type ADC of the first embodiment can achieve low power consumption, a small layout, and high A / D conversion accuracy.

(Specific configuration of the preamplifier portion of the shared operational amplifier 37)
4 to 10 are circuit diagrams showing examples of the internal configuration of the differential amplifier in the preamplifier portion of the shared operational amplifier 37, respectively. Both are realized by a 4-input 2-output differential amplifier. The shared operational amplifier 37 further has an amplifier (hereinafter referred to as “rear amplifier”) in the subsequent stage of the preamplifier.

  The differential amplifier OP1 shown in FIG. 4 includes NMOS transistors Q1 to Q7, and the NMOS transistors Q1 and Q2 and the NMOS transistors Q3 and Q4 form a differential pair.

  NMOS transistors Q1 and Q2 are provided in parallel between the nodes N32 and N30, NMOS transistors Q3 and Q4 are provided in parallel between the nodes N31 and N30, and input to the gates of the NMOS transistors Q1 to Q4 which form an input differential pair. Voltages V11 to V14 are applied.

  The node N30 is grounded via the NMOS transistor Q7, and a fixed voltage Vbn1 that is always turned on is applied to the gate of the NMOS transistor Q7. The NMOS transistor Q7 functions as a constant current source.

  The drains of the drain and gate common NMOS transistors Q5 and Q6 are connected to the power supply voltage Vdd, the source of the NMOS transistor Q5 is connected to the node N32, and the source of the NMOS transistor Q6 is connected to the node N31. NMOS transistors Q5 and Q6 function as a load.

  In such a configuration, the differential amplifier OP1 shown in FIG. 4 outputs the amplification result based on the potential difference between the input voltages V11 and V12 and the input voltages V13 and V14 as output voltages V31 and V32 from the nodes N31 and N32. Can do.

  The differential amplifier OP2 shown in FIG. 5 includes NMOS transistors Q1 to Q4 and Q7 and resistors R1 and R2, and the NMOS transistors Q1 and Q2 and the NMOS transistors Q3 and Q4 form a differential pair.

  The differential amplifier OP2 has the same configuration as that of the differential amplifier OP1 shown in FIG. 4 except that the NMOS transistors Q5 and Q6 are replaced with resistors R1 and R2. The resistors R1 and R2 function as a load.

  In such a configuration, the differential amplifier OP2 shown in FIG. 5 outputs the amplification result based on the potential difference between the input voltages V11 and V12 and the input voltages V13 and V14 as output voltages V31 and V32 from the nodes N31 and N32. Can do.

  The differential amplifier OP3 shown in FIG. 6 includes PMOS transistors Q11 to Q14, Q17 and resistors R11, R12, and the PMOS transistors Q11, Q12 and the PMOS transistors Q13, Q14 form a differential pair.

  PMOS transistors Q11 and Q12 are provided in parallel between nodes N34 and N50, PMOS transistors Q13 and Q14 are provided in parallel between nodes N33 and N50, and input voltages V11 to V14 are applied to the gates of PMOS transistors Q11 to Q14. Is done.

  The node N50 is connected to the power supply voltage Vdd via the PMOS transistor Q17, and a fixed voltage Vbp1 that is always on is applied to the gate of the PMOS transistor Q17. The PMOS transistor Q17 functions as a constant current source.

  One ends of the resistors R11 and R12 are connected to the nodes N34 and N33, and the other ends are grounded. Resistors R11 and R12 function as a load.

  In such a configuration, the differential amplifier OP3 shown in FIG. 6 outputs the amplification result based on the potential difference between the input voltages V11 and V12 and the input voltages V13 and V14 as output voltages V31 and V32 from the nodes N33 and N34. Can do.

  The differential amplifier OP4 shown in FIG. 7 includes PMOS transistors Q11 to Q14, Q17, Q31 to Q34 and NMOS transistors Q21 to Q24, and the PMOS transistors Q11 and Q12 and the PMOS transistors Q13 and Q14 form a differential pair.

  PMOS transistors Q11 and Q12 are provided in parallel between the nodes N39 and N50, PMOS transistors Q13 and Q14 are provided in parallel between the nodes N40 and N50, and input voltages V11 to V14 are applied to the gates of the PMOS transistors Q11 to Q14. Is done.

  The node N50 is connected to the power supply voltage Vdd via the PMOS transistor Q17, and a fixed voltage Vbp1 that is always on is applied to the gate of the PMOS transistor Q17. The PMOS transistor Q17 functions as a constant current source.

  The sources of the PMOS transistors Q31 and Q32 sharing the gate are both connected to the power supply voltage Vdd. The sources of the PMOS transistors Q33 and Q34 sharing the gate are connected to the drains of the PMOS transistors Q31 and Q32.

  A fixed voltage Vbp2 which is always on is applied to the gates of the PMOS transistors Q31 and Q32 sharing the gate. A fixed voltage Vbp3 that is always on is applied to the gates of the PMOS transistors Q33 and Q34 sharing the gate.

  The drains of the gate-shared NMOS transistors Q21 and Q22 are connected to the drains of the PMOS transistors Q33 and Q34. The drains of the NMOS transistors Q23 and Q24 sharing the gate are connected to the drains of the NMOS transistors Q21 and Q22, and the sources are both grounded.

  A fixed voltage Vbn2 that is always on is applied to the gates of the NMOS transistors Q21 and Q22 sharing the gate. A fixed voltage Vbn3 which is always on is applied to the gates of the NMOS transistors Q23 and Q24 sharing the gate.

  The drain of the PMOS transistor Q33 (NMOS transistor Q21) becomes the node N36, and the drain of the PMOS transistor Q34 (NMOS transistor Q22) becomes the node N35.

  The source of the NMOS transistor Q21 (the drain of the NMOS transistor Q23) is the node N40, and the source of the NMOS transistor Q22 (the drain of the NMOS transistor Q24) is the node N39.

  Thus, the cascode connection circuit 59 of the NMOS transistors Q21 to Q24 and the PMOS transistors Q31 to Q34 is configured.

  In such a configuration, the differential amplifier OP4 shown in FIG. 7 outputs the amplification result based on the potential difference between the input voltages V11 and V12 and the input voltages V13 and V14 as output voltages V31 and V32 from the nodes N35 and N36. Can do. At this time, the amplification factor can be increased by the cascode connection circuit 59.

  The differential amplifier OP5 shown in FIG. 8 includes PMOS transistors Q51 to Q53, Q31 to Q34 and NMOS transistors Q41 to Q43, Q21 to Q24. The PMOS transistors Q51 and Q52 form a differential pair, and the NMOS transistor Q41 and Q42 forms a differential pair.

  A PMOS transistor Q51 is provided between the nodes N39 and N50, a PMOS transistor Q52 is provided between the nodes N40 and N50, an NMOS transistor Q41 is provided between the nodes N37 and N30, and an NMOS transistor Q42 is provided between the nodes N38 and N30. It is done.

  Input voltages V11 and V13 are applied to the gates of the NMOS transistors Q41 and Q42, and input voltages V12 and V14 are applied to the gates of the PMOS transistors Q51 and Q52.

  Node N50 is connected to power supply voltage Vdd via PMOS transistor Q53, and fixed voltage Vbp4 which is always on is applied to the gate of PMOS transistor Q53. The PMOS transistor Q53 functions as a constant current source.

  The node N30 is grounded via the NMOS transistor Q43, and a fixed voltage Vbn4 that is always turned on is applied to the gate of the NMOS transistor Q43. The NMOS transistor Q43 functions as a constant current source.

  Further, the PMOS transistors Q31 to Q34 and the NMOS transistors Q21 to Q24 constitute a cascode connection circuit 59 in the same manner as the differential amplifier OP4 shown in FIG. Note that the drain of the PMOS transistor Q31 (source of the PMOS transistor Q33) becomes the node N38, and the drain of the PMOS transistor Q32 (source of the PMOS transistor Q34) becomes the node N37.

  In such a configuration, the differential amplifier OP5 shown in FIG. 8 converts the amplification result based on the potential difference between the input voltages V11 and V13 and the potential difference between the input voltages V12 and V14 as output voltages V31 and V32 from the nodes N35 and N36. Can be output. At this time, the amplification factor can be increased by the cascode connection circuit 59.

  A differential amplifier OP6 shown in FIG. 9 includes NMOS transistors Q1 to Q4, Q7, Q21 to Q24 and PMOS transistors Q31 to Q34, and the NMOS transistors Q1 and Q2 and the NMOS transistors Q3 and Q4 form a differential pair.

  NMOS transistors Q1 and Q2 are provided in parallel between the nodes N37 and N30, NMOS transistors Q3 and Q4 are provided in parallel between the nodes N38 and N30, and input voltages V11 to V14 are applied to the gates of the NMOS transistors Q1 to Q4. Is done.

  The node N30 is connected to the ground level via the NMOS transistor Q7, and a fixed voltage Vbn1 that is always on is applied to the gate of the NMOS transistor Q7. The NMOS transistor Q7 functions as a constant current source.

  Further, the PMOS transistors Q31 to Q34 and the NMOS transistors Q21 to Q24 constitute a cascode connection circuit 59 in the same manner as the differential amplifier OP4 shown in FIG.

  In such a configuration, the differential amplifier OP6 shown in FIG. 9 outputs the amplification result based on the potential difference between the input voltages V11 and V12 and the input voltages V13 and V14 as output voltages V31 and V32 from the nodes N35 and N36. Can do. At this time, the amplification factor can be increased by the cascode connection circuit 59.

  A differential amplifier OP7 shown in FIG. 10 includes PMOS transistors Q71 to Q75, Q31 to Q34 and NMOS transistors Q61 to Q65, Q21 to Q24. The NMOS transistors Q61 and Q62 and the NMOS transistors Q63 and Q64 form a differential pair. Eggplant. Further, the PMOS transistors Q71 and Q72 and the PMOS transistors Q73 and Q74 form a differential pair.

  NMOS transistors Q61 and Q62 are provided in parallel between nodes N37 and N30, and NMOS transistors Q63 and Q64 are provided in parallel between nodes N38 and N30. PMOS transistors Q71 and Q72 are provided in parallel between the nodes N39 and N50, and PMOS transistors Q73 and Q74 are provided in parallel between the nodes N40 and N50.

  Input voltages V11 to V14 are applied to the gates of the NMOS transistors Q61 to Q64. Similarly, input voltages V11 to V14 are applied to the gates of the PMOS transistors Q71 to Q74.

  The node N30 is grounded via the NMOS transistor Q65, and a fixed voltage Vbn5 that is always turned on is applied to the gate of the NMOS transistor Q65. The NMOS transistor Q65 functions as a constant current source.

  Node N50 is connected to power supply voltage Vdd via PMOS transistor Q75, and fixed voltage Vbp5 that is always on is applied to the gate of PMOS transistor Q75. The PMOS transistor Q75 functions as a constant current source.

  Further, the PMOS transistors Q31 to Q34 and the NMOS transistors Q21 to Q24 constitute a cascode connection circuit 59 in the same manner as the differential amplifier OP4 shown in FIG.

  In such a configuration, the differential amplifier OP7 shown in FIG. 10 outputs the amplification result based on the potential difference between the input voltages V11, V12 and the input voltages V13, V14 as output voltages V31, V32 from the nodes N35, N36. Can do. At this time, the amplification factor can be increased by the cascode connection circuit 59.

<Embodiment 2>
(First aspect)
FIG. 11 is a circuit diagram schematically showing the configuration of a stage circuit 1A which is the first mode in the second embodiment. The overall configuration of the first aspect of the pipeline type ADC of the second embodiment is the pipe of the first embodiment shown in FIG. 1 except that the internal configuration of the stage circuits 1 and 2 is changed to FIG. It is the same as the line type ADC.

  As shown in the figure, the stage circuit 1A mainly includes a first stage portion 13, a second stage portion 14, a shared operational amplifier 37, and switches SWc to SWf.

  FIG. 11 shows a switching state when the first stage portion 13 is in the sample mode (Sample Mode) and the second stage portion 14 is in the hold mode (Hold Mode).

  The first stage portion 13 includes a plurality of switches SW1 and SW2, capacitors 34 and 35, and a switch SWa. These connection configurations are the same as those of the first stage portion 11 shown in FIG.

  The second stage portion 14 includes a plurality of switches SW1 and SW2, capacitors 44 and 45, and a switch SWb. These connection configurations are the same as those of the second stage portion 12 shown in FIG.

  The node N3 of the first stage portion 13 is connected to the node N4 via the switch SWc, and this node N4 is connected to the first negative input of the shared operational amplifier 37P.

  Further, the node N4 is connected to the power supply voltage Vdd via the switch SWe. That is, the potential of the node N4 can be reset to the power supply voltage Vdd by turning off the switch SWc and turning on the switch SWe.

  Similarly, the node N8 of the second stage portion 14 is connected to the node N9 via the switch SWd, and this node N9 is connected to the second negative input of the shared operational amplifier 37P.

  The node N9 is connected to the power supply voltage Vdd via the switch SWf. That is, the potential of the node N9 can be reset to the power supply voltage Vdd by turning off the switch SWd and turning on the switch SWf.

  The switch SWc is turned on and off at the same timing as the switch SW2 of the first stage portion 13, and the switch SWe is turned on and off at the same timing as the switch SW1 of the first stage portion 13.

  Similarly, the switch SWd is turned on and off at the same timing as the switch SW2 of the second stage portion 14, and the switch SWf is turned on and off at the same timing as the switch SW1 of the second stage portion 14.

  Similar to the shared operational amplifier 37 of the first embodiment, the shared operational amplifier 37P has a 4-input 1-output configuration, and a potential difference between the first negative input and the first positive input and a potential difference between the second negative input and the second positive input. And an output voltage Vo is output from the node N10. Similarly to the first embodiment, the common voltage VCM is applied to the first and second positive inputs of the shared operational amplifier 37P.

  In the common operational amplifier 37P, the input differential pair of the preamplifier portion is configured by a PMOS transistor. For example, the shared operational amplifier 37P has a configuration of a differential amplifier OP3 (see FIG. 6) using PMOS transistors Q11 to Q14 as an input differential pair.

  FIG. 11 shows the first state (when the first stage portion 13 is in the sample mode and the second stage portion 14 is in the hold mode).

  In FIG. 11 showing the first state of the stage circuit 1A, the first stage portion 13 is in the sample mode, and includes a plurality of switches SW1, a plurality of switches SW2, and a plurality of switches SW1 among the switches SWa, SWc, and SWe. The switches SWa and SWe are turned on, and all the plurality of switches SW2 and the switch SWc are turned off.

  On the other hand, the second stage portion 14 is in the hold mode, and the plurality of switches SW1 and the plurality of switches SW2 and all the plurality of switches SW2 and the switches SWd among the switches SWa, SWd, and SWf are turned on, The switches SWa and SWf are turned off.

  At this time, the charge Qa on the node N3 side of the capacitors 34 and 35 in the first stage portion 13 is expressed by the above-described equation (1).

  On the other hand, when the switch SWc is turned off, the node N4 is electrically independent from the node N3. When the switch SWe is turned on in this state, the power supply voltage Vdd is applied to the node N4 of the first stage portion 13 as a reset voltage. As described above, the switch SWc and the switch SWe function as reset means (first reset means) for the potential of the node N4 in the sample mode.

  As a result, one PMOS transistor forming the input differential pair of the preamplifier portion of the shared operational amplifier 37P is completely turned off, and the total gain of the shared operational amplifier 37P as a whole is not attenuated.

  At this time, there is a potential difference between one electrode and the other electrode of a capacitor (not shown, corresponding to the capacitor 38 of the first embodiment shown in FIG. 2), which is an input capacitance associated with the first negative input of the shared operational amplifier 37P. Vdd−VCM) occurs, but since this potential difference is constant in the sample mode, the phenomenon that the offset increases as shown in the above formulas (6) to (9) does not occur. In other words, the offset associated with the “Memory Effect” is always constant between the expressions (6) to (9), so that the AD conversion accuracy does not deteriorate.

  Also on the second stage portion 14 side, the switch SWd and the switch SWf function as reset means (second reset means) for resetting the potential of the node N9 to the power supply voltage Vdd, so that the first stage portion 13 side. Has the same effect as

  As a result, in the first aspect of the ADC of the second embodiment, the common operational amplifier 37P is shared between the first stage portion 13 and the second stage portion 14, thereby reducing the power consumption and the layout area. In addition, high A / D conversion accuracy can be exhibited.

  In addition, a stage circuit 1A having a configuration in which a power supply voltage is used as a reset voltage for the common operational amplifier 37P having a differential input PMOS transistor configuration is realized. As a result, the first aspect of the ADC of the second embodiment has an effect that it can be effectively used without attenuating the total gain of the shared operational amplifier 37P.

(Second aspect)
FIG. 12 is a circuit diagram schematically showing the configuration of stage circuit 1B as the second mode in the second embodiment. The overall configuration of the second mode of the second embodiment is the same as that of the pipeline type ADC of the first embodiment shown in FIG. 1 except that the internal configuration of the stage circuits 1 and 2 is changed to FIG. It is.

  As shown in the figure, the stage circuit 1B mainly includes a first stage portion 13, a second stage portion 14, a shared operational amplifier 37, and switches SWc, SWd, SWg, and SWh.

  FIG. 12 shows the switching state when the first stage portion 13 is in the sample mode and the second stage portion 14 is in the hold mode. The first stage portion 13, the first stage portion 13, and the switches SWc and SWd are the same as those in the first mode shown in FIG.

  Node N4 is connected to the ground level via switch SWg. That is, the potential of the node N4 can be reset to the ground level by turning off the switch SWc and turning on the switch SWg. In this way, the switches SWc and SWg function as reset means (first reset means).

  Similarly, the node N9 is connected to the ground level via the switch SWh. That is, the potential of the node N9 can be reset to the ground level by turning off the switch SWd and turning on the switch SWh. In this way, the switches SWd and SWh function as reset means (second reset means).

  The switch SWg is turned on and off at the same timing as the switch SW1 of the first stage portion 13, and the switch SWh is turned on and off at the same timing as the switch SW1 of the second stage portion 14.

  Similar to the shared operational amplifier 37 of the first embodiment, the shared operational amplifier 37N has a 4-input 1-output configuration, and a potential difference between the first negative input and the first positive input and a potential difference between the second negative input and the second positive input. And an output voltage Vo is output from the node N10. The common voltage VCM is applied to the first and second positive inputs of the shared operational amplifier 37N.

  In the common operational amplifier 37N, the input differential pair in the preamplifier portion is configured by an NMOS transistor. For example, the shared operational amplifier 37N has a configuration of a differential amplifier OP1 (see FIG. 4) using NMOS transistors Q1 to Q4 as an input differential pair.

  FIG. 12 shows the first state (when the first stage portion 13 is in the sample mode and the second stage portion 14 is in the hold mode).

  In FIG. 12 showing the first state of the stage circuit 1B, the first stage portion 13 is in the sample mode, and among the plurality of switches SW1, the plurality of switches SW2, and the switches SWa, SWc and SWg, All switches SWa and SWg are turned on, and all the plurality of switches SW2 and SWc are turned off.

  On the other hand, the second stage portion 14 is in the hold mode state, and among the plurality of switches SW1, the plurality of switches SW2, and the switches SWa, SWd, and SWh, all the plurality of switches SW2 and the switch SWd are turned on, and the plurality of switches SW1. All switches SWa and SWh are turned off.

  At this time, the charge Qa on the node N3 side of the capacitors 34 and 35 in the first stage portion 13 is expressed by the above-described equation (1).

  On the other hand, when the switch SWc is turned off, the node N4 is electrically independent from the node N3. When the switch SWg is turned on in this state, the ground level is applied to the node N4 of the first stage portion 13. As a result, one NMOS transistor of the input differential pair in the preamplifier portion of the shared operational amplifier 37N is completely turned off, so that the total gain of the shared operational amplifier 37N is not attenuated.

  A potential difference (0-VCM) is provided between one electrode and the other electrode of a capacitor (not shown, corresponding to the capacitor 38 of the first embodiment shown in FIG. 2), which is an input capacitance associated with the first negative input of the shared operational amplifier 37N. However, since this potential difference is constant in the sample mode, the phenomenon that the offset increases as shown in the above-described equations (6) to (9) does not occur. In other words, the offset associated with the “Memory Effect” is always constant between the expressions (6) to (9), so that the AD conversion accuracy does not deteriorate.

  As a result, in the second aspect of the ADC of the second embodiment, the common operational amplifier 37N is shared between the first stage portion 13 and the second stage portion 14, thereby reducing the power consumption and the layout area. In addition, high A / D conversion accuracy can be exhibited.

  In addition, the stage circuit 1B having a configuration in which a differential input uses a ground level as a reset voltage for the common operational amplifier 37N having an NMOS transistor configuration is realized. As a result, the second aspect of the pipeline type ADC of the second embodiment has an effect that it can be effectively used without attenuating the total gain of the shared operational amplifier 37N.

<Embodiment 3>
(First aspect)
FIG. 13 is a circuit diagram showing a circuit configuration of a differential amplifier that is a preamplifier in the shared operational amplifier according to the third embodiment. The differential amplifier OP11 which is the first mode of the third embodiment is used for the preamplifier portion of the shared operational amplifier 37 in the ADC of the first embodiment or the shared operational amplifier 37N of the second mode in the ADC of the second embodiment. The configuration other than the shared operational amplifier is the same as that of the first or second embodiment.

  As shown in FIG. 13, in addition to the configuration of the differential amplifier OP2 shown in FIG. 5, NMOS transistors Q8 and Q9 are further added.

  The NMOS transistor Q8 is provided in parallel with the NMOS transistors Q1 and Q2 between the nodes N32 and N30, and the NMOS transistor Q9 is provided in parallel with the NMOS transistors Q3 and Q4 between the nodes N31 and N30. That is, the differential amplifier OP11 has a 6-input configuration having three differential pairs.

  The NMOS transistors Q8 and Q9 are set as the surplus transistor portions 15 and 16, and the gates of the NMOS transistors Q8 and Q9 are grounded to be fixed in a completely off state (completely inoperative state).

  As a result, the differential amplifier OP11 becomes a circuit equivalent to the differential amplifier OP2 shown in FIG. 5. As a four-input differential amplifier, the shared operational amplifier 37 according to the second embodiment of the first embodiment or the second embodiment and The common operational amplifier 37N can be used without any trouble.

(Second aspect)
FIG. 14 is a circuit diagram showing a circuit configuration of a differential amplifier constituting the preamplifier portion of the shared operational amplifier according to the third embodiment. The differential amplifier OP12 which is the second mode of the third embodiment is the shared operational amplifier 37 in the pipeline type ADC of the first embodiment or the shared operational amplifier 37P of the first mode in the pipeline type ADC of the second embodiment. Used. The configuration other than the shared operational amplifier is the same as in the first and second embodiments.

  As shown in FIG. 14, in addition to the configuration of the differential amplifier OP3 shown in FIG. 6, the configuration further includes PMOS transistors Q18 and Q19.

  The PMOS transistor Q18 is provided in parallel with the PMOS transistors Q11 and Q12 between the nodes N34 and N50, and the PMOS transistor Q19 is provided in parallel with the PMOS transistors Q13 and Q14 between the nodes N33 and N50. That is, the differential amplifier OP12 has a 6-input configuration having three differential pairs.

  Then, the PMOS transistors Q18 and Q19 are set as the surplus transistor portions 17 and 18, and the power supply voltage Vdd is applied to the gates of the PMOS transistors Q18 and Q19 to fix them in the completely off state (completely inoperative state).

  As a result, the differential amplifier OP12 becomes a circuit equivalent to the differential amplifier OP3 shown in FIG. 6, and the common operational amplifier 37 according to the first aspect of the first and second embodiments is used as a four-input differential amplifier. The common operational amplifier 37P can be used without any trouble.

<Embodiment 4>
FIG. 15 is a circuit diagram schematically showing the operating state of the first stage portion and the shared operational amplifier in the stage circuit constituting the pipeline type ADC in the fourth embodiment. FIG. 16 is a circuit diagram schematically showing the operation state of the second stage portion of the pipeline type ADC in the fourth embodiment.

  The first stage portion 7 shown in FIG. 15 is the first stage portion 11 of the second embodiment shown in FIGS. 2 and 3, or the first and second modes of the second embodiment shown in FIGS. This corresponds to the first stage portion 13 in FIG. On the other hand, the second stage portion 8 shown in FIG. 16 is the second stage portion 12 of the second embodiment shown in FIGS. 2 and 3, or the first and second portions of the second embodiment shown in FIGS. This corresponds to the second stage portion 14 in the embodiment.

  On the other hand, the shared operational amplifier 39 has a configuration of four inputs (inn1, inp1, inn2, inp2 (first to fourth amplification input units)) and two outputs (outp, outn). Note that the input voltage inn1 and the input voltage inp1, the input voltage inn2 and the input voltage inp2, and the output voltage outp (one output voltage) and the output voltage outn (the other output voltage) are complementary to each other.

  The shared operational amplifier 39 corresponds to the shared operational amplifier 37 of the first embodiment, the shared operational amplifier 37P of the second embodiment, or the shared operational amplifier 37N. However, the shared operational amplifier 37 (37N, 37P) of the first embodiment (2) applies a fixed common voltage VCM as the first and second comparison voltages applied to two of the four inputs and outputs two outputs. However, the common operational amplifier 39 uses all four inputs as variable inputs and uses two outputs as differential outputs.

  In FIG. 15, the first stage portion 7 shows the switching state in the sample mode state. The first stage portion 7 includes a positive input / output portion 7p and a negative input / output portion 7n.

  The positive input / output part 7p (first one input / output part) of the first stage part 7 is composed of a plurality of switches SW1, SW2, SWa and capacitors 34p, 35p, and has the same internal configuration as the first stage part 11. Presents. The capacitors 34p and 35p and the nodes N1p to N3p of the positive input / output part 7p correspond to the capacitors 34 and 35 and the nodes N1 to N3 of the first stage part 11.

  Further, the positive input / output part 7p of the first stage part 7 receives the input voltage Vinp (first one-input related voltage) instead of the input voltage Vi, and the switch SW2 changes the output voltage outp of the shared operational amplifier 39. The first stage portion 11 is different from the first stage portion 11 in that the reference voltage Vrp1 is input instead of the reference voltage Vr. Further, the positive input / output part 7p is different from the first stage part 11 in that the input voltage inp1 is obtained from the node N3p (first one stage output unit) in the hold mode. Note that the input voltage inp1 obtained from the node N3p in the hold mode of the first stage portion 7 corresponds to the first one-stage output voltage related to the potential difference between the input voltage Vinp1 and the reference voltage Vrp1. That is, the input voltage inp1 is a voltage obtained by the positive input / output portion 7p based on the input voltage Vinp1.

  On the other hand, the negative input / output portion 7n (first other input / output portion) of the first stage portion 7 includes a plurality of switches SW1, SW2, SWa and capacitors 34n, 35n. The internal configuration in the negative input / output part 7n is the same as that of the positive input / output part 7p. The capacitors 34n and 35n and the nodes N1n to N3n in the negative input / output part 7n correspond to the capacitors 34p and 35p and the nodes N1p to N3p in the positive input / output part 7p.

  In addition, the input voltage Vinn (first other input related voltage) is input instead of the input voltage Vinp, the output voltage outn of the shared operational amplifier 39 is input to the node N2n via the switch SW2, and the reference voltage Vrp1 The negative input / output part 7n is different from the positive input / output part 7p in that the reference voltage Vrn1 is input instead. Further, the negative input / output part 7n is different from the positive input / output part 7p in that the input voltage inn1 is obtained from the node N3n (first other stage output part) in the hold mode. Note that the input voltage inn1 obtained from the node N3n in the hold mode of the first stage portion 7 is the first other stage output voltage related to the potential difference between the input voltage Vinn1 and the reference voltage Vrn1. That is, the input voltage inn1 is a voltage obtained by the negative input / output part 7n based on the input voltage Vinn1.

  The node N3p of the positive input / output part 7p and the node N3n of the negative input / output part 7n are connected via the switch SWi. The switch SWi is turned on / off at the same timing as the switch SW1.

  When the switch SWi and the switch SWa are turned on in the sample mode of the first stage portion 7, the node N3p and the node N3n can be reset to the common voltage VCM. That is, the switch SWi and the switch SWa function as first reset means.

  Further, in the hold mode, the voltage obtained from the node N3p is input as the input voltage inp1 to the first positive input (second amplification input unit) of the common operational amplifier 39, and the voltage obtained from the node N3n is shared as the input voltage inn1. This is input to the first negative input (first amplification input unit) of the operational amplifier 39. Note that the connection between the node N3p (N3n) and the first positive input (first negative input) of the shared operational amplifier 39 may be always electrically connected as in the first embodiment (see FIG. 2), or implemented. As in the second embodiment (see FIG. 11), a configuration in which connection is selectively made through the switch SWc may be adopted.

  The input voltage Vinp and the input voltage Vinn mean a differential output obtained from a preceding circuit such as the sample hold unit 10. Reference voltages Vrp1 and Vrn1 mean differential reference voltages output from a first stage AD / DA conversion part having the same configuration as the first stage AD / DA conversion part 93 shown in FIG. That is, the reference voltages Vrp1 and Vrn1 correspond to voltages obtained by D / A converting differential conversion data corresponding to the conversion data D1 <1: 0> from the first stage AD / DA conversion part.

  On the other hand, in FIG. 16, the second stage portion 8 shows a switching state in the hold mode. The second stage portion 8 includes a positive input / output portion 8p and a positive input / output portion 8p.

  The positive input / output portion 8p of the second stage portion 8 is composed of a plurality of switches SW1, SW2, SWb and capacitors 44p, 45p, and has the same internal configuration as the second stage portion 12. The capacitors 44p and 45p and the nodes N6p to N8p of the positive input / output part 8p correspond to the capacitors 44 and 45 and the nodes N6 to N8 of the second stage part 12.

  Further, the output voltage outp of the shared operational amplifier 39 is input to the nodes N6p and N7p via the switch SW1, the point input to the node N6P via the switch SW2, and the reference voltage Vrp2 instead of the reference voltage Vr. The positive input / output part 8p is different from the second stage part 12 in that it is input. The output voltage outp at the time of sampling of the second stage portion 8 corresponds to the positive output of the remainder output ST1 (one remainder output ST1).

  Further, the positive input / output portion 8p applies the input voltage inp2 obtained from the node N8p (second one stage output unit) to the second positive input (fourth amplification input unit) of the shared operational amplifier 39 in the hold mode. This is different from the second stage portion 12 in that respect. Note that the input voltage inp2 obtained from the node N8p in the hold mode of the first stage portion 8 corresponds to a second one-stage output voltage related to the potential difference between the input voltage Vinp2 and the reference voltage Vrp2. That is, the input voltage inp2 is a voltage obtained by the positive input / output portion 8p based on the input voltage Vinp2.

  On the other hand, the negative input / output part 8n of the second stage part 8 is composed of a plurality of switches SW1, SW2, SWb and capacitors 44n, 45n. The internal configuration in the positive input / output part 8p is the same as that of the positive input / output part 8p. The capacitors 44n and 45n and the nodes N6n to N8n of the shared operational amplifier 37N correspond to the capacitors 44p and 45p and the nodes N6p to N8p of the positive input / output part 8p.

  However, the positive input / output part 8p is different from the positive input / output part 8p in that the output voltage outn is input instead of the output voltage outp and the reference voltage Vrn2 is input instead of the reference voltage Vrp2. The output voltage outn at the time of sampling of the second stage portion 8 corresponds to a negative output of the remainder output ST1 (the other remainder output ST1).

  Further, the positive input / output portion 8n applies the input voltage inn2 obtained from the node N8n (second second stage output unit) to the second negative input (third amplification input unit) of the shared operational amplifier 39 in the hold mode. . Note that the input voltage inn2 obtained from the node N8n in the hold mode of the second stage portion 8 corresponds to the second other stage output voltage related to the potential difference between the input voltage Vinn2 and the reference voltage Vrn2. That is, the input voltage inn2 is a voltage obtained by the negative input / output portion 8n based on the input voltage Vinn2.

  The node N8p of the positive input / output part 8p and the node N8n of the negative input / output part 8n are connected through the switch SWj. The switch SWj is turned on / off at the same timing as the switch SW1.

  When the switch SWj and the switch SWb are turned on in the sample mode of the second stage portion 8, the nodes N8p and N8n can be reset to the common voltage VCM. That is, the switch SWj and the switch SWb function as second reset means.

  Further, in the hold mode, the voltage obtained from the node N8p is input to the second positive input (fourth amplification input unit) of the common operational amplifier 39 as the input voltage inp2, and the voltage obtained from the node N8n is shared as the input voltage inn2. This is input to the second negative input (third amplification input unit) of the operational amplifier 39. Note that the connection between the node N8p (N8n) and the second positive input (second negative input) of the shared operational amplifier 39 may be always electrically connected as in the first embodiment (see FIG. 2) or may be implemented. As in the second embodiment (see FIG. 11), a configuration in which connection is selectively made via the switch SWd may be adopted.

  The reference voltages Vrp2 and Vrn2 mean differential reference voltages output from the first stage AD / DA conversion part having the same configuration as the second stage AD / DA conversion part 94 shown in FIG. That is, the reference voltages Vrp2 and Vrn2 correspond to voltages obtained by D / A converting differential conversion data corresponding to the conversion data D2 <1: 0> from the second stage AD / DA conversion part.

  15 and 16 show the first state (when the first stage portion 7 is in the sample mode and the second stage portion 8 is in the hold mode).

  In the first state, all of the plurality of switches SW1 and the switches SWb and SWi in the first stage portion 7 are turned on, and all of the plurality of switches SW2 are turned off. On the other hand, all of the plurality of switches SW1 and the switches SWb and SWj in the second stage portion 8 are turned off, and all of the plurality of switches SW2 are turned on.

  Therefore, in the first state, as in the first to third embodiments, the first stage portion 7 performs the operation in the sample mode state, and the second stage portion 8 performs the operation in the hold mode state. .

  However, in the first stage portion 7, the charges accumulated on the node N3p side of the capacitors 34p and 35p and the charges accumulated on the node N3n of the capacitors 34n and 35n are complementary to each other.

  The positive input / output portion 7p and the positive input / output portion 8p receive the output voltage outp as a feedback input from the common operational amplifier 39 via the switch SW2, and the negative input / output portion 7n and the negative input / output portion 8n pass through the switch SW2. An output voltage outn is received as a feedback input.

  Although not shown, the pipeline type ADC of the fourth embodiment is in the second state (the first stage portion 7 is in the hold mode and the second stage portion 8 is in the sample mode). Is executed in the same way as

  At this time, all of the plurality of switches SW1 and the switches SWb and SWi in the first stage portion 7 are turned off, and the plurality of switches SW2 are turned on. On the other hand, all the plurality of switches SW1 and the switches SWb and SWj in the second stage portion 8 are turned on, and all the plurality of switches SW2 are turned off.

  When the first stage portion 7 is in the hold mode, the shared operational amplifier 39 amplifies the potential difference between the input voltage inn1 and the input voltage inp1, and outputs the output voltage outp as one remainder output ST1 and the other as the remainder output ST1. The voltage outn is output. That is, the shared operational amplifier 39 uses the input voltage inp1 instead of the common voltage VCM as the first comparison voltage input to the first positive input.

  Similarly, when the second stage portion 8 is in the hold mode, the shared operational amplifier 39 amplifies the potential difference between the input voltage inn2 and the input voltage inp2, and outputs the output voltage outp as one remainder output ST2, and the other remainder output ST2 Output voltage outn. That is, the shared operational amplifier 39 uses the input voltage inp2 instead of the common voltage VCM as the second comparison voltage input to the second positive input.

  As described above, the pipeline type ADC of the fourth embodiment is similar to the first to third embodiments by sharing the common operational amplifier 39 between the first stage portion 7 and the second stage portion 8. Low power consumption and a small layout area can be achieved, and high A / D conversion accuracy can be exhibited.

  In addition, since the input amplitude can be doubled by fully utilizing the 4-input 2-output of the shared operational amplifier 39, the amplification operation is performed with high accuracy even at the time of low voltage operation where DC bias design is difficult. There is an effect.

It is a block diagram which shows the structure of the pipeline type ADC of the vertical type shared amplifier structure which is Embodiment 1 of this invention. FIG. 2 is a circuit diagram schematically showing an operation state (first state) of the stage circuit shown in FIG. 1. FIG. 2 is a circuit diagram schematically showing an operation state (second state) of the stage circuit shown in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an internal configuration example of a preamplifier portion of the shared operational amplifier illustrated in FIG. 1. FIG. 6 is a circuit diagram schematically showing a configuration of a stage circuit which is a first mode in the second embodiment. FIG. 6 is a circuit diagram schematically showing a configuration of a stage circuit which is a second mode in the second embodiment. 6 is a circuit diagram showing a circuit configuration of a first aspect of a differential amplifier in a preamplifier portion of a shared operational amplifier according to a third embodiment; FIG. FIG. 6 is a circuit diagram showing a circuit configuration of a second aspect of a differential amplifier in a preamplifier part of a shared operational amplifier according to a third embodiment. FIG. 10 is a circuit diagram schematically showing an operation state of a first stage portion and a shared operational amplifier in a stage circuit constituting an ADC in Embodiment 4. FIG. 10 is a circuit diagram schematically showing an operation state of a second stage part of an ADC in the fourth embodiment. It is a block diagram which shows the structure of the conventional pipeline type ADC. It is explanatory drawing which shows typically the internal structure of the stage circuit shown in FIG. FIG. 18 is a circuit diagram showing an actual circuit configuration of the stage circuit shown in FIG. 17. FIG. 18 is a circuit diagram showing an actual circuit configuration of the stage circuit shown in FIG. 17. It is a circuit diagram which shows the operation state of two stage circuits connected in series with each other. It is a circuit diagram which shows the operation state of two stage circuits connected in series with each other. It is a block diagram which shows the structure of the pipeline type ADC of the conventional vertical type shared amplifier structure. FIG. 24 is a circuit diagram showing an actual circuit configuration of the stage circuit shown in FIG. 23. FIG. 24 is a circuit diagram schematically showing an operation state of the stage circuit shown in FIG. 23. FIG. 24 is a circuit diagram schematically showing an operation state of the stage circuit shown in FIG. 23. It is explanatory drawing which shows typically the offset increase phenomenon by "Memory Effect".

Explanation of symbols

  1, 1A, 2 stage circuit, 5 3-bit DAC, 6 error correction circuit, 10 sample hold unit (S / H), 7, 11, 13 first stage portion, 8, 12, 14 second stage portion, 37, 37N, 37P, 39 Shared operational amplifier.

Claims (6)

A pipeline type ADC having a plurality of stage portions each capable of performing partial A / D conversion processing independently at each stage within a predetermined range,
The pipeline type ADC has at least one stage circuit including first and second stage portions included in the plurality of stage portions,
The at least one stage circuit comprises:
A first stage portion that samples an input-related voltage related to an analog input in the sample mode, and outputs a first stage output voltage based on the input-related voltage from the first stage output section that is the output section in the hold mode; ,
A second stage portion that samples the first remainder output in the sample mode, and outputs a second stage output voltage based on the first remainder output from the second stage output section that is the output section in the hold mode;
Having first to fourth amplification input sections, amplifying the potential difference between the first and second amplification input sections and the potential difference of the third and fourth amplification input sections, and generating an output voltage from the amplification output section; The first amplification input section is connected to the first stage output section in the hold mode of the first stage portion, and the third amplification input section is a hold of the second stage section. It is connected to the second stage output unit at the time of mode, and the first and second comparison voltages are applied to the second and fourth amplification input units,
Between the first and second stage portions, the sample mode and the hold mode are alternately executed without overlapping each other,
The shared amplifier obtains the output voltage as the first remainder output in the hold mode of the first stage portion, obtains the output voltage as a second remainder output in the hold mode of the second stage portion,
The at least one stage circuit comprises:
A first reset means for initializing a potential of the first amplification input unit to a reset voltage in the sample mode of the first stage portion;
A second reset unit that initializes the potential of the third amplification input unit to the reset voltage in the sample mode of the second stage portion;
Pipeline type ADC. The pipeline type ADC according to claim 1,
The reset voltage is the same voltage as the first and second comparison voltages,
The first stage output unit and the first amplification input unit are always electrically connected, and the second stage output unit and the third amplification input unit are always electrically connected,
The first reset means includes means provided in the first stage portion, and initializes the potential of the first stage output section to the reset voltage in the sample mode of the first stage portion,
The second reset unit includes a unit provided in the second stage portion, and initializes the potential of the second stage output unit to the reset voltage in the sample mode of the second stage portion.
Pipeline type ADC. The pipeline type ADC according to claim 1,
The shared amplifier includes a shared amplifier in which a differential input portion having the first to fourth amplification input portions is configured by a P-type transistor,
The reset voltage includes a power supply voltage,
Pipeline type ADC. The pipeline type ADC according to claim 1,
The shared amplifier includes a shared amplifier in which a differential input portion having the first to fourth amplification input portions is configured by an N-type transistor,
The reset voltage includes a ground level;
Pipeline type ADC. The pipeline type ADC according to any one of claims 1 to 4,
The shared amplifier includes a multi-input shared amplifier having a multi-input differential input unit having a differential input unit of 5 or more,
In the multi-input shared amplifier, a surplus portion that is not used as the first to fourth amplification input units in the multi-input differential input unit is fixed in a completely non-operating state.
Pipeline type ADC. The pipeline type ADC according to any one of claims 1 to 5,
The input related voltages include one and the other input related voltages that are complementary to each other;
The first remainder output includes a first one remainder output and a first other remainder output that are complementary to each other;
The second remainder output includes a second one remainder output and a second other remainder output that are complementary to each other;
The output voltage of the shared amplifier includes one and the other output voltages complementary to each other;
The first stage portion includes a first one input / output portion and a first other input / output portion, and the first stage output portion includes a first one stage output portion and a first other stage output portion. ,
The first one input / output portion samples the first one input related voltage in the sample mode, and outputs the first one stage output voltage based on the first one input related voltage in the output mode in the hold mode. Output from the first one stage output unit,
The first other input / output portion samples the first other input related voltage in the sample mode, and outputs a first other stage output signal based on the first other input related voltage in the output mode in the hold mode. Output from the first other stage output unit,
The second stage portion includes a second one input / output portion and a second other input / output portion,
The second one input / output portion samples the first one remainder output in the sample mode, and outputs the second one stage output voltage based on the first one remainder output in the hold mode as the output section. Output from the second one stage output unit,
The second other input / output portion samples the first other remainder output in the sample mode, and outputs the second other stage output differential voltage based on the first other remainder output in the hold mode. Output from the second other stage output unit,
The first reset means includes reset means for initializing the potentials of the first one stage output section and the first other stage output section to the reset voltage in the sample mode of the first stage portion. 2 reset means includes a reset means for initializing the potentials of the second one stage output section and the second other stage output section to the reset voltage in the sample mode of the second stage portion,
In the shared amplifier, the first amplification input section is connected to the first other stage output section in the hold mode of the first stage portion, and the second amplification input section is connected to the hold mode of the first stage section. Sometimes connected to the first one stage output section, the third amplification input section is connected to the second other stage output section in the hold mode of the second stage portion, and the fourth amplification input section is connected Connected to the second one stage output section during the hold mode of the second stage portion;
The first comparison voltage includes the first one-stage output voltage obtained from the first one-stage output unit in the hold mode of the first stage portion, and the second comparison voltage is the first comparison voltage. Including the second one-stage output voltage obtained from the second one-stage output unit in a two-stage part hold mode;
The shared amplifier obtains the one and other output voltages as the first one remainder output and the first other remainder output in the hold mode of the first stage portion, and the share amplifier in the hold mode of the second stage portion. Obtaining said one and other output voltages as a second one remainder output and a second other remainder output,
Pipeline type ADC.

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