JP4937498B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor power device that is suitable for a high power consumption type device such as a lighting device or an air conditioner and is used for high withstand voltage and large current at high temperature.

  Since silicon carbide (silicon carbide, SiC) is a semiconductor having a larger band gap than silicon (Si), it has a high withstand voltage and is a semiconductor that is stable even at high temperatures. Semiconductor devices formed in this way are expected to be applied to next-generation power devices and high-temperature devices. In general, a power device is a generic term for devices that perform conversion and control of large power, and is called a power diode, a power transistor, or the like. Applications of power devices include, for example, transistors and diodes that are placed in inverter control units in devices such as vacuum cleaners, washing machines, refrigerators, fluorescent lamps, and air conditioners. It is thought to do.

  In general, for these uses, a plurality of semiconductor chips are connected by wiring according to the use and purpose, and are placed in one package to be modularized. For example, wiring is formed on the substrate so as to constitute a circuit corresponding to the application, and each semiconductor chip is attached on the substrate, whereby a desired circuit is constituted by the semiconductor chip and the wiring. Here, as a conventional example of a semiconductor power device circuit, an inverter circuit of a fluorescent lamp using a Schottky diode and a MOS field effect transistor will be described.

  FIG. 18 is a cross-sectional view showing the structure of a conventional bulb-type fluorescent lamp device 250 disclosed in PCT application JP00 / 02054. As shown in the figure, the fluorescent lamp device 250 includes a fluorescent lamp 201 formed by connecting three substantially U-shaped arc tubes by a bridge, and an element such as a semiconductor chip for lighting the fluorescent lamp 201. Including a lighting circuit 202, a cover 203 that houses the lighting circuit 202, a base 204 attached to the tip of the cover 203, and a globe 205 that surrounds the fluorescent lamp 201.

  FIG. 19 is an electric circuit diagram showing the configuration of the lighting circuit 202 in the fluorescent lamp device 250. As shown in the figure, the lighting circuit 202 includes a line filter circuit 212, a rectifier circuit 213, a power supply smoothing capacitor 214, an inverter circuit 215, a choke coil 207, and a resonance capacitor 216. It is configured. The inverter circuit 215 includes an inverter driving IC 217, FETs 208 and 209 that are switching elements driven by the inverter driving IC 217, and an inverter capacitor 218. The fluorescent lamp 201 is arranged in parallel with the resonance capacitor 216, and is configured to emit fluorescence by flowing a discharge current between the electrodes 221 and 222 at both ends in the fluorescent lamp 201.

  In this conventional fluorescent lamp device 250, after each circuit is formed as an individual external component, a line filter circuit 212, a power source smoothing capacitor 214, a choke coil 207, A resonance capacitor 216, an inverter capacitor 218, and the like are disposed, and a rectifier circuit 213, an inverter driving IC 217, FETs 208, 209, and the like are disposed on the back surface 206b of the circuit board 206. That is, components with relatively low heat resistance, such as the rectifier circuit 213, the inverter driving IC 217, and the FETs 208 and 209 in the inverter circuit 215, are arranged on a different surface and away from the choke coil 207 that is a heat generating component. Yes.

  Here, since the current flowing through the electrodes 221 and 222 of the fluorescent lamp 202 is a large current in order to ensure the brightness of the lamp, the FETs 208 and 209 disposed in the inverter circuit 215 include pMOSFETs and nMOSFETs that are power transistors. Is used. In addition, a power diode is used as a diode arranged in the rectifier circuit 213. The basic function of the power device including the power transistor and the power diode is an AC-DC-AC converter that converts from 50/60 Hz to, for example, 50 kHz. As such power transistors and power diodes, power devices provided on the SiC substrate as described above are often employed.

  However, the conventional fluorescent lamp device has the following problems.

  In the conventional fluorescent lamp device 250, solder or the like is usually used to attach a transistor or a diode to a substrate. However, since this solder does not have durability at high temperatures, it cannot be placed near a fluorescent lamp that generates a large amount of heat, for example, and the size of the entire fluorescent lamp system increases.

  The lighting circuit 202 is formed by mounting individual components on the circuit board 206 and connecting them to each other by wiring. However, in order to avoid a high temperature for a component having low heat resistance, the lighting circuit 202 has a severe position. There are some restrictions. As a result, the lighting circuit 202 itself has to be large in size although various positional relationships among the components are devised.

  Here, as described above, it is conceivable that the semiconductor device provided on the SiC substrate is placed in a device that is exposed to a high temperature, such as a lighting circuit, using the high heat resistance of the SiC substrate. However, since power transistors and power diodes provided on a conventional SiC substrate are discrete devices, it is difficult to prevent the lighting circuit 202 itself from becoming large.

  The object of the present invention is to arrange the active element and / or the passive element on a compound semiconductor substrate having high heat resistance so that the operating temperature and space restrictions are placed under severe conditions. To provide a semiconductor device suitable for the above.

  A first semiconductor device of the present invention includes a compound semiconductor layer provided on a substrate, at least one first semiconductor layer provided on the compound semiconductor layer and functioning as a carrier traveling region, and a high concentration An active region including at least one second semiconductor layer containing carrier impurities and having a thickness smaller than that of the first semiconductor layer and capable of carrier distribution by a quantum effect, and the active region A plurality of active elements provided on the region.

  With this structure, when a voltage is applied so that the active element is turned on, carriers in the second semiconductor layer spread to the first semiconductor layer and carriers are distributed throughout the active region. Since the impurity concentration in the first semiconductor layer is low and the impurity ion scattering in the first semiconductor layer is reduced, a particularly high carrier traveling speed is obtained when a MISFET or a diode is provided on the active region. It is done. In addition, although the average impurity concentration in the active region is not low, the entire active region is depleted in the off state, and no carriers exist in the active region. Therefore, the first semiconductor layer having a low impurity concentration The withstand voltage is defined, and a high withstand voltage value is obtained in the entire active region.

  That is, since a high-functional active element integrated on the compound semiconductor layer can be obtained, the semiconductor device can be disposed at a desired site without using solder even when used at a high temperature, for example. Therefore, the degree of freedom of arrangement of the semiconductor device in the equipment is improved, and the equipment itself using the semiconductor device can be downsized.

  The plurality of active elements include a MISFET having the first semiconductor layer immediately below the gate insulating film, so that the impurity concentration of the first semiconductor layer is low. The number of charges trapped in the vicinity of the interface between the film and the active region is also reduced, and the disturbing effect on the traveling of carriers by the trapped charges is reduced. Thus, an integrated semiconductor device having a MISFET with higher channel mobility is obtained.

  As the active region, a carrier active in the second semiconductor layer is formed on the first active region in which the carrier impurity in the second semiconductor layer is a first conductivity type impurity and on the first active region. A second active region in which the impurity is a second conductivity type impurity, a part of the second active region is removed, and the first active region is exposed in the uppermost layer of the substrate, In the portion where the first active region is exposed, a second conductivity type MISFET is provided, while in the second active region, the first conductivity type MISFET is provided, whereby a pMOSFET is provided. And a semiconductor device functioning as a CMOS device including nMOSFETs.

  By making the compound semiconductor layer one semiconductor layer selected from a SiC layer, a GaN layer, an InP layer, an InGaAs layer, and an InGaPN layer, the characteristics of these compound semiconductor layers can be utilized to achieve particularly high heat resistance. A semiconductor device having high pressure resistance is obtained.

  A second semiconductor device of the present invention includes a semiconductor layer selected from a SiC layer, a GaN layer, an InP layer, an InGaAs layer, and an InGaPN layer provided on a substrate, and an inductor provided on the semiconductor layer. And.

  This makes it possible to provide an inductor having a fine pattern using the high heat resistance and high thermal conductivity of the SiC layer, GaN layer, InP layer, InGaAs layer, and InGaPN layer, and it is possible to provide a large area in a small area. An inductor having an inductance can be provided.

  The semiconductor layer includes at least one first semiconductor layer functioning as a carrier traveling region and a carrier impurity having a high concentration, and is thinner than the first semiconductor layer and capable of carrier distribution by a quantum effect. At least one second semiconductor layer is alternately stacked, and the semiconductor device further includes a plurality of active elements provided on the semiconductor layer, whereby the first semiconductor device is also formed on the semiconductor layer. The highly functional semiconductor device provided above is obtained.

  A circuit including a MISFET provided on the semiconductor layer; a rectifier circuit including a Schottky diode provided on the active region of the semiconductor layer; and a capacitor provided on the semiconductor layer. By functioning as a lighting circuit of a fluorescent lamp device, a semiconductor device that is extremely miniaturized and integrated on a common substrate can be placed in a high-temperature and narrow space of the fluorescent lamp.

According to the first semiconductor device of the present invention, on the compound semiconductor layer of the substrate, at least one first semiconductor layer functioning as a carrier traveling region, and a carrier effect due to a quantum effect including high-concentration carrier impurities. Since an active region configured by alternately stacking at least one second semiconductor layer capable of distribution is provided and a plurality of active elements are provided on the active region, high carrier running characteristics and pressure resistance Thus, it is possible to provide a semiconductor device in which active elements having the above are integrated on a common substrate.

  According to the second semiconductor device of the present invention, since the inductor is provided on the SiC layer or InGaAs layer of the substrate, the high heat resistance and high thermal conductivity of the SiC substrate, InP substrate or InGaPN substrate are utilized. Thus, an inductor having a fine pattern can be provided, and an inductor having a large inductance in a small area can be provided.

  Hereinafter, some embodiments of the present invention will be described.

(First embodiment)
FIG. 1 is a cross-sectional view of an integrated semiconductor device in which a Schottky diode, a MOSFET, a capacitor, and an inductor are integrated on a SiC substrate according to the first embodiment of the present invention.

The SiC substrate 10, which is a 4H—SiC substrate, includes an n-type first active region 12 doped with nitrogen having an average concentration of about 1 × 10 ¹⁷ atoms · cm ⁻³ , and an average concentration of about 1 × 10 ^17. A p-type second active region 13 doped with aluminum of atoms · cm ⁻³ is provided in order from below, and a part of the second active region 13 is removed to form a first on the substrate. A part of the active region 12 is exposed. An element isolation region 11 in which a silicon oxide film is embedded in a trench is provided for partitioning each active region 12 and 13 for each element.

Here, as shown enlarged below in FIG. 1, the first active region 12 is an n-type doped layer having a thickness of about 10 nm containing nitrogen at a high concentration (for example, 1 × 10 ¹⁸ atoms · cm ⁻³ ). 12a and undoped layers 12b made of undoped 4H—SiC single crystal and having a thickness of about 50 nm are alternately stacked to form 20 layers each. On the other hand, the second active region 13 is formed of a p-type doped layer 13a having a thickness of about 10 nm containing aluminum at a high concentration (for example, 1 × 10 ¹⁸ atoms · cm ⁻³ ) and an undoped 4H—SiC single crystal. The undoped layers 13b of about 50 nm are alternately stacked to form 20 layers each. The n-type doped layer 12a and the p-type doped layer 13a are both thin enough to allow the carriers to ooze into the undoped layers 12b and 13b by the quantum effect.

  Further, a Schottky diode 20 (rectifying element) and a pMOSFET 30 (switching element) are provided on a portion of the SiC substrate 10 where the first active region 12 is exposed. An nMOSFET 40 (switching element), a capacitor 50 (capacitance element), and an inductor 60 (inductive element) are provided on the portion where the second active region 13 is present at the top.

The Schottky diode 20 includes a Schottky electrode 21 made of nickel (Ni) in Schottky contact with the first active region 12 and a high concentration of nitrogen (for example, about 1 × 10 ¹⁸ atoms · The electrode lead-out layer 22 formed by injecting cm ⁻³ ) and the ohmic electrode 23 made of nickel (Ni) in ohmic contact with the electrode lead-out layer 22 are provided.

The pMOSFET 30 includes a gate insulating film 31 made of SiO ₂ formed on the first active region 12, a gate electrode 32 made of a Ni alloy film formed on the gate insulating film 31, and a first active region. A p-type source region 33a and drain region 33b formed by implanting aluminum having a concentration of 1 × 10 ¹⁸ cm ⁻³ into regions located on both sides of the gate electrode 32 in the region 12, and the source region 33a and drain region A source electrode 34 and a drain electrode 35 made of a Ni alloy film are provided in ohmic contact with 43b, respectively.

The nMOSFET 40 includes a gate insulating film 41 made of SiO ₂ formed on the second active region 13, a gate electrode 42 made of a Ni alloy film formed on the gate insulating film 41, and a second active region. An n-type source region 43a and drain region 43b formed by implanting nitrogen having a concentration of 1 × 10 ¹⁸ cm ⁻³ into regions located on both sides of the gate electrode 42 in the region 13, and the source region 43a and drain region A source electrode 44 and a drain electrode 45 made of a Ni alloy film are provided in ohmic contact with 43b, respectively.

  The capacitor 50 includes a base insulating film 51 made of a SiN film provided on the second active region 13, a lower electrode 52 made of a platinum (Pt) film provided on the base insulating film 51, and A capacitive insulating film 53 made of a high dielectric film such as BST provided on the lower electrode 52 and an upper electrode made of a platinum (Pt) film facing the lower electrode 52 with the capacitive insulating film 53 interposed therebetween are provided. ing.

  The inductor 60 includes a dielectric film 61 made of a SiN film provided on the first active region 12 and a conductor film 62 made of a spiral Cu film formed on the dielectric film 61. I have. Here, the width of the conductor film 62 is about 9 μm, the thickness is about 4 μm, and the gap between the conductor films 62 is about 4 μm. However, since the SiC substrate 10 has high heat resistance and high thermal conductivity, the conductor film 62 can be miniaturized depending on the amount of current, and a finer pattern, for example, a width of 1 to 2 μm and a gap However, a shape of about 1 to 2 μm is also possible.

  An interlayer insulating film 70 made of a silicon oxide film is formed on the substrate, and a wiring 72 made of an aluminum alloy film, a Cu alloy film, or the like is provided on the interlayer insulating film 70. The conductor portions of the elements 20, 30, 40, 50, 60 are connected to the wiring 72 through contacts 71 made of an aluminum alloy film or the like that fills the contact holes formed in the interlayer insulating film 70.

  FIG. 2 is a plan view schematically showing a planar pattern of the semiconductor device in the present embodiment. As shown in the figure, a rectifier circuit including four Schottky diodes 20, an inverter circuit including pMOSFET 30 and nMOSFET 40, a capacitor 50, and an inductor 60 are connected by a wiring 72. A control signal is input to the gate electrodes 32 and 42 of the pMOSFET 30 and the nMOSFET 40 of the inverter circuit via the pad 75. Note that a smoothing capacitor (corresponding to the capacitor 214 shown in FIG. 19) may be inserted between the rectifier circuit and the inverter circuit.

  According to the semiconductor device of the present embodiment, since the Schottky diode 20, the pMOSFET 30, the nMOSFET 40, the capacitor 50, and the inductor 60 are integrated on the common SiC substrate 10, it has high power and high withstand voltage characteristics, a vacuum cleaner, Semiconductor devices suitable for devices such as washing machines, refrigerators, fluorescent lamps, and air conditioners can be provided. In particular, by mounting the inductor 60 that has been externally attached by soldering together with other elements on the SiC substrate 10 in the past, a semiconductor device can be freely placed in a limited space within the equipment without being restricted by temperature. Can be arranged. In addition, by integrating many elements on a common SiC substrate, it is possible to eliminate the trouble of parts assembly and to reduce the manufacturing cost of the semiconductor device. In addition, it is known that an element having an active region in which a δ-doped layer and a lightly doped layer are stacked can improve yield, and cost can be reduced by improving yield.

In particular, when a semiconductor device is applied to a device that handles a high-frequency signal on the order of GHz, it is preferable that the dielectric film 61 of the inductor 60 is composed of a BCB film (benzocyclobutene film). A BCB film | membrane means the film | membrane which contains BCB obtained by baking after melt | dissolving a BCB-DVS monomer in a solvent, and apply | coating. The BCB film has a characteristic that the relative dielectric constant is as small as about 2.7, and a thick film of about 30 μm can be easily formed by one application. Further, since the tan δ of the BCB film is about 0.006 at 60 GHz, which is about an order of magnitude smaller than SiO ₂ , the BCB film can particularly exhibit excellent characteristics as a dielectric film constituting an inductor or a microstrip line. .

  In the present embodiment, since the first active region 12 and the second active region 13 having the structure shown in the lower part of FIG. 1 are provided on the SiC substrate 10, the following remarkable effects are obtained for each element. Can be demonstrated.

  First, in the Schottky diode 20, when a forward bias is applied to the Schottky diode 20, the potential of the first active region 12 is increased, and the energy level of the conduction band edge in the n-type doped layer 12a and the undoped layer 12b is increased. Rises. At this time, since the carriers in the n-type doped layer 12a also penetrate into the undoped layer 12b due to the quantum effect, the Schottky electrode can be easily passed through both the n-type doped layer 12a and the undoped layer 12b in the first active region 12. A current flows through 21. That is, not only the n-type doped layer 12a of the first active region 12 but also the undoped layer 12b functions as a carrier traveling region. At this time, since the impurity concentration in the undoped layer 12b is low, the impurity scattering is reduced in the undoped layer 12b. Therefore, the resistance value can be kept small, and low power consumption and large current can be realized. On the other hand, when a reverse bias is applied to the Schottky diode 20, a depletion layer spreads from the undoped layer 12b of the first active region 12 to the n-type doped layer 12a, and the entire first active region 12 is easily depleted. Therefore, a large withstand voltage value can be obtained. Therefore, it is possible to realize a high-power and high-withstand-voltage power diode with low on-resistance. In particular, by making this power diode a horizontal structure, it becomes easy to integrate the power diode together with a power MOSFET on a common SiC substrate.

  Next, in the pMOSFET 30, in the inverted state where a driving voltage is applied to the gate electrode 32 and the carriers travel, the positive voltage is applied to the end of the valence end bent upward by the potential eV corresponding to the applied voltage V. The holes gather, and the holes travel through the portion serving as the channel layer of the first active region 12 according to the potential difference between the source region 33a and the drain region 33b. At this time, since the concentration of carriers (here, holes) is distributed so as to be higher and lower as it goes directly below the gate insulating film 31, it is actually an undoped region that is immediately below the gate insulating film 31. Layer 12b will occupy most of the channel layer. However, since the undoped layer 12b is hardly doped with impurities, impurity ion scattering with respect to carriers traveling through the undoped layer 12b is reduced. That is, high channel mobility can be obtained by reducing impurity ion scattering that hinders carrier travel in the first active region 12.

  In addition, since the gate insulating film of the MOSFET is an oxide film formed by heat treatment of the substrate in most cases, the positive charge trapped in the gate insulating film 31 formed by thermally oxidizing the undoped layer 12b is Few. Accordingly, since the holes flowing in the uppermost undoped layer 12b in the first active region 12 are hardly affected by the running interference due to the interaction with the charges in the gate insulating film 31, the channel mobility is improves. In addition, when no driving voltage is applied to the gate electrode 32, even if a high voltage is applied between the source region 33a and the drain region 33b, the depletion layer becomes an undoped layer as in the case of the Schottky diode 20. Since it easily spreads from 12b to the n-type doped layer 12a, a high breakdown voltage can be exhibited.

  That is, it can exhibit excellent characteristics such as high breakdown voltage, low on-resistance, large current capacity, and high transconductance. For example, a stable drain current can be obtained without breakdown even when the drain voltage is 400 V or higher, and the breakdown voltage in an off-state MOSFET is 600 V or higher.

  In the nMOSFET 40, as in the case of the pMOSFET, electrons traveling in the channel region are hardly affected by scattering due to impurity ions in the channel region or interference due to negative charges trapped in the impurities in the gate insulating film. Therefore, it is possible to exhibit a high withstand voltage, a low on-resistance, a large current capacity, and a high transconductance characteristic.

  Next, the manufacturing process of the semiconductor device in the present embodiment will be described with reference to FIGS. 3 (a) to 5 (b). Here, FIGS. 3A to 3C are cross-sectional views showing steps from the formation of the first and second active regions to the formation of the element isolation region in the manufacturing process of the semiconductor device of the present embodiment. . 4A to 4C are cross-sectional views showing steps from the formation of the source / drain regions to the formation of the electrodes or conductor films of the elements in the manufacturing process of the semiconductor device of the present embodiment. FIGS. 5A and 5B are cross-sectional views showing the steps from the formation of the upper electrode of the capacitor to the formation of the contact hole to the conductor portion of each element in the manufacturing process of the semiconductor device of the present embodiment.

  First, in the step shown in FIG. 4A, a p-type SiC substrate 10 is prepared. In the present embodiment, as the SiC substrate 10, a 4H—SiC substrate having a principal surface whose orientation coincides with the {11-20} plane (A plane) is used. However, an SiC substrate having an orientation whose principal surface is shifted by several degrees from the (0001) plane (C plane) may be used.

Then, the SiC substrate 10 is thermally oxidized at 1100 ° C. for about 3 hours in a water vapor atmosphere bubbled with oxygen at a flow rate of 5 (l / min) to form a thermal oxide film having a thickness of about 40 nm on the surface, and then a buffer. The thermal oxide film is removed with dehydrofluoric acid (hydrofluoric acid: ammonium fluoride aqueous solution = 1: 7). Then, the SiC substrate 10 is placed in the chamber of the CVD apparatus, and the inside of the chamber is depressurized until the degree of vacuum is about 10 ⁻⁶ Pa (≈10 ⁻⁸ Torr). Next, hydrogen gas with a flow rate of 2 (l / min) and argon gas with a flow rate of 1 (l / min) are supplied as dilution gases into the chamber, the pressure in the chamber is 0.0933 MPa, and the substrate temperature is about 1600. Control at ℃. While maintaining the flow rates of hydrogen gas and argon gas at the above-described constant values, propane gas having a flow rate of 2 (ml / min) and silane gas having a flow rate of 3 (ml / min) are introduced into the chamber as source gases. . The source gas is diluted with hydrogen gas at a flow rate of 50 (ml / min). Then, nitrogen (doping gas), which is an n-type impurity, is supplied in a pulsed manner while supplying the source gas and the dilution gas in the chamber, so that n of about 10 nm in thickness is formed on the main surface of the SiC substrate 10. A type doped layer 12a (highly doped layer) is formed. Here, as the doping gas, for example, nitrogen is stored in a high-pressure cylinder, and a pulse valve is provided between the high-pressure cylinder and the doping gas supply pipe. Then, by repeatedly opening and closing the pulse valve while supplying the source gas and the dilution gas, the doping gas can be supplied in a pulse shape directly above the SiC substrate 10 in the chamber.

  When the epitaxial growth of the n-type doped layer 12a is completed, the supply of the doping gas is stopped, that is, the propane gas and the silane gas are supplied onto the SiC substrate 10 with the pulse valve completely closed. On the main surface of the SiC substrate 10, an undoped layer 12b (lightly doped layer) made of undoped SiC single crystal and having a thickness of about 50 nm is epitaxially grown.

In this manner, the n-type doped layer 12a is formed by simultaneously opening and closing the pulse valve and introducing the doping gas while supplying the source gas, and without supplying the doping gas with the pulse valve closed. The first active region 12 formed by alternately stacking the n-type doped layers 12a and the undoped layers 12b for 20 periods is formed by repeating the formation of the undoped layer 12b only by supplying 20 times each. At this time, the undoped layer 12b is formed as the uppermost layer, and the thickness thereof is about 15 nm thicker than the other undoped layers 12b. The average nitrogen concentration in the first active region 12 is about 1 × 10 ¹⁷ atoms · cm ⁻³ , and the total thickness after the thermal oxidation of the first active region 12 is 1100 nm.

Next, the source gas and the dilution gas are left as they are, and the doping gas is switched to a gas containing aluminum as a p-type impurity (doping gas), thereby forming a p-type film having a thickness of about 10 nm on the first active region 12. A type doped layer 13a (highly doped layer) is formed. Note that after the formation of the first active region 12, the supply of the source gas and the dilution gas is continued for a while to form a relatively thick undoped layer on the first active region 12, and then the p-type is formed. It is preferable to form the doped layer 13a. Here, as the doping gas, for example, hydrogen gas containing about 10% of trimethylaluminum (Al (CH ₃ ) ₃ is used, and the source gas is changed in the same manner as the procedure for forming the first active region 12 described above. At the same time, the p-type doped layer 13a is formed by introducing a doping gas (hydrogen gas containing trimethylaluminum) by simultaneously opening and closing the pulse valve, and the source gas without supplying the doping gas with the pulse valve closed. The second active region 13 is formed by alternately stacking the p-type doped layers 13a and the undoped layers 13b for 20 periods by repeating the formation of the undoped layer 13b only by supplying 20 times each. An undoped layer 13b is formed as the uppermost layer, and the thickness thereof is about 15 nm thicker than other undoped layers 13b. Put. Aluminum concentration of the average in the second active region 13 is about ^{1 × 10 17 atoms · cm -3} , the total thickness after completion thermal oxidation of the second active region 13 is about 1100 nm.

  Next, in the step shown in FIG. 3B, the portion of the second active region 13 where the Schottky diode 20 and the pMOSFET 30 are to be formed is removed by selective etching, so that the Schottky diode 20 and the pMOSFET 30 are formed. The first active region 12 is exposed in the region where the film is to be formed.

  Next, in the step shown in FIG. 3C, a trench for forming an element isolation region is formed in the substrate, and a silicon oxide film is buried in the trench to form the element isolation region 11.

Next, in the step shown in FIG. 4A, the electrode lead layer 22 of the Schottky diode 20 and the source region 33a and the drain region 33b of the pMOSFET 30 are formed by implanting p-type impurities (for example, aluminum ions Al +). To do. At this time, after forming an implantation mask made of a silicon oxide film or the like covering the region other than the region where the p-type impurity ions are implanted on the substrate and opening the region where the p-type impurity ions are implanted, the substrate temperature is set to 500 to 500. By heating between 800 ° C., ion implantation of aluminum ions (Al ⁺ ) or the like is performed from above the implantation mask. Further, annealing for impurity activation is performed at a temperature of 1500 ° C. for 10 minutes, whereby the electrode lead layer 22, the source region 33a, and the drain region 33b having a p-type impurity concentration of about 1 × 10 ¹⁸ atoms · cm ⁻³ are formed. Form. At this time, aluminum ions (Al ⁺ ) are implanted into the substrate in, for example, six ion implantation steps having different implantation energies. For example, the conditions for the first ion implantation are an acceleration voltage of 180 keV and a dose amount of 1.5 × 10 ¹⁴ atoms · cm ⁻² , and the conditions for the second ion implantation are an acceleration voltage of 130 keV and a dose amount of 1 × 10 ¹⁴ atoms. in · cm ^-2, the third ion implantation conditions are an acceleration voltage 110 keV, dose amount ^{5 × 10 13 atoms · cm -2} , the fourth ion implantation conditions are an acceleration voltage 100 keV, a dose of 8 × 10 ^{At 13} atoms · cm ⁻² , the condition of the fifth ion implantation is an acceleration voltage of 60 keV and a dose amount of 6 × 10 ¹³ atoms · cm ⁻² , and the condition of the sixth ion implantation is an acceleration voltage of 30 keV and a dose amount of 5 × 10 ¹³ atoms · cm ^-2 In each case, the ion implantation direction is inclined by 7 ° with respect to the normal line of the SiC substrate 10 and the implantation depth is about 0.3 μm.
It is.

Similarly, the source region 43a and the drain region 43b of the nMOSFET 40 are formed by implanting an n-type impurity (for example, nitrogen ion N +). At this time, after forming an implantation mask made of a silicon oxide film or the like covering the region other than the region for implanting n-type impurity ions and opening the region for implanting n-type impurity ions, the substrate temperature is set to 500 to 500. Heating is performed at 800 ° C., and ion implantation such as nitrogen ions (N ⁺ ) is performed from above the implantation mask. Further, annealing for impurity activation is performed at a temperature of 1500 ° C. for 10 minutes, so that the source region 43a having an implantation depth of about 0.8 μm and an n-type impurity concentration of about 1 × 10 ¹⁸ atoms · cm ⁻³ and A drain region 43b is formed.

  Next, in the step shown in FIG. 4B, after removing the implantation mask on the substrate, a SiN film having a thickness of about 0.4 μm is formed by the plasma CVD method, and then the SiN film is patterned, A base insulating film 51 and a dielectric film 61 are formed on a region where the capacitor 50 and the inductor 60 are to be formed in the two active regions 13.

  Next, in the step shown in FIG. 4C, in the MOSFET formation region, the surface portions (about approximately) of the uppermost undoped layers 12b and 13b of the first and second active regions 12 and 13 at a temperature of approximately 1100 ° C. The gate insulating films 31 and 41 made of a thermal oxide film having a thickness of about 30 nm are formed by thermally oxidizing (15 nm thickness). Next, portions of the gate insulating films 31 and 41 located above the source region 33a and the drain region 33b are removed to provide an opening, and the source electrode made of a Ni alloy film formed by a vacuum evaporation method in the opening. 34 and 44 and drain electrodes 35 and 45 are formed. At the same time, an ohmic electrode 23 made of a Ni alloy film is also formed on the electrode lead layer 22 of the Schottky diode 20. Further, annealing is performed at 1000 ° C. for 3 minutes in order to make ohmic contact between the source electrodes 34 and 44, the drain electrodes 35 and 45, and the ohmic electrode 23 and each active region 12, 13 or the electrode lead layer 22. Subsequently, a titanium (Ti) alloy film is deposited on the gate insulating films 31 and 41 to form gate electrodes 32 and 42 made of a titanium alloy film and having a gate length of about 1 μm. Also, nickel (Ni) is deposited on the region of the first active region 12 where the Schottky diode 20 is to be formed to form a Schottky electrode 21 made of nickel, and the underlying insulating film 51 of the capacitor 50 is formed. The lower electrode 52 made of platinum is formed by depositing platinum (Pt) thereon.

Next, after forming a resist film having a spiral opening in a region where the inductor 60 is to be formed, a Cu film having a thickness of about 4 μm is deposited thereon, lift-off is performed, and the dielectric film 61 is formed. The spiral conductor film 62 is left on the surface. Note that the conductor film may be made of an aluminum alloy film instead of the Cu film. In this case, after depositing an aluminum alloy film, the aluminum alloy film is patterned by RIE dry etching using Cl ₂ gas and BCl ₃ gas to form a spiral conductor film 62.

  Next, in the step shown in FIG. 5A, a BST film is formed on the lower electrode of the capacitor 50 by a sputtering method, and then a platinum (Pt) film is formed on the BST film by an evaporation method. Then, the platinum film and the BST film are patterned into a predetermined shape to form the upper electrode 54 and the capacitor insulating film 53.

  Next, an interlayer insulating film 70 made of a silicon oxide film is deposited on the substrate, and the Schottky electrode 21 and the ohmic electrode 23 of the Schottky diode 20, the source electrode 34 and the drain electrode 35 of the pMOSFET 30 are deposited on the interlayer insulating film 70. Then, contact holes 74 reaching the source electrode 44 and the drain electrode 45 of the nMOSFET 40, the upper electrode 54 and the lower electrode 52 of the capacitor 50, and the center of the spiral of the conductor film 62 of the inductor 60 are formed.

  Thereafter, an aluminum alloy film is formed in each contact hole 74 and on the interlayer insulating film 70, and then patterned to obtain the structure of the semiconductor device shown in FIG.

  In this embodiment, the SiC layer is used. However, not only the semiconductor device provided on the SiC layer but also, for example, a GaAs layer, a GaN layer, an AlGaAs layer, a SiGe layer, a SiGeC layer, an InP layer, an InGaAs layer, an InGaPN layer, and the like. The present embodiment can be applied to all semiconductor devices provided on a compound semiconductor substrate made of a compound of a plurality of elements. Even in this case, the active region in which the δ-doped layer and the lightly doped layer (including the undoped layer) are stacked is provided below the gate insulating film, thereby reducing impurity ion scattering and the entire channel region in the off state. The channel mobility and the breakdown voltage can be improved by utilizing the depletion of δ and trapping charges in the impurities of the δ-doped layer. In particular, when a SiC layer, InP layer, InGaAs layer, InGaPN layer, or GaN layer is used, a device with extremely high channel mobility can be obtained.

(Second Embodiment)
Next, a second embodiment that is an example in which the semiconductor device described in the first embodiment is used in a lamp lighting circuit will be described.

  FIG. 6 is a cross-sectional view showing the structure of the bulb-type fluorescent lamp device 80 in the present embodiment. As shown in the figure, the fluorescent lamp device 80 includes a fluorescent lamp 81 configured by connecting three substantially U-shaped arc tubes by a bridge, and elements such as a semiconductor chip for lighting the fluorescent lamp 81. Including a lighting circuit 82, a cover 83 that houses the lighting circuit 82, a base 84 attached to the tip of the cover 83, a globe 85 that covers the fluorescent lamp 81, and a circuit board for mounting the lighting circuit 82 86.

  FIG. 7 is an electric circuit diagram showing the configuration of the lighting circuit 82 in the fluorescent lamp device 80. As shown in the figure, the lighting circuit 82 includes a line filter circuit 87, a rectifier circuit 88, a power supply smoothing capacitor 89, an inverter circuit 90, an inductor 91, and a resonance capacitor 92. Has been. The inverter circuit 90 is composed of a pMOSFET, an nMOSFET, and an inverter capacitor. The fluorescent lamp 81 is arranged in parallel with the resonance capacitor 92, and is configured such that fluorescence is emitted by flowing a discharge current between the electrodes 93 and 94 at both ends in the fluorescent lamp 81.

  Here, the feature of the fluorescent lamp device 80 in the present embodiment is that, as shown in FIG. 6, each member in the lighting circuit 82 is mounted on one SiC substrate, and the entire lighting circuit 82 is downsized. It is a point. That is, as will be described later, the lighting circuit 82 in the present embodiment can be reduced in size to, for example, about 10 to 15 mm square, and the entire thickness thereof is equal to the thickness of the SiC substrate, such as a laminated film or an interlayer insulating film. Therefore, the entire lighting circuit 82 has a very thin structure. As a result, the lighting circuit 82 can be disposed in a small diameter portion near the base 84, and the size of the lamp itself can be reduced. In particular, as described in the first embodiment, since active elements such as MOSFETs and Schottky diodes have a lateral structure, MOSFETs and Schottky diodes can be provided in a common SiC substrate. Integration became easy. Further, by allowing passive elements such as inductors to be mounted on a common SiC substrate, further miniaturization can be achieved.

FIG. 8 shows a lighting circuit 82 of the present embodiment and a conventional lighting circuit described in the above publication (
It is a figure which compares and shows the magnitude | size with reference to a broken line. In the present embodiment, the space occupied by each member can be reduced as follows.

  Since the gate length of the MOSFET is 1 μm, the area as an inverter can be accommodated within an area of about several tens μm to several hundreds μm square. A rectifier circuit composed of four Schottky diodes can be accommodated within the same or smaller area.

  On the other hand, if the inductor is provided with a spiral conductor film having a line width of 9 μm and an interval of 4 μm in an area of about 5 mm square, the number of turns becomes about 160 and the inductance becomes 780 μH. Normally, the inductance of the inductor used in the lighting circuit of the fluorescent lamp device is about 400 to 700 μH as a whole, so that an inductor satisfying this specification can be provided if it has an area of about 5 mm square.

  For example, when a BST film is formed with an area of 5 mm square, the capacitor (capacitor) has a relative dielectric constant of about 1000 and a thickness of about 10 nm. can get. Usually, the capacitance of the capacitor used for the smoothing capacitor in the lighting circuit of the fluorescent lamp device is about 20 to 30 μF. In addition, capacitors arranged in other circuits need only have an nF-order capacitance, and thus do not require a large area. Therefore, as shown in FIG. 8, it is possible to secure a region for arranging the capacitor of the entire lighting circuit on a 10 to 20 mm square SiC substrate.

  Further, the temperature at which the normal operation of the MOSFET and the Schottky diode formed on the SiC substrate can be ensured is around 400 ° C., so that the FET provided on the conventional Si substrate is premised. Various restrictions due to the severe upper limit of 150 ° C. are greatly relaxed. For example, in a conventional fluorescent lamp device, when the temperature due to heat generation of the choke coil exceeds 150 ° C. and heat dissipation from the lamp is taken into consideration, the FET in the inverter circuit, the diode in the rectifier circuit, and the choke coil are combined. It was necessary to arrange in a distant position. However, in the present embodiment, since the heat resistance of the MOSFET and the Schottky diode on the SiC substrate is high, even if all the elements are arranged close to each other, there is almost no problem due to the heat resistance. In addition, since the lighting circuit can be greatly reduced in size, it is possible to secure a high degree of freedom in arrangement in the lamp, and since the SiC substrate has high thermal conductivity and good heat dissipation, It is possible to easily avoid each of the elements from being adversely affected by the heat dissipation of the fluorescent lamp 81.

  Further, in the lighting circuit 82 of the present embodiment, a part of the inductor or capacitor can be disposed on the back surface of the SiC substrate to effectively use the area of the substrate. It is also possible to adopt a structure in which the entire chip of the SiC substrate is embedded in a glass such as quartz glass and placed in a light bulb.

  Further, in the second embodiment, the example in which the semiconductor device using the SiC substrate is disposed in the lighting circuit of the lamp has been described. However, the semiconductor device of the present invention can of course be used for other equipment. is there. For example, in a device such as an air conditioner, a vacuum cleaner, a washing machine, and a refrigerator, the semiconductor device of the present invention is disposed when it is used at a high temperature or when a control circuit needs to be stored in a narrow space. Thus, the effects described in the above embodiment can be exhibited. However, strict heat resistance and intensiveness are required for devices that are particularly small and generate a large amount of heat, such as lamp lighting circuits. it can.

  In each of the above embodiments, the SiC layer is used, but it is composed of a semi-insulating layer other than the SiC layer, for example, a GaAs layer, a GaN layer, an AlGaAs layer, a SiGe layer, a SiGeC layer, an InP layer, InGaPN, or the like. Even if a substrate is used, the same effect as described above can be exhibited. In particular, when an InP substrate or InGaPN substrate is used, a transistor operating at an extremely high speed can be obtained.

  Further, in each of the above embodiments, a horizontal diode or MOSFET is provided as an active element. However, the active element of the present invention is not limited to such an embodiment, and a vertical diode, a vertical power MOSFET, etc. It can also be applied to. That is, the vertical active element and the horizontal active element may be provided on a common substrate such as a SiC substrate, or a plurality of vertical active elements may be provided on a common substrate such as a SiC substrate. .

  Next, actual measurement data relating to the diodes and MOSFETs used in the above embodiments will be described.

FIG. 9 shows the result of measuring the impurity concentration by the CV method for a Schottky diode in order to examine in detail the profile of the δ-doped layer when the nitrogen concentration is 1 × 10 ¹⁸ atoms · cm ^−3. FIG. The measurement by the CV method shows that a bias is applied to a Schottky diode having a circular Ni Schottky electrode having a diameter of 300 μm between 0.5 V and −0.2 V and between −0.2 V and −2 V. And a high frequency signal of 1 MHz with a minute amplitude was applied by superimposing it. The impurity concentration profile shown in the figure is for a δ-doped layer extracted from a laminate of a δ-doped layer having a thickness of 10 nm and an undoped layer having a thickness of 50 nm. As shown in the figure, the concentration profile in the depth direction is almost vertically symmetric, indicating that the doping memory effect (dopant residual effect) during epitaxial growth by CVD can be ignored by the epitaxial method of the embodiment of the present invention. ing. The planar carrier concentration of the δ-doped layer by the CV method is 1.5 × 10 ¹² cm ⁻² , and the planar carrier concentration obtained from the Hall coefficient measurement is about 2.5 × 10 ¹² cm 2. Matches ^-2 relatively well. And the half width of this pulse-like profile is formed with 12 nm, and shows a remarkable steepness.

FIG. 10 is a diagram showing the measurement result of the band edge photoluminescence spectrum of the δ-doped layer in the 6H—SiC substrate. This spectrum was obtained at a temperature of 8K, and a He—Cd laser having an intensity of 0.5 mW was used as an excitation source. Here, a spectrum obtained from an undoped layer of a stack of a δ-doped layer having a thickness of 10 nm and an undoped layer having a thickness of 50 nm is compared with a spectrum obtained from an undoped layer having a thickness of 1 μm. As shown in the figure, since both spectrum patterns have emission peaks with the same intensity in the same wavelength region, it can be seen that the impurity concentrations of both are the same. In other words, the undoped layer in the laminated structure composed of the δ-doped layer and the undoped layer shows almost no increase in impurity concentration due to the diffusion of impurities from the δ-doped layer, while maintaining a substantially desired impurity concentration profile. It can be seen that they are stacked. It should be noted that the impurity concentration of the undoped layer is controlled to a low value of about 5 × 10 ¹⁶ atoms · cm ⁻³ . By using the PL method, the impurity concentration of the undoped layer in the active region obtained by alternately laminating the δ-doped layer and the undoped layer of the present invention is as low as about 5 × 10 ¹⁶ atoms · cm ^−3. It was confirmed.

FIGS. 11A and 11B are data showing the temperature dependence of the electron mobility and the temperature dependence of the electron concentration of the 6H—SiC layer, respectively. 11 (a) and 11 (b), the data marked with ◯ is a 6H—SiC layer (sample A) formed by laminating a δ-doped layer having a thickness of 10 nm (a dopant is nitrogen) and an undoped layer having a thickness of 50 nm. ). The data marked with (2) is the data for the low concentration uniformly doped layer (1.8 × 10 ¹⁶ cm ⁻³ ) of 6H—SiC, and the data marked with ▲ is the highly doped layer with high concentration of 6H—SiC (1.3 × ³ ). × 10 ¹⁸ cm ^-3 ). As shown in FIGS. 11A and 11B, in the 6H—SiC low concentration uniform doped layer (1.8 × 10 ¹⁶ cm ⁻³ ), the impurity concentration is low, so that the carrier is an impurity during the traveling of the carrier. As the scattering received from the electron beam decreases, the mobility of electrons increases. On the other hand, in the high concentration uniform doped layer (1.3 × 10 ¹⁸ cm ⁻³ ) of 6H—SiC, since the impurity concentration is high, the scattering that the carriers receive from the impurities during the traveling of the carriers increases, so that the electron mobility is increased. Is small. That is, the carrier concentration and the running characteristics of the carrier are in a trade-off relationship with each other. In contrast, in the δ-doped layer in the active region of sample A, it can be seen that the electron concentration is as high as the high-concentration uniformly doped layer and the electron mobility is high. That is, since the active region of the present invention can achieve high electron mobility while having a high electron concentration, it can be seen that the active region has a structure suitable for the region where electrons of diodes and transistors travel. . It should be noted that even when the carriers are holes, in principle, there is no difference from the case of electrons, so that it is possible to achieve high hole mobility while increasing the hole concentration in the p-type δ layer. Can do.

  FIG. 12 shows a sample A having an active region formed by stacking the above-mentioned δ-doped layer having a thickness of 10 nm and an undoped layer having a thickness of 50 nm, a δ-doped layer having a thickness of 20 nm, and an undoped layer having a thickness of 100 nm. It is data which shows the temperature dependence of the electron mobility in the sample B which has the active region formed by laminating. This electron mobility data is measured in the temperature range of 77 to 300K. As described above, although the ratio of the thicknesses of the δ-doped layer and the undoped layer in Samples A and B are both 1: 5, the average impurity concentration of Samples A and B is the same. As shown in the figure, it can be seen that the electron mobility in sample A is larger than the electron mobility in sample B. In particular, in the low temperature region, the electron mobility in the sample B decreases due to scattering by ionized impurities as the temperature decreases, but in the sample A, the electron mobility increases even when the temperature decreases. It is shown that mobility is maintained.

FIGS. 13A and 13B are diagrams showing the results of simulating the band structure at the conduction band edge in Sample A having a δ-doped layer having a thickness of 10 nm, and the results of simulating the carrier concentration distribution. . FIGS. 14A and 14B are diagrams showing the results of simulating the band structure at the conduction band edge in Sample B having a δ-doped layer having a thickness of 20 nm, and the results of simulating the carrier concentration distribution. . As shown in FIGS. 13A and 14A, in a cross section orthogonal to the δ-doped layer, electrons are V-type Coulomb potential (quantum well) constituted by a positively charged donor layer. And a quantum state is formed in this well. The effective mass of electrons is 1.1, and the relative dielectric constant of the 6H—SiC layer is 9.66. The background carrier concentration of the 6H—SiC layer used for the undoped layer is about 1 × 10 ¹⁵ cm ⁻³ , and the carrier concentration of the n-type δ doped layer is 1 × 10 ¹⁸ cm ⁻³ .

As shown in FIG. 13B, in the δ-doped layer (sample A) having a thickness of 10 nm, two-dimensional electrons are widely distributed to the undoped layer sandwiched between two δ-doped layers, and the electron concentration is The region of 2 × 10 ¹⁶ m ⁻³ or more is a range of 25 nm from the interface. In other words, it can be seen that carriers have oozed from the n-type doped layer 12a (δ-doped layer) to the undoped layer 12b shown in FIG.

On the other hand, as shown in FIG. 14B, in a thick δ-doped layer (sample B) having a thickness of 20 nm, a region having a high carrier existence probability defined by an electron wave function and a δ having an ionized scattering center. The region where the doped layer strongly overlaps and the electron concentration is 2 × 10 ¹⁶ cm ⁻³ or more is in the range of 11 nm from the interface. That is, it can be seen that the carrier leaching from the δ-doped layer to the undoped layer is relatively small.

When the above embodiment and other simulation data are combined, it has been found that the thickness of the highly doped layer is preferably one monolayer or more and less than 20 nm when the SiC layer is used. The thickness of the lightly doped layer (including the undoped layer) is preferably about 10 nm or more and about 100 nm or less. The thicknesses of the high-concentration doped layer and the low-concentration doped layer can be appropriately selected according to the type and purpose of the active element (diode, transistor, etc.) formed using them.

(Third embodiment)
In the third embodiment, an ACCUFET (AccumulationModeFET) functioning as a high-current switching transistor using a laminated structure of a δ-doped layer and an undoped layer is used instead of the MOSFET of the integrated semiconductor device in the first embodiment. Use.

FIG. 15 is a cross-sectional view showing the structure of only the ACCUFET portion in the present embodiment. As shown in the figure, on the p-type SiC substrate 130 doped with aluminum (p-type impurity) having a concentration of 1 × 10 ¹⁸ atoms · cm ⁻³ , the average concentration is about 1 × 10 ¹⁷ atoms · cm ^−. A p-type lower active region 131 doped with ³ aluminum, and an n-type upper active region 132 formed on the lower active region 131 and doped with nitrogen having an average concentration of about 1 × 10 ¹⁷ atoms · cm ^−3. And n-type source region 133a and drain region 133b formed by implanting nitrogen at a concentration of 1 × 10 ¹⁸ cm ⁻³ into the upper active region 132 and the lower active region 131, and the upper active region 132. a gate insulating film 134 made of SiO ₂ and a gate electrode 135 made of Ni alloy film formed on the gate insulating film 134, to the source region 133a and drain region 133b Omikkuko It includes a source electrode 136a and drain electrode 136b made of Ni alloy film tact, a back electrode 137 made of Ni alloy film in ohmic contact with the back surface of the SiC substrate 130.

Here, as shown on the right side of FIG. 15, the lower active region 131 has a p-type doped layer 131a having a thickness of about 10 nm containing high concentration (for example, 1 × 10 ¹⁸ atoms · cm ⁻³ ) of aluminum. And about 40 layers of the undoped layers 131b made of undoped SiC single crystal and having a thickness of about 50 nm are alternately stacked. The total thickness is about 2400 nm. Since the p-type doped layer 131a is thin enough to allow the carriers to bleed into the undoped layer 131b due to the quantum effect, the p-type doped layer 131a is negatively charged as the carriers ooze out. Charge is trapped.

On the other hand, as shown on the left in FIG. 15, the upper active region 132 includes an n-type doped layer 132a having a high concentration (for example, 1 × 10 ¹⁸ atoms · cm ⁻³ ) of nitrogen and a thickness of about 10 nm. The undoped SiC single crystal and the undoped layer 132b having a thickness of about 50 nm are alternately stacked to form five layers each. That is, the total thickness is about 300 nm. Then, quantum levels are generated in the n-type doped layer 132a by the quantum effect, and the wave function of the localized electrons in the n-type doped layer 132a has a certain extent. As a result, as described above, the distribution state is such that electrons exist not only in the n-type doped layer 132a but also in the undoped layer 132b. In this state, when the potential of the upper active region 132 is increased and electrons are spread from the n-type doped layer 132a to the undoped layer 132b by the quantum effect, electrons are continuously supplied to the n-type doped layer 132a and the undoped layer 132b. The Since electrons flow through the undoped layer 132b having a low impurity concentration, high channel mobility can be obtained by reducing impurity ion scattering. On the other hand, in the off state, the entire upper active region 132 is depleted and no electrons exist in the upper active region 132. Therefore, the breakdown voltage is defined by the undoped layer 132b having a low impurity concentration, and a high breakdown voltage value is obtained in the entire upper active region 132. Will be obtained. Therefore, in the ACCUFET configured to flow a large current between the source / drain regions 133a and 133b using the upper active region 132, it is possible to simultaneously realize high channel mobility and high breakdown voltage.

  Further, as described above, since the impurity concentration in the undoped layer 132b is low, the upper active region 132 is used as a channel layer, so that the gate insulating film 134 and the interface between the gate insulating film 134 and the upper active region 132 are located in the vicinity. It is possible to improve channel mobility by reducing trapped charges, improve channel mobility by reducing impurity ion scattering, and improve pressure resistance.

  Then, by using the ACCUFET of this embodiment instead of the MOSFET in the first embodiment, a semiconductor device suitable for a lamp apparatus that requires higher power can be configured.

When the gate voltage dependency of the current-voltage characteristics (the relationship between the drain current and the drain voltage) of the ACCUFET of this embodiment was examined, the saturation current amount further increased as compared with the n-channel MOSFET in the first embodiment. I found out. Further, a stable drain current was obtained without breakdown even when the drain voltage was 400 V or higher, the dielectric breakdown voltage in the off state was 600 V or higher, and the on-resistance was as low as 1 mΩ · cm ² .

  In particular, ACCUFET is characterized in that the saturation current value is large and the on-resistance is small. However, one of the major reasons that ACCUFET has not yet been put into practical use is that it has poor withstand voltage in the off state. However, in the ACCUFET of this embodiment, since the high breakdown voltage in the OFF state can be secured by using the laminated structure of the δ-doped layer and the undoped layer as described above, the ACCUFET is greatly advanced to practical use. I can say that.

  Note that the manufacturing process of the integrated semiconductor device having the ACCUFET of this embodiment is basically the same as the manufacturing process of the integrated semiconductor device in the first embodiment, and a description thereof will be omitted.

  In the present embodiment, the lower active region 131 formed by alternately stacking the δ-doped layer and the undoped layer is provided, but the lower active region is not necessarily required. Further, a lightly doped layer or an undoped layer that is uniformly doped may be provided instead of the lower active region. However, by providing the lower active region 131 in which the δ-doped layer and the undoped layer are alternately stacked, the breakdown voltage in the channel lower region can be further increased.

  FIG. 16 is a diagram showing IV characteristics (change characteristics of drain current with respect to changes in drain voltage) when the gate bias Vg is changed from −5 V to 25 V in increments of 5 V for the ACCUFET of this embodiment. As can be seen from the IV characteristics, a large drain current of about 220 mA / mm is obtained even when the gate bias is set to 15 V, which is a relatively low value in a power device. That is, it was confirmed that the ACCUFET of the present invention has a large current driving force.

FIG. 17 is a diagram showing the gate voltage dependence of the effective channel mobility obtained by calculation based on the data of FIG. As shown in the figure, it is confirmed that the ACCUFET of this embodiment has an effective channel mobility of 50 (cm ² / Vs) or more even when the gate bias is increased. That is, the current driving force of the FET is proportional to the effective channel mobility, but the ACCUFET of this embodiment has a structure in which the δ-doped layer and the undoped layer are alternately stacked as described above, and thus is high. It can be seen that the effective channel mobility is exhibited, and as a result, a large current driving force is exhibited.

(Other embodiments)
A semiconductor layer other than the SiC layer can also be used. For example, In on the InP substrate
A P layer, an InGaAs layer, or an InGaPN layer can be used. A GaN layer on a sapphire substrate, a GaN substrate, or the like can also be used. Furthermore, known compound semiconductor layers such as a GaAs layer, an AlGaAs layer, a GaN layer, an AlGaN layer, a SiGe layer, and a SiGeC layer can be used. In the case of these compound semiconductor layers, the thickness of the highly doped layer (δ-doped layer) is determined appropriately depending on the material. For example, when a GaAs layer is used, one monolayer δ-doped layer can be provided. In general, it can be said that as long as the carrier supply capability can be properly maintained, the thickness of the high-concentration doped layer (δ-doped layer) is preferably as small as possible in order to improve the pressure resistance value with the same thickness.

  In particular, a case where an InP substrate is used will be described. The semiconductor device structure in this case is basically the same as the structure shown in FIG. 1, and an integrated semiconductor in which a Schottky diode, MOSFET, capacitor and inductor are integrated using an InGaAs layer on an InP substrate. The device can be configured.

In that case, instead of the Si substrate 10, a semi-insulating InP substrate having a thickness of about 100 μm doped with high-concentration iron (Fe) is used. Further, instead of the first active region 12, an InGaAs single crystal having a thickness of about 1 nm containing Si (silicon) at a high concentration (for example, 1 × 10 ²⁰ atoms · cm ⁻³ ) (the component ratio is, for example, In _0.53 Ga _0.47 An n-type doped layer made of As) and an undoped layer made of InGaAs single crystal (having a component ratio of, for example, In _0.53 Ga _0.47 As) and having a thickness of about 10 nm are alternately stacked. Further, instead of the second active region 13, a p-type doped layer containing Zn (Be) at a high concentration (for example, 1 × 10 ²⁰ atoms · cm ⁻³ ) and having a thickness of about 1 nm, and an undoped InAlAs single crystal ( As the component ratio, for example, an undoped layer made of In _0.52 Al _0.48 As and having a thickness of about 10 nm is alternately stacked.

  It is known that when an InGaAs layer or InGaPN layer formed on an InP substrate is used as an electron transit region, extremely high electron mobility can be obtained. Therefore, a lighting circuit equipped with a switching transistor that operates in an extremely high frequency wave region (30 GHz to 60 GHz) can be obtained using this characteristic.

  Even when an InGaAs layer on an InP substrate is used, a Schottky diode, a capacitor, and an inductor can be provided as in the first embodiment. In particular, since the InP substrate has high heat resistance and high thermal conductivity, the conductor film constituting the inductor can be miniaturized even when the inductor is provided, and a finer pattern, for example, a width of 1 can be obtained. A shape with a gap of about 1-2 μm and a gap of about 1-2 μm is also possible.

It is sectional drawing of the semiconductor device formed by integrating a Schottky diode, MOSFET, a capacitor, and an inductor on the SiC substrate in the 1st Embodiment of this invention. It is a top view which shows roughly the plane pattern of the semiconductor device in 1st Embodiment. (A)-(c) is sectional drawing which shows the process from formation of the 1st, 2nd active region to formation of an element isolation area | region among the manufacturing processes of the semiconductor device of 1st Embodiment. (A)-(c) is sectional drawing which shows the process from formation of a source / drain area | region to formation of the electrode or conductor film of each element among the manufacturing processes of the semiconductor device of 1st Embodiment. (A), (b) is sectional drawing which shows the process from formation of the upper electrode of a capacitor to formation of the contact hole to the conductor part of each element among the manufacturing processes of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the structure of the fluorescent lamp apparatus in 2nd Embodiment. It is an electric circuit diagram which shows the structure of the lighting circuit in the fluorescent lamp apparatus in 2nd Embodiment. It is a figure which compares and shows the magnitude | size of the lighting circuit of 2nd Embodiment, and the conventional lighting circuit. It is a figure which shows the result of having performed the impurity concentration measurement by CV method about the Schottky diode in 1st Embodiment. It is a figure which shows the measurement result of the band edge photoluminescence spectrum of (delta) dope layer in the 6H-SiC substrate which concerns on 1st Embodiment. (A), (b) is data which shows the temperature dependence of the electron mobility of the 6H-SiC layer in 1st Embodiment, and the temperature dependence of an electron concentration, respectively in order. It is data which shows the temperature dependence of the electron mobility in the samples A and B in 1st Embodiment. (A), (b) is a figure which shows the result of having simulated the band structure of the conduction band edge in the sample A in 1st Embodiment, and the figure which shows the result of having simulated the carrier concentration distribution. (A), (b) is a figure which shows the result of having simulated the band structure of the conduction band edge in the sample B in 1st Embodiment, and the figure which shows the result of having simulated the carrier concentration distribution. It is sectional drawing of ACCUFET in 2nd Embodiment. It is a figure which shows the IV characteristic of ACCUFET created in 2nd Embodiment. It is a figure which shows the gate voltage dependence of the effective channel mobility obtained by the calculation based on the data of FIG. It is sectional drawing which shows the structure of the conventional fluorescent lamp apparatus. It is an electric circuit diagram which shows the structure of the lighting circuit in the conventional fluorescent lamp apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 SiC substrate 11 Element isolation region 12 1st active region 12a n-type doped layer 12b undoped layer 13 2nd active region 13a p-type doped layer 13b undoped layer 20 Schottky diode 21 Schottky electrode 22 Electrode extraction layer 23 Ohmic electrode 30 pMOSFET
31 Gate insulating film 32 Gate electrode 33a Source region 33b Drain region 34 Source electrode 35 Drain electrode 40 nMOSFET
41 Gate insulating film 42 Gate electrode 43a Source region 43b Drain region 44 Source electrode 45 Drain electrode 50 Capacitor 51 Base insulating film 52 Lower electrode 53 Capacitor insulating film 54 Upper electrode 60 Inductor 61 Dielectric film 62 Conductive film 70 Interlayer insulating film 71 Contact 72 Wiring 74 Contact hole 75 Pad 80 Fluorescent lamp device 81 Fluorescent lamp 82 Lighting circuit 83 Cover 84 Base 85 Globe 86 Circuit board 87 Line filter circuit 88 Rectifier circuit 89 Power source smoothing capacitor 90 Inverter circuit 91 Inductor 92 Resonance capacitor 93, 94 electrode

Claims (4)

A compound semiconductor layer provided on the SiC substrate;
A plurality of first semiconductor layers provided on the compound semiconductor layer and functioning as a carrier traveling region, and containing a high concentration of carrier impurities, the thickness of the carrier is smaller than that of the first semiconductor layer and due to quantum effects. A plurality of active elements in which an active region formed by alternately stacking a plurality of second semiconductor layers capable of distribution becomes a channel layer ;
An inductor provided on the compound semiconductor layer ,
The semiconductor power device , wherein the plurality of first semiconductor layers and the plurality of second semiconductor layers are SiC layers . A compound semiconductor layer provided on the SiC substrate;
One first semiconductor layer provided on the compound semiconductor layer and functioning as a carrier traveling region, and containing a high concentration of carrier impurities, the thickness of the carrier is smaller than that of the first semiconductor layer and due to quantum effects. A plurality of active elements in which an active region formed by stacking one second semiconductor layer capable of distribution becomes a channel layer;
An inductor provided on the compound semiconductor layer;
With
The semiconductor power device, wherein the first semiconductor layer and the second semiconductor layer are SiC layers . The semiconductor power device according to claim 1 or 2 ,
The plurality of active elements, a semiconductor power device which comprises a MISFET having the first semiconductor layer just below the gate insulating film. The semiconductor power device according to claim 1 or 2 ,
As the active region, a carrier active in the second semiconductor layer is formed on the first active region in which the carrier impurity in the second semiconductor layer is a first conductivity type impurity and on the first active region. A second active region in which the impurity is a second conductivity type impurity;
A portion of the second active region is removed, and the first active region is exposed on the top layer of the substrate;
The portion where the first active region is exposed is provided with a second conductivity type MISFET, while the second active region is provided with a first conductivity type MISFET. Semiconductor power device.

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