JP4929852B2 - Electro-optical device, drive circuit, and electronic device - Google Patents

Description

  The present invention relates to a technique for suppressing a voltage amplitude of a data line with a simple configuration in an electro-optical device such as a liquid crystal.

In an electro-optical device such as a liquid crystal, a pixel capacitor (liquid crystal capacitor) is provided corresponding to the intersection of a scanning line and a data line. When this pixel capacitor needs to be AC driven, the voltage amplitude of the data signal is positive or negative. Therefore, in the data line driving circuit for supplying a data signal to the data line, a breakdown voltage corresponding to the voltage amplitude is required for the constituent elements. For this reason, a storage capacitor is provided in parallel with the pixel capacitor, and a capacitor line commonly connected to the storage capacitor in each row is driven in binary in synchronization with the selection of the scanning line, thereby suppressing the voltage amplitude of the data signal. A technique has been proposed (see Patent Document 1).
See JP 2001-83943 A

By the way, in this technique, the circuit for driving the capacitance line is equivalent to the scanning line driving circuit (substantially shift register) for driving the scanning line, so that the circuit configuration for driving the capacitance line is complicated. End up.
SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device, a driving circuit, and an electronic apparatus that can suppress the voltage amplitude of a data line with a simple configuration. There is to do.

To achieve the above object, a driving circuit of an electro-optical device according to the present invention, the scanning lines arranged in the row direction, and data lines arranged in a column direction, provided in correspondence with the front Kihashi査線and capacity lines, which are, before and pixel electrodes provided corresponding to intersections of the Kihashi査線before Kide over data lines, a common electrode that forms the pixel electrode and the pixel capacitor, and the pixel electrode the storage capacitor is formed, and connected to the capacitor electrode to the capacitor line, a scanning line driving circuit for selecting the scanning lines with respect to the capacitor line, the first feed line when the scanning line is selected an electrical potential is applied and the potential of the first feeder line when the scanning line to be selected after the next line or the predetermined line from a scanning line spaced the scanning line a scanning line of the scanning line is selected different second and a capacitive line driving circuit for applying a potential of the feed line, the first feed line, odd The first feed line corresponding to the odd row is connected to the capacitor line corresponding to the odd row, and the first feed line corresponding to the even row corresponds to the even row. One of two potentials that are lower and higher than the potential of the second feeder line is applied to the first feeder line corresponding to the odd-numbered row, and the other is the first potential corresponding to the even-numbered row. While being applied to one feeder line, the two different voltages are replaced at a predetermined cycle . According to the present invention, the voltage amplitude of the data line can be suppressed with a simple configuration.

The present invention can be conceptualized not only as a drive circuit for an electro-optical device, but also as an electro-optical device, and further as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the electro-optical device according to the first embodiment of the invention.
As shown in this figure, the electro-optical device 10 has a display area 100, and a control circuit 20, a scanning line driving circuit 140, a capacitor line driving circuit 150, and a data line driving circuit 190 are arranged around the display area 100. The arrangement is arranged. Among these, the display area 100 is an area where the pixels 110 are arranged. In this embodiment, 321 rows of scanning lines 112 extend in the row (X) direction, while 240 columns of data lines 114 are columns (Y ) Of the pixels corresponding to the intersection of the scanning lines 112 in the 1st to 320th rows other than the final 321st row and the data lines 114 in the 1st to 240th columns. 110 are arranged. Therefore, in the present embodiment, the scanning line 112 in the 321st row does not contribute to the vertical scanning of the display area 100 (operation for sequentially selecting scanning lines for voltage writing to the pixels 110).
In the present embodiment, the pixels 110 are arranged in a matrix of 320 rows × 240 columns in the display region 100, but the present invention is not limited to this arrangement.
In addition, corresponding to the scanning lines 112 in the first to 320th rows, capacitance lines 132 are provided extending in the X direction, respectively. For this reason, in the present embodiment, the capacity lines 132 are provided for 1 to 320 rows excluding the dummy 321st scanning line 112.

Here, a detailed configuration of the pixel 110 will be described.
FIG. 2 is a diagram illustrating the configuration of the pixel 110, and 2 × 2 total 4 corresponding to the intersections of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto. A configuration for pixels is shown.
Note that i is a symbol generally indicating a row in which the pixels 110 are arranged, and is an integer of 1 to 320, and j and (j + 1) generally indicate a column in which the pixels 110 are arranged. The symbol of the case, which is an integer from 1 to 240. Here, (i + 1) is an integer of 1 or more and 320 or less when generally indicating the row in which the pixels 110 are arranged, but is a dummy 321 when describing the row of the scanning line 112. Since it is necessary to include the line, it is an integer between 1 and 321 inclusive.

As shown in FIG. 2, each pixel 110 includes an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 that functions as a pixel switching element, a pixel capacitor (liquid crystal capacitor) 120, And a storage capacitor 130. Since each pixel 110 has the same configuration, a description will be given by representatively assuming that the pixel 110 is located in the i row and j column. In the pixel 110 in the i row and j column, the gate electrode of the TFT 116 is connected to the scanning line 112 in the i row. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 that is one end of the pixel capacitor 120.
The other end of the pixel capacitor 120 is a common electrode 108. The common electrode 108 is common to all the pixels 110 as shown in FIG. 1 and is supplied with a common signal Vcom. In the present embodiment, the common signal Vcom is constant at the voltage LCcom in terms of time as will be described later.
In FIG. 2, Yi and Y (i + 1) indicate scanning signals supplied to the i and (i + 1) th scanning lines 112, respectively, and Ci and C (i + 1) indicate i and (i + 1), respectively. ) The voltage of the capacitor line 132 in the row is shown.

  In the display region 100, a pair of substrates, an element substrate on which the pixel electrode 118 is formed and a counter substrate on which the common electrode 108 is formed, are bonded to each other with a certain gap so that the electrode formation surfaces face each other. The liquid crystal 105 is sealed in the gap. For this reason, the pixel capacitor 120 has a configuration in which the liquid crystal 105 which is a kind of dielectric is sandwiched between the pixel electrode 118 and the common electrode 108, and holds a differential voltage between the pixel electrode 118 and the common electrode 108. . In this configuration, in the pixel capacitor 120, the amount of transmitted light changes according to the effective value of the holding voltage. In the present embodiment, for convenience of explanation, if the effective voltage value held in the pixel capacitor 120 is close to zero, the light transmittance is maximized to display white, while the effective voltage value is increased. Assume that it is a normally white mode in which the amount of light decreases and finally the black display with the minimum transmittance is achieved.

  The storage capacitor 130 in the pixel 110 in the i row and j column has one end connected to the pixel electrode 118 (the drain electrode of the TFT 116) and the other end connected to the i-th capacitor line 132. Here, the capacitance values in the pixel capacitor 120 and the storage capacitor 130 are Cpix and Cs, respectively.

Returning again to FIG. 1, the control circuit 20 outputs various control signals to control each part in the electro-optical device 10, and the second capacitance signal Vc <b> 1 is supplied to the first power supply line 165. The capacitance signal Vc2 is supplied to the second power supply line 167, respectively. In addition, the control circuit 20 supplies the common signal Vcom to the common electrode 108.
Around the display region 100, peripheral circuits such as a scanning line driving circuit 140, a capacitor line driving circuit 150, and a data line driving circuit 190 are provided. Among these, the scanning line driving circuit 140 sends the scanning signals Y1, Y2, Y3,..., Y320, Y321 to 1, 2, 3,. This is supplied to the scanning line 112 in the row. That is, the scanning line driving circuit 140 selects the scanning lines in the order of the first, second, third,..., 320, and 321st rows, and sets the scanning signal to the selected scanning line to the H level corresponding to the selection voltage Vdd. The scanning signals for the other scanning lines are set to the L level corresponding to the non-selection voltage (ground potential Gnd).

In detail, as shown in FIG. 4, the scanning line driving circuit 140 sequentially shifts the start pulse Dy supplied from the control circuit 20 in accordance with the clock signal Cly, etc., so that the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 are output.
In the present embodiment, as shown in FIG. 4, the period of one frame is an effective scanning period Fa from when the scanning signal Y1 becomes H level until the scanning signal Y320 becomes L level,
And a blanking period Fb from when the dummy scanning signal Y321 becomes H level to when the scanning signal Y1 becomes H level again. A period during which one row of scanning lines 112 is selected is a horizontal scanning period (H).

  In the present embodiment, the capacitor line driving circuit 150 includes a set of TFTs 156 and 158 provided corresponding to the capacitor lines 132 in the first to 320th rows. Here, the TFTs 156 and 158 corresponding to the i-th capacitor line 132 will be described. The gate electrode of the TFT 156 (first transistor) is connected to the i-th scanning line 112, and the source electrode thereof is the first electrode. While connected to the power supply line 165, the gate electrode of the TFT 158 (second transistor) is connected to the scanning line 112 in the (i + 1) th row, and its source electrode is connected to the second power supply line 167, The drain electrodes of the TFTs 156 and 158 are connected to the i-th capacitor line 132.

The data line driving circuit 190 is a voltage corresponding to the gray level of the pixel 110 located on the scanning line 112 selected by the scanning line driving circuit 140, and has a polarity voltage data signal X1 designated by the polarity instruction signal Pol. , X2, X3,..., X240 are supplied to the data lines 114 in the 1, 2, 3,.
Here, the data line driving circuit 190 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area has a gradation value (brightness) of the corresponding pixel 110. Display data Da for designating the data is stored. The display data Da stored in each storage area is rewritten by the display circuit Da after the change together with the address by the control circuit 20 when the display contents are changed.
The data line driving circuit 190 reads out the display data Da of the pixel 110 located on the selected scanning line 112 from the storage area, and converts it into a data signal having a voltage corresponding to the gradation value and having a specified polarity. The operation of converting and supplying to the data line 114 is executed for each of the 1 to 240 columns positioned on the selected scanning line 112.

Here, the polarity instruction signal Pol is a signal for designating positive polarity writing when it is at the H level, and for designating negative polarity writing when it is at the L level. In this embodiment, as shown in FIG. The polarity is inverted every frame period. That is, in this embodiment, the surface inversion method is used in which all the polarities to be written to the pixels in the period of one frame are the same, and the writing polarity is inverted every period of one frame. The reason for polarity inversion is to prevent deterioration of the liquid crystal due to application of a direct current component.
As for the writing polarity in the present embodiment, when the voltage corresponding to the gradation is held in the pixel capacitor 120, the potential of the pixel electrode 118 is higher than the voltage LCcom of the common electrode 108. It is called positive polarity, and the case of the lower side is called negative polarity. On the other hand, the voltage is based on the ground potential Gnd of the power supply unless otherwise specified.

The control circuit 20 supplies the latch pulse Lp to the data line driving circuit 190 at the timing when the logic level of the clock signal Cly changes. As described above, the scanning line driving circuit 140 outputs the scanning signals Y1, Y2, Y3, Y4,..., Y320, Y321 by sequentially shifting the start pulse Dy according to the clock signal Cly. The start timing of the period in which is selected is the timing at which the logic level of the clock signal Cly changes. Therefore, the data line driving circuit 190 starts the selection depending on, for example, which row scanning line is selected by continuously counting the latch pulse Lp over a period of one frame and the supply timing of the latch pulse Lp. You can know the timing.

In this embodiment, in addition to the scanning lines 112, the data lines 114, the TFTs 116, the pixel electrodes 118, and the storage capacitors 130 in the display region 100, the element substrates include the TFTs 156, 158, the first in the capacitor line driving circuit 150. A feed line 165, a second feed line 167, and the like are also formed.

FIG. 3 is a plan view showing a configuration in the vicinity of the boundary between the capacitive line driving circuit 150 and the display region 100 in such an element substrate.
As shown in this figure, in this embodiment, the TFTs 116, 156, and 158 are amorphous silicon types, and the bottom gate type in which the gate electrode is located below the semiconductor layer. Specifically, the scanning line 112 and the capacitor line 132 are formed by patterning the gate electrode layer serving as the first conductive layer, a gate insulating film (not shown) is formed thereon, and the semiconductor layers of the TFTs 116, 156, and 158 are further formed. Is formed in an island shape. On the semiconductor layer, a rectangular pixel electrode 118 is formed by patterning an ITO (indium tin oxide) layer serving as a second conductive layer via a protective layer, and further aluminum or the like serving as a third conductive layer. By patterning the metal layer, the data line 114, the first power supply line 165, the second power supply line 167, and the like serving as the source / drain electrodes of the TFTs 116, 156, and 158 are formed.

  Here, the gate electrode of the TFT 156 is a portion branched in a T shape in the Y (down) direction from the scanning line 112, and the gate electrode of the TFT 158 is branched in a T shape in the Y (up) direction from the scanning line 112. It is the part which did. The storage capacitor 130 has a structure in which the gate insulating film is sandwiched between the pixel electrode 118 and a portion of the capacitor line 132 formed so as to be wide in the lower layer of the pixel electrode 118. In addition, the common drain electrode of the TFTs 156 and 158 and the capacitor line 132 are electrically connected via a contact hole (indicated by X in the drawing) penetrating the gate insulating film. Note that the common electrode 108 facing the pixel electrode 118 is formed on the counter substrate, and thus does not appear in FIG. 3 showing a plan view of the element substrate.

FIG. 3 is merely an example, and the TFT type may be another structure, for example, the top gate type in terms of the arrangement of the gate electrodes, or the polysilicon type in terms of the process. Further, instead of building the element of the capacitor line driving circuit 150 in the display region 100, an IC chip may be mounted on the element substrate side.
When the IC chip is mounted on the element substrate side, the scanning line driving circuit 140 and the capacitor line driving circuit 150 may be integrated as a semiconductor chip together with the data line driving circuit 190, or may be separate chips. The control circuit 20 is FPC (flexible printed
circuit) may be connected via a substrate or the like, or may be configured to be mounted on an element substrate as a semiconductor chip.
When the present embodiment is a reflective type instead of a transmissive type, the reflective conductive layer may be patterned for the pixel electrode 118, or a separate reflective metal layer may be provided. Furthermore, a so-called transflective type that combines both a transmissive type and a reflective type may be used.

Next, the operation of the electro-optical device 10 according to this embodiment will be described.
As described above, in this embodiment, the surface inversion method is used. Therefore, the control circuit 20 designates the positive polarity writing as the H level in the period of a certain frame (denoted as “n frame”) for the polarity instruction signal Pol, as shown in FIG. The negative polarity writing is designated as the L level during the period of (n + 1) frames, and the writing polarity is similarly reversed every frame period thereafter.
Further, the control circuit 20 sets the first capacitance signal Vc1 and the second capacitance signal Vc2 to the same potential in the n frame, while the first capacitance signal Vc1 is set to be higher than the second capacitance signal Vc2 in the (n + 1) frame. The voltage is relatively increased by ΔV. Therefore, as shown in FIG. 4, if the second capacitance signal Vc2 is constant regardless of the writing polarity at the voltage Vs1, the first capacitance signal Vc1 is the same voltage Vsl in the n frames, and (n + 1) ) The voltage Vsh is higher than the voltage Vsl by ΔV in the frame.

In the n frame, the scanning signal driving circuit 140 first sets the scanning signal Y1 to the H level.
On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y1 becomes the H level, the data line driving circuit 190 displays the display data of the pixels in the first row and the first, second, third,. While reading Da, only the voltage specified by the display data Da is converted into voltage data signals X1, X2, X3,.
, 240 are supplied to the data lines 114 of 1, 2, 3,.
Thus, for example, a positive voltage that is higher than the voltage LCcom by the voltage specified by the display data Da of the pixel 110 in the first row and jth column is applied to the jth data line 114 as the data signal Xj. The
Now, when the scanning signal Y1 becomes the H level, the TFTs 116 in the pixels in the first row and the first column to the first row and the 240th column are turned on, so that the data signals X1, X2, X3,. Is done. For this reason, a positive voltage corresponding to each gradation is written in the pixel capacitors 120 in the first row and the first column to the first row and the 240th column. On the other hand, if the scanning signal Y1 is at the H level, in the capacitor line driving circuit 150, the TFT 156 corresponding to the capacitor line 132 in the first row is turned on, but the TFT 158 is off (the scanning signal Y2 is at the L level). Therefore, the capacitor line 132 in the first row is connected to the first power supply line 165 and becomes the voltage Vsl. For this reason, the differential voltage between the positive voltage and the voltage Vsl corresponding to each gradation is written in the storage capacitor 130 in the first row and the first column to the first row and the 240th column.

Next, the scanning signal Y1 becomes L level and the scanning signal Y2 becomes H level.
When the scanning signal Y1 becomes L level, the TFTs 116 in the pixels in the first row and first column to the first row and 240th column are turned off. If the scanning signal Y1 is at the L level and the scanning signal Y2 is at the H level, the TFT 156 corresponding to the capacitor line 132 in the first row is turned off and the TFT 158 is turned on in the capacitor line driving circuit 150. The capacity line 132 of the eye is connected to the second power supply line 167, but in the n frame designating positive writing, the second power supply line 167 has the same voltage Vsl as the first power supply line 165. Therefore, the potential does not fluctuate.
Therefore, if the polarity instruction signal Pol is at the H level and the positive polarity writing is instructed, even if the scanning signal Y2 becomes the H level, the pixel capacitors 120 and the storage capacitors in the 1st row 1st column to the 1st row 240th column There is no change in the voltage held at 130.

On the other hand, when the latch pulse Lp is output at the timing when the scanning signal Y2 becomes H level, the data line driving circuit 190 is the second row and the gray levels of the pixels in the 1, 2, 3,. .., X240 are supplied to the data lines 114 of 1, 2, 3,..., 240 columns, respectively. When the scanning signal Y2 becomes H level, the TFTs 116 in the pixels in the 2nd row and the 1st column to the 2nd row and the 240th column are turned on, so that the data signals X1, X2, X3,. As a result, the positive voltage corresponding to the gradation is written in each of the pixel capacitors 120 in the first row and the first column to the first row and the 240th column.
Note that if the scanning signal Y2 is at the H level, the TFT 156 corresponding to the capacitor line 132 in the second row is turned on in the capacitor line driving circuit 150, but the TFT 158 is off (the scanning signal Y3 is at the L level). Therefore, the capacitor line 132 in the second row has a voltage Vsl. Therefore, the storage capacitor 130 in the second row, first column to the second row, 240th column has a difference between the positive voltage and the voltage Vsl corresponding to each gradation. A voltage will be written.

Next, the scanning signal Y2 becomes L level and the scanning signal Y3 becomes H level.
When the scanning signal Y2 becomes L level, in the capacitor line driving circuit 150, the TFT 156 corresponding to the capacitor line 132 in the first row is turned off and the TFT 158 is also turned off, so that the capacitor line 132 in the first row is electrically It becomes a high impedance state that is not connected anywhere. For this reason, the capacitor line 132 in the first row is held at the voltage Vsl in a state immediately before the TFT 158 is turned off by the parasitic capacitance, and thus the pixel capacitor 120 and the storage capacitor 130 in the first row and first column to the first row and 240 columns. The voltage held at the time does not change thereafter. After all, the pixel capacitance 120 in the first row and first column to the first row and 240th column has a difference between the voltage of the data signal applied to the pixel electrode 118 and the voltage LCcom of the common electrode 108 when the scanning signal Y1 becomes H level. The voltage, that is, the voltage corresponding to the gradation is continuously held.
Further, when the latch pulse Lp is output at the timing when the scanning signal Y3 becomes H level, the data line driving circuit 190 is the gradation of the pixels in the third row and in the first, second, third,. .., X240 are supplied to the data lines 114 of 1, 2, 3,..., 240 columns, respectively, whereby 3 rows 1 columns to 3 rows 240 are supplied. A positive voltage corresponding to each gradation is written in the pixel capacitors 120 in the column.
If the scanning signal Y3 is at the H level, in the capacitor line driving circuit 150, the TFT 156 corresponding to the capacitor line 132 in the third row is turned on, but the TFT 158 is off (the scanning signal Y4 is at the L level). Therefore, the capacitor line 132 in the third row has a voltage Vsl. Therefore, the storage capacitor 130 in the third row, first column to the third row, 240th column has a difference between the positive voltage and the voltage Vsl corresponding to each gradation. A voltage will be written.

In the n frame period in which the polarity instruction signal Pol is at the H level, the same operation is repeated until the scanning signal Y321 is at the H level, whereby all the pixel capacitors 120 are applied to the pixel electrode 118. Thus, the voltage difference between the data signal voltage and the voltage LCcom of the common electrode 108 is continuously held.

Next, the control circuit 20 will describe the operation of (n + 1) frames in which the polarity signal Pol becomes L level.
The operation of the (n + 1) frame is different from the operation of the n frame mainly in the following two points. That is, first, the control circuit 20 sets the first capacitance signal Vc1 to a voltage Vsh higher by ΔV than the voltage Vsl as shown in FIG. 4, and secondly, the scanning signal Yi is at the H level. When the latch pulse Lp is output at the timing, the data line driving circuit 190 performs n frames until the point at which the display data Da of the pixels in the 1, 2, 3,. However, the data signals X1, X2, X3,..., X240 are n frames in that they correspond to the display data Da and have a voltage corresponding to the negative polarity (this meaning will be described later). The operation is different.
Therefore, with respect to the operation in the (n + 1) frame, the voltage written in the pixel capacitor 120 in the i row and j column when the scanning signal Yi becomes H level is the scanning signal Y (i + 1), centering on this difference. It will be explained from the viewpoint of how it changes when the value becomes H level.

FIG. 5 is a diagram for explaining a voltage change of the pixel capacitor 120 of i rows and j columns in the (n + 1) frame.
First, when the scanning signal Yi becomes H level, as shown in FIG. 5A, the TFTs 116 in i rows and j columns are turned on, so that the data signal Xj is connected to one end (pixel electrode 118) of the pixel capacitor 120 and the storage capacitor. The voltage is applied to one end of 130. On the other hand, if the scanning signal Yi is at the H level, the TFT 156 corresponding to the i-th capacitor line 132 is turned on and the TFT 158 is kept off in the capacitor line driving circuit 150, so that the voltage of the i-th capacitor line 132 is maintained. Ci is the voltage Vsh of the first feeder 165. The common electrode 108 is constant at the voltage LCcom.
Therefore, if the voltage of the data signal Xj at this time is Vj, the pixel capacitor 120 in the i row and j column is charged with the voltage (Vj−LCcom), and the storage capacitor 130 is charged with the voltage (Vj−Vsh). The

Next, when the scanning signal Yi becomes L level, as shown in FIG. 5B, the TFTs 116 in the i rows and j columns are turned off. When the scanning signal Yi becomes L level, the next scanning signal Y (i +
1) becomes H level ((i + 1) row is not shown in FIG. 5B), the TFT 156 corresponding to the i-th capacitor line 132 is turned off and the TFT 158 is turned on in the capacitor line driving circuit 150. For this reason, the voltage Ci of the capacitance line 132 in the i-th row becomes the voltage Vsl of the second power supply line 167, which is lower by the voltage ΔV than when the scanning signal Yi is at the H level, but the common electrode 108 is Constant at voltage LCcom. Therefore, the charge stored in the pixel capacitor 120 moves to the storage capacitor 130, so that the voltage of the pixel electrode 118 decreases.
Specifically, in the serial connection of the pixel capacitor 120 and the storage capacitor 130, the other end (common electrode) of the pixel capacitor 120 is maintained at a constant voltage, and the other end of the storage capacitor 130 is reduced by the voltage ΔV. The voltage of the pixel electrode 118 also decreases.
Therefore, the voltage of the pixel electrode 118 that is the series connection point is
Vj− {Cs / (Cs + Cpix)} · ΔV
Therefore, the capacitance ratio {Cs / (Cs + Cpix) of the pixel capacitor 120 and the storage capacitor 130 is more than the voltage change ΔV of the capacitor line 132 in the i-th row than the voltage Vj of the data signal when the scanning signal Yi is at H level. )}. That is, the i-th capacitance line 1
When the voltage Ci of 32 is reduced by ΔV, the voltage of the pixel electrode 118 becomes {Cs / (Cs + Cpix)} · ΔV (= Δ) rather than the voltage Vj of the data signal when the scanning signal Yi is at the H level.
Vpix). However, the parasitic capacitance of each part is ignored.

Here, in the (n + 1) frame in which negative polarity writing is designated, the data signal Xj when the scanning signal Yi is at the H level is set to the voltage Vj in anticipation that the pixel electrode 118 is lowered by the voltage ΔVpix. . That is, the voltage of the pixel electrode 118 after being lowered is set to be lower than the voltage LCcom of the common electrode 108, and the difference voltage between the two is set to a value corresponding to the gradation of i rows and j columns.
Specifically, in the present embodiment, as shown in FIG. 7, in the n frame for positive polarity writing, the data signal has a voltage Vb (+) corresponding to black b from a voltage Vw (+) corresponding to white w. ), And when the voltage becomes higher than the voltage LCcom as the gradation becomes lower (darker), the voltage Vb ( In the case where the pixel is black b, the voltage Vw (+) is set to be the same as the positive voltage range and the gradation relationship is reversed. Second, after the voltage of the data signal is written in the (n + 1) frame, when the pixel electrode 118 is lowered by the voltage ΔVpix, the voltage of the pixel electrode 118 is changed from the voltage Vw (−) corresponding to negative white to black. And a decrease in the voltage ΔV of the capacitor line 132 is set so as to be symmetrical to the positive voltage with reference to the voltage LCcom.
As a result, in the (n + 1) frame designating the negative polarity writing, the voltage of the pixel electrode 118 when the voltage ΔVpix is lowered is a negative polarity voltage corresponding to the gradation, that is, the voltage Vw ( In the range from-) to the voltage Vb (-) corresponding to black b, the voltage shifts to a voltage lower than the voltage LCcom as the gradation becomes lower (darker).
In FIG. 5, the pixel capacitor 120 and the storage capacitor 130 in the i row and j column are described, but the same operation is similarly performed for the i row that also functions as the scanning line 112 and the capacitor line 132. In the (n + 1) frame, as in the n frame, the scanning signals Y1, Y2, Y3,..., Y320, Y321 are sequentially at the H level, so that the operation in each row is 1, 2, 3,. The processing is also performed in order for the 320 rows of pixels.

Therefore, in this embodiment, the voltage range a of the data line in the (n + 1) frame designating the negative polarity writing is the same as the n frame designating the positive polarity writing, but the voltage of the pixel electrode 118 after the shift. Becomes a negative voltage corresponding to the gradation. Thus, according to the present embodiment, not only the withstand voltage of the elements constituting the data line driving circuit 190 is reduced, but also the voltage amplitude in the data line 114 where the capacitance is parasitic is reduced, so that the parasitic capacitance is wasteful. Power is not consumed.
That is, when the pixel capacitor 120 is AC-driven in a configuration in which the common electrode 108 is maintained at the voltage LCcom and the voltage of the capacitor line 132 is constant over each frame, the pixel electrode 118 has a gradation in a certain frame. Accordingly, when writing is performed with a voltage in the range from the positive voltage Vw (+) to the voltage Vb (+), if there is no change in gradation, the voltage from the voltage Vw (−) corresponding to the negative polarity will be applied in the next frame. A voltage up to Vb (−) and inverted with respect to the voltage LCcom must be written. For this reason, in the configuration in which the voltage of the common electrode 108 is constant, when the voltage of the capacitor line 132 is constant, the voltage of the data signal covers the range b in the figure, so that the breakdown voltage of the elements constituting the data line driving circuit 190 is also in the range. It is not only necessary to correspond to b, but if the voltage changes in the range b in the data line 114 where the capacitance is parasitic, power is also wasted due to the parasitic capacitance. Such inconvenience is eliminated.

Furthermore, according to the present embodiment, as shown in FIG. 6, the voltage Ci of the capacitance line 132 in the i-th row in the frame instructing positive polarity writing is the TFT 156 when the scanning signal Yi becomes H level. Is turned on to become the voltage Vsl of the first feed line 165, and when the next scanning signal Y (i + 1) becomes the H level, the TFT 158 is turned on to become the voltage Vsl of the second feed line 167. For this reason, the voltage Ci of the capacitor line 132 in the i-th row does not change at the timing when the scanning signal Y (i + 1) becomes the H level in the frame instructing the positive writing.
On the other hand, the voltage Ci of the capacitor line 132 in the i-th row in the frame instructing negative polarity writing becomes the voltage Vsh of the first power supply line 165 by turning on the TFT 156 when the scanning signal Yi becomes H level. When the next scanning signal Y (i + 1) becomes H level, the TFT 158 is turned on, so that the voltage Vsl of the second feeder 167 is obtained. For this reason, the voltage Ci of the capacitance line 132 in the i-th row decreases by the voltage ΔV at the timing when the scanning signal Y (i + 1) becomes H level in the frame instructing negative polarity writing.
In the present embodiment, two TFTs 156 and 158 are sufficient to drive the capacitor line 132 for one row in this way, and no additional control signal or control voltage is required. Therefore, the configuration of the capacitor line driving circuit 150 that drives the capacitor line 132 corresponding to each row can be prevented from becoming complicated.
FIG. 6 is a diagram showing the voltage relationship among the scanning signal, the capacitor line, and the pixel electrode, and the voltage change of the pixel electrode 118 in i row and j column is indicated by Pix (i, j).

  Here, the voltage range of the data signal when the positive polarity writing is designated is matched with the voltage range of the data signal when the negative polarity writing is designated. The voltage amplitude of the data signal can be suppressed by the voltage change of the capacitor line 132.

In this description, by setting the second capacitance signal Vc2 to be constant at the voltage Vsl, when the scanning signal Y (i + 1) becomes H level in the n frame designating the positive writing, the i-th row While the voltage of the capacitor line 132 is not changed, when the scanning signal Y (i + 1) becomes H level in the (n + 1) frame designating negative polarity writing, the capacitor line 132 in the i-th row is lowered by the voltage ΔV. Thus, the pixel electrode 118 written when the scanning signal Yi is at the H level is decreased by the voltage ΔVpix, but this may be reversed.
That is, as shown in FIG. 8, by making the second capacitance signal constant at the voltage Vsh, when the scanning signal Y (i + 1) becomes H level in the frame designating negative polarity writing, i rows While the voltage of the capacitive line 132 of the eye is not changed, when the scanning signal Y (i + 1) becomes the H level in the frame designating the positive writing, the capacitive line 132 of the i-th row is raised by the voltage ΔV. The pixel electrode 118 written when the scanning signal Yi is at the H level may be raised by the voltage ΔVpix.
In this configuration, the voltage relationship of the data signal is reversed with respect to FIG. 7A and FIG. 7B with reference to the voltage LCcom, and positive writing is set to negative writing and negative writing is set to positive polarity. What is necessary is just to read each for sex writing.

Furthermore, in this explanation, the polarity to be written to the pixels in the period of one frame is all the same, and the surface inversion method is used in which the writing polarity is inverted every period of one frame, but the writing polarity is inverted every row. A scanning line (line) inversion method may be used.
When the scanning line inversion method is used, the polarity instruction signal Pol is inverted every horizontal scanning period (H) as shown in FIG. 9, and the same scanning signal becomes H level in adjacent frames ( This relationship is also reversed when viewed during a period in which the same scanning line is selected.
The first capacitance signal Vc1 becomes the voltage Vsl when the polarity instruction signal Pol is at the H level, and becomes the voltage Vsh when the polarity instruction signal Pol is at the L level.
Accordingly, in the n frame of FIG. 9, the odd-numbered (1, 3, 5,..., 319) rows of capacitor lines 132 are transferred to the next even (2, 4, 6,..., 320) rows of scanning lines 112. Even if the scanning signal becomes H level, the voltage does not change, but the capacitor line 132 in the even-numbered row decreases by the voltage ΔV when the scanning signal to the next odd-numbered scanning line 112 becomes H level. Therefore, in the n frame of FIG. 9, the positive polarity writing similar to that in FIG. 7A is executed in the odd-numbered rows, while the negative polarity writing similar to that in FIG. 7B is executed in the even-numbered rows.
On the other hand, in the (n + 1) frame in FIG. 9, the odd-numbered capacitor lines 132 decrease by the voltage ΔV when the scanning signal to the next even-numbered scanning line 112 becomes H level, The voltage of the capacitor line 132 does not change even when the scanning signal to the next odd-numbered scanning line 112 becomes H level. Therefore, in the (n + 1) frame of FIG. 9, the negative polarity writing similar to FIG. 7B is executed in the odd-numbered rows, while the positive polarity writing similar to FIG. 7A is executed in the even-numbered rows. .
In FIG. 9, the second capacitance signal Vc2 is the voltage Vsl. However, the voltage Vsh may be used to increase the voltage of the capacitance line 132 by ΔV.

Further, when the scanning line inversion method is used in this way, the second capacitance signal Vc2 may be constant at the voltage LCcom as shown in FIG.
When the second capacitance signal Vc2 is constant at the voltage LCcom, in the n frame of FIG. 10, when the scanning signal to the next even-numbered scanning line 112 becomes H level, The voltage Vsl rises to the voltage LCcom, and the capacitance line 132 in the even-numbered row falls from the voltage Vsh to the voltage LCcom when the scanning signal to the next odd-numbered scanning line 112 becomes H level, while (n + 1) ) In the frame, the odd-numbered capacitive lines 132 drop from the voltage Vsh to the voltage LCcom when the scanning signal to the next even-numbered scanning line 112 becomes H level. When the scanning signal to the next odd-numbered scanning line 112 becomes H level, the voltage rises from the voltage Vsl to the voltage LCcom.
Here, when the amount of increase from the voltage Vsl to the voltage LCcom and the amount of change from the voltage LCcom to the voltage Vsl are equally ΔV, as shown in FIG. The operation of shifting the voltage written when the signal becomes H level by the voltage ΔVpix by changing the capacitance line 132 of the i-th row by the voltage ΔV when the scanning signal Y (i + 1) becomes the H level. The positive polarity writing and the negative polarity writing are alternately executed every one frame period.

Here, the data signal has the same effect as in FIG. 4 if the voltage range a when the negative polarity writing is designated matches the voltage range a when the positive polarity writing is designated. . That is, as shown in FIG. 12, when the center of the voltage range a is set to coincide with the voltage LCcom in the n frame for positive polarity writing, and the voltage Vw (+) increases when the voltage ΔVpix increases. To the voltage Vb (+), and when the voltage ΔVpix falls, the voltage ΔV (= Vsh−LCcom = LCcom−) so as to shift to the range from the voltage Vw (−) to the voltage Vb (−). Vsl) may be set. However, in the voltage range a in FIG. 12, when positive polarity writing is specified, the white w side is low and the black b side is high, but when negative polarity writing is specified, the white w side is high and black b The side becomes low, and the relationship of gradation is reversed.
Note that even if the voltage range of the data signal when the positive polarity writing is designated and the voltage range of the data signal when the negative polarity writing is designated do not coincide with each other, the data changes due to the voltage change of the capacitor line 132. The voltage amplitude of the signal can be suppressed.

By the way, as shown in FIG. 3, the first power supply line 165 and the second power supply line 167 intersect with the scanning line 112 (while maintaining insulation), and thus parasitic capacitance is generated. Therefore, when the potentials of the first power supply line 165 and the second power supply line 167 change, useless power is consumed by this parasitic capacitance. In general, if the parasitic capacitance is C, the change voltage is V, and the change frequency (frequency) is f, the power consumption can be expressed by CV ² f. Therefore, as shown in FIG. 13, the voltage waveform of the second capacitance signal Vc2 is made the same as that of the first capacitance signal Vc1, and its voltage amplitude is made half of the first capacitance signal Vc1 in FIG. Then, as in the case of FIG. 9, a scanning line inversion method in which positive polarity writing and negative polarity writing are alternately executed for each scanning line is performed.
Here, the power consumption due to the parasitic capacitances of the first feed line 165 and the second feed line 167, respectively,
C (V / 2) ² f
However, since both the first feed line 165 and the second feed line 167 change, after all,
2C (V / 2) ² f = (1/2) CV ² f
Thus, compared with the case of FIG. 9, the power consumption by the first feeder 165 and the second feeder 167 can be halved.
Note that when the first capacitance signal Vc1 and the second capacitance signal Vc2 are changed as shown in FIG. 13, the voltage range of the data signal may be defined as shown in FIG. 12, for example.

On the other hand, as shown in FIG. 3, the capacitor line 132 intersects with the second feeder line 167 (while maintaining insulation), but does not intersect with the first feeder line 165. However, when a configuration other than the configuration shown in FIG. 3 is taken, for example, when the configuration is such that the capacitive line 132 intersects not only the second feed line 167 but also the first feed line 165, the capacitive line 132 is electrically coupled to both the first power supply line 165 and the second power supply line 167 via parasitic capacitances.
In particular, in this embodiment, if both the scanning signals Yi and Y (i + 1) are at the L level, the capacitor line 132 in the i-th row is in a high impedance state. When the voltage of the electric wire 167 changes, the voltage change may propagate to the capacitance line 132 through the parasitic capacitance, and the potential in the high impedance state may be changed. When both the scanning signals Yi and Y (i + 1) are at the L level, if the potential of the capacitor line 132 in the i-th row fluctuates, the charge accumulated in the pixel capacitor 120 moves, and the voltage corresponding to the gradation is changed. I want to suppress such voltage fluctuations as much as possible.
First, as shown in FIG. 14, the gate electrode of the TFT 158 in the i-th row is connected not to the (i + 1) -th scanning line 112 but to the (i + 2) -th scanning line 112 in the other row. Then, as shown in FIG. 15, as the first capacitance signal Vc1, the voltage Vsl is set when the polarity indicating signal Pol is at the H level, and the voltage Vsh is set when the polarity indicating signal Pol is at the L level. Sometimes, the voltage Vsl and Vsh of the first capacitance signal Vc1 may be interchanged as the voltage of the second capacitance signal Vc2.
When the first capacitance signal Vc1 and the second capacitance signal Vc2 are changed as shown in FIG. 15, the voltage range of the data signal may be defined as shown in FIG. 12, for example.

Thus, when the first capacitance signal Vc1 is the voltage Vsl, the second capacitance signal Vc2 is the voltage Vsh, and when the first capacitance signal Vc1 is the voltage Vsh, the second capacitance signal Vc2 is the voltage Vsl. When the complementary relationship is set, when the voltage of the first capacitance signal Vc1 changes, the second capacitance signal Vc2 changes in the opposite direction by the same voltage.
For this reason, if the parasitic capacitance between the capacitor line 132 and the first feeder line 165 and the parasitic capacitance between the capacitor line 132 and the second feeder line 167 are the same, the voltage change of the first feeder line 165 causes the capacitance line 132 to change. Is offset by the influence of the voltage change of the second power supply line 167 on the capacitance line 132. Therefore, the potential fluctuation of the capacitance line 132 in the high impedance state can be suppressed.

Further, in the case shown in FIG. 15, the voltage ΔV of the i-th capacitive line 132 is determined by the relative change between the first capacitive signal Vc1 and the second capacitive signal Vc2. Therefore, the amplitude of the capacitance signal is larger than that in the configuration (FIGS. 4, 8, 9, and 10) in which the voltage of the first capacitance signal Vc1 is changed while the voltage of the second capacitance signal Vc2 is constant. This is halved (this is also true for FIG. 13).
If the parasitic capacitance between the capacitor line 132 and the first feeder line 165 is different from the parasitic capacitance between the capacitor line 132 and the second feeder line 167, the first capacitance is changed according to the magnitude of the parasitic capacitance. The voltage amplitude of the capacitance signal Vc1 may be different from the voltage amplitude of the second capacitance signal Vc2.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. FIG. 16 is a block diagram illustrating a configuration of an electro-optical device according to the second embodiment of the invention.
The part shown in this figure is different from the first embodiment (see FIG. 1) in that an auxiliary capacitor 180 and a common power supply line 182 are provided. In this regard, the auxiliary capacitor 180 is provided corresponding to the capacitor lines 132 of 1 to 320 rows, one end is connected to the capacitor line 132, and the other end is connected to the common power supply line 182. The common power supply line 182 extends in the Y direction, is provided so as to intersect with each capacitor line 132, and is grounded to a constant potential, for example, the potential Gnd.

FIG. 17 is a plan view showing a configuration in the vicinity of the boundary between the capacitive line driving circuit 150 and the display region 100 in the element substrate in the second embodiment.
In this figure, the part different from the first embodiment (see FIG. 3) is that the capacitor line 132 is formed to be wide at the part intersecting the common power supply line 182, and the common power supply line 182 is the third part. The metal layer serving as the conductive layer is provided so as to overlap with the wide portion of the capacitor line 132 by patterning. Therefore, the auxiliary capacitor 180 has a configuration in which the gate insulating film is sandwiched between the capacitor line 132 and the common power supply line 182 as a dielectric.
A portion of the common power supply line 182 that intersects the scanning line 112 is formed to be narrower than a wide portion of the auxiliary capacitor 180.

As described above, the i-row capacitance line 132 is in a high impedance state if both of the scanning signals Yi and Y (i + 1) are at the L level, and therefore the voltage fluctuation of the portion coupled via the parasitic capacitance is reduced. Although easily affected (except for the example of FIG. 15), according to the second embodiment, the capacitor line 132 that has entered the high impedance state is the auxiliary capacitor that holds the voltage immediately before the high impedance state is established. 180 to keep it stable.
For this reason, according to the second embodiment, it is possible to prevent the voltage held in the pixel capacitor 120 from being changed due to the potential fluctuation of the capacitor line 132 and deviating from the target gradation.

Here, the purpose of the auxiliary capacitor 180 is that in the i-th row, the scanning signals Yi and Y (i + 1) are both at the L level, and the voltage of the i-th capacitor line 132 is set to be just before the TFT 158 is turned off. For example, the other end of the auxiliary capacitor 180 may be connected to the i-th scanning line 112. Even if the other end of the auxiliary capacitor 180 is connected to the i-th scanning line 112, the scanning signal Yi is kept constant at the L level over the period when the i-th capacitance line 132 is in the high impedance state. Thus, the same effect as that of the common power supply line 182 can be obtained.
Actually, the capacitor line 132 has various parasitic capacitances, parasitic capacitances of the TFTs 156 and 158 (particularly, capacitances of the gate / drain electrodes), and further, capacitance due to facing the common electrode 108. Even if it becomes a high impedance state due to the capacitance, it has a certain voltage holding property. However, as in the second embodiment, the potential of the capacitor line 132 can be further stabilized by positively providing the auxiliary capacitor 180.

<Third Embodiment>
When the scanning line inversion method is used (see FIGS. 9 and 10), the first capacitance signal Vc1 needs to be switched between the voltages Vsl and Vsh every horizontal scanning period (H). For this reason, if a capacitance is parasitic on the first power supply line 165 that supplies the first capacitance signal Vc1, power is wasted due to this voltage switching. A third embodiment that eliminates this point will be described.

FIG. 18 is a block diagram illustrating a configuration of an electro-optical device according to the third embodiment of the invention. The difference between the configuration shown in this figure and the first embodiment (see FIG. 1) is that, first, the control circuit 20 outputs two types as the first capacitance signal, and second, the capacitance line In the drive circuit 150, the source electrode of the TFT 156 corresponding to the odd-numbered capacitance line 132 is connected to the power supply line that supplies one of the two types of first capacitance signals, while the TFT 156 corresponding to the even-numbered capacitance line 132. The source electrode is connected to a power supply line that supplies the other.
Since the others are the same, the description thereof will be omitted, and in the following, this difference will be mainly described.

Specifically, the control circuit 20 supplies the first capacitance signals Vc1a and Vc1b to the first power supply lines 165a and 165b, respectively, instead of the first capacitance signal Vc1.
Here, as shown in FIG. 20, the first capacitance signal Vc1a is constant in voltage over each frame, is the voltage Vsl in the n frame, and switches to the voltage Vsh in the next (n + 1) frame. That is, in the first capacitance signal Vc1a, the voltages Vsl and Vsh are alternately switched every frame period.
On the other hand, the first capacitance signal Vc1b has a relationship in which the voltages Vsl and Vsh are interchanged with respect to the first capacitance signal Vc1a. That is, the first capacitance signal Vc1b becomes the voltage Vsh when the first capacitance signal Vc1a is the voltage Vsl in the n frame, and becomes the voltage Vsl when the first capacitance signal Vc1a is the voltage Vsh in the (n + 1) frame. The second capacitance signal Vc2 is constant at the voltage LCcom.
In the capacitor line driving circuit 150, the source electrode of the TFT 156 corresponding to the odd-numbered capacitor line 132 is connected to the first feeder line 165a, and the source electrode of the TFT 156 corresponding to the even-numbered capacitor line 132 is the first feeder line. 165b.

FIG. 19 is a plan view showing a configuration near the boundary between the capacitive line driving circuit 150 and the display region 100 in the element substrate in the third embodiment.
As shown in this figure, the second feed line 167 is positioned closer to the first feed line 165b in the odd-numbered i rows between the first feed lines 165a and 165b, and the first feed line in the even-numbered (i + 1) rows. Each line is folded so as to be positioned closer to the electric wire 165a.
The common semiconductor layers of the TFTs 156 and 158 cover the region from the first feed line 165a to the second feed line 167 with respect to the X direction in the odd-numbered i rows, and the number of the common semiconductor layers in the even-numbered (i + 1) rows with respect to the X direction. The second power supply line 167 is provided over a region from the first power supply line 165b. For this reason, the TFTs 156 and 158 corresponding to the odd-numbered i-th row and the TFTs 156 and 158 corresponding to the even-numbered (i + 1) -th row are in opposite relations to each other.
In the third embodiment, i is an odd number and (i + 1) is an even number for convenience.

In the third embodiment, in the n frame, the capacitance line 132 corresponding to the odd-numbered row becomes the voltage Vsl of the first capacitance signal Vc1a when the scanning signal of the same row becomes H level, and the scanning signal of the next row is H. Since the voltage LCcom of the second capacitance signal Vc2 is reached when the level is reached, the voltage rises by the voltage (LCcom−Vsl), while the scanning signal of the same row is at the H level in the capacitance line 132 corresponding to the even-numbered row. The voltage Vsh of the first capacitance signal Vc1b at this time, and the voltage LCcom of the second capacitance signal Vc2 when the scanning signal of the next row becomes the H level, so that the voltage (Vsh−LCcom) drops.
On the other hand, in the next (n + 1) frame, the capacity line 132 in the odd-numbered row drops by the voltage (Vsh−LCcom) when the scanning signal in the next row becomes H level, and the capacity line 132 in the even-numbered row. Increases by a voltage (LCcom−Vsl) when the scanning signal of the next row becomes H level.
Therefore, in the third embodiment, as in the example shown in FIGS. 9 and 10, the voltage of each capacitor line 132 changes, so that the data signal is supplied in the voltage range as shown in FIGS. Thus, the voltage to the pixel can be written by the scanning line inversion method.
In particular, according to the third embodiment, two first capacitance signals Vc1a and Vc1b are required. The voltage switching between the two first capacitance signals Vc1a and Vc1b is not a horizontal scanning period (H) but a frame. Therefore, it is possible to suppress power that is wasted due to parasitic capacitance due to voltage switching.

In each of the embodiments described above, in the capacitor line driving circuit 150, the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 is connected to the next (i + 1) -th scanning line 112, but (i + 1) A configuration in which the scanning lines 112 are connected to the scanning lines 112 separated by a certain number m (m is an integer of 2 or more), such as the scanning lines 112 after the first line, is sufficient. However, if m increases, it is necessary to connect the gate electrode of the TFT 158 corresponding to the capacitor line 132 in the i-th row to the scanning line 112 in the (i + m) -th row, and the wiring becomes complicated.
Further, in order to drive up to the TFT 158 corresponding to the capacitor line 132 in the final 320th row, m dummy scanning lines 112 are required. However, if m is “1” as in each embodiment, the blanking period Fb is eliminated and the gate electrode of the TFT 158 corresponding to the 320th capacitor line 132 is connected to the first scan line 112. For example, if m is “2”, the blanking period Fb is eliminated, and the gate electrodes of the TFTs 158 corresponding to the capacitor lines 132 in the 319th and 320th rows are respectively connected to the first and second rows. If it is configured to connect to the eye scanning line 112, it is not necessary to provide a dummy scanning line.
Furthermore, the voltage Vcom of the common electrode 108 is set to a low level when the positive polarity writing is designated,
A configuration may be adopted in which high-order switching is performed when negative polarity writing is designated.

In each embodiment, the liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108 as the pixel capacitor 120, and the electric field direction applied to the liquid crystal is set to the substrate surface vertical direction. A common electrode may be stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
On the other hand, in each embodiment, since the vertical scanning direction is a direction from the top to the bottom in FIG. 1, the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 is used as the (i + 1) -th scanning line. 112, but when the vertical scanning direction is the direction from the bottom to the top, it may be connected to the scanning line 112 in the (i-1) th row. That is, the gate electrode of the TFT 158 corresponding to the i-th capacitor line 132 is a scan line other than the i-th scan line, and is selected after the i-th scan line is selected. Any configuration may be used as long as it is connected to.

In each of the above-described embodiments, when the pixel capacitor 120 is taken as a unit, the writing polarity is inverted every frame period, because the pixel capacitor 120 is only for AC driving. The inversion period may be a period of two frames or more.
Furthermore, although the pixel capacitor 120 is in the normally white mode, it may be in a normally black mode in which the pixel capacitor 120 becomes dark when no voltage is applied. In addition, one dot may be formed by three pixels of R (red), G (green), and B (blue), and color display may be performed, and another color (for example, cyan (C)) may be used. In addition, one dot may be configured with these four color pixels to improve the color reproducibility.

In the above description, the reference of the writing polarity is the voltage LCcom applied to the common electrode 108. This is a case where the TFT 116 in the pixel 110 functions as an ideal switch. -Due to the parasitic capacitance between the drains, a phenomenon that the potential of the drain (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, penetration, field-through, etc.) occurs. In order to prevent the deterioration of the liquid crystal, the pixel capacitor 120 must be AC driven. However, if the AC driving is performed with the applied voltage LCcom applied to the common electrode 108 as a reference for the writing polarity, the negative polarity writing is performed for pushdown. The effective voltage value of the pixel capacitor 120 due to is slightly larger than the effective value due to positive polarity writing (when the TFT 116 is n-channel). For this reason, in actuality, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are separated, and more specifically, the reference voltage of the write polarity is set to the voltage LCcom so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.
Further, since the storage capacitor 130 is insulated in terms of direct current, it is sufficient that only the potential difference applied to the first feeder 165 and the second feeder 167 has the above-described relationship, for example, the voltage LCcom and The potential difference may be any number of volts.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 21 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 10 according to any of the embodiments.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 10 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that the components of the electro-optical device 10 corresponding to the display region 100 do not appear as appearance.

  As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 21, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the negative polarity writing of the same electro-optical apparatus. FIG. 6 is a voltage waveform diagram for explaining the operation of the same electro-optical device. It is a figure which shows the relationship between the data signal and holding voltage of the same electro-optical device. FIG. 6 is a diagram for explaining another operation (part 1) of the electro-optical device. FIG. 10 is a diagram for explaining another operation (part 2) of the same electro-optical device. FIG. 11 is a diagram for explaining another operation (part 3) of the same electro-optical device. It is a voltage waveform diagram for demonstrating another operation | movement (the 3). It is a figure which shows the relationship between the data signal and holding voltage in another operation | movement (the 3). FIG. 11 is a diagram for explaining yet another operation (part 4) of the same electro-optical device. It is a figure which shows another structure of the same electro-optical apparatus. FIG. 11 is a diagram for explaining yet another operation (No. 5) of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a third embodiment of the invention. FIG. 3 is a diagram illustrating a configuration of a boundary between a display area and a capacitive line driving circuit of the electro-optical device. FIG. 6 is a diagram for explaining an operation of the electro-optical device. It is a figure which shows the structure of the mobile telephone using the electro-optical apparatus which concerns on embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 20 ... Control circuit, 100 ... Display area, 108 ... Common electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 120 ... Pixel capacity, 130 ... Storage capacity, 132 ... capacitance line, 140 ... scanning line drive circuit, 150 ... capacitance line drive circuit, 156, 158 ... TFT, 165, 165a, 165b ... first feed line, 167 ... second feed line, 180 ... auxiliary capacitor, 182 ... auxiliary Feed line, 1200 ... mobile phone

Claims (3)

Scanning lines arranged in the row direction ;
Data lines arranged in the column direction ;
And capacity lines provided corresponding to the front Kihashi査線,
And pixel electrodes provided corresponding to intersections of the front Kihashi査線before Kide over data lines,
A common electrode forming a pixel capacitance with the pixel electrode;
A capacitor electrode that forms a storage capacitor with the pixel electrode and is connected to the capacitor line;
A scanning line driving circuit for selecting the scanning lines,
Relative to the capacitor line, the potential of the first feeder line is applied when the scanning line is selected, the next row or the scanning lines from the scanning line a predetermined row spaced scan lines of the scan lines A capacitive line driving circuit that applies a potential of a second power supply line different from the potential of the first power supply line when a scanning line to be selected later is selected,
The first feeder line is divided into an odd line and an even line,
The first power supply line corresponding to the odd row is connected to a capacitor line corresponding to the odd row,
The first power supply line corresponding to the even-numbered row is connected to a capacitor line corresponding to the even-numbered row;
One of two potentials, which are lower and higher than the potential of the second feeder line, is applied to the first feeder line corresponding to the odd row, and the other is applied to the first feeder line corresponding to the even row. In addition, the drive circuit of the electro-optical device , wherein the two different voltages are exchanged at a predetermined cycle . An electro-optical device comprising the drive circuit for the electro-optical device according to claim 1 . An electronic apparatus comprising the electro-optical device according to claim 2 .

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