JP4924720B2 - Semiconductor memory having self-timing circuit - Google Patents

Description

  The present invention relates to a semiconductor memory having a sense amplifier circuit for reading data held in a memory cell, and more particularly to a self-timing circuit for controlling the activation timing of a sense amplifier activation signal in accordance with the characteristics of an internal memory cell. The present invention relates to a semiconductor memory in which a data read margin is improved.

  Generally, static RAM (Static RAM, hereinafter referred to as SRAM) has a memory cell array in which memory cells in which a pair of inverters are cross-connected are arranged in a matrix. In each memory cell, the interconnection point of the inverter pair is connected to the bit line pair via a pair of transfer transistors, and the gate of the transfer transistor pair is connected to the word line. The bit line pair is connected to a sense amplifier circuit.

  In the read operation of the SRAM, first, a clock signal and an address signal are supplied from the outside, and a corresponding word line is selected by decoding the address signal in synchronization with the clock signal. Selection of the word line turns on the transfer transistor pair of the corresponding memory cell, whereby the inverter pair of the corresponding memory cell is connected to the bit line pair. The bit line pair is driven based on data held in the inverter pair of the memory cell. The potential difference between the driven bit line pair is amplified by the sense amplifier circuit in response to the sense amplifier activation signal, and the data held in the memory cell is read out. Conventionally, a generation circuit using a self-timing circuit is known as a generation circuit for a sense amplifier activation signal that activates a sense amplifier circuit in the above-described read operation. (For example, see Patent Document 1.)

FIG. 1 is a schematic diagram of a circuit configuration of an SRAM having a conventional self-timing circuit.
The conventional self-timing circuit 11 includes at least one self-timing dummy memory cell SDMC, a dummy word line DWL for selecting a dummy memory cell, and a dummy bit line pair DBL for detecting data held in the dummy memory cell. , XDBL, and a timing control circuit 12 that generates a self-timing signal SLF based on the potentials of the dummy bit line pair DBL, XDBL. Similar to the normal memory cell MC in the memory cell array, the self-timing dummy memory cell SDMC has an inverter pair and a transfer gate pair.

  The self-timing dummy memory cells SDMC are sequentially arranged from the position farthest from the timing control circuit 12 on the dummy bit line pair DBL, XDBL. In order to match the load caused by the wiring capacity of the dummy word line DWL and the dummy bit line pair DBL, XDBL to that of the word line WL and the bit line pair BL, XBL in the memory cell array MCA, the dummy word line DWL and the dummy bit line A plurality of load dummy memory cells LDMC are provided for the pair DBL and XDBL, respectively.

  The operation of the conventional self-timing circuit 11 will be described with reference to FIG. As shown in FIG. 2, the dummy word line DWL is selected in synchronization with the selection of a predetermined word line WL in the memory cell array MCA. By selecting the dummy word line DWL, the transfer gate pair of the self-timing dummy memory cell SDMC is turned on, and the inverter pair of the self-timing dummy memory cell SDMC is connected to the dummy bit line pair DBL and XDBL and driven by the dummy The bit line pair DBL, XDBL generates a predetermined potential difference.

  The timing control circuit 12 detects the potential of one of the dummy bit line pair DBL and XDBL (XDBL in the figure), and when the potential of the dummy bit line (XDBL) to be detected becomes smaller than a predetermined value The self-timing signal SLF is activated. The self-timing signal SLF is supplied to the control circuit 13 and is delayed by a predetermined time by a delay circuit 14 provided in the control circuit 13. The control circuit 13 supplies the output signal of the delay circuit 14 to the sense amplifier circuit 14 as the sense amplifier activation signal SA. In response to the supplied sense amplifier activation signal SA, the sense amplifier circuit 14 amplifies the potential difference between the bit line pair BL and XBL driven by the selected normal memory cell MC, and reads the retained data.

  At this time, the drive capability for the dummy bit line pair DBL and XDBL is adjusted by adjusting the load of the load dummy memory cell LDMC, and the activation amount of the sense amplifier activation signal SA is adjusted by adjusting the delay amount of the delay circuit 14. Adjust to the optimal timing.

  Here, even if the driving capability of the normal memory cell MC in the memory cell array MCA varies due to manufacturing variations, the driving capability of the dummy memory cell SDMC also varies in the same manner because it is manufactured in the same manufacturing process. Have. That is, when the drive capability of the normal memory cell MC varies in a direction that becomes faster, the drive capability of the dummy memory cell SDMC also varies in a direction that becomes faster. In the generation circuit of the sense amplifier activation signal using the self-timing circuit 11 of FIG. 1, the activation timing of the sense amplifier activation signal SA is determined based on the potentials of the dummy bit line pair DBL and XDBL driven by the dummy memory cell SDMC. Therefore, the activation timing of the sense amplifier activation signal SA can be automatically adjusted to the optimum timing according to the manufacturing variation of the driving capability of the normal memory cell MC.

  On the other hand, in the load dummy memory cell LDMC connected to the dummy bit line pair DBL, XDBL, the gate potential is set so that the transfer transistor pair is always turned off. Therefore, originally, the load dummy memory cell LDMC only adds the same wiring capacitance as the memory cell array MCA to the dummy bit line pair DBL and XDBL, and does not drive the dummy bit line pair DBL and XDBL. .

However, in recent years, miniaturization of semiconductor integrated circuits has progressed, and in an actual SRAM, the leakage current I _leak in the off state of the transfer transistor in the memory cell cannot be ignored. Therefore, in an actual SRAM, the dummy bit line pair DBL, XDBL is also driven by the above-described off-leakage current I _{leak in} the load dummy memory cell LDMC.

When the dummy bit line (XDBL) to be detected by the timing control circuit 12 is driven by the off-leak current I _leak of not only the self-timing dummy memory cell SDMC but also the load dummy memory cell LDMC, the off-leak current I _leak The decrease rate of the potential of the dummy bit line (XDBL) to be detected is increased by the amount of driving. As a result, the activation timing of the self-timing signal SLF becomes earlier than the original timing, and the sense amplifier activation signal SA is activated earlier than the original timing correspondingly. As a result, there is a possibility that erroneous reading of data held in the normal memory cell MC may occur in the sense amplifier circuit 14.

On the other hand, which bit line of the dummy bit line pair DBL and XDBL is pulled down in the L level direction by the off-leakage current I _leak depends on the data held by the load dummy memory cell LDMC. Determined. The data held in the load dummy memory cell LDMC is arbitrarily determined when the SRAM is powered on when the connection node of the inverter pair is in a floating state, and is unspecified unlike the self-timing dummy memory cell SDMC.

In consideration of the above, in order to minimize the influence of driving due to the off-leakage current I _leak of the dummy memory cell for load LDMC on the dummy bit line (XDBL) to be detected by the timing control circuit 12, In the timing circuit 11, a technique is known in which the data held in the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC connected to the dummy bit line pair DBL, XDBL are set to be opposite to each other. . (For example, see Patent Document 1.)

  FIG. 3 shows an example of a setting pattern of data held in the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC connected to the dummy bit line pair DBL, XDBL. As shown in FIG. 3, the potential of the connection nodes n1 and n2 of the inverter pair INV1 and INV2 is fixed reversely between the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC. Yes.

With this configuration, the potential of the dummy bit line XDBL is lowered to the L level only by the self-timing dummy memory cell SDMC, while all the load dummy memory cells LDMC are driven by the off-leak current to the dummy bit line DBL. . Since the self-timing signal SLF is generated based on the potential of the dummy bit line XDBL, it is possible to prevent the activation timing of the sense amplifier activation signal SLF from being earlier than the original timing due to the influence of driving due to the off-leakage current I _leak. it can.

However, even in the self-timing circuit 11 shown in FIG. 3, when the SRAM is in a high temperature state due to a change in ambient temperature or the like, the amount of off-leakage current I _leak increases, thereby causing the sense amplifier circuit 14 to There is a problem that erroneous reading may occur.

  FIG. 4 is a diagram for explaining the above-described problem. Consider a case in which all of the data held in the non-selected memory cells is the reverse of the data held in the selected memory cell in the bit line pair BL, XBL to which the selected memory cell is connected in the memory cell MCA.

As shown in FIG. 4, in this case, when the amount of off-leakage current I _leak increases, one bit line (BL in the figure) is greatly lowered in the L-level direction by the inverter pair of the selected memory cell and the other bit The line (XBL in the figure) is also pulled down in the L level direction by the off-leakage current I _leak of the unselected memory cell, and the potential of the bit line XBL decreases with time. Therefore, in the above case, the timing at which the potential difference between the bit line pair BL and XBL becomes the predetermined potential difference is the latest.

On the other hand, in the self-timing circuit 11 shown in FIG. 3, the self-timing signal SLF is applied to the dummy memory cells SDMC and LDMC so that the influence of the drive due to the off-leak current I _leak on the dummy bit line XBL to be detected is minimized. After holding data is set, it is activated by detecting the potential of only the dummy bit line XDBL. For this reason, the activation timing of the self-timing signal SLF is hardly affected by the magnitude of the off-leakage current I _leak . That is, the sense amplifier activation signal SA is activated at almost the same timing regardless of the magnitude of the off-leakage current I _leak .

Therefore, when the off-leakage current I _leak increases, the activation timing of the sense amplifier activation signal SA may be earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL, and erroneous reading of retained data may occur. There is.

  FIG. 5 shows a layout example of dummy memory cells SDMC and LDMC in the conventional self-timing circuit of FIG. As shown in FIG. 5, the conventional dummy memory cell is laid out as a unit including a portion composed of an inverter pair and a transfer transistor pair.

  A conventional dummy memory cell includes a normal layout unit 51 including inverters 53 and 54 and a transfer transistor pair 57, and a symmetrical layout unit including inverters 55 and 56 and a transfer transistor pair 58 having a point-symmetrical or line-symmetrical relationship with the normal layout unit 51. 52 are alternately arranged along the dummy bit line pair DBL, XDBL.

  As the self-timing dummy memory cell SDMC, for example, a plurality of dummy memory cells are designated in order from the position farthest from the timing control circuit 12 on the dummy bit line. In FIG. 5, the gates of the transfer transistor pairs 57, 58 of the self-timing dummy memory cells SDMC1, 2 are connected to a common dummy word line DWL (not shown), and the gates of the transfer transistor pairs of the load dummy memory cells LDMC1, 2 are Connected to ground VSS.

  In the drawing, the white area represents the impurity diffusion layer on the semiconductor wafer, and the deep hatched area represents the gate polysilicon layer formed on the semiconductor wafer. A broken line represents a local wiring in the memory cell, a thick line represents dummy bit lines DBL and XDBL, and a circle represents a contact with the dummy bit line. Further, as can be seen from FIG. 5, in each of the normal layout unit 51 and the symmetrical layout unit 52, the layouts of the two inverters constituting the inverter pair are not line-symmetric with each other.

  Here, in the layout example of the dummy memory cell in FIG. 5, when misalignment occurs between the impurity diffusion layer and the gate polysilicon layer in the photoetching step of the manufacturing process or the like, erroneous reading of data retained in the memory cell MC is performed. There is a problem that may occur.

  As shown in FIG. 6, the actual finished shape is rounded at the corners of the impurity diffusion layer and the gate polysilicon layer. For this reason, when the above-described misalignment occurs, for example, when the gate polysilicon layer is entirely displaced in the lower left direction in the figure with respect to the impurity diffusion layer (see FIG. 6), the normal layout unit 51 and the symmetrical layout unit At 52, there is a difference in drive capability between the inverters constituting the inverter pair.

  Specifically, in the normal layout unit 51, due to the position shift in the lower left direction, the characteristics of the inverter change as follows. That is, in the inverter 54 located on the left side, the channel length is shortened in the upper transistor, and in the lower transistor, the channel length is lengthened and the channel width is narrowed. The channel length is increased, and the channel width is increased in the lower transistor.

  On the other hand, in the symmetrical layout unit 52, the characteristics of the inverter change as follows due to the position shift in the lower left direction. That is, in the inverter 56 located on the left side, the channel width is narrowed in the upper transistor and the channel length is shortened in the lower transistor, whereas in the inverter 55 located on the right side, the channel length is shortened in the upper transistor, The channel width is increased, and the channel length is increased in the lower transistor.

  As described above, the driving ability is different between the four inverters 53 to 56 constituting the inverter pair of the normal layout unit 51 and the symmetric layout unit 52 due to the positional deviation. As a result, there is a difference in driving capability between the dummy memory cell SDMC1 having the normal layout unit 51 and the dummy memory cell SDMC2 having the symmetric layout unit 52 according to the positional deviation.

  Correspondingly, the driving capability for the dummy bit line XDBL to be detected by the timing control circuit 12 also changes in accordance with the positional deviation. As a result, the activation timing of the self-timing signal SLF also changes in accordance with the positional deviation, which may be earlier than the original timing.

  On the other hand, the memory cells MC in the memory cell array MCA also have a layout similar to the layout example of the dummy memory cells SDMC and LDMC in FIG. 5 for the bit lines BL and XBL. For this reason, when the misalignment occurs and the memory cell MC selected at the time of reading is a cell having a layout unit with a smaller driving ability of the normal layout unit 51 and the symmetrical layout unit 52, the bit line pair BL, There is a possibility that the timing at which a predetermined potential difference occurs in XBL is later than the original timing.

  Accordingly, the activation timing of the sense amplifier activation signal SA becomes earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL according to the positional deviation, and there is a possibility that held data is erroneously read. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that can prevent erroneous reading of data held in a normal memory cell MC even when an interlayer displacement occurs in the manufacturing process.

JP 2003-36678 A

  An object of the present invention is to provide a semiconductor memory that can surely prevent erroneous reading of data held in a normal memory cell MC regardless of various device characteristic variation factors such as manufacturing variations.

  According to the first aspect of the present invention for achieving the above-described object, a plurality of word lines, a plurality of bit lines, and a plurality of word lines arranged at intersections of the plurality of word lines and the plurality of bit lines are provided. A semiconductor memory comprising: a memory cell array having a plurality of memory cells; and a self-timing circuit that is disposed in the vicinity of the memory cell array and generates a self-timing signal that determines an operation timing of an internal circuit when the memory cell is read, In the self-timing circuit, a dummy word line selected in response to the selection of the word line and a plurality of first self-timing dummy memory cells connected to the dummy word line and configured by a normal layout unit are consecutive. A first dummy bit line arranged in a row and the normal layout unit connected to the dummy word line. A second dummy bit line in which a plurality of second self-timing dummy memory cells composed of symmetrical layout units having a point-symmetrical or line-symmetrical relationship with the second dummy bit are arranged in succession, and the first dummy bit And a second dummy bit line are input, and the self-timing signal is output based on the potential change of the dummy bit line having the slower potential change speed of the first and second dummy bit lines. And a control circuit.

  According to the first aspect described above, in the semiconductor memory of the present invention, the activation timing of the sense amplifier activation signal SA even when a positional shift occurs between the impurity diffusion layer and the gate polysilicon layer due to manufacturing variation or the like. Therefore, the activation timing of the sense amplifier activation signal SA can be earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC. It is possible to prevent erroneous reading of retained data.

  Therefore, in the semiconductor memory of the present invention, it is possible to reliably prevent erroneous reading of data held in the normal memory cell MC regardless of various device characteristic fluctuation factors such as manufacturing variations.

It is the schematic of the circuit structure of SRAM provided with the conventional self-timing circuit. It is a figure for demonstrating operation | movement of the conventional self-timing circuit. It is a figure which shows the example of the setting pattern of the retention data of the dummy memory cell for self-timing connected to the dummy bit line pair of the conventional self-timing circuit, and the dummy memory cell for load. It is a figure for demonstrating the problem of SRAM provided with the conventional self-timing circuit. It is a figure which shows the example of a layout of the dummy memory cell in the conventional self-timing circuit. It is a figure which shows a layout in case the gate polysilicon layer has shifted | deviated entirely to the lower left direction in the figure with respect to the impurity diffusion layer in the conventional layout example. It is a schematic block diagram which shows 1st Embodiment. FIG. 6 is a diagram illustrating a setting pattern of data held in a timing dummy memory cell and a load dummy memory cell in each dummy bit line pair in the self-timing circuit according to the first embodiment. 1 is a schematic diagram illustrating a circuit configuration of a timing control circuit according to a first embodiment. It is a figure for demonstrating operation | movement of the timing control circuit of 1st Embodiment. It is a figure for demonstrating 2nd Embodiment. It is a figure for demonstrating 3rd Embodiment. It is a figure for demonstrating operation | movement of the timing control circuit of 3rd Embodiment. It is a schematic block diagram which shows 4th Embodiment. It is the schematic which shows the circuit structure of the timing control circuit of 4th Embodiment. It is a figure for demonstrating operation | movement of the timing control circuit of 4th Embodiment. It is a figure for demonstrating 5th Embodiment. It is a figure for demonstrating 6th Embodiment. It is a figure for demonstrating 7th Embodiment. It is a figure for demonstrating 8th Embodiment. It is a figure for demonstrating 9th Embodiment. It is a figure for demonstrating 10th Embodiment. It is a schematic block diagram which shows 11th Embodiment. It is a figure which shows the example of a layout of the dummy memory cell in each dummy bit line pair of the self-timing circuit of 11th Embodiment. In the layout example of 11th Embodiment, it is a figure which shows a layout in case a gate polysilicon layer has shifted | deviated to the direction of the lower left in the figure entirely with respect to an impurity diffusion layer. In the layout example of 11th Embodiment, it is a figure which shows a layout in case a gate polysilicon layer has shifted | deviated to the direction of the lower left in the figure entirely with respect to an impurity diffusion layer. It is the schematic which shows the circuit structure of the timing control circuit of 11th Embodiment. It is a figure for demonstrating operation | movement of the timing control circuit of 11th Embodiment. It is a figure for demonstrating 12th Embodiment. FIG. 38 is a diagram illustrating a layout example of dummy memory cells in a dummy bit line pair of the self-timing circuit according to the twelfth embodiment. It is a figure which shows a layout in case the gate polysilicon layer has shifted | deviated entirely to the lower left direction in the figure with respect to the impurity diffusion layer in the layout example of 12th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. However, such embodiments do not limit the technical scope of the present invention, and the technical scope of the present invention extends to the claims and their equivalents.

  FIG. 7 is a schematic configuration diagram showing the first embodiment of the present invention. The SRAM shown in FIG. 7 has a self-timing circuit as a generation circuit of a sense amplifier activation signal that activates the sense amplifier circuit. The SRAM circuit configuration shown in FIG. 6 differs from the conventional circuit configuration shown in FIG. 1 in that the self-timing circuit 11 is replaced with a self-timing circuit 61, and the other configurations are the same.

  The self-timing circuit 61 of FIG. 7 has two pairs of dummy bit lines DBL1, XDBL1, DBL2, and XDBL2. Each dummy bit line pair has at least one self-timing dummy memory cell SDMC and a plurality of load dummy memory cells LDMC, as in the self-timing circuit 11 of FIG.

  The pattern of data held in the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC differs between the dummy bit line pairs DBL1, XDBL1, DBL2, and XDBL2. In each dummy bit line pair, for example, a plurality of dummy memory cells are designated as the self-timing dummy memory cell SDMC in order from the position farthest from the timing control circuit 62 on the dummy bit line.

  Of the first pair of dummy bit lines DBL1, XDBL1, the dummy bit line XDBL1 is connected to the timing control circuit 62 as a dummy bit line to be detected. Of the second dummy bit line pair DBL2, XDBL2, the dummy bit line pair XDBL2 is connected to the timing control circuit 62 as a dummy bit line to be detected. The timing control circuit 62 receives the dummy bit lines XDBL1 and XDBL2, and outputs a self timing signal SLF based on the detection result of the potentials of the dummy bit lines XDBL1 and XDBL2.

  The dummy memory lines SDMC for self-timing of the dummy bit line pairs DBL1, XDBL1, DBL2, and XDBL2 are connected to a common dummy word line DWL. By selecting the dummy word line DWL, all the self-timing dummy memory cells SDMC are simultaneously selected.

  FIG. 8 is a diagram illustrating a setting pattern of data held in the dummy memory cell for timing SDMC and the dummy memory cell for load LDMC in the dummy bit line pair DBL1, XDBL1, DBL2, and XDBL2 in the self-timing circuit 61.

As shown in FIG. 8, the retention data setting pattern in the first dummy bit line pair DBL1, XDBL1 is the same as the conventional setting pattern shown in FIG. That is, a setting pattern is obtained in which the potentials of the connection nodes n1 and n2 of the inverter pair INV1 and INV2 are fixed opposite to each other between the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC. In the setting pattern of the first dummy bit line pair DBL1, XDBL1, the influence of the drive due to the off-leakage current I _leak of the dummy memory cell for load LDMC on the dummy bit line XDBL1 to be detected by the timing control circuit 62 is minimized. Thus, the dummy bit line XDBL1 is driven only by the self-timing dummy memory cell SDMC.

On the other hand, the holding data setting pattern in the second dummy bit line pair DBL2, XDBL2 is the connection node n1 of the inverter pair INV1, INV2 between the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC. , N2 potentials are all fixed at the same potential. The setting pattern of the second dummy bit line pair DBL2, XDBL2 is set so that the influence of the off-leakage current I _leak of the load dummy memory cell LDMC is maximized on the dummy bit line XDBL2 to be detected. XDBL2 is driven by the self-timing dummy memory cell SDMC and is driven by the off-leakage current I _leak of all the load dummy memory cells LDMC.

Therefore, the difference in drive capability between the dummy bit lines XDBL1 and XDBL2 is caused by the drive by the off-leak current I _leak of the load dummy memory cell LDMC. The difference in time from when the dummy word line DWL is selected until the potential of the dummy bit lines XDBL1 and XDBL2 becomes a predetermined value varies depending on the amount of off-leakage current I _leak of the load dummy memory cell LDMC.

  FIG. 9 is a schematic diagram showing a circuit configuration of the timing control circuit 62. As shown in FIG. 9, the timing control circuit 62 includes a delay control unit 81, an inverter 82, and a delay control signal generation unit 83.

  The delay control signal generation unit 83 includes an inverter 84, an inverter 85, and an EXOR circuit 86. The inverters 84 and 85 have, for example, the same threshold voltage. Inverter 84 receives dummy bit line XDBL1 and outputs an H level signal to EXOR circuit 86 in response to the potential of dummy bit line XDBL1 becoming lower than a predetermined threshold voltage. Inverter 85 receives dummy bit line XDBL2, and outputs an H level signal to EXOR circuit 86 in response to the potential of dummy bit line XDBL2 becoming lower than the threshold voltage. The EXOR circuit 86 receives the output signals of the inverters 84 and 85 and generates a delay control signal DCNT by taking an exclusive OR of the two output signals.

  The delay control unit 81 includes a transfer switch 87 and an inverter 88. The transfer switch 87 includes a PMOS transistor and an NMOS transistor whose sources and drains are connected to each other, and connects the dummy bit line XDBL1 to the input node of the inverter 82. The delay control signal DCNT from the delay control signal generator 83 is supplied as it is to the gate of the PMOS transistor, and the delay control signal DCNT is supplied to the gate of the NMOS transistor via the inverter 88. The delay control unit 81 receives the dummy bit line XDBL1 and the delay control signal DCNT, delays the potential of the dummy bit line XDBL1 by a predetermined time based on the delay control signal DCNT, and outputs it to the input node of the inverter 82.

  Inverter 82 receives an output signal from delay control unit 81, and activates self-timing signal SLF in response to the potential of the output signal being lower than a predetermined value.

  The operation of the timing control circuit 62 will be described below with reference to FIG. When a predetermined word line WL in the memory cell array MCA is selected and the dummy word line DWL is selected in response thereto, the potentials of the dummy bit lines XDBL1 and XDBL2 are changed from the precharge level (H level) to the L level. Be lowered.

Here, as described above, there is a difference between the driving capabilities for the dummy bit lines XDBL1 and XDBL2 due to the driving due to the off-leakage current I _leak of the dummy memory cell for load LDMC, and the rate of decrease in the potential of the dummy bit line XDBL2 Is faster than that of the dummy bit line XDBL1 by an amount corresponding to the amount of off-leakage current I _leak .

For this reason, the timing t1 when the output signal of the inverter 85 becomes H level is earlier than the timing t2 when the output signal of the inverter 84 becomes H level by a period corresponding to the amount of off-leakage current I _leak . Therefore, the delay control signal DCNT generated by the EXOR circuit 86 has an H level period Δt having a length depending on the amount of the off leak current I _leak . The H level period Δt becomes longer as the amount of off-leakage current I _leak increases.

  The transfer switch 87 of the delay control unit 81 operates in response to the delay control signal DCNT having the H level period Δt. The transfer switch 87 is turned on during the H level period Δt and turned off during periods other than the H level period Δt. Therefore, the potential change at the input node n3 of the inverter 82 is as follows.

  In a period before the timing t1, the transfer switch 87 is turned on, so that the potential of the input node n3 is lowered from the precharge level (H level) to the L level following the decrease in the potential of the dummy bit line XDBL1. In the period from the timing t1 to the timing t2 (H level period Δt), the transfer switch 87 is turned off, so that the potential of the input node n3 does not follow the decrease in the potential of the dummy bit line XDBL1, and is kept at the potential at the timing t1. Is done. Since the transfer switch 87 is turned on in the period after the timing t2, the potential of the input node n3 changes again following the decrease in the potential of the dummy bit line XDBL1, and is lowered from the potential at the timing t1 to the L level.

  Inverter 82 activates and outputs self-timing signal SLF at timing t3 when the potential of input node n3 becomes smaller than the threshold voltage. The threshold voltage of the inverter 82 is desirably set smaller than the threshold voltages of the inverters 84 and 85.

  As can be seen from FIG. 10, the waveform of the potential change of the input node n3 after the timing t2 is obtained by shifting the waveform of the potential change of the dummy bit line XDBL1 after the timing t1 by the H level period Δt. For this reason, the activation timing t3 of the self-timing signal SLF in the timing control circuit 62 is delayed by the H level period Δt compared to the activation timing t4 in the conventional case determined directly from the potential of the dummy bit line XDBL1. become.

As described above, since the H level period Δt becomes longer as the amount of off-leakage current I _leak increases, self-timing circuit 61 determines the activation timing of self-timing signal SLF for off-leakage current I _leak of dummy memory cell for load LDMC. The delay according to the amount of current can be delayed, and the delay amount of the activation timing of the self-timing signal SLF can be increased as the amount of off-leakage current I _leak increases.

Therefore, in the first embodiment of the present invention, as shown in FIG. 10, even when the off-leakage current I _leak increases due to a change in ambient temperature or the like, the activation timing of the sense amplifier activation signal SA is off-leaked. Since the delay according to the current amount of the current I _leak can be delayed, the activation timing of the sense amplifier activation signal SA is earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC. And erroneous reading of retained data can be prevented.

  Next, a second embodiment of the present invention will be described with reference to FIG. The circuit configuration of the second embodiment of the present invention is different from the circuit configuration of the first embodiment shown in FIG. 7 in that the timing control circuit 62 is replaced with a timing control circuit 101. Since other configurations are the same, description thereof is omitted. FIG. 11 shows a circuit configuration of the timing control circuit 101 according to the second embodiment.

  As shown in FIG. 11, the timing control circuit 101 is different in that the delay control unit 81 is replaced with a delay control unit 102 in the timing control circuit 62 of FIG. 9. Other configurations are the same, and description thereof is omitted.

  The delay control unit 102 includes a switch transistor 103, an additional capacitor 104, and an inverter 105. The switch transistor 103 and the additional capacitor 104 are connected in series between the input node n3 of the inverter 82 and the ground VSS. The switch transistor 103 includes a PMOS transistor and an NMOS transistor whose sources and drains are connected to each other. A delay control signal DCNT from the delay control signal generator 83 is supplied to the gate of the PMOS transistor via the inverter 105, and the NMOS transistor The gate is supplied with the delay control signal DCNT as it is.

  The delay control unit 102 receives the dummy bit line XDBL1 and the delay control signal DCNT, delays the potential of the dummy bit line XDBL1 by a predetermined time based on the delay control signal DCNT, and outputs it to the input node n3 of the inverter 82. The operation of the delay control unit 102 will be described below.

  The switch transistor 103 is turned on only during the H level period Δt of FIG. 10 in response to the delay control signal DCNT, and connects the additional capacitor 104 to the input node n3. For this reason, the wiring capacitance at the input node n3 is the parasitic capacitance plus the additional capacitance 104 only during the H level period Δt (the period from timing t1 to timing t2), and the period before timing t1 and after timing t2 Compared with that of the increase greatly. Correspondingly, the rate of decrease in the potential of the input node n3 is greatly reduced only during the period from the timing t1 to the timing t2, compared to the period before the timing t1 and the period after the timing t2.

  Therefore, during the period from the timing t1 to the timing t2, the amount of decrease in the potential of the input node n3 from the potential at the timing t1 can be reduced, whereby the potential of the input node n3 is held approximately at the potential at the timing t1. be able to. Therefore, the potential change at the input node n3 in the timing control circuit 101 is the same as that in the timing control circuit 62 shown in FIG.

Therefore, in the second embodiment of the present invention, as in the first embodiment, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA is set to the off-leak current I _leak . Since it can be delayed by a period corresponding to the amount of current, erroneous reading of data held in the normal memory cell MC can be prevented.

  Note that the capacitance value of the additional capacitor 104 is determined at the timing t1 of the potential of the input node n3 during the period from the timing t1 to the timing t2, depending on the driving capability for the dummy bit line XDBL1 and the parasitic capacitance of the input node n3. What is necessary is just to set so that the fall amount from an electric potential may fully decrease.

  Next, a third embodiment of the present invention will be described with reference to FIG. The circuit configuration of the third embodiment of the present invention is different from the circuit configuration of the first embodiment shown in FIG. 7 in that the timing control circuit 62 is replaced with a timing control circuit 111. Since other configurations are the same, description thereof is omitted. FIG. 12 shows a circuit configuration of the timing control circuit 111 according to the third embodiment.

  As shown in FIG. 12, the timing control circuit 111 is different in that the delay control unit 81 is replaced with a delay control unit 112 in the timing control circuit 62 of FIG. Further, unlike the timing control circuit 62, the inverter 82 of the timing control circuit 111 is included in the delay control unit 112. Other configurations are the same, and description thereof is omitted.

  The delay control unit 112 includes an inverter 82, an inverter array 113, a transfer switch 114, and an inverter 115. An inverter string 113 is connected between dummy bit line XDBL1 and output node n4 of self-timing signal SLF. In parallel with the inverter row 113, an inverter 82 and a transfer switch 114 are connected in series between the dummy bit line XDBL1 and the output node n4 of the self-timing signal SLF.

  The transfer switch 114 includes a PMOS transistor and an NMOS transistor whose sources and drains are connected to each other. The delay control signal DCNT from the delay control signal generator 83 is supplied as it is to the gate of the PMOS transistor, and the delay is supplied to the gate of the NMOS transistor. A control signal DCNT is supplied via the inverter 115. The inverter row 113 is configured by connecting a plurality of inverters in series, and is configured by an odd number of inverters. It is desirable that the threshold voltage of each inverter constituting the inverter 82 and the inverter row is set smaller than the threshold voltage of the inverters 84 and 85.

  The transfer switch 114 operates in response to the delay control signal DCNT and is turned off only during the H level period Δt in FIG. For this reason, the output node of the inverter 82 and the output node n4 of the self-timing signal become non-conductive only during the H level period Δt (period from timing t1 to timing t2), and before timing t1 and after timing t2. In a period, it becomes conductive.

  The delay control unit 112 receives the dummy bit line XDBL1 and the delay control signal DCNT, and delays and outputs the self timing signal SLF by a predetermined time based on the potential of the dummy bit line XDBL1 and the delay control signal DCNT. The operation of the timing control circuit 111 will be described below with reference to FIG.

  In a period before the timing t1, the potential of the input node n5 of the inverter 82 and the inverter row 113 is lowered from the precharge level (H level) to the L level following the decrease in the potential of the dummy bit line XDBL1. Inverter 82 transitions the output voltage from the L level to the H level at timing t5 when the potential of input node n5 becomes smaller than the threshold value, and outputs the result to transfer switch 114. Inverter train 113 shifts the output voltage from the L level to the H level at timing t6 after a period corresponding to the operation time of the plurality of inverters, and outputs the output voltage to output node n4 of the self timing signal. The delay time between the timing t5 and the timing t6 can be adjusted by adjusting the number and capacity of the inverters constituting the inverter row 113.

  Here, the operation of the delay control unit 112 related to the output of the self-timing signal SLF is classified according to the positional relationship between the falling timing t2 of the delay control signal DCNT shown in FIG. 10 and the timings t5 and t6. explain.

(1) When the timing t2 is earlier than the timing t5
The transfer switch 114 is once turned off at the timing t1, and then turned on again at the timing t2 before the timing t5 at which the inverter 82 outputs the H level. That is, at the timing t5, the transfer switch 114 is held in a conductive state.
For this reason, inverter 82 changes the potential of output node n4 of the self-timing signal from L level to H level at timing t5. Thereby, the self-timing signal SLF is activated at the timing t5.

(2) When timing t2 is later than timing t6,
After the transfer switch 114 is turned off at the timing t1, the transfer switch 114 is turned on again at the timing t2 after the timing t6 at which the inverter array 113 outputs the H level. That is, the transfer switch 114 is held in a non-conductive state at both timing t5 and timing t6.
Therefore, the inverter 82 cannot output the H level to the self-timing signal output node n4 during the period from the timing t5 to the timing t6, and the potential of the self-timing signal output node n4 is determined by the inverter array 113 at the timing t6. A transition is made from the L level to the H level. As a result, the self-timing signal SLF is activated at timing t6.

(3) When timing t2 is later than timing t5 and earlier than timing t6,
After the transfer switch 114 is turned off at the timing t1, the transfer switch 114 is turned on again at the timing t2 after the timing t5 when the inverter 82 outputs the H level and before the timing t6 when the inverter row 113 outputs the H level. In other words, the transfer switch 114 is held in the non-conductive state at the timing t5, and becomes conductive at the timing t2 between the timing t5 and the timing t6, and is held in the conductive state at the timing t6.
Therefore, the inverter 82 cannot output the H level to the output node n4 of the self timing signal at the timing t5. Instead, inverter 82 changes the potential of output node n4 of the self-timing signal from L level to H level at timing t2 between timing t5 and timing t6. Thereby, the self-timing signal SLF is activated at the timing t2.

  As described above, the timing control circuit 111 changes the activation timing of the self-timing signal SLF from the timing t5 to the timing t6 according to the falling timing t2 of the delay control signal DCNT, and the self-timing as the timing t2 becomes late. The activation timing of the signal SLF is also delayed.

Since the falling timing t2 of the delay control signal DCNT is delayed as the amount of the off-leakage current I _leak of the load dummy memory cell LDMC increases, the self-timing circuit determines the activation timing of the self-timing signal SLF as the off-leakage current I _leak current. It is possible to delay by the period corresponding to the amount, and to increase the delay amount of the activation timing of the self-timing signal SLF as the current amount of the off-leakage current I _leak increases.

Therefore, in the third embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. Therefore, it is possible to prevent erroneous reading of data held in the normal memory cell MC.

  In the third embodiment described above, the inverter row 13 in which a single inverter 82 and three inverters are connected in series is provided in parallel between the dummy bit line XDBL1 and the output node n4 of the self-timing signal SLF. However, the present invention is not limited to this configuration, and any configuration may be used as long as two inverter rows having different numbers of inverters connected in series are provided in parallel. Alternatively, two inverters having different driving capabilities and outputting signals at different timings for the same input signal may be provided in parallel.

  In the first to third embodiments described above, the transfer switch and the switch transistor are configured by the PMOS transistor and the NMOS transistor in which the source and the drain are interconnected. However, the present invention is not limited to this. A single transistor or NMOS transistor may be used.

  In the first to third embodiments, two pairs of dummy bit lines DBL and XDBL are provided, and the delay control signal DCNT is generated from each set of dummy bit lines XDBL. There is no limitation, and three or more pairs of dummy bit lines DBL and XDBL may be provided, and the delay control signal DCNT may be generated from each pair of dummy bit lines XDBL.

  In this case, for example, a plurality of dummy bit line pairs are divided into two groups, and in the first group, data is held in the same setting pattern as the first dummy bit line pair DBL1, XDBL1, and the second The group is configured to hold data in the same setting pattern as the second dummy bit line pair DBL2, XDBL2. Then, the delay control signal DCNT is changed to the H level based on the potential of the dummy bit line XDBL having the fastest potential decrease speed among the dummy bit lines belonging to the second group, and the dummy bits belonging to the first group The delay control signal DCNT may be shifted to the level based on the potential of the dummy bit line XDBL whose potential decrease rate is the slowest among the lines.

  FIG. 14 is a schematic configuration diagram showing the fourth embodiment. The SRAM shown in FIG. 14 has a self-timing circuit as a generation circuit of a sense amplifier activation signal that activates the sense amplifier circuit. The SRAM circuit configuration shown in FIG. 14 differs from the conventional circuit configuration shown in FIG. 1 in that the self-timing circuit 11 is replaced by a self-timing circuit 131, and the other configurations are the same.

  The self-timing circuit 131 shown in FIG. 14 has dummy bit line pairs DBL and XDBL, similar to the self-timing circuit 11 shown in FIG. The dummy bit line pair DBL, XDBL includes at least one self-timing dummy memory cell SDMC and a plurality of load dummy memory cells LDMC. As the self-timing dummy memory cell SDMC, for example, a plurality of dummy memory cells are designated in order from the position farthest from the timing control circuit 132 on the dummy bit line. The dummy bit line pair DBL and XDBL are connected to the timing control circuit 132, respectively.

  The timing control circuit 132 receives the dummy bit line pair DBL and XDBL, and outputs a self-timing signal SLF based on the detection result of the potential of the dummy bit line pair DBL and XDBL. Each dummy memory cell SDMC for self-timing of the dummy bit line pair DBL, XDBL is connected to a common dummy word line DWL. By selecting the dummy word line DWL, all the self-timing dummy memory cells SDMC are simultaneously selected.

  The setting pattern of retained data in the dummy memory cell for timing SDMC and the dummy memory cell for load LDMC is the same as the conventional setting pattern shown in FIG. That is, a setting pattern is obtained in which the potentials of the connection nodes n1 and n2 of the inverter pair INV1 and INV2 are fixed opposite to each other between the self-timing dummy memory cell SDMC and the load dummy memory cell LDMC.

These setting patterns minimize the influence of the off-leakage current I _leak of the load dummy memory cell LDMC on the dummy bit line XDBL, and the dummy bit line XDBL is driven only by the self-timing dummy memory cell SDMC. In addition, the dummy bit line DBL is driven by the off-leak current I _leak of all the load dummy memory cells LDMC.

  FIG. 15 is a schematic diagram showing a circuit configuration of the timing control circuit 132. As shown in FIG. 15, the timing control circuit 132 includes a delay control unit 141 and an inverter row 142, and the delay control unit 141 and the inverter row 142 are connected in series between the dummy bit line XDBL and the output node n6 of the self-timing signal SLF. It has a connected structure.

  The delay control unit 141 has a transfer gate composed of a PMOS transistor 143 and an NMOS transistor 144 whose sources and drains are interconnected. The PMOS transistor 143 has a gate connected to the ground VSS and is always turned on. The gate of the NMOS transistor 144 is connected to the dummy bit line DBL. The delay control unit 141 receives the dummy bit lines BDL and XDBL, delays the potential of the dummy bit line XDBL by a predetermined time based on the potential of the dummy bit line DBL, and outputs it to the input node of the inverter row 142.

  The inverter row 142 is configured by connecting a plurality of inverters in series. The inverter train 142 receives the output signal from the delay control unit 141, and activates the self-timing signal SLF in response to the potential of the output signal becoming lower than a predetermined value.

  The operation of the timing control circuit 132 will be described below with reference to FIG. When a predetermined word line WL in the memory cell array MCA is selected and the dummy word line DWL is selected in response thereto, the potential of the dummy bit line XDBL is driven by the self-timing dummy memory cell SDMC and precharged. It is lowered from the level (H level) to the L level.

At the same time, the dummy bit line DBL is also driven by the off-leakage current I _leak of all the load dummy memory cells LDMC, and pulled down from the precharge level (H level) to the L level. The amount of potential decrease from the precharge level of the dummy bit line DBL varies depending on the amount of off-leakage current I _leak of the load dummy memory cell LDMC. As the amount of off-leakage current I _leak increases, the amount of decrease in the potential of dummy bit line DBL also increases accordingly.

  Here, as described above, the potential of the dummy bit line DBL is input to the gate of the NMOS transistor 144 constituting the delay control unit 141. Therefore, the on-resistance value of the NMOS transistor 144 changes according to the potential of the dummy bit line DBL, and increases as the amount of potential decrease from the precharge level of the dummy bit line DBL increases.

Accordingly, the on-resistance value in the delay control unit 141 increases as the amount of decrease in the potential of the dummy bit line DBL increases. Correspondingly, the delay amount of the signal in the delay control unit 141 also increases as the amount of decrease in the potential of the dummy bit line DBL increases. Since the amount of decrease in the potential of the dummy bit line DBL corresponds to the amount of off-leakage current I _leak , the amount of signal delay in the delay control unit 141 depends on the amount of off-leakage current I _{leak in} the load dummy memory cell LDMC. It changes and increases as the amount of off-leakage current I _leak increases.

Therefore, the delay control unit 141 delays the input potential of the dummy bit line XDBL by a time Δt corresponding to the amount of off-leakage current I _leak and outputs the delayed potential to the inverter array 142. The inverter train 142 receives the potential of the dummy bit line DBL delayed by the delay control unit 141, and activates the self-timing signal SLF in response to the potential becoming lower than a predetermined threshold voltage.

Therefore, the self-timing circuit 131 delays the activation timing of the self-timing signal SLF by a time Δt corresponding to the amount of off-leak current I _leak of the load dummy memory cell LDMC, and the amount of off-leak current I _leak increases. Accordingly, the delay amount of the activation timing of the self timing signal SLF can be increased.

Therefore, in the fourth embodiment of the present invention, the activation timing of the sense amplifier activation signal SA is set according to the amount of the off-leak current I _leak even when the off-leak current I _leak increases due to a change in ambient temperature or the like. Therefore, the activation timing of the sense amplifier activation signal SA can be prevented from being earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC. Erroneous reading can be prevented.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the fifth embodiment of the present invention is that the timing control circuit 132 is replaced with a timing control circuit 161 or 162 as compared with the circuit configuration of the fourth embodiment shown in FIG. Different. Since other configurations are the same, description thereof is omitted. FIG. 17A shows a circuit configuration of the timing control circuit 161 in the fifth embodiment. FIG. 17B shows a circuit configuration of the timing control circuit 162 in the fifth embodiment.

  As shown in FIG. 17A, the timing control circuit 161 is provided with an inverter row 164 composed of a plurality of inverters between the dummy bit line XDBL and the self-timing signal output node n6, and further inverters constituting the inverter row 164 The delay control unit 163 is inserted between the two.

  The delay control unit 163 has a structure in which a plurality of transfer gates each composed of a PMOS transistor and an NMOS transistor whose sources and drains are connected to each other are connected in series. In each transfer gate, the gate of the PMOS transistor is connected to the ground VSS, and the gate of the NMOS transistor is connected to the dummy bit line DBL. The structure of each transfer gate is the same as that of the transfer gate in the delay control unit 141 of FIG.

  As shown in FIG. 17B, the timing control circuit 162 is provided with an inverter row 165 including a plurality of inverters between the dummy bit line XDBL and the self-timing signal output node n6. Each of the transfer gates constituting the delay control unit 166 is inserted between the inverters.

  The delay control unit 166 has a plurality of transfer gates composed of a PMOS transistor and an NMOS transistor whose sources and drains are interconnected. In each transfer gate, the gate of the PMOS transistor is connected to the ground VSS, and the gate of the NMOS transistor is connected to the dummy bit line DBL. The structure of each transfer gate is the same as that of the transfer gate in the delay control unit 141 of FIG.

  Each of the inverter trains 164 and 165 receives the dummy bit line XDBL, and activates the self-timing signal SLF in response to the potential of the dummy bit line XDBL becoming smaller than a predetermined value.

  Here, as described above, transfer gates constituting the delay control units 163 and 166 are inserted between the inverters of the inverter arrays 164 and 165, respectively. Therefore, the activation timing of the self-timing signal SLF by the inverter trains 164 and 165 is delayed by a predetermined time by the delay control units 163 and 166 based on the potential of the dummy bit line DBL.

Similarly to the delay control unit 141 of FIG. 15, the transfer gates of the delay control units 163 and 166 respectively delay the signal by a time corresponding to the amount of off-leakage current I _leak of the load dummy memory cell LDMC. Furthermore, since the delay control units 163 and 166 are constituted by a plurality of transfer gates, the influence of the current amount of the off-leakage current I _{leak on} the signal delay amount is emphasized. Therefore, the delay amount of the signals of the delay control units 163 and 166 with respect to the same current amount of the off-leakage current I _leak is larger than that of the delay control circuit 141.

Therefore, each of the timing control circuits 161 and 162 has a delay amount of the activation timing of the self-timing signal SLF more than that of the timing control circuit 132 for the same current amount of the off-leakage current I _leak of the load dummy memory cell LDMC. Can be big. Thereby, even when the off-leakage current I _leak increases, the activation timing margin of the self-timing signal SLF with respect to the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC can be increased.

Therefore, in the fifth embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. In addition, since the delay amount of the activation timing of the sense amplifier activation signal SA can be further increased, it is possible to increase the read margin of the data held in the normal memory cell MC and more reliably prevent erroneous reading. .

  Next, a sixth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the sixth embodiment of the present invention is different from the circuit configuration of the fourth embodiment shown in FIG. 14 in that the timing control circuit 132 is replaced with a timing control circuit 171. Since other configurations are the same, description thereof is omitted.

  FIG. 18 shows a circuit configuration of the timing control circuit 171 in the sixth embodiment. The timing control circuit 171 includes a delay control unit 172 and an inverter row 173, and has a structure in which the delay control unit 172 and the inverter row 173 are connected in series between the dummy bit line XDBL and the output node n6 of the self-timing signal SLF.

  The delay control unit 172 has an inverter structure in which a PMOS transistor 174, an NMOS transistor 175, and an NMOS transistor 176 are connected in series between a power supply voltage VDD and a ground VSS. The gates of the PMOS transistor 174 and the NMOS transistor 175 are both connected to the dummy bit line XDBL. The gate of the NMOS transistor 176 is connected to the dummy bit line DBL. The delay control unit 172 receives the dummy bit lines BDL and XDBL, operates in response to the potential of the dummy bit line XDBL becoming smaller than a predetermined value, and sets the self timing signal SLF to the potential of the dummy bit line DBL. Based on this, activation is delayed for a predetermined time.

  Self-timing signal SLF is output to the input node of inverter array 173. The inverter row 173 is configured by connecting a plurality of inverters in series. Inverter train 173 buffers the output signal from delay control unit 172 and outputs self-timing signal SLF to self-timing signal output node n6.

  The operation of the timing control circuit 171 will be described below. In the delay control unit 172, the PMOS transistor 174 and the NMOS transistor 175 constitute an inverter circuit that receives the dummy bit line XDBL. Further, in the inverter circuit, an NMOS transistor 176 that receives the dummy bit line DBL at the gate is provided between the NMOS transistor 175 and the ground VSS. The drive capability of the inverter circuit in the delay control unit 172 changes depending on the on-resistance value of the NMOS transistor 176, and decreases as the on-resistance value of the NMOS transistor 176 increases.

  The on-resistance value of the NMOS transistor 176 changes according to the potential of the dummy bit line DBL, and increases as the amount of potential decrease from the precharge level of the dummy bit line DBL increases. For this reason, the drive capability of the inverter circuit in the delay control unit 172 changes according to the potential of the dummy bit line DBL, and decreases as the amount of decrease in potential from the precharge level of the dummy bit line DBL increases.

Correspondingly, the delay amount of the signal in the delay control unit 172 increases as the potential decrease amount of the dummy bit line DBL increases. Since the amount of decrease in the potential of the dummy bit line DBL corresponds to the amount of off-leakage current I _leak , the delay amount of the signal in the delay control unit 172 depends on the amount of off-leakage current I _{leak in} the load dummy memory cell LDMC. It changes and increases as the amount of off-leakage current I _leak increases. Therefore, the delay control unit 172 performs self-timing at a timing delayed by a time corresponding to the amount of off-leakage current I _leak from the timing when the potential of the input dummy bit line XDBL becomes lower than a predetermined threshold voltage. The signal SLF is activated and output.

For this reason, the timing control circuit 171 delays the activation timing of the self-timing signal SLF by a time corresponding to the amount of off-leak current I _leak of the load dummy memory cell LDMC, and as the amount of off-leak current I _leak increases. The delay amount of the activation timing of the self timing signal SLF can also be increased.

Therefore, in the sixth embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. Therefore, it is possible to prevent the activation timing of the sense amplifier activation signal SA from being earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC, thereby preventing erroneous reading of retained data. it can.

  Next, a seventh embodiment of the present invention will be described with reference to FIG. The circuit configuration of the seventh embodiment of the present invention is that the timing control circuit 171 is replaced by timing control circuits 181 and 182 with respect to the circuit configuration of the sixth embodiment shown in FIG. Different. Since other configurations are the same, description thereof is omitted. FIG. 19A shows a circuit configuration of the timing control circuit 181 in the seventh embodiment. FIG. 19B shows a circuit configuration of the timing control circuit 182 in the seventh embodiment.

  As illustrated in FIG. 19A, the timing control circuit 181 includes a delay control unit 183. The delay control unit 183 has a structure in which a plurality of inverter circuits are connected in series between the dummy bit line XDBL and the self-timing signal output node n6. Each inverter circuit has a structure similar to that of the delay control unit 172 of FIG. In each inverter circuit, a dummy bit line DBL is connected to the gate of the NMOS transistor 185.

  As illustrated in FIG. 19B, the timing control circuit 182 includes a delay control unit 184. The delay control unit 184 has a structure in which a plurality of inverter circuits are connected in series between the dummy bit line XDBL and the self-timing signal output node n6. The series connection of the inverter circuits has a structure similar to that of the delay control unit 183 in FIG. 19A, but the NMOS transistor 186 connected to the ground VSS is provided in common for a plurality of inverter circuits. Is different.

  The delay control units 183 and 184 receive the dummy bit lines BDL and XDBL, operate in response to the potential of the dummy bit line XDBL becoming lower than a predetermined value, and send the self timing signal SLF to the dummy bit line DBL. The activation is delayed for a predetermined time based on the potential. Self-timing signal SLF is output to self-timing signal output node n6.

  Here, as described above, each inverter circuit of the delay control units 183 and 184 includes the NMOS transistors 185 and 186 that input the dummy bit line DBL to the gates. Therefore, the activation timing of the self-timing signal SLF by the delay control units 183 and 184 is delayed by a predetermined time based on the potential of the dummy bit line DBL.

The NMOS transistors 185 and 186 of the delay control units 183 and 184 change the drive capability of the inverter circuit in accordance with the potential of the dummy bit line DBL, respectively, similarly to the delay control unit 172 of FIG. 18, and precharge the dummy bit line DBL. Decrease as the amount of potential decrease from the level increases. Thereby, the delay control units 183 and 184 delay the activation timing of the self-timing signal by a time corresponding to the amount of off-leakage current I _leak of the load dummy memory cell LDMC.

Furthermore, since the delay control units 183 and 184 are provided with NMOS transistors 185 and 186 for a plurality of inverter circuits connected in series, the influence of the amount of off-leakage current I _{leak on} the timing delay amount is emphasized. . Therefore, the delay amount of the timings of the delay control units 183 and 184 with respect to the same current amount of the off-leakage current I _leak is larger than that of the delay control circuit 172.

Therefore, each of the timing control circuits 181 and 182 has a delay amount of the activation timing of the self-timing signal SLF in comparison with the timing control circuit 171 with respect to the same current amount of the off-leakage current I _leak of the dummy memory cell for load LDMC. Can be big. Thereby, even when the off-leakage current I _leak increases, the activation timing margin of the self-timing signal SLF with respect to the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC can be increased.

Therefore, in the seventh embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. In addition, since the delay amount of the activation timing of the sense amplifier activation signal SA can be further increased, it is possible to increase the read margin of the data held in the normal memory cell MC and more reliably prevent erroneous reading. .

  In the timing control circuit 182 of FIG. 19B, the NMOS transistor to which the dummy bit line DBL is input is shared among a plurality of inverter circuits, so that it is compared with the timing control circuit 181 of FIG. The circuit scale can be reduced.

  Next, an eighth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the eighth embodiment of the present invention is that the timing control circuit 132 is replaced with a timing control circuit 191 or 194 as compared with the circuit configuration of the fourth embodiment shown in FIG. Different. Since other configurations are the same, description thereof is omitted. FIG. 20A shows a circuit configuration of the timing control circuit 191 in the eighth embodiment. FIG. 20B shows a circuit configuration of the timing control circuit 194 in the eighth embodiment.

  As shown in FIG. 20A, the timing control circuit 191 is different from the circuit configuration of the timing control circuit 132 in FIG. 15 in that the delay control unit 141 is replaced with a delay control unit 193. Since other configurations are the same, description thereof is omitted.

  The delay control unit 193 includes a transfer gate including a PMOS transistor 143 and an NMOS transistor 144 whose sources and drains are interconnected. The PMOS transistor 143 has a gate connected to the ground VSS and is turned on. The delay control signal DCNT output from the delay control signal generator 192 is input to the gate of the NMOS transistor 144.

  The delay control signal generation unit 192 has a structure in which an NMOS transistor 196 and an NMOS transistor 196 are connected in series between the power supply voltage VDD and the ground VSS. The gate of the NMOS transistor 196 is connected to the dummy bit line DBL. The gate of the NMOS transistor 197 is connected to the power supply voltage VDD and is always turned on. The delay control signal generation unit 192 outputs a delay control signal DCNT from a connection node between the NMOS transistor 196 and the NMOS transistor 197. The delay control unit 193 receives the dummy bit lines DBL and XDBL, delays the potential of the dummy bit line XDBL by a predetermined time based on the potential of the dummy bit line DBL, and outputs it to the input node of the inverter row 142.

  As shown in FIG. 20B, the timing control circuit 194 is different from the circuit configuration of the timing control circuit 191 in FIG. 20A in that the delay control signal generation unit 192 in the delay control unit 193 is included in the delay control unit 195. The delay control signal generation unit 198 is replaced with the above. Since other configurations are the same, description thereof is omitted. The delay control signal generation unit 205 has a structure in which the NMOS transistor 197 is replaced with a PMOS transistor 199 with respect to the circuit configuration of the delay control signal generation unit 192. The PMOS transistor 206 has a gate connected to the ground VSS and is always turned on.

  The operation of the timing control circuits 191 and 194 will be described below. In the delay control signal generation units 192 and 198, the dummy bit line DBL is connected to the gate of the NMOS transistor 196. Therefore, the on-resistance value of the NMOS transistor 196 changes according to the potential of the dummy bit line DBL, and increases as the amount of decrease in potential from the precharge level (H level) of the dummy bit line DBL increases.

Accordingly, the potential of the connection node between the NMOS transistor 196 and the NMOS transistor 196 in the delay control signal generation unit 192 and the connection node between the NMOS transistor 196 and the PMOS transistor 199 in the delay control signal generation unit 198 are determined from the precharge level of the dummy bit line DBL. As the amount of decrease in potential increases, it decreases. That is, the level of the delay control signal DNT decreases as the amount of potential decrease from the precharge level of the dummy bit line DBL increases. Since the decrease in the potential of the dummy bit line DBL corresponds to the current amount of the off leak current I _leak, the level of the delay control signal DCNT is lowered in accordance with the current amount of the off leak current I _leak increases.

Here, as described above, the delay control signal DCNT is input to the gates of the NMOS transistors 144 of the delay control units 193 and 195. For this reason, the on-resistance value of the NMOS transistor 144 increases as the amount of off-leakage current I _leak increases. Correspondingly, the delay amount of the signal in the delay control units 193 and 195 changes depending on the amount of off-leakage current I _leak of the load dummy memory cell LDMC, and as the amount of off-leakage current I _leak increases. To increase.

Accordingly, the timing control circuits 191 and 194 delay the activation timing of the self-timing signal SLF by a time corresponding to the amount of off-leakage current I _leak of the load dummy memory cell LDMC, as in the self-timing circuit 132 of FIG. In addition, the delay amount of the activation timing of the self-timing signal SLF can be increased as the amount of off-leakage current I _leak increases.

Therefore, in the eighth embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. Therefore, it is possible to prevent erroneous reading of data held in the normal memory cell MC.

  Further, the timing control circuits 191 and 194 do not directly input the dummy bit line DBL to the gate of the NMOS transistor 144 as in the timing control circuit 132 of FIG. 15, but delay control signals based on the potential of the dummy bit line DBL. The generation units 192 and 198 generate a delay control signal DCNT, and the delay control signal DCNT is input to the gate of the NMOS transistor 144. Therefore, the delay control signal generators 192 and 198 can amplify the amount of decrease in the potential of the dummy bit line DBL, and the amplified result can be input to the gate of the NMOS transistor 144 as the delay control signal DCNT.

Therefore, the timing control circuits 191 and 194 have a larger delay amount of the activation timing of the self-timing signal SLF than the timing control circuit 132 with respect to the same current amount of the off-leak current I _leak of the load dummy memory cell LDMC. Can be a thing. Thereby, in the eighth embodiment of the present invention, even when the off-leakage current I _leak increases, the activation of the self-timing signal SLF with respect to the timing at which a predetermined potential difference occurs in the bit line pair BL, XBL of the normal memory cell MC. It is possible to increase the margin of the read timing, increase the read margin of the retained data, and more reliably prevent erroneous reading.

  Next, a ninth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the ninth embodiment of the present invention differs from the circuit configuration of the fourth embodiment shown in FIG. 15 in that the timing control circuit 132 is replaced with a timing control circuit 201 or 202. Different. Since other configurations are the same, description thereof is omitted. FIG. 21A shows a circuit configuration of the timing control circuit 201 according to the ninth embodiment. FIG. 21B shows a circuit configuration of the timing control circuit 202 in the ninth embodiment.

  As shown in FIG. 21A, the timing control circuit 201 is different from the circuit configuration of the timing control circuit 132 in FIG. 15 in that the delay control unit 141 is replaced with a delay control unit 204. Since other configurations are the same, description thereof is omitted.

  The delay control unit 204 has a transfer gate composed of a PMOS transistor 143 and an NMOS transistor 144 whose sources and drains are interconnected. The NMOS transistor 144 has a gate connected to the ground VSS and is always turned on. The delay control signal DCNT output from the delay control signal generation unit 205 is input to the gate of the PMOS transistor 143.

  The delay control signal generation unit 205 has a structure in which an NMOS transistor 206 and an NMOS transistor 207 are connected in series between a power supply voltage VDD and a ground VSS. The gate of the NMOS transistor 207 is connected to the dummy bit line DBL. The NMOS transistor 206 has a gate connected to the power supply voltage VDD, and is always turned on. The delay control signal generation unit 205 outputs a delay control signal DCNT from a connection node between the NMOS transistor 206 and the NMOS transistor 207. The delay control unit 204 receives the dummy bit lines DBL and XDBL, delays the potential of the dummy bit line XDBL by a predetermined time based on the potential of the dummy bit line DBL, and outputs it to the input node of the inverter row 142.

  As shown in FIG. 21B, the timing control circuit 202 is different from the circuit configuration of the timing control circuit 201 in FIG. 21A in that the delay control signal generation unit 205 in the delay control unit 204 is included in the delay control unit 203. The delay control signal generator 208 is replaced with a delay control signal generator 208 of FIG. Since other configurations are the same, description thereof is omitted. The delay control signal generation unit 208 has a structure in which the NMOS transistor 206 is replaced with a PMOS transistor 209 with respect to the circuit configuration of the delay control signal generation unit 205. The PMOS transistor 209 has a gate connected to the ground VSS and is always turned on.

  The operation of the timing control circuits 201 and 202 will be described below. In the delay control signal generation units 205 and 208, the dummy bit line DBL is connected to the gate of the NMOS transistor 207. Therefore, the on-resistance value of the NMOS transistor 207 changes according to the potential of the dummy bit line DBL, and increases as the amount of decrease in potential from the precharge level (H level) of the dummy bit line DBL increases.

Accordingly, the potential of the connection node between the NMOS transistor 206 and the NMOS transistor 207 in the delay control signal generation unit 205 and the connection node between the PMOS transistor 209 and the NMOS transistor 207 in the delay control signal generation unit 208 are determined from the precharge level of the dummy bit line DBL. As the amount of potential decrease increases, it increases. That is, the level of the delay control signal DNT increases as the amount of potential decrease from the precharge level of the dummy bit line DBL increases. Since the amount of decrease in the potential of the dummy bit line DBL corresponds to the amount of off-leakage current I _leak , the level of the delay control signal DCNT increases as the amount of off-leakage current I _leak increases.

Here, as described above, the delay control signal DCNT is input to the gates of the PMOS transistors 143 of the delay controllers 203 and 204. For this reason, the on-resistance value of the PMOS transistor 144 increases as the amount of off-leakage current I _leak increases. Correspondingly, the delay amount of the signal in the delay control units 203 and 204 changes depending on the amount of off-leakage current I _leak of the dummy memory cell for load LDMC, and as the amount of off-leakage current I _leak increases. To increase.

Accordingly, the timing control circuits 201 and 202 delay the activation timing of the self-timing signal SLF by a time corresponding to the amount of the off-leakage current I _leak of the load dummy memory cell LDMC, similarly to the timing control circuit 132 of FIG. In addition, the delay amount of the activation timing of the self-timing signal SLF can be increased as the amount of off-leakage current I _leak increases.

Therefore, in the ninth embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the amount of the off-leak current I _leak. Therefore, it is possible to prevent erroneous reading of data held in the normal memory cell MC.

  Further, in the timing control circuits 201 and 202, a delay control signal DCNT is generated by the delay control signal generators 192 and 198 based on the potential of the dummy bit line DBL, and the delay control signal DCNT is input to the gate of the PMOS transistor 143. ing. Therefore, the delay control signal generation units 205 and 208 can amplify the amount of decrease in the potential of the dummy bit line DBL, and the amplified result can be input to the gate of the PMOS transistor 143 as the delay control signal DCNT.

Therefore, the timing control circuits 201 and 202 have a larger delay amount of the activation timing of the self-timing signal SLF than the timing control circuit 132 with respect to the same amount of off-leakage current I _leak of the load dummy memory cell LDMC. Can be a thing. Accordingly, in the ninth embodiment of the present invention, even when the off-leakage current I _leak increases, the activation of the self-timing signal SLF with respect to the timing at which a predetermined potential difference occurs in the bit line pair BL, XBL of the normal memory cell MC. It is possible to increase the margin of the read timing, increase the read margin of the retained data, and more reliably prevent erroneous reading.

  Next, a tenth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the tenth embodiment of the present invention is different from the circuit configuration of the fourth embodiment shown in FIG. 15 in that the timing control circuit 132 is replaced with a timing control circuit 211. Since other configurations are the same, description thereof is omitted.

  The timing control circuit 211 includes a delay control unit 212 and an inverter row 213, and has a structure in which the delay control unit 212 and the inverter row 213 are connected in series between the dummy bit line XDBL and the output node n6 of the self-timing signal SLF.

  The delay control unit 212 receives the dummy bit lines BDL and XDBL, delays the potential of the dummy bit line XDBL by a predetermined time based on the potential of the dummy bit line DBL, and outputs the delayed signal to the input node n7 of the inverter row 213. The inverter array 213 is configured by connecting a plurality of inverters in series, and receives an output signal from the delay control unit 212, and in response to the potential of the output signal becoming smaller than a predetermined value, the self-timing signal SLF To activate.

  The delay control unit 212 includes a PMOS transistor 214 provided between the input node n7 of the inverter train 213 and the power supply voltage VDD. A dummy bit line XDBL is connected to the gate of the PMOS transistor 214, and its on-resistance value decreases as the potential decrease from the precharge level (H level) of the dummy bit line DBL increases. For this reason, the amount of current flowing into the input node n7 of the inverter array via the PMOS transistor 214 increases as the amount of decrease in the potential of the dummy bit line DBL increases.

Since the decrease in the potential of the dummy bit line DBL corresponds to the current amount of the off leak current I _leak, the amount of current flowing into the input node n7 through the PMOS transistor 214 increases in accordance with the current amount of the off leak current I _leak increases. Whereby the potential of the input node n7 is pulled to the H level at a strength corresponding to the current amount of the off leak current I _leak by the PMOS transistor 214, it is pulled more strongly H-level according to the current amount of the off leak current I _leak increases .

After selecting the dummy word line DWL, the potential of the input node n7 is lowered to L level in response to the dummy bit line XDBL being lowered to L level. At the same time, the potential of the input node n7 is raised to the H level by the PMOS transistor 214 with the intensity corresponding to the amount of the off-leakage current I _leak of the load dummy memory cell LDMC as described above. As a result, the rate of decrease in the potential of the input node n7 becomes slow according to the amount of off leak current I _leak . Correspondingly, the activation timing of the self-timing signal SLF by the inverter train 213 is delayed by a time corresponding to the amount of off-leakage current I _leak .

For this reason, the timing control circuit 211 delays the activation timing of the self-timing signal SLF by a time corresponding to the amount of off-leakage current I _leak , and activates the self-timing signal SLF as the amount of off-leakage current I _leak increases. The amount of timing delay can also be increased. Therefore, in the tenth embodiment of the present invention, even when the off-leak current I _leak increases, the activation timing of the sense amplifier activation signal SA can be delayed by a period corresponding to the off-leak current I _leak current amount. Thus, it is possible to prevent erroneous reading of data held in the normal memory cell MC.

  Furthermore, in the tenth embodiment, the delay control unit can be configured with only one PMOS transistor, and the circuit scale can be reduced. Therefore, compared with the fourth to ninth embodiments described above. The circuit scale of the timing control circuit can be reduced.

In the fourth to tenth embodiments described above, the delay amount of the activation timing of the self-timing signal SLF is controlled using only the pair of dummy bit line pairs DBL and XDBL. It is not limited to. A dummy bit line driven only by the self-timing dummy memory cell and a dummy bit line driven only by the off-leakage current I _{leak of the} load dummy memory cell LDMC are provided independently, and these two dummy bit lines are provided. The delay amount of the activation timing of the self-timing signal SLF may be used.

  FIG. 23 is a schematic configuration diagram showing the eleventh embodiment. The SRAM shown in FIG. 23 has a self-timing circuit as a generation circuit of a sense amplifier activation signal that activates the sense amplifier circuit. The SRAM circuit configuration shown in FIG. 23 differs from the conventional circuit configuration shown in FIG. 1 in that the self-timing circuit 11 is replaced with a self-timing circuit 221 and the other configurations are the same.

  The self-timing circuit 221 shown in FIG. 23 has two pairs of dummy bit lines DBL1, XDBL1, DBL2, and XDBL2. Each dummy bit line pair has at least one self-timing dummy memory cell SDMC and a plurality of load dummy memory cells LDMC, as in the self-timing circuit 11 of FIG.

  The data held in the self-timing dummy memory cell SDMC connected to each dummy bit line pair is set to the H level at the connection node n1 of the inverter pair in the dummy memory cell, as in the conventional setting pattern shown in FIG. The connection node n2 may be set to the L level. In each dummy bit line pair, for example, a plurality of dummy memory cells are designated as the self-timing dummy memory cell SDMC in order from the position farthest from the timing control circuit 222 on the dummy bit line.

  Of the first dummy bit line pair DBL1, XDBL1, the dummy bit line XDBL1 is connected to the timing control circuit 222 as a dummy bit line to be detected. Of the second dummy bit line pair DBL2, XDBL2, the dummy bit line pair XDBL2 is connected to the timing control circuit 222 as a dummy bit line to be detected. The timing control circuit 222 receives the dummy bit lines XDBL1 and XDBL2, and outputs a self timing signal SLF based on the detection result of the potentials of the dummy bit lines XDBL1 and XDBL2.

  The dummy memory lines SDMC for self-timing of the dummy bit line pairs DBL1, XDBL1, DBL2, and XDBL2 are connected to a common dummy word line DWL. By selecting the dummy word line DWL, all the self-timing dummy memory cells SDMC are simultaneously selected, and the dummy bit line pairs DBL1, XDBL1, DBL2, and XDBL2 are simultaneously driven. Thereby, each driven dummy bit line pair generates a predetermined potential difference.

  FIG. 24 shows a layout example of dummy memory cells SDMC and LDMC in the dummy bit line pair DBL1, XDBL1 and DBL2, XDBL2 of the self-timing circuit 221. Each dummy memory cell SDMC, LDMC is laid out as a unit including a portion composed of an inverter pair and a transfer transistor pair.

  In the self-timing dummy memory cell SDMC in the first dummy bit line pair DBL1, XDBL1, at least one normal layout unit 231 including inverters 233, 234 and a transfer transistor pair 237 is arranged along the dummy bit line pair DBL1, XDBL1. Is laid out to do.

  On the other hand, the self-timing dummy memory cell SDMC in the second dummy bit line pair DBL2, XDBL2 is symmetrical with the normal layout 231 and is composed of inverters 235, 236 and transfer transistor pair 238. The layout unit 232 is laid out so as to be arranged along at least one dummy bit line pair DBL2, XDBL2.

  Load dummy memory cells LDMC (not shown) in each dummy bit line pair are laid out by a normal layout unit or a symmetrical layout unit, and any layout unit is arbitrary. For example, in each dummy bit line pair, the load dummy memory cell LDMC alternates the normal layout unit 231 and the symmetrical layout unit 232 along the dummy bit line pair in the same manner as the conventional dummy memory cell shown in FIG. Lay out to place. Alternatively, in each dummy bit line pair, all the dummy memory cells for load LDMC may be laid out by one of the normal layout unit 231 and the symmetrical layout unit 232.

  In the figure, the gates of the transfer transistor pairs 237, 238 of the self-timing dummy memory cells SDMC11-14, 21-24 are connected to a common dummy word line DWL (not shown). The gate of the transfer transistor pair of the load dummy memory cell LDMC (not shown) in each dummy bit line pair is connected to the ground VSS.

  Further, in the figure, the white area represents the impurity diffusion layer on the semiconductor wafer, and the deep hatched area represents the gate polysilicon layer formed on the semiconductor wafer. A broken line represents a local wiring in the memory cell, a thick line represents bit lines DBL and XDBL, and a circle represents a contact contact with a dummy bit line. Further, as can be seen from FIG. 23, in each of the normal layout unit 231 and the symmetrical layout unit 232, the layouts of the two inverters constituting the inverter pair are not line-symmetric with each other.

  Here, in the layout example of the dummy memory cells SDMC and LDMC in FIG. 23, consider a case where a positional shift occurs between the impurity diffusion layer and the gate polysilicon layer in the photoetching step of the manufacturing process. 25 and 26 show layouts in the case where the gate polysilicon layer is entirely displaced in the lower left direction in the drawing with respect to the impurity diffusion layer.

  As shown in FIGS. 25 and 26, the actual finished shape is rounded at the corners of the impurity diffusion layer and the gate polysilicon layer. For this reason, when the position shift in the lower left direction in the figure occurs as described above, the dummy memory cells SDMC 11 to 14 having the normal layout unit 231 in the first dummy bit line pair DBL 1 and XDBL 1 and the second dummy bit line. In the dummy memory cells SDMC 21 to 24 having the symmetrical layout unit 232 in the bit line pair DBL2, XDBL2, there is a difference in driving capability between the inverters constituting the inverter pair.

  Specifically, as shown in FIG. 25, in the dummy memory cells SDMC 11 to 14 having the normal layout unit 231, due to the position shift in the lower left direction, as in the dummy memory cell SDMC 1 of FIG. The characteristics of the inverters 233 and 234 change. That is, in the inverter 234 located on the left side, the channel length is shortened in the upper transistor and the channel length is lengthened and narrowed in the lower transistor, whereas in the inverter 233 located on the right side, in the upper transistor The channel length is increased, and the channel width is increased in the lower transistor.

  On the other hand, in the dummy memory cells SDMC 21 to 24 having the symmetrical layout unit 232 as shown in FIG. 26, due to the position shift in the lower left direction, as in the dummy memory cell SDMC2 in FIG. The characteristics of the inverter change. That is, in the inverter 236 located on the left side, the channel width is narrowed in the upper transistor and the channel length is shortened in the lower transistor, whereas in the inverter 235 located on the right side, the channel length is shortened in the upper transistor, The channel width is increased, and the channel length is increased in the lower transistor.

  As described above, driving is performed between the four inverters 233 to 236 constituting the inverter pair of the dummy memory cells SDMC 11 to 14 having the normal layout unit 231 and the dummy memory cells SDMC 21 to 24 having the symmetric layout unit 232 due to misalignment. Capabilities become different from each other. As a result, there is a difference in driving capability between the dummy memory cells SDMC 11 to 14 having the normal layout unit 231 and the dummy memory cells SDMC 21 to 24 having the symmetric layout unit 232 according to the positional deviation. Corresponding to this, a difference also occurs between the driving capabilities for the dummy bit lines XDBL1 and XDBL2 in accordance with the positional deviation.

  FIG. 27 shows a schematic diagram of a circuit configuration of the timing control circuit 222 of FIG. As shown in FIG. 27, the timing control circuit 222 includes inverters 251 and 252 and an AND circuit 253. For example, the inverters 251 and 252 have the same threshold voltage.

  Inverter 251 receives dummy bit line XDBL1, and outputs an H level signal to AND circuit 253 in response to the potential of dummy bit line XDBL1 becoming lower than a predetermined threshold voltage. Inverter 252 receives dummy bit line XDBL2, and outputs an H level signal to AND circuit 253 in response to the potential of dummy bit line XDBL2 becoming lower than a predetermined threshold voltage. The AND circuit 253 receives the output signals of the inverters 251 and 252 and activates and outputs the self-timing signal SLF by taking the logical product of the two output signals.

  The operation of the timing control circuit 222 will be described below with reference to FIG. When a predetermined word line WL in the memory cell array MCA is selected and the dummy word line DWL is selected in response thereto, the potentials of the dummy bit lines XDBL1 and XDBL2 are set by the dummy memory cells SDMC11 to 14 and SDMC21 to 24, respectively. The precharge level (H level) is lowered to the L level.

  Here, as described above, the drive capability of the dummy memory cells SDMC11 to 14 having the normal layout unit 231 for the dummy bit line XDBL1, and the drive capability of the dummy memory cells SDMC21 to 24 having the symmetric layout unit 232 to the dummy bit line XDBL2 Between the impurity diffusion layer and the gate polysilicon layer, there is a difference depending on the positional deviation, and accordingly, there is a difference between the potential decreasing speeds of the dummy bit lines XDBL1 and XDBL2 depending on the positional deviation. Arise.

  FIG. 28 shows an example in which the drive capability of the dummy memory cells SDMC 11 to 14 having the normal layout unit 231 is larger than that of the dummy memory cells SDMC 21 to 24 having the symmetric layout unit 232. The decreasing speed of the potential of the line XDBL1 is higher than that of the dummy bit line XDBL2. For this reason, the timing t7 when the output signal of the inverter 251 becomes H level is earlier than the timing t8 when the output signal of the inverter 252 becomes H level by a period Δt corresponding to the positional deviation.

  The AND circuit 253 takes a logical product of the output signals of the inverters 251 and 252 and outputs a self timing signal SLF. For this reason, the activation timing of the self-timing signal SLF is determined by the later timing of the timing t7 and the timing t8. In FIG. 28, the self-timing signal SLF is activated and output at timing t8.

  Accordingly, in the timing control circuit 222, the activation timing of the self-timing signal SLF depends on the positional deviation between the dummy memory cells SDMC11-14 having the normal layout unit 231 and the dummy memory cells SDMC21-24 having the symmetrical layout unit 232. This is determined on the basis of the potential of the dummy bit line driven by the one having the smaller driving capability. In the timing control circuit 222, the activation timing of the self-timing signal SLF is determined according to the positional deviation between the impurity diffusion layer and the gate polysilicon layer. It is adjusted according to ability.

  On the other hand, in the memory cell MC in the memory cell array MCA, as in the layout example of the dummy memory cells SDMC and LDMC in FIG. 5, the normal layout unit 231 and the symmetrical layout unit 232 are alternately arranged along the respective bit line pairs BL and XBL. Is laid out. For this reason, when misalignment occurs, the memory cell MC includes a memory cell having a layout unit with a smaller driving capability of the normal layout unit 231 and the symmetrical layout unit 232 and a layout unit with a larger driving capability. Are mixed with memory cells.

  When the memory cell MC selected at the time of reading is a cell having a layout unit with a smaller driving capability, the bit line pair BL, XBL is connected to the bit line pair BL, XBL than when it is a cell having a layout unit with a larger driving capability. The timing at which the predetermined potential difference occurs is delayed. The timing at which a predetermined potential difference occurs in the bit line pair BL, XBL is a cell in which the memory cell MC selected at the time of reading has a layout unit with a smaller driving capability or a cell with a layout unit with a larger driving capability. It depends on whether it is.

  Here, as described above, the timing control circuit 222 matches the driving capability of the memory cell having the layout unit whose driving capability is reduced according to the positional deviation between the impurity diffusion layer and the gate polysilicon layer. Then, the activation timing of the self-timing signal SLF is adjusted.

  For this reason, even if the misalignment occurs between the impurity diffusion layer and the gate polysilicon layer and the memory cell MC selected at the time of reading is a cell having a layout unit with a smaller driving capability, the self Since the activation timing of the timing signal is appropriately adjusted according to the positional deviation, the activation timing of the sense amplifier activation signal SA is more than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the selected memory cell. It can be surely slowed down.

  Therefore, in the eleventh embodiment of the present invention, the activation timing of the sense amplifier activation signal SA is determined even when a positional shift occurs between the impurity diffusion layer and the gate polysilicon layer due to manufacturing variation or the like. Since it can be adjusted appropriately according to the deviation, the activation timing of the sense amplifier activation signal SA is prevented from being earlier than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the normal memory cell MC. Thus, erroneous reading of retained data can be prevented.

  In the eleventh embodiment, two pairs of dummy bit lines DBL and XDBL are provided and the self-timing signal SLF is generated from each pair of dummy bit lines XDBL. However, the present invention is not limited to this. In other words, three or more pairs of dummy bit lines DBL and XDBL may be provided, and the self-timing signal SLF may be generated from each pair of dummy bit lines XDBL.

  In this case, for example, a plurality of dummy bit line pairs are divided into two groups. In the first group, dummy memory cells are laid out in the same layout pattern as the first dummy bit line pair DBL1, XDBL1, and the second In the group, the dummy memory cells are laid out in the same layout pattern as the second dummy bit line pair DBL2, XDBL2. Then, the timing control circuit is configured to cause the self-timing signal SLF to transition to the H level based on the potential of the dummy bit line XDBL having the slowest potential decrease speed among the dummy bit lines belonging to the first and second groups. What is necessary is just to comprise.

  Next, a twelfth embodiment of the present invention will be described with reference to FIG. The circuit configuration of the twelfth embodiment of the present invention is different from the circuit configuration of the eleventh embodiment shown in FIG. 23 in that the self-timing circuit 221 is replaced with a self-timing circuit 271. Since other configurations are the same, description thereof is omitted.

  The self-timing circuit 271 of FIG. 29 has a dummy bit line pair DBL, XDBL to which at least one self-timing dummy memory cell SDMC and a plurality of load dummy memory cells LDMC are connected. As the self-timing dummy memory cell SDMC, for example, a plurality of dummy memory cells are designated in order from the position farthest from the timing control circuit 272 on the dummy bit line. The dummy bit line pair DBL and XDBL are both connected to the timing control circuit 272 as dummy bit lines to be detected.

  The timing control circuit 272 receives the dummy bit lines DBL and XDBL, and outputs a self-timing signal SLF based on the detection results of the potentials of the dummy bit lines DBL and XDB. The circuit configuration of the timing control circuit 272 is the same as that of the timing control circuit 222 of FIG. 27 except that the inverters 251 and 252 receive the dummy bit lines DBL and XDBL instead of the dummy bit lines XDBL1 and XDBL2. Yes, explanation is omitted.

  FIG. 30 shows a layout example of the dummy memory cells SDMC and LDMC in the dummy bit line pair DBL and XDBL of the self-timing circuit 271. As shown in FIG. 30, each of the dummy memory cells SDMC and LDMC is laid out with a portion including an inverter pair and a transfer transistor pair as one unit.

  Similar to the layout example of the dummy memory cell in FIG. 5, the dummy memory cell in FIG. 30 has a normal layout unit 231 including the inverters 233 and 234 and the transfer transistor pair 237 and a point-symmetrical or line-symmetrical relationship therewith. The symmetrical layout unit 232 including the inverters 235 and 236 and the transfer transistor pair 238 is laid out alternately along the dummy bit line pair DBL and XDBL.

  In each of the self-timing dummy memory cells SDMC1 to SDMC4, unlike the dummy memory cell layout example of FIG. 5, the gate electrodes of the two transistors constituting the transfer transistor pair 237 and 238 are electrically isolated from each other.

  In the transfer transistor pair 237 of the self-timing dummy memory cells SDMC1 and 3, the gate of the transfer transistor connected to the output node n1 of the inverter 234 on the dummy bit line DBL side is connected to a common dummy word line DWL (not shown). The gate of the transfer transistor connected to the output node n2 of the inverter 233 on the dummy bit line XDBL side is connected to the ground VSS.

  The data held in the self-timing dummy memory cells SDMC1, 3 is set so that the connection node n1 of the inverter pair is set to L level and the connection node n2 is set to H level. Thereby, in the dummy memory cells for self-timing SDMC1 and 3, when the dummy word line DWL is selected, the dummy bit line DBL is pulled down from the precharge level (H level) to the L level by the inverter 234 on the dummy bit line DBL side.

  In the transfer transistor pair 238 of the dummy memory cells SDMC2 and 4 for self-timing, the gate of the transfer transistor connected to the output node n1 of the inverter 236 on the dummy bit line DBL side is connected to the ground VSS, while on the dummy bit line XDBL side The gates of the transfer transistors connected to the output node n2 of the inverter 235 are connected to a common dummy word line DWL (not shown).

  The data held in the self-timing dummy memory cells SDMC2 and SDMC is set so that the connection node n1 of the inverter pair is at the H level and the connection node n2 is at the L level. Thereby, in the dummy memory cells SDMC2 and 4 for self-timing, when the dummy word line DWL is selected, the dummy bit line XDBL is pulled down from the precharge level (H level) to the L level by the inverter 235 on the dummy bit line XDBL side.

  As described above, the connection pattern for connecting the separated gate electrodes of the transfer transistor pair 237, 238 to the common dummy word line DWL or the ground VSS is the dummy memory cell for self-timing adjacent along the dummy bit line. The SDMCs are set to be opposite to each other. That is, the connection patterns of the self-timing dummy memory cell SDMC having the normal layout 231 and the self-timing dummy memory cell SDMC having the symmetrical layout unit 232 are set to be opposite to each other.

  Accordingly, the dummy bit line DBL is driven only by the self-timing dummy memory cells SDMC 1 and 3 having the normal layout unit 232, and the dummy bit line XDBL is driven only by the self-timing dummy memory cells SDMC 2 and 4 having the symmetrical layout unit 232. Driven.

  Here, when a positional shift occurs between the impurity diffusion layer and the gate polysilicon layer as described above (see FIG. 31), the driving capability of the dummy memory cell SDMC having the normal layout unit 231 and the symmetrical layout unit 232 are changed. A difference corresponding to the positional deviation occurs between the driving capabilities of the dummy memory cells SDMC.

  For this reason, a difference corresponding to the positional deviation also occurs between the driving capabilities for the dummy bit line DBL and the dummy bit line XDBL, so that the dummy bit lines DBL and XDBL in FIG. Similar to the case of the bit lines XDBL1 and XDBL2, a difference is generated according to the positional deviation.

  Accordingly, as in the case of the timing control circuit 222 of FIG. 27, in the timing control circuit 272, the activation timing of the self-timing signal SLF has the dummy memory cells SDMC1, 3 having the normal layout unit 231 and the symmetrical layout unit 232. It is determined based on the potential of the dummy bit line driven by the one of the dummy memory cells SDMC2, 4 whose driving capability is reduced in accordance with the positional deviation.

  Thereby, the timing control circuit 272 adjusts the self-timing signal in accordance with the driving capability of the memory cell having the layout unit whose driving capability is reduced according to the positional deviation between the impurity diffusion layer and the gate polysilicon layer. The activation timing of SLF can be adjusted.

  For this reason, even if the misalignment occurs between the impurity diffusion layer and the gate polysilicon layer and the memory cell MC selected at the time of reading is a cell having a layout unit with a smaller driving capability, the self Since the activation timing of the timing signal is appropriately adjusted according to the positional deviation, the activation timing of the sense amplifier activation signal SA is more than the timing at which a predetermined potential difference is generated in the bit line pair BL, XBL of the selected memory cell. It can be surely slowed down.

  Therefore, in the twelfth embodiment of the present invention, the activation timing of the sense amplifier activation signal SA is set to the bit line of the normal memory cell MC even when a positional shift occurs between the impurity diffusion layer and the gate polysilicon layer. It is possible to prevent the predetermined potential difference between the pair BL and XBL from becoming earlier than the timing at which the pair of BL and XBL is generated, and to prevent erroneous reading of retained data.

  In the twelfth embodiment, the self-timing signal SLF is generated from the pair of dummy bit line pairs DBL and XDBL. However, the present invention is not limited to this. A line pair DBL, XDBL may be provided, and the self-timing signal SLF may be generated after being based on the potential of the dummy bit line having the slowest potential decrease rate among all the dummy bit lines DBL, XDBL.

  In the eleventh and twelfth embodiments described above, the setting pattern of the data held in the plurality of load dummy memory cells LDMC connected to each dummy bit line pair can be an arbitrary pattern. For example, the setting pattern of retained data in the plurality of load dummy memory cells LDMC may be reversed from the setting pattern of the self-timing dummy memory cell SDMC, similarly to the setting pattern of FIG. Alternatively, by holding the connection nodes n1 and n2 of the inverter pair of each load dummy memory cell LDMC in a floating state, the data held in each load dummy memory cell LDMC may be indefinite.

  In the eleventh and twelfth embodiments described above, the layout examples of the normal layout unit and the symmetrical layout unit of the memory cell are not limited to those shown in FIG. Any layout having the above may be used.

  In each of the above-described embodiments, the example in which the self-timing signal is generated by the timing control circuit having the dummy memory cell and the sense amplifier activation signal is generated based on the self-timing signal has been described. However, other timing signals, for example, a bit line equalize signal, an equalize signal for a sense amplifier output line, and an output enable signal for an output circuit may be generated.

  In each of the above embodiments, the SRAM has been described as an example. However, the present invention is not limited to this, and the present invention can be applied to other semiconductor memories such as DRAM and FeRAM. Of course.

  As described above, the present invention is effective for use in a semiconductor memory having a self-timing circuit as a generation circuit of a sense amplifier activation signal for activating a sense amplifier circuit, and in particular, various device characteristics such as temperature change and manufacturing variation. Regardless of the variation factor, it is required to reliably prevent erroneous reading of data held in the normal memory cell MC, and it is preferable to use it for a semiconductor memory that requires a sufficient read margin.

Claims (5)

Multiple word lines,
Multiple bit lines,
A memory cell array having a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
A semiconductor memory including a self-timing circuit that is arranged in the vicinity of the memory cell array and generates a self-timing signal that determines an operation timing of an internal circuit when the memory cell is read;
The self-timing circuit is
A dummy word line selected in response to the selection of the word line;
A first dummy bit line in which a plurality of first self-timing dummy memory cells connected to the dummy word line and configured from a normal layout unit are continuously arranged;
A second dummy in which a plurality of second self-timing dummy memory cells connected to the dummy word line and composed of a symmetrical layout unit having a point-symmetrical or line-symmetrical relationship with the normal layout unit are continuously arranged. Bit lines,
The first dummy bit line and the second dummy bit line are inputted, and the self is based on the potential change of the dummy bit line having the slower potential change speed of the first and second dummy bit lines. A semiconductor memory comprising a timing control circuit for outputting a timing signal.   2. The semiconductor memory according to claim 1, wherein the memory cells in the memory cell array are laid out so that the normal layout units and the symmetrical layout units are alternately arranged along the bit lines. A sense amplifier circuit for detecting a potential output to the bit line when the memory cell is read;
2. The semiconductor memory according to claim 1, wherein an activation timing of a sense amplifier activation signal for activating the sense amplifier circuit is determined based on the self-timing signal. Multiple word lines,
Multiple bit lines,
A memory cell array having a plurality of memory cells arranged at intersections of the plurality of word lines and the plurality of bit lines;
A semiconductor memory including a self-timing circuit that is arranged in the vicinity of the memory cell array and generates a self-timing signal that determines an operation timing of an internal circuit when the memory cell is read;
The self-timing circuit is
A dummy word line selected in response to the selection of the word line;
A first self-timing dummy memory cell configured from a normal layout unit; and a second self-timing dummy memory cell configured from a symmetrical layout unit having a point-symmetric or line-symmetric relationship with the normal layout unit. A dummy bit line pair having,
A timing control circuit that inputs the dummy bit line pair and outputs the self-timing signal based on the potential change of the dummy bit line of the dummy bit line pair whose potential change rate is slower,
Each of the first and second self-timing dummy memory cells includes:
A pair of inverters with one output node cross-connected to the other input node;
A pair of transfer transistors connecting the first connection node of the pair of inverters to one dummy bit line of the pair of dummy bit lines and connecting the second connection node of the pair of inverters to the other dummy bit line And
A semiconductor memory, wherein the gates of the pair of transfer transistors are electrically isolated from each other. Of the separated gates of the pair of transfer transistors of the first self-timing dummy memory cell, the gate on the one dummy bit line side is connected to the dummy word line,
The gate on the other dummy bit line side among the separated gates of the pair of transfer transistors of the second self-timing dummy memory cell is connected to the dummy word line. 4. The semiconductor memory according to 4.

Images