JP4917292B2 - Test apparatus and test method - Google Patents

Description

  The present invention relates to a test apparatus and a test method for testing a memory under test. In particular, the present invention relates to a test apparatus that evaluates a memory under test based on a time during which the memory under test returns from a busy state to a ready state when a predetermined signal is input to the memory under test.

  Conventionally, as an item for testing a memory under test such as a flash memory, predetermined data is written into the memory under test, and the memory under test is determined based on whether the data read from the memory under test matches the expected value data. Items to be evaluated are known. Further, there is a demand for evaluating the memory under test based on the time from when a predetermined signal is input to the memory under test such as a flash memory until the memory under test returns from the busy state to the ready state. .

  Since related patent documents are not recognized at present, the description is omitted.

  On the other hand, the conventional test apparatus includes a pattern generation unit that writes predetermined data to the memory under test, and a logic comparison circuit that determines whether the data read from the memory under test matches the expected value data. ing. However, there is no means for accurately measuring the time until the memory under test returns from the busy state to the ready state.

  For example, a conventional test apparatus may have a counter that measures the period of the clock signal output from the memory under test, but the time until the memory under test returns from the busy state to the ready state using the counter. It did not have a function of measuring.

  Therefore, an object of the present invention is to provide a test apparatus and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

In order to solve the above problems, a first aspect of the present invention, there is provided a test apparatus for testing a memory under test, a plurality of test patterns, see write sequentially written to the memory under test, and, in the test pattern A pattern generator that outputs a measurement cycle signal indicating the start timing of writing to the memory under test, and a logical value of the MUT signal output from the memory under test after writing the measurement cycle signal writes the next test pattern. By counting the number of pulses of the reference clock having a predetermined frequency , the period until switching from the first logical value indicating the incapable state to the second logical value indicating that the next test pattern can be written becomes possible. Provided is a test apparatus including a period measuring unit for measuring.

  The memory under test indicates the first logic value when the test pattern is written and the next test pattern cannot be written, and the second logic when the next test pattern can be written. The MUT signal indicating the value is output, the pattern generation unit outputs the measurement cycle signal indicating the start timing of writing the test pattern, and the period measurement unit receives the measurement cycle signal, and then the logical value of the MUT signal is The number of pulses of the reference clock may be counted during the period from when one logic value is switched to the second logic value.

  The test apparatus generates a pulse signal having a pulse width corresponding to a period from when the measurement cycle signal is received until the logical value of the MUT signal switches from the first logical value to the second logical value, and based on the pulse signal You may further provide the set reset latch which controls the pulse count period in a period measurement part. The test apparatus may further include a capture memory that stores a measurement result in the period measurement unit.

  The test apparatus selects either the evaluation unit that evaluates the memory under test based on the measurement result in the period measurement unit, the measurement result in the period measurement unit, or the evaluation result in the evaluation unit, and outputs the selected result to the capture memory. 1 result selection part may be further provided.

  The test apparatus includes: a logical comparison unit that determines pass / fail of each address of the memory under test based on read data read from the memory under test; a determination result in the logical comparison unit; or a signal output from the first result selection unit A second result selection unit that selects one of them and stores it in the capture memory may be further provided.

  The evaluation unit may include a plurality of registers that store different reference values, and a comparison circuit that compares each reference value with the measurement result and outputs an evaluation value according to the comparison result.

  The test apparatus outputs a time-out signal when the logical value of the MUT signal is not switched from the first logical value to the second logical value after a predetermined period elapses after the writing of the test pattern to the memory under test is started. May be further provided, and the evaluation unit may evaluate the memory under test further based on the timeout signal.

  The pattern generation unit sequentially inputs each test pattern to the memory under test at a predetermined test cycle for each test pattern, and the error detection unit starts writing each test pattern and then If the logic value of the MUT signal does not switch from the first logic value to the second logic value during the test period corresponding to, a timeout signal may be output.

  The test apparatus may further include an initialization unit that initializes the count value of the cycle measurement unit for each test cycle. The period measurement unit may integrate the count values for the respective test patterns.

In the second embodiment of the present invention, there is provided a test method for testing a memory under test, a plurality of test patterns, see write sequentially written to the memory under test, and the initiation of writing to the memory under test a test pattern A pattern generation stage for outputting a measurement cycle signal indicating timing, and a first logical value indicating that the logical value of the MUT signal output from the memory under test cannot write the next test pattern after receiving the measurement cycle signal A period measurement step for measuring a period from when the first test pattern is written to a second logical value indicating that the next test pattern can be written by counting the number of pulses of a reference clock having a predetermined frequency. Provide test methods.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 is a diagram showing an outline of the configuration of a test apparatus 100 according to an embodiment of the present invention. The test apparatus 100 is an apparatus for testing a memory under test 200 such as a flash memory, and includes a control unit 10, a test cycle generation unit 12, a pattern generation unit 14, a logic comparison unit 16, an input / output circuit 18, and a cycle measurement unit 24. A capture memory 26 and a bus 29. The control unit 10 controls the test cycle generation unit 12, the pattern generation unit 14, the logic comparison unit 16, the input / output circuit 18, the cycle measurement unit 24, and the capture memory 26 via the bus 29.

  Further, the test apparatus 100 writes predetermined data into the memory under test 200, and based on the data read from the memory under test 200, a memory cell test for determining pass / fail of the memory under test 200, and predetermined memory in the memory under test 200 And the operation completion time test for judging whether the memory under test 200 is good or not based on the time until the memory under test 200 returns from the busy state to the ready state. Here, the busy state refers to a state where the next signal cannot be input to the memory under test 200, for example, and the ready state refers to a state where a signal can be input to the memory under test 200, for example.

  First, the operation of the test apparatus 100 when performing a memory cell test will be described. The control unit 10 controls each component of the test apparatus 100 based on a test program and a test pattern given in advance. For example, the control unit 10 causes the pattern generation unit 14 to generate a desired test pattern based on the test pattern. Further, the control unit 10 causes the test cycle generation unit 12 to generate a test cycle signal having a desired cycle based on a test program given in advance. The pattern generator 14 inputs each data of the test pattern to the memory under test 200 via the input / output circuit 18 in accordance with the test cycle signal generated by the test cycle generator 12.

  The input / output circuit 18 includes a driver 20 and a comparator 22. The driver 20 shapes the test pattern output from the pattern generator 14 and inputs the test pattern to the memory under test 200. The comparator 22 compares the signal output from the memory under test 200 with a predetermined threshold voltage and converts the output signal into digital data.

  The logic comparison unit 16 compares the data output from the comparator 22 with the expected value data given from the pattern generation unit 14 to determine whether the memory under test 200 is good or bad. For example, the logical comparison unit 16 may compare the data value read from each address of the memory under test 200 with the expected value data corresponding to the address, and determine the quality of each address. Further, the pattern generation unit 14 may supply the same data as the test pattern written in the memory under test 200 to the logic comparison unit 16 as expected value data.

  The capture memory 26 stores the determination result in the logic comparison unit 16. For example, the capture memory 26 stores the determination result for each address of the memory under test 200 in association with each address. With such an operation, it is possible to determine whether the memory cell of the memory under test 200 is good or bad. In addition, the failure analysis of the memory under test 200 can be performed by fetching the determination result into the capture memory 26.

  Next, the operation of the test apparatus 100 when performing the operation completion time test will be described. The pattern generator 14 sequentially inputs a plurality of test patterns for operating the memory under test 200 to the memory under test 200. Further, the pattern generator 14 outputs a measurement cycle signal indicating the cycle in which the test is performed. For example, the measurement cycle signal may be a signal indicating H logic from the timing at which the test is to be started to the timing at which the test is to be ended.

  When the memory under test 200 receives each test pattern, the memory under test 200 outputs a MUT signal indicating whether or not the next test pattern can be input. For example, the MUT signal is a signal indicating a first logical value when the next test pattern cannot be written, and indicating a second logical value when the next test pattern can be written. In this example, the case where the first logic value is L logic and the second logic value is H logic will be described.

  The cycle measuring unit 24 calculates the cycle from the start of writing the test pattern to the memory under test 200 until the memory under test 200 becomes ready to write the next test pattern at a predetermined frequency. It is measured by counting the number of reference clock pulses. For example, the period measurement unit 24 may be a counter that counts the number of pulses of the reference clock during a period from when the rising edge of the measurement cycle signal is input until the logical value of the MUT signal is switched from L logic to H logic.

  The period measurement unit 24 may receive the MUT signal via the comparator 22. For example, the test apparatus 100 may include a plurality of input / output units 18 corresponding to the plurality of pins of the memory under test 200. The period measurement unit 24 may receive the MUT signal via the comparator 22 corresponding to the pin of the memory under test 200 that outputs the MUT signal.

  Further, the period measuring unit 24 may determine pass / fail of the memory under test 200 based on the count result. The period measuring unit 24 may further have a function of receiving the clock signal output from the memory under test 200 via the comparator 22 and measuring the period of the clock signal. The control unit 10 may control which measurement is performed by the period measurement unit 24. The capture memory 26 stores a count result or a determination result in the period measurement unit 24. By such an operation, an operation completion time test can be performed.

  FIG. 2 is a diagram illustrating an example of a detailed configuration of the test apparatus 100. FIG. 2 shows a configuration for performing an operation completion time test, and shows a test apparatus 100 in which the control unit 10, test cycle generation unit 12, pattern generation unit 14, logic comparison unit 16, input / output circuit 18, and bus 29 are omitted. Show.

  In addition to the configuration described in FIG. 1, the test apparatus 100 includes a trigger generation unit 28, a divided clock selection unit 30, a counter clock selection unit 32, a register 34, a frequency divider 36, a set / reset latch 38, a pulse selection unit 40, An initialization unit 42, an error detection unit 54, and a measurement result transmission unit 56 are further provided.

  The trigger generation unit 28 generates a trigger signal for controlling the cycle measurement unit 24 based on the measurement cycle signal output from the pattern generation unit 14 and the test cycle signal given through the bus 29. For example, the trigger generation unit 28 outputs a trigger signal in accordance with the pulse of the test cycle signal that is first given after the measurement cycle signal indicates H logic.

  The set / reset latch 38 generates a pulse signal based on the trigger signal and the MUT signal output from the memory under test 200. For example, the set / reset latch 38 generates a pulse signal having a pulse width corresponding to a period from when the trigger signal is received until the logical value of the MUT signal is switched from L logic to H logic. The set / reset latch 38 supplies the pulse signal to the period measurement unit 24 via the pulse selection unit 40 and controls the pulse counting period in the period measurement unit 24.

  The period measurement unit 24 counts the number of pulses of the reference clock given through the counter clock selection unit 32 during the period in which the pulse signal indicates H logic. With such a configuration, it is possible to measure the time until the memory under test 200 returns from the busy state to the ready state.

  The measurement result transmission unit 56 stores the measurement result in the period measurement unit 24 in the capture memory 26. Further, the measurement result transmission unit 56 may determine pass / fail of the memory under test 200 based on the measurement result in the period measurement unit 24 and store the determination result in the capture memory 26.

  In this example, the measurement result transmission unit 56 includes an evaluation unit 44, a first result selection unit 46, and a second result selection unit 48. The evaluation unit 44 determines pass / fail of the memory under test 200 based on the measurement result in the period measurement unit 24. The first result selection unit 46 selects and outputs either the measurement result in the period measurement unit 24 or the evaluation result in the evaluation unit 44. With such a configuration, any desired data of the raw measurement data in the period measurement unit 24 or the evaluation result in the evaluation unit 44 can be stored in the capture memory 26.

  The second result selection unit 48 selects either the comparison result in the logic comparison unit 16 or the signal output from the first result selection unit 46 and stores it in the capture memory 26. With such a configuration, a desired test result of either the memory cell test or the operation completion time test can be stored in the capture memory 26.

  In addition, when a plurality of test patterns are sequentially input to the memory under test 200 and the time until the memory under test 200 changes from the busy state to the ready state is measured for each test pattern, the initialization unit 42 The count value in the period measurement unit 24 may be reset to the initial value for each test pattern. Since each test pattern is input to the memory under test 200 according to the test cycle, the initialization unit 42 may reset the count value in the cycle measurement unit 24 to the initial value according to the test cycle.

  Moreover, the initialization part 42 may reset the measured value in the period measurement part 24 to an initial value for every some test pattern. In this case, the period measurement unit 24 can integrate the count values for the respective test patterns. That is, the count values for a predetermined number of test patterns can be integrated by not resetting the measurement values in the period measurement unit 24 for each test pattern. Thus, for example, when the memory under test 200 has a plurality of address blocks, when inputting a test pattern for each address block, the count values for a predetermined number of address blocks can be integrated.

  Further, the error detection unit 54 outputs a time-out signal when the MUT signal does not switch from the L logic to the H logic until a predetermined period elapses after the writing of the test pattern to the memory under test 200 is started. To do. In this example, the error detection unit 54 detects the timing at which writing of the test pattern is started based on the measurement cycle signal and the test cycle. Further, based on the signal output from the set / reset latch 38, it is detected whether or not the MUT signal has been switched from L logic to H logic. The evaluation unit 44 may determine pass / fail of the memory under test 200 based on the timeout signal.

  Further, in the case where the test apparatus 100 performs testing by inputting the same test pattern in parallel to a plurality of memories under test 200, when the time-out signal is detected for any of the memories under test 200, the control unit 10 May end the test cycle using the test pattern and perform the test using the next test pattern on all the memories under test 200. The predetermined period for detecting the timeout may be substantially the same length as the test cycle for performing the test. For example, the error detection unit 54 determines that the MUT signal is L logic after the pattern generation unit starts inputting the test pattern in synchronization with the test cycle signal and detects a pulse indicating the next test cycle in the test cycle signal. A timeout signal may be output when the logic is not switched from H to H.

  The period measuring unit 24 may be a clock period measuring counter included in a conventional test apparatus. In this case, in the conventional test apparatus, the measurement result of the counter is read to the control unit 10 via the bus 29. On the other hand, the test apparatus 100 in this example can store the measurement result in the period measurement unit 24 in the capture memory 26 via the measurement result transmission unit 56. For this reason, data processing after measurement can be performed at high speed.

  When measuring the period of the clock signal output from the memory under test 200 using the period measurement unit 24, the pulse selection unit 40 receives the clock signal output from the memory under test 200 as the MUT signal and selects the MUT signal. And supplied to the period measuring unit 24. In this case, the pulse selector 40 may receive the clock signal via the comparator 22 (see FIG. 1) corresponding to the pin of the memory under test 200 that outputs the clock signal.

  The period measurement unit 24 counts the number of pulses of the reference clock during the period when the MUT signal indicates H logic. With such a configuration, the period of the clock signal output from the memory under test 200 can be measured.

  In addition, the period measurement unit 24 may receive a clock signal divided by a predetermined division ratio and count the number of pulses of the reference clock according to the signal. Thereby, in the clock signal, the period for each predetermined number of cycles determined by the division ratio can be measured. In this case, the frequency divider 36 receives the clock signal via the frequency-divided clock selection unit 30 and divides the clock signal by the frequency division ratio set in the register 34. The pulse selection unit 40 selects the frequency-divided clock output from the frequency divider 36 and supplies it to the period measurement unit 24.

  According to the test apparatus 100 in this example, the time for the memory under test 200 to return from the busy state to the ready state can be accurately measured. In addition, by providing the set / reset latch 38 and the pulse selector 40, the return time can be measured using a counter included in a conventional test apparatus. Therefore, the return time can be measured with a small circuit. Further, by providing the measurement result transmission unit 56, the measurement result can be stored in the capture memory 26. For this reason, data transmission and data processing can be performed at high speed.

  FIG. 3 is a diagram illustrating an example of the configuration of the evaluation unit 44. The evaluation unit 44 includes a comparison circuit 50 and a plurality of registers 52. The plurality of registers 52 store different reference values. The comparison circuit 50 compares the measurement result in the period measurement unit 24 with a plurality of reference values stored in the respective registers 52, and evaluates the memory under test 200 in a plurality of stages. The capture memory 26 may store evaluations according to the plurality of stages.

  FIG. 4 is a diagram illustrating an example of a timing chart showing the operation of the test apparatus 100. When performing a memory cell test of the memory under test 200, the test cycle generator 12 generates test cycle signals having substantially the same cycle, as shown in FIG. The pattern generator 14 inputs a test pattern such as an address pattern or a data pattern to the memory under test 200 in synchronization with the test cycle signal.

  When the operation completion time test of the memory under test 200 is performed, the test cycle generator 12 generates a test cycle signal at a cycle corresponding to the period during which the test is to be performed. Further, the pattern generator 14 outputs a measurement cycle signal having a pulse width corresponding to the period in which the test is to be performed.

  As described above, the trigger generator 28 generates a trigger signal having a pulse corresponding to the test cycle signal and the measurement cycle signal. Further, as described above, the memory under test 200 outputs a MUT signal indicating whether or not the next program is ready to be executed after a predetermined program is input.

  The set / reset latch 38 generates a pulse signal having a pulse width from the timing of the trigger signal to the timing of the rising edge of the MUT signal. The period measurement unit 24 counts the reference clock pulses while the pulse signal indicates H logic. With such an operation, the operation completion time of the memory under test 200 can be measured.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  As is clear from the above, according to the present invention, it is possible to accurately measure the time for the memory under test to return from the busy state to the ready state. In addition, the return time can be measured using a counter included in a conventional test apparatus. Therefore, the return time can be measured with a small circuit. In addition, the measurement result can be stored in a capture memory included in a conventional test apparatus. For this reason, data transmission and data processing can be performed at high speed.

It is a figure which shows the outline | summary of a structure of the test apparatus 100 which concerns on embodiment of this invention. 2 is a diagram illustrating an example of a detailed configuration of a test apparatus 100. FIG. 3 is a diagram illustrating an example of a configuration of an evaluation unit 44. FIG. FIG. 3 is a diagram illustrating an example of a timing chart showing the operation of the test apparatus 100.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Control part, 12 ... Test period generation part, 14 ... Pattern generation part, l6 ... Logic comparison part, 18 ... Input / output circuit, 20 ... Driver, 22 ... Comparator, 24... Period measurement unit, 26... Capture memory, 28... Trigger generation unit, 29 .. bus, 30 .. divided clock selection unit, 32. 34 ... Register, 36 ... Frequency divider, 38 ... Set / reset latch, 40 ... Pulse selection unit, 42 ... Initialization unit, 44 ... Evaluation unit, 46 ... No. 1 result selection unit, 48 ... second result selection unit, 50 ... comparison circuit, 52 ... register, 54 ... error detection unit, 56 ... measurement result transmission unit, 100 ... test Apparatus, 200... Memory under test

Claims (12)

A test apparatus for testing a memory under test,
A pattern generator for sequentially writing a plurality of test patterns to the memory under test and outputting a measurement cycle signal indicating a start timing of writing the test pattern to the memory under test;
After receiving the measurement cycle signal, the next test pattern can be written from the first logic value indicating that the logic value of the MUT signal output from the memory under test cannot write the next test pattern. A test apparatus comprising: a period measuring unit that measures a period until switching to a second logical value indicating that a state is reached by counting the number of pulses of a reference clock having a predetermined frequency. A pulse signal having a pulse width corresponding to a period from when the measurement cycle signal is received until the logical value of the MUT signal is switched from the first logical value to the second logical value is generated, and based on the pulse signal The test apparatus according to claim 1, further comprising a set / reset latch that controls a pulse counting period in the period measurement unit. The test apparatus according to claim 2, further comprising a capture memory that stores a measurement result in the period measurement unit. An evaluation unit that evaluates the memory under test based on a measurement result in the period measurement unit;
The test apparatus according to claim 3, further comprising: a first result selection unit that selects either the measurement result in the period measurement unit or the evaluation result in the evaluation unit and outputs the selected result to the capture memory. A logical comparison unit for determining pass / fail of each address of the memory under test based on read data read from the memory under test;
The test apparatus according to claim 4, further comprising: a second result selection unit that selects either a determination result in the logical comparison unit or a signal output from the first result selection unit and stores the selected result in the capture memory. The evaluation unit is
A plurality of registers each storing different reference values;
The test apparatus according to claim 4, further comprising: a comparison circuit that compares each of the reference values with the measurement result and outputs an evaluation value according to the comparison result. A time-out occurs when the logical value of the MUT signal does not change from the first logical value to the second logical value after a predetermined period of time has elapsed since the start of writing of the test pattern to the memory under test. An error detection unit for outputting a signal;
The test apparatus according to claim 4, wherein the evaluation unit evaluates the memory under test based on the timeout signal. The pattern generation unit sequentially inputs each of the test patterns to the memory under test at a predetermined test cycle for each of the test patterns.
The error detection unit starts writing the respective test patterns and then changes the logical value of the MUT signal from the first logical value to the second logical value during the test cycle corresponding to the test pattern. The test apparatus according to claim 7, wherein a time-out signal is output when the mode is not switched to. The test apparatus according to claim 8, further comprising an initialization unit that initializes a count value of the cycle measurement unit for each test cycle. The test apparatus according to claim 2, wherein the period measurement unit accumulates count values for the respective test patterns. A test cycle signal having a predetermined cycle and the measurement cycle signal are received, and after the measurement cycle signal indicates a predetermined logic value, a trigger signal is output in response to a pulse of the test cycle signal that is first applied. A trigger generating unit for
The pattern generation unit inputs each data of the test pattern to the memory under test according to the test cycle signal,
The set-reset latch generates a pulse signal having a pulse width corresponding to a period from when the trigger signal is received until a logical value of the MUT signal is switched from the first logical value to the second logical value. Item 11. The test apparatus according to any one of Items 2 to 10. A test method for testing a memory under test,
A pattern generation stage in which a pattern generation unit of the test apparatus sequentially writes a plurality of test patterns to the memory under test and outputs a measurement cycle signal indicating a start timing of writing the test pattern to the memory under test;
After the period measurement unit of the test apparatus receives the measurement cycle signal, the logical value of the MUT signal output from the memory under test is changed from the first logical value indicating the state in which the next test pattern cannot be written to A period measuring step of measuring a period until switching to the second logical value indicating that the test pattern can be written by counting the number of pulses of a reference clock having a predetermined frequency. .

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