JP4911943B2 - Insulated gate field effect transistor - Google Patents

Description

  The present invention relates to a semiconductor element used as a field effect transistor, a light emitting diode, and various sensors.

Diamond has a thermal conductivity of 20W / cm · K, the band gap 5.47 eV, saturated electron mobility 2000cm ² / V · s, and the hole mobility is 2100cm ² / V · s, has excellent device characteristics Application to electronic devices, high-power devices, high-frequency devices, and the like that operate under harsh environments exposed to high temperatures and radiation is expected.

  Conventionally, as a structure of a field effect transistor (FET) using a diamond thin film, an insulated gate field effect transistor (Metal Insulator Semiconductor) in which an insulating layer is inserted between a gate electrode and a channel layer as an operation layer. Field Effect Transistor (MISFET) has been proposed (see Patent Document 1). FIG. 5 is a cross-sectional view showing a MISFET described in Patent Document 1. In FIG. As shown in FIG. 5, in the MISFET 100 described in Patent Document 1, a semiconductor diamond layer 102 is formed on an insulating diamond single crystal substrate 101, and an insulating layer 103 is locally formed on the semiconductor diamond layer 102. Yes. A source electrode 104 and a drain electrode 105 are formed on the semiconductor diamond layer 102 with an insulating layer 103 interposed therebetween, and a gate electrode 106 is formed on the insulating layer.

Conventionally, an FET having a structure using a high-resistance diamond layer as a channel layer has also been proposed (see Patent Document 2). FIG. 6 is a diagram schematically showing the FET described in Patent Document 2. As shown in FIG. As shown in FIG. 6, the FET 110 described in Patent Document 2 includes a semiconductor diamond layer 111 that is in contact with the source electrode 114 and a semiconductor diamond layer 113 that is in contact with the drain electrode 116 and has the same conductivity type as the semiconductor diamond layer 111. A high resistance diamond layer 112 is formed therebetween, and a gate electrode 115 is formed so as to be in contact with the high resistance diamond layer 112. In the FET 110, carriers that reach the drain electrode 116 from the source electrode 114 flow in the semiconductor diamond layer 111, the high resistance diamond layer 112, and the semiconductor diamond layer 113 in this order. By varying the voltage V _G applied to the gate electrode 115, by changing the potential of the high-resistivity diamond layer 112, the amount of carrier injected from the semiconductor diamond layer 111 where the source electrode 114 is in contact to the high-resistivity diamond layer 112 Can be controlled.

  In the FET having such a structure, a pair of semiconductor diamond layers serving as a source and a drain is formed of p-type diamond, and a high-resistance diamond layer serving as a channel is formed of high-purity diamond. -It is called an i-p type FET. Note that “i” in the p-i-p type FET indicates “intrinsic semiconductor”.

Further, a FET (see Patent Document 3) in which a high-resistance diamond layer is formed of p-type diamond having a carrier concentration of 1 × 10 ¹⁵ cm ⁻³ or less, and a pair of p-type semiconductor regions serving as a source region and a drain region There has also been proposed an FET in which a third semiconductor region serving as a channel region is formed on a gap formed therebetween (see Patent Document 4). Further, Patent Document 4 discloses that a low-resistance substrate may be used and a charge path may be provided in the substrate.

  In the p-i-p type FET described above, when the gate electrode is on, charges are injected from the p layer into the i layer, which is the channel region, and a current flows between the source and drain.

Japanese Patent Laid-Open No. 1-158774 Japanese Patent No. 3273985 JP 2002-76369 A JP 2002-57167 A

However, the conventional techniques described above have the following problems. In the conventional FET, the channel layer is generally doped with about 1 × 10 ^{15 to} 1 × 10 ¹⁸ cm ^{−3 of a} dopant serving as an acceptor or a donor. Therefore, the influence of the Fermi level of the substrate is small. The pi-type FET described above has a problem that the dopant concentration in the channel layer is lower than that of the conventional FET, and therefore the influence of the Fermi level of the substrate becomes so large that it cannot be ignored.

  For example, in the FET having a structure in which the channel layer and the substrate are in contact, when a high-resistance substrate is used, the channel layer and the substrate have different conductivity types, and the conductivity type is the same as that of the channel layer, but the type of dopant. When a substrate having a significantly different value is used, the Fermi level in the band gap may be significantly different from 0.5 eV or more between the substrate and the channel layer. In such a case, the influence of the Fermi level of the substrate on the channel layer is further increased, and as a result, the conductance of the channel layer is reduced. When the conductance of the channel layer is reduced, it is convenient to reduce the leakage current when the FET is off. However, since a large bias must be applied to the gate electrode when the FET is on, the transconductance is reduced.

  The present invention has been made in view of such a problem, and an object thereof is to provide a semiconductor element capable of reducing the influence of the Fermi level of a substrate.

A semiconductor device according to the present invention includes a semiconductor substrate, a buffer layer formed on one surface of the semiconductor substrate with the same semiconductor material as the semiconductor substrate and having a different kind or concentration of dopant from the semiconductor substrate, and the buffer layer. The first and second semiconductor layers are locally formed respectively, and the first and second semiconductor layers are made of the same semiconductor material as the semiconductor substrate and have a lower dopant concentration than the first and second semiconductor layers. A third semiconductor layer serving as a channel region between the semiconductor layers, and a difference between the Fermi level of the semiconductor substrate and the Fermi level of the third semiconductor layer is V (eV), and the concentration of the effective donors when the conductivity type n type, when the p-type and the concentration of the effective acceptor n _S and _(m ^-3), wherein when the conductivity type of the buffer layer is n-type that effective donors The concentration of p In the case of the shape, the effective acceptor concentration is N _B (m ⁻³ ), the channel length which is the length between the first and second semiconductor layers is L (m), the elementary charge is e, and the buffer When the relative dielectric constant of the layer is ε _B and the dielectric constant of the vacuum is ε ₀ , the thickness D (m) of the buffer layer is within the range represented by the following formula 1.

In the present invention, a buffer layer is provided between the semiconductor substrate and the third semiconductor layer serving as a channel, and the thickness D of the buffer layer is within the range shown in Formula 1 above. And the Fermi level of the third semiconductor layer can be suppressed, and the Fermi level of the third semiconductor layer, which is the channel layer, can be brought to an optimum position. In Equation 1, the elementary charge e is 1.60 × 10 ⁻¹⁹ C, and the vacuum dielectric constant ε ₀ is 0.8854 × 10 ⁻¹¹ F / m.

The effective donor or effective acceptor concentration N _B (m ⁻³ ) in the buffer layer is less than ½ of the effective donor or effective acceptor concentration N _S (m ⁻³ ) in the semiconductor substrate, and the third The effective donor concentration or the effective acceptor concentration N _C (m ⁻³ ) in the semiconductor layer may be less than 10 times. As a result, the thickness of the buffer layer can be set within a practical range, and a decrease in mutual conductance due to variations in film thickness can be prevented.

  The buffer layer may have a conductivity type different from that of the semiconductor substrate. Thereby, the suppression effect of the Fermi level interaction can be further improved.

  Furthermore, the semiconductor substrate, the buffer layer, and the third semiconductor layer are at least one selected from the group consisting of diamond, aluminum nitride, boron nitride, barium nitride, indium nitride, silicon carbide, titanium oxide, and tin oxide. The semiconductor material can be used. When these wide band gap semiconductors are used, higher effects can be obtained.

Furthermore, when the conductivity type of the semiconductor substrate is n-type, the conductivity type of the buffer layer and the first and second semiconductor layers is p-type, and the third semiconductor layer has an intrinsic semiconductor or dopant concentration. You may form by the p-type semiconductor of 5 * 10 < ¹⁷ > cm <^-3> or less. Alternatively, when the conductivity type of the semiconductor substrate is p-type, the conductivity type of the buffer layer and the first and second semiconductor layers is n-type, and the third semiconductor layer has an intrinsic semiconductor or dopant concentration of 5 It can also be formed of an n-type semiconductor of × 10 ¹⁷ cm ⁻³ or less. Thus, a higher effect can be obtained when the third semiconductor layer is formed of an intrinsic semiconductor or a semiconductor having a dopant concentration of 5 × 10 ⁻¹⁷ cm ⁻³ or less.

  According to the present invention, since the buffer layer is provided between the semiconductor substrate and the third semiconductor layer, and the thickness of the buffer layer is optimized, the Fermi level of the semiconductor substrate and the third channel layer are formed. Interaction with the Fermi level of the semiconductor layer can be suppressed.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. In order to solve the above-mentioned problems, the present inventors have conducted extensive experimental research. As a result, problems caused by the interaction between the Fermi level of the channel layer and the Fermi level of the substrate are caused by the following factors. I found. When the Fermi level of the channel layer and the Fermi level of the substrate are different, a Fermi level transition layer is formed in the vicinity of the interface between the channel layer and the substrate. In this transition layer, the Fermi level of the channel layer is pushed toward the center of the band gap, the Fermi level becomes deep, and a carrier depletion state occurs.

  When the channel layer is thick, the Fermi level gradually approaches the position inherent to the channel layer as the channel layer moves away from the substrate. However, since the channel layer is generally as thin as 10 to 200 nm, the entire channel layer has the Fermi level of the substrate. In some cases, the entire channel layer may be depleted. In the case of the above-described p-i-p-type FET and the like, if the Fermi level of the channel layer is deep, the potential barrier in the charge injection into the channel layer becomes high, and it becomes difficult to inject the charge, so the conductance decreases. To do.

  Such a problem can be prevented by using a substrate whose Fermi level is the same as or approximately the same as that of the channel layer. Leakage current increases, and a new problem arises that wasteful current is consumed when the switch is off.

  When the substrate and the channel layer have the same conductivity type, there is little or no interaction between the Fermi level of the substrate and the Fermi level of the channel layer. This is because these Fermi levels are located on the same side of the band gap, that is, on the conduction band side if the conductivity type is n-type, and on the valence band side if p-type. This is because the position is the same when the dopant is the same, and the position is hardly changed even when the dopant is different. However, when the substrate and the channel layer are formed of a semiconductor having a large band gap, even if the conductivity type is the same, if the dopant is different, the difference in Fermi level may be, for example, 1 eV or more. When the conductivity type differs from that of the channel layer, the Fermi level difference may be several eV or more.

  Therefore, in the semiconductor element of this embodiment, a buffer layer is formed between the channel layer and the substrate to suppress the interaction between the Fermi level of the channel layer and the Fermi level of the substrate. FIG. 1 is a cross-sectional view showing the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor element 10 of the present embodiment is a FET or a diode having a p-i-p-type or n-i-n type structure. A buffer layer 2 made of the same semiconductor material as the semiconductor substrate 1 and having a different dopant type or concentration from the semiconductor substrate 1 is formed. On the buffer layer 2, semiconductor layers 3a and 3b, which are first and second semiconductor layers serving as a source and a drain, are locally formed, and the semiconductor layers 3a and 3b are opposed to each other. A channel layer 4, which is a third semiconductor layer made of the same semiconductor material as that of the semiconductor substrate 1 and having a dopant concentration lower than that of the semiconductor layers 3 a and 3 b, is formed on and between the end portions. Furthermore, a source electrode 5 and a drain electrode 6 are formed on the regions of the semiconductor layers 3a and 3b where the channel layer 4 is not formed. Furthermore, an insulating layer 7 is formed so as to cover the end portions of the source electrode 5 and the drain electrode 6 facing each other and the channel layer 4, and a gate electrode 8 is formed in the insulating layer 7 immediately above the channel layer 4. Is formed. In this semiconductor element 10, a region sandwiched between the semiconductor layers 3 a and 3 b in the channel layer 4 becomes a channel.

The semiconductor substrate 1, the buffer layer 2, and the channel layer 4 in the semiconductor element 10 of this embodiment are all formed of the same material or similar materials. The material forming these is preferably a wide gap semiconductor, for example, diamond, aluminum nitride (AlN), boron nitride (BN), barium nitride (BaN), indium nitride (InN), silicon carbide (SiC). Alternatively, a mixed crystal thereof, titanium oxide (TiO ₂ ), a compound obtained by adding a metal element to TiO ₂ , tin oxide (SnO ₂ ), a compound obtained by adding a metal element to SnO ₂ , or the like can be given.

In the semiconductor element 10 of this embodiment, the channel layer 4 is preferably formed of a high purity semiconductor or a semiconductor doped with a dopant at a low concentration. In other words, it is preferably a pip type semiconductor element or an nin type semiconductor element. When the structure is p-ip type, the conductivity type of the semiconductor substrate 1 is n-type, the conductivity types of the buffer layer 2 and the channel layer 4 are p-type, for example, the channel layer 4 (i region). However, when the trace amount of p-type dopant is less than 5 × 10 ¹⁷ cm ⁻³ , the semiconductor layers 3a and 3b may have a higher p-type dopant concentration. On the other hand, when the structure is an n-n-type, the conductivity type of the semiconductor substrate 1 is p-type, and the conductivity types of the buffer layer 2 and the channel layer 4 are n-type.

Furthermore, the thickness of the buffer layer 2 in the semiconductor element 10 of the present embodiment and the effective donor concentration when the conductivity type is n-type or the effective acceptor concentration when the conductivity type is p-type affect the Fermi level. Thus, the Fermi level of the channel layer 4 which changes is compensated. Specifically, the thickness of the buffer layer 2 is D (m) , the difference between the Fermi level of the semiconductor substrate 1 and the Fermi level of the channel layer 4 is V (eV), and when the semiconductor substrate 1 is n-type the concentration of the effective donors, the concentration of the effective acceptor when the p-type n _{S (m} ^-3), the concentration of the effective donors when the buffer layer 2 of n-type, when the p-type that the effective acceptor When the concentration of N _B (m ⁻³ ) and the length between the semiconductor layer 3 a and the semiconductor layer 3 b, that is, the channel length is L (m), the value of A represented by the following Equation 2 is 20 to 150 To be.

In addition, the effective acceptor concentration and the effective donor concentration in the above formula 2 are concentrations that do not include the compensation component. For example, when both the donor and the acceptor exist and are both monovalent, To do. Further, e is an elementary charge ( 1.60 × 10 ⁻¹⁹ C ), ε _B is a relative dielectric constant of the buffer layer, and ε ₀ is a vacuum dielectric constant (0.8854 × 10 ⁻¹¹ F / m). .

When the value of A represented by the above mathematical formula 2 is less than 20 , the leakage current at the time of OFF exceeds 1 mA / mm, and accordingly, the so-called standby power becomes so large as to be impractical. On the other hand, when the value of A exceeds 150 , the mutual conductance falls below 200 mS / mm, which is generally regarded as practical. The value of A is preferably 50 or more and 150 or less, whereby the mutual conductance can be 250 mS / mm or more. At this time, the leakage current is also 50 μA / mm or less, which is a level with no practical problem.

  Therefore, in the semiconductor element 10 of this embodiment, the thickness D of the buffer layer 2 is in the range represented by the following mathematical formula 3.

  Further, the thickness D of the buffer layer 2 is more preferably in a range represented by the following mathematical formula 4.

The concentration N _B of the effective donors or effective acceptor in the buffer layer 2 is, for more than half of the concentration N _S of effective donors or the effective acceptor in the semiconductor substrate 1, and an extremely thin thickness of the buffer layer 2, further The thickness must be adjusted precisely. For example, in the range of N _B ≧ (1/2) × N _S , if the thickness D of the buffer layer 2 becomes slightly thicker than the range of the above formula 3, it flows between the semiconductor layer 3a and the semiconductor layer 3b. Carriers flow through the buffer layer 2 rather than the channel layer 4, and as a result, the mutual conductance becomes small. Similarly, when the semiconductor device 10 of this embodiment, the concentration N _B of the effective donors or effective acceptor in the buffer layer 2 is not less than 10 times the concentration N _C effective donor or effective acceptor of the channel layer 4, the buffer When the thickness of the layer 2 has to be strictly adjusted and the thickness D of the buffer layer 2 is slightly larger than the range of the above mathematical formula 3, carriers flowing between the semiconductor layer 3a and the semiconductor layer 3b are generated. , The buffer layer 2 flows more than the channel layer 4. However, it is technically difficult to precisely adjust the thickness of the extremely thin buffer layer 2. Therefore, in the semiconductor device 10 of this embodiment, the concentration N _B of the effective donors or effective acceptor in the buffer layer 2, less than half the concentration N _S of effective donors or the effective acceptor in the semiconductor substrate 1, and channel It is set to be less than 10 times N _C (m ⁻³ ) indicating the effective donor concentration (when n-type) or effective acceptor concentration (when p-type) of the layer 4.

  Note that the n-type dopant (donor) added to each layer constituting the semiconductor element 10 of the present embodiment differs depending on the type of semiconductor and can be arbitrarily selected therein. For example, in the case of a group IV semiconductor such as diamond and silicon carbide, in addition to nitrogen, group V or group VI elements such as phosphorus, arsenic, antimony, sulfur, oxygen, and the like can be given. In the case of III-V semiconductors such as aluminum nitride, boron nitride, barium nitride, and indium nitride, Group VI elements can be used. In some cases, group V elements are also n-type dopants. In a metal oxide semiconductor such as titanium oxide or tin oxide, an element having a valence of 1 less than that of a constituent metal such as indium is likely to be an n-type dopant. Examples of the p-type dopant include group III elements such as aluminum, gallium, and indium in addition to boron in the case of a group IV semiconductor such as diamond and silicon carbide. In the case of group III-V semiconductors such as aluminum nitride, boron nitride, barium nitride, indium nitride, group II elements may be mentioned. In some cases, group V elements are also p-type dopants. In a metal oxide semiconductor such as titanium oxide or tin oxide, an element having a valence of 1 higher than that of a constituent metal such as indium is likely to be a p-type dopant.

  In the semiconductor element 10 of the present embodiment, the buffer layer 2 is provided between the semiconductor substrate 1 and the channel layer 4, the thickness of the buffer layer 2 and the doping amount are optimized, and the thickness D of the buffer layer 2 is set to the above formula. Therefore, the interaction between the Fermi level of the semiconductor substrate 1 and the Fermi level of the channel layer 4 can be suppressed, and the Fermi level of the channel layer can be set to an optimal position. As a result, the off-state leakage current can be reduced and the on-state current can be increased.

  Moreover, the semiconductor element 10 of this embodiment improves the effect of suppressing the interaction of the Fermi level generated between them by reversing the conductivity type of the semiconductor substrate 1 and the conductivity type of the buffer layer 2. be able to.

  The above-described effects can be obtained regardless of the type of material forming the semiconductor element. In particular, when the semiconductor substrate 1 and the channel layer 4 are formed of a wide band gap semiconductor, A great effect can be obtained when formed of a high-purity semiconductor or a lightly doped semiconductor.

Hereinafter, the effect of the embodiment of the present invention will be described by taking a field effect transistor using a diamond thin film as an example in comparison with a comparative example that is out of the scope of the present invention. In the present embodiment, by the following method, the concentration _N S ^{(m -3)} of effective donors of the semiconductor substrate 1, the thickness of the buffer layer 2 and the effective acceptor concentration _N B ^{(m -3),} the channel layer The length L (m) and the effective acceptor concentration N _C (m ⁻³ ) were different, and a p-i-p type FET having the structure shown in FIG. 1 was produced. First, as the semiconductor substrate 1, a high-pressure synthetic single crystal diamond substrate having a (100) surface and being an n-type semiconductor was used. The isolated substituted nitrogen concentration of this high-pressure synthetic single crystal diamond substrate measured by the infrared absorption method was 1 × 10 ^{18 to} 3 × 10 ¹⁹ cm ⁻³ . In the high-pressure synthetic single crystal diamond substrate used in this example, since the concentration of boron serving as an acceptor was less than 1/10 of the concentration of nitrogen serving as a donor, the above-mentioned isolated substitution nitrogen concentration was set as an effective donor concentration. .

A diamond film doped with B at a low concentration was formed as a buffer layer 2 on the high-pressure synthetic single crystal diamond substrate by a microwave plasma CVD method to a thickness of 50 to 200 nm. The film forming conditions at that time are a microwave CVD apparatus of 2.45 GHz, a reactive gas is a mixed gas of hydrogen, methane 0.3 to 0.5 volume% and diborane 0.1 to 2 ppm, The pressure in the reaction vessel was 6.6 kPa (50 Torr), and the substrate temperature was 750 to 800 ° C. The low-concentration B-doped diamond film thus obtained had an elemental B concentration measured by SIMS of 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . In this low-concentration B-doped diamond film, since the compensation ratio obtained by measuring the Hall effect was less than 1/10, the boron concentration measured by SIMS was determined as the effective acceptor concentration.

Next, after depositing an alumina film on the low-concentration B-doped diamond film, a linear pattern having a width of 0.1 to 1.0 μm was formed by lithography. Then, a diamond film doped with B at a high concentration is formed with a thickness of 50 nm by microwave plasma CVD, and then the alumina film is removed to form a B-doped diamond film with an interval of 0.2 μm. A pair of p-type semiconductor layers 3a and 3b was formed. The film forming conditions at that time are a microwave CVD apparatus of 2.45 GHz, and the reaction gas is a mixed gas of hydrogen, methane 0.3 to 0.5% by volume and diborane 0.01 to 0.05% by volume. The pressure in the reaction vessel was 6.6 kPa (50 Torr), and the substrate temperature was 750 to 800 ° C. The high-concentration B-doped diamond film thus obtained had a B concentration measured by secondary ion mass spectroscopy (SIMS) of 1 × 10 ^{20 to} 5 × 10 ²⁰ cm ⁻³ . In this high-concentration B-doped diamond film, since the compensation ratio obtained by measuring the Hall effect was less than 1/10, the B concentration measured by SIMS was determined as the effective acceptor concentration.

Next, a low-concentration B-doped diamond film having a thickness of 50 nm was formed as a channel layer 4 (i region) on the gap between the p-type semiconductor layers 3a and 3b and the ends facing each other. At that time, the diborane concentration in the reaction gas was set to 0.1 to 2 ppm, and other film formation conditions and pattern formation methods were the same as those of the p-type semiconductor layers 3a and 3b described above. The low-concentration B-doped diamond film thus obtained had an elemental B concentration measured by SIMS of 1 × 10 ^{16 to} 5 × 10 ¹⁷ cm ⁻³ . In this low-concentration B-doped diamond film, since the compensation ratio obtained by measuring the Hall effect was less than 1/10, the boron concentration measured by SIMS was determined as the effective acceptor concentration.

  Next, platinum electrodes were formed on the p-type semiconductor layers 3a and 3b by sputtering, and these were used as the source electrode 5 and the drain electrode 6, respectively. Then, an alumina film having a thickness of 50 nm was deposited as the insulating layer 7 by vapor deposition so as to cover the entire channel layer 4. Thereafter, a gold film was formed as a gate electrode 8 on the region immediately above the low-concentration B-doped diamond film of the alumina film by vapor deposition, and the p-i-p type FETs of Examples 1 to 14 and Comparative Examples 1 to 5 Was made.

  FIG. 2 is a cross-sectional view showing an FET of Comparative Example 6 of the present invention. Further, as shown in FIG. 2, the buffer layer is not provided, and the p-type semiconductor layers 13a and 13b made of the high-concentration B-doped diamond film and the low-concentration B-doped diamond film are formed on the high-pressure synthetic single crystal diamond substrate 11. A channel layer 14 was formed. Thereafter, platinum electrodes were formed on the p-type semiconductor layers 13 a and 13 b by sputtering, and these were used as the source electrode 15 and the drain electrode 16. And after vapor-depositing the alumina film used as the insulating layer 17, the gold film was formed as the gate electrode 18, and the pi-type FET20 of the comparative example 6 was produced. The configuration, manufacturing method, and manufacturing conditions of the FET 20 of Comparative Example 6 other than those described above were the same as those of the above-described Examples and Comparative Examples.

Next, when a potential was applied to each electrode of the FETs of Examples 1 to 14 and Comparative Examples 1 to 6, all showed typical FET operations. And in FET of the comparative example 6 which does not provide the buffer layer, when the drain voltage is -14V and the gate voltage is -10V, the normalized transconductance is 1 to 9 mS / mm. Table 1 below shows the value of A, the normalized leakage current at the OFF time, and the normalized transconductance in the FETs of Examples 1 to 14 and Comparative Examples 1 to 5 in which the buffer layer is provided between the substrate and the channel layer. Show. The normalized leakage current shown in Table 1 below is the value when the gate voltage is 0 V and the drain voltage is 30 V, and the normalized transconductance is when the gate voltage is −10 V and the drain voltage is −14 V. Is the value of Further, the following Table 1 Concentration _N S of effective donors of the substrate in each FET ^{(m -3),} the concentration _N B of the thickness and effective acceptor buffer layer ^{(m -3),} and the length of the channel layer L ( m) and effective acceptor concentration N _C (m ⁻³ ) are shown together. FIG. 3 is a graph showing the relationship between the value of A and the leakage current, with A on the horizontal axis and leakage current on the vertical axis. FIG. 4 shows A on the horizontal axis and A on the vertical axis. It is a graph which shows the relationship between the value of A, and a mutual conductance taking a mutual conductance.

As shown in Table 1, FIG. 3 and FIG. 4, the FETs of Examples 1 to 14 in which the value of A is in the range of 20 to 150 have a high mutual conductance of 200 mS / mm or more. The FETs of Examples 1, 2, 4, 5, 7, 9, 11 to 14 having an A of 50 or more exhibited excellent transistor characteristics with a leakage current of 50 μA / mm or less and a mutual conductance of 250 mS / mm or more. On the other hand, the FETs of Comparative Examples 1 to 5 in which the value of A exceeds 150 have a low mutual conductance of 190 mS / mm or less, and in particular, the FET of Comparative Example 5 with a thin buffer layer 2 of 0.1 nm. Only the characteristics equivalent to those of the FET of Comparative Example 6 in which the buffer layer 2 was not provided were obtained. In Comparative Example 6, since the value of A was less than 20 , the leakage current was as large as 10,000 μA / mm, and the mutual conductance was as low as 160 mS / mm.

It is sectional drawing which shows the semiconductor element of embodiment of this invention. It is sectional drawing which shows the semiconductor element of the comparative example 6 of this invention. FIG. 5 is a graph showing the relationship between the value of A and leakage current, with A on the horizontal axis and leakage current on the vertical axis. It is a graph which shows the relationship between the value of A and a mutual conductance, taking A on the horizontal axis and taking the mutual conductance on the vertical axis. It is sectional drawing which shows MISFET of patent document 1. FIG. It is sectional drawing which shows FET described in patent document 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1; Semiconductor substrate 2; Buffer layer 3a, 3b, 13a, 13b; Semiconductor layer 4, 14; Channel layer 5, 15, 104, 114; Source electrode 6, 16, 105, 116; Drain electrode 7, 17, 103; Insulating layer 8, 18, 106, 115; gate electrode 10; semiconductor element 11; high-pressure synthetic single crystal diamond substrate 20, 100, 110; FET
101; Insulating diamond single crystal substrate 102, 111, 113; Semiconductor diamond layer 112; High resistance diamond layer

Claims (6)

A semiconductor substrate, a buffer layer formed of the same semiconductor material as that of the semiconductor substrate on one surface of the semiconductor substrate and having a different kind or concentration of dopant from the semiconductor substrate, and locally formed on the buffer layer, respectively. The first and second semiconductor layers are formed of the same semiconductor material as that of the semiconductor substrate and have a dopant concentration lower than that of the first and second semiconductor layers to form a channel region between the first and second semiconductor layers. When the difference between the Fermi level of the semiconductor substrate and the Fermi level of the third semiconductor layer is V (eV), and the conductivity type of the semiconductor substrate is n-type the concentration of the effective donors, when the p-type and the concentration of the effective acceptor and n _{S (m} ^-3), the concentration of the effective donors when conductivity type is n-type of the buffer layer, when p-type Is its valid accept N _B (m ⁻³ ), the channel length which is the length between the first and second semiconductor layers is L (m), the elementary charge is e, and the relative dielectric constant of the buffer layer is An insulated gate field effect transistor characterized in that the thickness D (m) of the buffer layer is within a range represented by the following formula, where ε _B and the dielectric constant of vacuum is ε ₀ .

The effective donor or effective acceptor concentration N _B (m ⁻³ ) in the buffer layer is less than ½ of the effective donor or effective acceptor concentration N _S (m ⁻³ ) in the semiconductor substrate, and the third 2. The insulated gate field effect transistor according to claim 1, wherein the concentration is less than 10 times the effective donor concentration or the effective acceptor concentration N _C (m ⁻³ ) in the semiconductor layer. 3. The insulated gate field effect transistor according to claim 1, wherein the buffer layer has a conductivity type different from that of the semiconductor substrate. The semiconductor substrate, the buffer layer, and the third semiconductor layer are at least one semiconductor selected from the group consisting of diamond, aluminum nitride, boron nitride, barium nitride, indium nitride, silicon carbide, titanium oxide, and tin oxide. 4. The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is made of a material. The conductivity type of the semiconductor substrate is n-type, the conductivity type of the buffer layer and the first and second semiconductor layers is p-type, and the third semiconductor layer has an intrinsic semiconductor or dopant concentration of 5 × 10 5. 5. The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is formed of a p-type semiconductor of ¹⁷ cm ⁻³ or less. The conductivity type of the semiconductor substrate is p-type, the conductivity type of the buffer layer and the first and second semiconductor layers is n-type, and the third semiconductor layer has an intrinsic semiconductor or dopant concentration of 5 × 10 5. 5. The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is formed of an n-type semiconductor of ¹⁷ cm ⁻³ or less.

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