JP4905080B2 - Transfer circuit, transfer control method, imaging apparatus, control program - Google Patents

Description

The present invention relates to a transfer circuit suitable for use in an imaging apparatus such as a digital camera , a transfer control method, an imaging apparatus using these , and a control program .

  2. Description of the Related Art Conventionally, in a digital camera that records digital image data acquired by photographing on a recording medium, multiple stages of image processing are performed in the process of finally obtaining image data to be recorded. For example, Bayer interpolation processing for converting Bayer data temporarily stored in the memory at the time of shooting, that is, image data composed of pixels of color information corresponding to the color filter of the primary color Bayer array into YUV data composed of RGB data for each pixel is performed. It has been broken.

  In this Bayer interpolation processing, a plurality of pixels around the corresponding pixel, for example, 7 × 7 pixels, are used to generate one pixel of YUV data. Therefore, when converting the original Bayer data into YUV data of a desired image size, for example, when converting the Bayer data of 640 × 480 pixels into YUV data of the same 640 × 480 pixels, It is necessary to add a plurality of pixels called ring pixels around the data.

  Further, in such image processing, the entire image data (Bayer data or YUV data) is not used as a processing unit, but a band-like shape obtained by dividing the original image in the vertical direction from the relationship with restrictions caused by transfer capability. Data for a plurality of lines called a belt is used as a processing unit, and data is sequentially transferred from a working memory for each belt and processed (see FIG. 7).

On the other hand, when JPEG encoding processing is performed mainly after conversion to YUV data, if the encoding format is 4: 2: 2, for example, encoding is performed in units of 8 × 8 pixel blocks (MCU). If 4: 2: 0, encoding is performed in block units of 16 × 16 pixels. For this reason, for the purpose of speeding up the processing, the number of lines of the belt is preferably 8 lines in terms of YUV data or 16 lines that is a multiple thereof. In terms of Bayer data, for example, when 7 × 7 pixels of Bayer data are used to generate 1 pixel of YUV data, 3 pixels of Bayer data are required around each pixel. Therefore, it corresponds to 14 lines or 22 lines, respectively. In the first belt and the final belt, transfer is performed by adding the ring pixels as a shortage of Bayer data in advance to a fixed number of lines, for example, three lines (for example, Patent Document 1).
JP 2006-211402 A

  However, the number of lines of Bayer data may be a prime number that does not have a divisor, such as 479 lines or 29 lines. In such a case, the lines are transferred one line at a time in terms of YUV data conversion. . That is, in order to perform transfer with a simpler circuit configuration, the number of lines is matched between the belts instead of changing the number of lines between the belts. When transferring one line at a time in terms of YUV data conversion lines as described above, the second belt, the third belt, or the final -2nd belt is also used in addition to the first belt and the final belt. In addition, the ring pixel needs to be added to the Bayer data even in the last-first belt. Therefore, as in the prior art described above, only in the first belt and the final belt, the ring pixels are fixedly transferred, for example, by 3 lines, and the addition of ring pixels in other belts is considered. The transfer device that is not capable of handling the transfer particularly when the number of lines of the Bayer data is a prime number cannot be accommodated.

The present invention has been made in view of such a conventional problem. A transfer circuit capable of performing transfer by adding ring pixels without any problem regardless of the number of lines of Bayer data , and transfer It is an object to provide a control method, an imaging apparatus , and a control program .

The transfer circuit according to claim 1 is a transfer circuit for adding a ring pixel to the Bayer data stored in the storage means and transferring it, and the number of ring pixels added to the Bayer data stored in the storage means Is a storage unit that is stored in advance, an acquisition unit that acquires the number of pixels of Bayer data stored in the storage unit, and a transfer that is a transfer unit based on the number of pixels of Bayer data acquired by the acquisition unit A setting unit that sets the number of pixels, a determination unit that determines whether or not to add the ring pixel at each transfer with the number of transfer pixels set by the setting unit, and a ring pixel that is added by the determination unit When the determination is made, the number of ring pixels stored in the storage means and the number of transfer pixels set by the setting means are determined. A variable setting means for variably setting the number of rings pixels to be added at the time of transfer, and further comprising a.

According to a second aspect of the present invention, the setting means sets a divisor with respect to the total number of lines of Bayer data acquired by the acquisition means as the number of transfer lines as the transfer unit.

According to a third aspect of the present invention, the setting means has a maximum divisor that is less than or equal to the maximum number of lines that can be transferred at one time among the divisors of the total number of lines of Bayer data acquired by the acquisition means. Is set as the number of transfer lines serving as the transfer unit.

The variable setting means further compares the number of transfer lines set by the setting means with the number of ring pixels stored in the storage means, and based on the comparison result, the variable setting means It is characterized in that the number of ring pixels added at the time of transfer is variably set.
In the invention according to claim 5, the setting means sets the number of transfer lines as the transfer unit to one line when the total number of lines of the Bayer data acquired by the acquisition means is a prime number, When the total number of lines of Bayer data is not a prime number, a divisor with respect to the total number of lines of Bayer data is set as the number of transfer lines serving as the transfer unit.
According to a sixth aspect of the present invention, when the setting means sets the transfer line number serving as the transfer unit to a divisor with respect to the total number of Bayer data, the determining means sets the transfer unit thus set. If it is determined that a ring pixel is added only during the first transfer and the last transfer according to (1) and the number of transfer lines as the transfer unit is set by the setting means, the first transfer by the set transfer unit is determined. It is characterized in that it is determined that a ring pixel is added at the time of a plurality of transfers following the transfer and a plurality of transfers before the last transfer.
According to a seventh aspect of the present invention, the variable setting means is determined by the determining means to add a ring pixel at the time of a plurality of transfers following the first transfer and a plurality of transfers before the last transfer. In some cases, the maximum number of ring pixels added during the first transfer and the last transfer is maximized, and the number of ring pixels before and after the first transfer or the last transfer is less than this maximum number of ring pixels. To do.
According to an eighth aspect of the present invention, there is provided an image pickup apparatus comprising the transfer circuit according to any one of the first to seventh aspects, wherein the image pickup means picks up an image of a subject and acquires Bayer data; Storage control means for storing the acquired Bayer data in the storage means, and image data processing means for performing predetermined image data processing on the Bayer data transferred with the ring pixels added from the transfer circuit, It is further provided with the feature.
According to a ninth aspect of the present invention, there is provided a computer having an image pickup apparatus including the transfer circuit according to any one of the first to seventh aspects of the present invention, an image pickup unit that picks up an image of a subject and acquires Bayer data, and the image pickup unit. Storage control means for storing the acquired Bayer data in the storage means, image data processing means for performing predetermined image data processing on the Bayer data transferred with the ring pixels added from the transfer circuit, It is characterized by functioning.
The invention according to claim 10 is further a transfer control method for controlling transfer of a transfer circuit for adding a ring pixel to the Bayer data stored in the storage means and transferring the Bayer data, wherein the Bayer data stored in the storage means An acquisition step for acquiring the number of pixels, a setting step for setting the number of transfer pixels as a transfer unit based on the number of pixels of the Bayer data acquired by the acquisition step, and a transfer pixel number set by the setting step A determination step for determining whether or not to add the ring pixel at each transfer, and a ring pixel to be added to the Bayer data stored in the storage means when it is determined by the determination step that the ring pixel is to be added The number of ring pixels stored in the storage means in which the number is stored in advance, and the setting step. Based on the number of transfer pixels which are characterized by having a variable setting step for variably setting the number of rings pixels to be added at the time of the transfer, the.

According to the present invention, regardless of the number of lines of Bayer data, it is possible to efficiently transfer by adding ring pixels without any trouble.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a main configuration related to image processing of the camera device according to the present embodiment. As shown in FIG. 1, the camera apparatus according to the present embodiment includes a CPU 1, an ASIC (Application Specific Integrated Circuit) 2, a RAM 3, a CCD 4, a ROM 5, an LCD (Liquid Crystal Display) 6, a keyboard 7, and the like. And a power supply unit 8 for supplying power to each unit.

  The CPU 1 controls the entire camera apparatus by executing a program stored in the ROM 5. The CPU 1 outputs a control signal to the ASIC 2 through the control bus 9, and performs various data input / output processes and image processing in the ASIC 2. To control. The ASIC 2 executes various processes such as image processing with data addition to the image data in the present embodiment under the control of the CPU 1. The ASIC 2 executes input of image data from the imaging system, key input control on the keyboard 7, display control on the LCD 6, and the like. The ASIC 2 performs various image processing on the image data while performing DMA (Direct Memory Access) control with the RAM 3.

  The RAM 3 stores image data and the like, and data is transferred to and from the ASIC 2 through the data bus 10. The ROM 5 stores a program executed by the CPU 1. A CCD 4 that is an image pickup device disposed behind the photographing optical axis of an optical lens system (not shown) is driven to scan and performs photoelectric conversion output corresponding to a light image formed at regular intervals. This photoelectric conversion output is appropriately adjusted for each primary color component of RGB in the state of an analog value signal, then sampled and held, and converted into digital data.

  The keyboard 7 includes a power SW, a shutter key, a mode switch, a menu key, a selection key, a zoom button, a cross key (cursor key), and the like, and signals associated with these key operations are ASIC 2 (keyboard control described later). Part 21). The LCD 6 displays a through image in real time as an electronic viewfinder in the shooting mode, or displays a shot image taken in accordance with the operation of the shutter key. Although not shown, in addition to the configuration shown in FIG. 1, a memory card that is detachably mounted as a recording medium for recording a captured image and a built-in memory that is fixedly incorporated are provided. .

  FIG. 2 is a block diagram showing a detailed configuration of the ASIC 2 shown in FIG. The ASIC 2 includes an LCD control unit 20, a keyboard control unit 21, a CCD control unit 22, a data I / F (interface) unit 23, an image data transfer unit 24, an image processing unit 25, and the number of pixels. Functions such as a conversion unit 26 and a deblocking filter unit 27 are provided.

  The LCD control unit 20 drives the LCD 6 to control image display. The keyboard control unit 21 captures key input information accompanying a user operation on the keyboard 7. The CCD control unit 22 controls the imaging system (CCD 4), captures image data (Bayer data) acquired by the CCD 4, and outputs it to the data I / F unit 23. The data I / F unit 23 writes image data acquired from the CCD 4 to the RAM 3 under the control of the CCD control unit 22, reads image data written in the RAM 3, or receives an image data processing block from the image data transfer unit 24. Data control such as writing of image data into the RAM 3 after various image processing by the control unit 28 is performed.

  The image data transfer unit 24 controls data transfer between the data I / F unit 23 and the image data processing block 28. Under the control of the CPU 1, the image data transfer unit 24 converts the image data input via the data I / F unit 23 to one of the image data processing blocks 28, that is, the image processing unit 25, the pixel number conversion unit 26, The image data is transferred to any of the blocking filter units 27, and the image data processed in the image data processing block 28 is transferred to the data I / F unit 23. When transferring image data to the image data processing block 28, the image data transfer unit 24 adds ring pixels necessary for image processing to the periphery of the original image for the original image data to be processed. Transfer to the image data processing block 28. The image data transfer unit 24 can selectively change the number of ring pixels to be added to the original image data according to the content of the image processing under the control of the CPU 1.

  The image processing unit 25 executes image processing for converting Bayer data into YUV data. The pixel number conversion unit 26 performs enlargement / reduction processing for converting the number of images by interpolation processing on image data in order to enlarge or reduce the image. The deblocking filter unit 27 executes a filter process for reducing blocking noise during MPEG4 decoding.

  In the image processing in the image data processing block 28, processing is performed on the target pixel to be processed using data of surrounding pixels. Therefore, for example, when the image size of YUV data obtained by image processing is made the same as that of the original image data, a ring pixel is added to the periphery of the original image, and image processing is executed by including the image data of the ring pixel. Correspond.

  In the present embodiment, when the ring pixels necessary for image processing are not added to the image data expanded and stored in the RAM 3, the original image data stored in the RAM 3 is transferred to the image data processing block 28. In addition, the image data transfer unit 24 adds ring pixel data according to the necessity of image processing. In the image data processing block 28, each image processing is executed while recognizing the pixel position of each data based on the transfer order of a plurality of data constituting the image data to be processed. The corresponding data is sequentially transferred to the image data processing block 28 while sequentially generating pixel positions corresponding to the transfer order of the data recognized when the image processing is executed in the processing block 28. The data bus 10 is a 32-bit bus, and the DMA is 16 bursts.

  Next, an image processing operation in the camera device according to the present embodiment will be described. Image data captured by the imaging system (CCD 4) is captured by the CCD control unit 22 and written to the RAM 3 via the data I / F unit 23. FIG. 3 shows image data (Bayer data) developed and stored in the RAM 3. The Bayer data shown in FIG. 3 is data in which one pixel is 8 bits.

  Here, in order to convert the Bayer data into YUV data in the image processing unit 25, as shown in FIG. 4, three pixels of ring pixels are required around the Bayer data (data block processed by the image processing unit 25). The required number of ring pixels is stored in the ROM 5 in advance. That is, here, description will be made assuming that conversion to YUV data is performed using Bayer data of 7 × 7 pixels centered on the pixel of interest.

  On the other hand, when the CPU 1 executes the program stored in the ROM 5, the camera device operates as shown in the flowchart of FIG. That is, the CPU 5 acquires the vertical size of the image data (Bayer data) developed in the RAM 3 (acquisition means), and determines whether or not the acquired vertical size of the Bayer data is a prime number (step S1). .

  In the camera device, when the vertical size of the image data (Bayer data) developed in the RAM 3 is a prime number, but only 640 horizontal × 479 vertical, the image data developed in the RAM 3 in step S1. It may be determined whether or not the vertical size of (Bayer data) is horizontal 640 × vertical 479.

  If this determination is NO and the vertical size of the Bayer data is not a prime number, for example, horizontal 640 × vertical 480, the fixed number of lines in the Bayer data is only applied to the first belt and the final belt. A normal image process is performed in which ring pixels are added and transferred (step S2).

  In this normal image processing, the image data transfer unit 24 sequentially reads the Bayer data stored in the RAM 3 via the data I / F unit 23 and, as shown in FIG. 6, data in a predetermined unit (belt unit). Each image is divided in the vertical direction (for example, divided into 30 in units of 16 pixels), and ring pixels (3 pixels) are added as necessary, while the image processing unit 25 is vertically divided in units of 1 pixel (8 bits). Transfer data. In FIG. 6, 3-pixel data is added to each of the upper, lower, left, and right sides of one belt and transferred to the image processing unit 25.

  The entire Bayer data stored in the RAM 3 is transferred to the image processing unit 25 in units of belts as shown in FIG. For the first belt data, the image data transfer unit 24 adds 3 lines of ring pixels on the belt to the 19th line from the upper side of the Bayer data (16 lines + the lower additional line). Forward. That is, when image data exists, such as between the first belt and the second belt, ring pixel addition is not performed by the image data transfer unit 24, and the original data is output to the image processing unit 25. From the second belt to the 29th belt, the Bayer data of 22 lines (upper additional 3 lines + 16 lines + lower additional 3 lines) is transferred. In the 30th belt (final belt), the image data transfer unit 24 adds 3 lines of ring pixels below the belt to the 19th line from the lower side of the Bayer data (3 lines + 16 lines on the upper side). ). That is, here, the Bayer data is transferred so that the number of lines in each belt is 16 lines in terms of YUV data.

  In the figure, only the upper and lower ring pixels of each belt are described, but the image data transfer unit 24 adds ring pixel data for three lines vertically to the left and right of each belt. It is transferred to the processing unit 25.

  The image processing unit 25 processes the data while recognizing the pixel position of each data for each division unit (belt unit) with respect to the data transferred in a predetermined order from the image data transfer unit 24 to obtain 640 × 16 pixels. YUV data is generated and output to the image data transfer unit 24. The image data transfer unit 24 writes the image data from the image processing unit 25 into the RAM 3 via the data I / F unit 23.

  As described above, when ring pixel data is required for the process of converting Bayer data into YUV data in the image processing unit 25, the image data transfer unit is not added to the Bayer data expanded and stored in the RAM 3. 24, the data is added to the image processing unit 25 immediately before the data is output. Therefore, only the original image data needs to be stored in the RAM 3, and the occupied area of the image data is not increased.

  Here, a detailed configuration and operation of the image data transfer unit 24 for executing processing for adding ring pixels to image data will be described. First, an outline of a functional configuration for adding ring pixels of the image data transfer unit 24 will be described.

(1) Image data storage First, image data (including data at each pixel position) acquired by the CCD 4 is stored in an actual memory (input buffer). Here, for example, it is assumed that the image data acquired by the CCD 4 divided into a plurality of times for each belt is read and temporarily stored. For example, the data length of data stored in the real memory (input buffer) is stored as 32 bits.

(2) Pixel range setting The entire pixel range (Xmin Ymin, Xmax, Ymax) in the image data to be transferred to the image data processing block 28 and ring pixels added according to the contents of the image processing around this pixel range The pixel range (Xmin0, Ymin0, Xmax0, Ymax0) is set. Here, the pixel range (Xmin Ymin, Xmax, Ymax) is image data of one belt.

(3) Pixel position designation Pixel positions (X, Y) to be transferred in the entire pixel range (Xmin0, Ymin0, Xmax0, Ymax0) are designated sequentially. For example, when image data is stored in units of belts in the real memory (input buffer), each of the plurality of belts is processed in order. In the processing for the image data of one belt, the pixel positions are sequentially updated in the order of the Y direction and the X direction.

  In the above description, the case where the image data is stored in the real memory in units of belts is described as an example, but the present invention is not limited to the processing divided in units of belts. Further, the order of specifying pixel positions for the image data is not limited to the order of the Y direction and the X direction.

(4) Pixel position determination It is determined whether or not the pixel position (X, Y) is included in the pixel range (Xmin Ymin, Xmax, Ymax), that is, whether there is data corresponding to the designated pixel position. Here, when the condition (X <Xmin) or (X> Xmax) or (Y <Ymin) or (Y> Ymax) is satisfied, it can be determined that there is no data corresponding to the designated pixel position.

(5) Pixel position conversion The pixel position (X, Y) to be transferred is converted into the pixel position of the data to be transferred within the pixel range (Xmin Ymin, Xmax, Ymax). For example, in the case of Bayer data or the like in which 2 × 2 pixels are a unit block, if (X <Xmin), (the remainder of (Xmin + ((Xmin−1−X) / 2)) is converted to X, and ( When X> Xmax), (Xmax + (the remainder of (X−Xmin + 1) / 2)) is converted to X, and when (Y <Ymin), (Ymin + ((Ymin−1−Y) / 2) (Remainder of (Ymax + ((Y−Ymin + 1) / 2)) is converted to Y if (Y> Ymax).

(6) Pixel position selection Based on the determination result of the pixel position determination, the pixel position (X, Y) designated to be transferred in the pixel position designation or the pixel position (X, Y) converted by the pixel position conversion Select either of these. That is, when it is determined that there is no data corresponding to the pixel position specified by the pixel position specification, the pixel position (X, Y) converted by the pixel position conversion is selected.

(7) Memory address conversion The pixel position (X, Y) selected by the pixel position selection is converted into the memory address and data bit position of the real memory where the image data is stored. Here, the pixel position and the memory address are appropriately converted according to the configuration and storage method of the real memory (input buffer) that temporarily stores the data (pixel information) acquired by the CCD 4. For example, when one pixel is 8 bits and the data length of the real memory is 32 bits, one pixel position is designated by the memory address and the data bit position.
(8) Data transfer control.
Data transfer at a predetermined timing is controlled according to the memory address (and data bit position) obtained by the conversion by the memory address conversion.

  Next, details of the image data transfer unit 24 will be described. FIG. 8 is a block diagram showing a configuration for adding ring pixels of the image data transfer unit 24. As shown in FIG. 8, the image data transfer unit 24 includes an input buffer 240, an address generation unit 241, a vertical line counter 242, a vertical ring pixel counter 243, a horizontal pixel counter 244, a horizontal ring pixel counter 245, and a data selection unit 246. A data selector 247 is provided.

  The input buffer 240 stores data input from the data I / F unit 23. For example, the buffer area for 32 bits × 16 bursts × 32 lines for input data, and 32 bits × 16 bursts × for output data. A buffer area for 16 lines is provided. Note that the buffer area of the input buffer 240 is not limited to this.

  The address generation unit 241 generates an address of the input buffer 240 according to the counter value of the vertical line counter 242 and the counter value of the vertical ring pixel counter 243. Based on the address indicated by the input buffer 240, data of 32 bits (4 pixels) is read out. The vertical line counter 242 counts the number of lines in order to generate an address of data stored in the input buffer 240. The vertical ring pixel counter 243 counts the number of vertical ring pixels (vertical ring pixels) to be added to the data stored in the input buffer 240.

  The horizontal pixel counter 244 counts pixel positions in one line of data stored in the input buffer 240. The horizontal ring pixel counter 245 counts the number of horizontal ring pixels (horizontal ring pixels) added to the data stored in the input buffer 240. The data selection unit 246 selects either the horizontal pixel counter 244 or the horizontal ring pixel counter 245 and outputs a value counted by the selected counter. The data selector 247 selects one pixel (8 bits) of data from the address data (32 bits) indicated by the address generation unit 241 based on the value output from the data selection unit 246, and the image processing unit 25. Output to. Note that the data selector 247 is configured to be able to select data (for example, one pixel) to be transferred to the image processing unit 25 according to the configuration of the input buffer 240 in which the image data is stored and the buffering method.

  The input buffer 240 of the image data transfer unit 24 is provided with a storage capacity for 32 bits × 16 bursts × 32 lines for input data, and since the Bayer data stored in the RAM 3 is 8 bits per pixel, 64 pixels × 32 lines can be captured. Since the size of the image data is horizontal 640 pixels (FIG. 3), the data for one belt can be processed by repeating the fetching into the input buffer 240 ten times.

  A storage capacity of 32 bits × 16 bursts × 16 lines is provided for output data, and the image data of YUV422 obtained by image processing in the image processing unit 25 is 32 bits × 2 pixels, so 32 pixels × 16 lines. Minutes can be captured. Since the image size is 640 pixels horizontally, data for one belt can be processed by repeating the data fetching of the input buffer 240 20 times.

  First, for the first belt, the data read from the RAM 3 (32 bits × 16 bursts × 19 lines) is written to the input buffer 240 as shown in FIG. The numbers described in FIG. 9 represent line numbers and horizontal pixel numbers. 1-1 indicates one pixel on the first line, and 2-5 indicates five pixels on the second line. At the time of writing to the input buffer 240, data is written by leaving 32 lines for every 32 bits. For example, after writing 1-1, 1-2, 1-3, 1-4 data (32 bits), 1-5, 1-6, 1-7, 1 after the capacity of 32 lines Write the data of -8.

  The image data transfer unit 24 counts the pixel position corresponding to the data to be transferred stored in the input buffer 240 by the vertical line counter 242 and the horizontal pixel counter 244, and for the data stored in the input buffer 240. Count the ring pixels to add (pixel range setting, pixel position specification). Data to the image processing unit 25 is read from a buffer address continuous by the number of belt lines counted by the vertical line counter 242, and 8 bits out of the read 32 bits are counted by the horizontal pixel counter 244. Select according to the output.

  Here, as shown in FIG. 4, in order to add three lines of ring pixels to the data stored in the input buffer 240, three pixels are counted by the vertical ring pixel counter 243 and the horizontal pixel counter 244. The initial values of the vertical line counter 242, the vertical ring pixel counter 243, the horizontal pixel counter 244, and the horizontal ring pixel counter 245 are set to 1, respectively. The vertical line counter 242 stops counting until the vertical ring pixel counter 243 finishes counting the ring pixels. The horizontal pixel counter 244 is stopped until the horizontal ring pixel counter 245 finishes counting for the ring pixels.

  When the position of the ring pixel counted by the vertical ring pixel counter 243 is an odd position, the address generation unit 241 generates an address corresponding to a value obtained by adding 1 to the counter value counted by the vertical line counter 242. If it is an even position, an address corresponding to the counter value is generated. In addition, when the position of the ring pixel counted by the horizontal ring pixel counter 245 is an odd position, the data selection unit 246 has a value obtained by adding 1 to the counter value counted by the horizontal pixel counter 244 and an even position. In this case, a counter value is selected.

  The data selector 247 selects 8 bits out of 32 bits stored in the address generated by the address generation unit 241 according to the counter value selected by the data selection unit 246 and outputs the selected 8 bits to the image processing unit 25 (memory). change address). It is assumed that there is no data corresponding to the pixel positions corresponding to the count values of the vertical line counter 242 and the horizontal pixel counter 244 until the count for the ring pixels is completed by the vertical ring pixel counter 243 and the horizontal ring pixel counter 245 (pixels). Position determination), based on the count values counted by the vertical line counter 242 and the horizontal pixel counter 244, the pixel position for outputting the data stored in the input buffer 240 is determined by the address generation unit 241 and the data selection unit 246. Find (pixel position selection, pixel position conversion). Therefore, at the first belt, as indicated by arrows in FIG. 10, the data stored in the input buffer 240 is 2-2, 1-2, 2-2, 1-2, 2-2, 3-2. Are output to the image processing unit 25 in the order of 4-2.

  Similarly, the ring pixel counter is stopped even at the end of the belt, and when the vertical ring pixel counter 243 is in an odd position, a buffer address is generated by the line counter value +1 by the vertical line counter 242 and in the even position by the line counter value. Data is output to the image processing unit 25 in the order shown in FIG. 10 by selecting 8 bits out of 32 bits based on the horizontal pixel counter value -1 when the counter 244 is an odd position and the horizontal pixel counter value when the counter 244 is an even position.

  For the belt from the second belt to the belt immediately before the final belt, the data of the belts located above and below (3 lines) are used, and therefore ring pixels are added only in the horizontal direction (left and right) in the same manner as described above. FIG. 11 shows data for the second belt. As shown in FIG. 11, 14 to 16 lines of data are added as ring pixels to the upper ring pixel 3 lines, and 33 to 35 lines of data are added to the lower ring pixel 3 lines.

  The ring pixel addition at the belt start position of the final belt is performed by generating a buffer address based on the line counter value -1 by the vertical line counter 242 when the vertical ring pixel counter 243 is an odd position, and the line counter value at an even position. When the counter 245 indicates an odd position, the horizontal pixel counter value +1 is selected by the horizontal pixel counter 244, and at the even position, 8 bits out of 32 bits are selected and output. At the belt end position, a buffer address is generated by the line counter value -1 by the vertical line counter 242 when the vertical ring pixel counter 243 is an odd position, and by the line counter value at an even position, and the horizontal ring pixel counter 245 is an odd position. , The horizontal pixel counter value -1 by the horizontal pixel counter 244 is selected, and 8 bits out of 32 bits are selected and output at the even position by the horizontal pixel counter value.

  On the other hand, in the flowchart of FIG. 5, when the determination in step S1 is YES and the Bayer data is horizontal 640 × vertical 479 and this Bayer data of horizontal 640 × vertical 479 is converted into YUV data, step S1 To step S3. In this case, since the vertical size is “479” and a prime number, one belt is 1 effective pixel + ring pixel. Therefore, as shown in FIG. 12, ring pixel addition must be performed for other than the first belt and the final belt. That is, it is necessary to change the number of ring pixels added to the Bayer data between the belts.

  Therefore, it is first determined whether or not the Bayer data transferred to the image data processing block 28 is the first belt (step S3). In the case of the first belt, since it is necessary to add ring pixels for three lines on the upper side, the number of lines to be added is set to “3” and the image data transfer unit 24 sets the image data processing block 28. (Step S4). In the case of the second belt (step S5; YES), since it is necessary to add ring pixels for two lines on the upper side, the line to be added is set to “2” (step S6). If it is the third belt (step S7; YES), it is necessary to add one line of ring pixels to the upper side, so the line to be added is set to “1” (step S8).

  If all the determinations in steps S3, S5, and S7 are NO and none of the first to third belts, it is determined whether or not the final second belt (step S9). It is determined whether it is the belt (step S11) and whether it is the final belt (step S13). As a result, if all of the determinations in steps S9, S11, and S13 are NO and none of the last -2nd belt, the last -1st belt, and the last belt is reached, the process proceeds from step S13 to step S14. The line to be added is set to “0”, and transfer is performed without adding ring pixels.

  Therefore, the transfer from the image data transfer unit 24 to the image data processing block 28 is performed without adding ring pixels from the 4th belt to the last -2nd belt.

  Further, when transferring the last-second belt, it is necessary to add one ring pixel to the lower side. At this time, the determination in step S9 is YES. Accordingly, the process proceeds from step S9 to step S10, and the line to be added is set to “1” and transferred. If it is the final first belt (step S11; YES), it is necessary to add two lines of ring pixels to the lower side, so the line to be added is set to “2” and transferred. However, if it is the last belt (step S13; YES), it is necessary to add ring pixels for three lines on the lower side, so the line to be added is set to “3”. (Step S15).

  Therefore, when the number of lines of Bayer data is the 480 line having a divisor, it is a matter of course, and even if it is a 479 line that is a prime number having no divisor, ring pixels can be added without any trouble and efficiency. Transfer can be performed automatically.

  Of course, the processing after the transfer from the image data transfer unit 24 to the image data processing block 28 is the same as the processing described in the normal image processing (step S2) described above.

  A register for setting whether or not ring pixel addition is automatically performed may be provided. In this case, if not automatically performed, ring pixel addition in the upper and left directions is performed using the values set in the registers. If it is set to perform automatically, the number of ring pixels necessary for each process is determined (for example, 5 pixels for the enlargement process), and a value obtained by rounding a half of the ring pixels in the upper and left directions And so on. However, when the original image has a size that can include ring pixels, ring pixels are not added. For example, when 640 × 480 is required as an input image and the ring pixel is 5 pixels, ring pixel addition is not performed if the original image has a size of 645 × 485 or more.

  In the above-described embodiment, the case has been described in which it is determined whether or not the total number of lines of Bayer data is a prime number. Of the divisors with respect to the total number of lines of Bayer data, YUV data conversion is possible at a time. The maximum number of lines (the maximum number of lines that can be set as the number of lines for each belt) is equal to or less than the value converted into the number of lines in the Bayer data, and the maximum divisor (hereinafter referred to as “optimal transfer”). The number of lines) and the number of ring pixels stored in advance to be added to the Bayer data. If the number of ring pixels is equal to or greater than the optimum number of transfer lines, the first belt and the final belt For this, select a process that adds a ring pixel with a fixed number of lines to the Bayer data, and the number of ring pixels is less than the optimal number of transfer lines. If the may be configured to select the processing such the number rings pixels to be added to the Bayer data between each belt transfers by varying.

  In other words, in terms of the optimum number of transfer lines, when transferring Bayer data, the number of lines that can minimize the number of belts (the number of transfers can be minimized) among the conditions that can equalize the number of transfer lines between the belts. Line number).

  That is, based on the total number of lines (or the number of pixels) of Bayer data, the number of lines of each belt that is ideal for transfer efficiency (the number of pixels as a transfer unit) is set as the optimal number of transfer lines, and the number of ring pixels is If the number of transfer lines is greater than or equal to the optimum transfer line number, a fixed line number is added to the Bayer data only for the first and last belts, and the number of ring pixels is less than the optimum transfer line number. Since ring pixels are required in addition to the first belt and the final belt, the number of ring pixels added between the belts may be varied to add the required number of ring pixels. Thereby, it is possible to improve transfer efficiency and to appropriately add a ring pixel to the Bayer data. Note that the number of ring pixels added to each belt may be stored in advance in correspondence with the relationship between the optimum number of transfer lines and the ring pixels, for example. Accordingly, whether or not to add a ring pixel to each belt can be appropriately determined for each belt when it is determined that a ring pixel is to be added.

  In the above description, a camera device such as a digital still camera or a digital video camera is targeted. However, a mobile phone with a camera function or a portable information processing device (PDA (personal digital assistant) or PC (Personal Computer)). Etc.).

It is a block diagram which shows the main structures relevant to the image processing of the camera apparatus in embodiment of this invention. It is a block diagram which shows the detailed structure of ASIC shown in FIG. It is a figure which shows an example of the image data (Bayer data) expand | deployed and memorize | stored in RAM in this Embodiment. The figure which shows the ring pixel added to the circumference | surroundings of Bayer data in the embodiment. It is a flowchart which shows the operation | movement of the embodiment. It is explanatory drawing which shows the data transfer to the image process part in the embodiment. It is explanatory drawing which shows the data transfer per belt to the image process part in the embodiment. It is a block diagram which shows the structure for adding the ring pixel of the image data transfer part in the embodiment. It is a figure which shows an example of the data memorize | stored in the input buffer same embodiment in the embodiment. It is a figure which shows the ring pixel added to the 1st belt in the embodiment. It is a figure which shows the ring pixel added to the 2nd belt in the embodiment. It is a pixel block diagram of the 1st-3rd belt and the last belt -1-the last belt in case the number of lines is 479 in the embodiment.

Explanation of symbols

1 CPU
2 ASIC
3 RAM
4 CCD
5 ROM
6 LCD
7 Keyboard 8 Power supply unit 9 Control bus 10 Data bus 20 LCD control unit 21 Keyboard control unit 22 CCD control unit 23 Data I / F unit 24 Image data transfer unit 25 Image processing unit 26 Pixel number conversion unit 27 Deblocking filter unit 240 Input Buffer 241 Address generation unit 242 Vertical line counter 243 Vertical ring pixel counter 244 Horizontal pixel counter 245 Horizontal ring pixel counter 246 Data selection unit 247 Data selector

Claims (10)

A transfer circuit for adding a ring pixel to the Bayer data stored in the storage means and transferring the data,
Storage means in which the number of ring pixels to be added to the Bayer data stored in the storage means is stored in advance;
Obtaining means for obtaining the number of pixels of Bayer data stored in the storage means;
Setting means for setting the number of transfer pixels as a transfer unit based on the number of pixels of Bayer data acquired by the acquisition means;
Determining means for determining whether or not to add the ring pixel at each transfer with the number of transfer pixels set by the setting means;
A ring pixel to be added at the time of transfer based on the number of ring pixels stored in the storage means and the number of transfer pixels set by the setting means when it is determined by the determination means to add a ring pixel Variable setting means for variably setting the number;
A transfer circuit comprising: 2. The transfer circuit according to claim 1, wherein the setting unit sets a divisor with respect to the total number of lines of Bayer data acquired by the acquiring unit as the number of transfer lines serving as the transfer unit. The setting means is a transfer line that is equal to or less than the maximum number of lines that can be transferred at one time and is the transfer unit that is the transfer unit among the divisors of the total number of lines of Bayer data acquired by the acquisition means. The transfer circuit according to claim 2, wherein the transfer circuit is set as a number. The variable setting means compares the number of transfer lines set by the setting means with the number of ring pixels stored in the storage means, and based on the comparison result, the number of ring pixels added at the time of transfer is variable. The transfer circuit according to claim 3, wherein the transfer circuit is set. When the total number of lines of Bayer data acquired by the acquisition unit is a prime number, the setting unit sets the number of transfer lines as the transfer unit to one line, and the total number of lines of Bayer data is not a prime number. 3. The transfer circuit according to claim 2, wherein a divisor for the total number of lines of Bayer data is set as the number of transfer lines serving as the transfer unit. When the number of transfer lines serving as the transfer unit is set to a divisor with respect to the total number of lines of Bayer data by the setting means, the determining means determines the first transfer and the last transfer of the set transfer unit. When it is determined that a ring pixel is added only when the number of transfer lines serving as the transfer unit is set to one line by the setting unit, a plurality of transfers following the first transfer by the set transfer unit and 6. The transfer circuit according to claim 5, wherein it is determined that a ring pixel is added in a plurality of transfers before the last transfer. The variable setting means, when it is judged by the judging means that a ring pixel is added at the time of a plurality of transfers following the first transfer and a plurality of transfers before the last transfer, 7. The transfer circuit according to claim 6, wherein the number of ring pixels added at the time of transfer is maximized, and the number of ring pixels before and after the first transfer or the last transfer is less than the maximum number of ring pixels. . An imaging apparatus comprising the transfer circuit according to claim 1,
  Imaging means for capturing a subject and acquiring Bayer data;
Storage control means for storing Bayer data acquired by the imaging means in the storage means;
Image data processing means for performing predetermined image data processing on the Bayer data transferred with the ring pixels added from the transfer circuit;
An image pickup apparatus further comprising: A computer included in an imaging apparatus including the transfer circuit according to claim 1,
Imaging means for capturing a subject and acquiring Bayer data;
Storage control means for storing Bayer data acquired by the imaging means in the storage means;
Image data processing means for performing predetermined image data processing on the Bayer data transferred with the ring pixels added from the transfer circuit;
A control program characterized by functioning as a function. A transfer control method for controlling transfer of a transfer circuit that adds a ring pixel to Bayer data stored in a storage means and transfers the data,
An acquisition step of acquiring the number of pixels of Bayer data stored in the storage means;
A setting step for setting the number of transfer pixels as a transfer unit based on the number of pixels of the Bayer data acquired by the acquisition step;
A determination step of determining whether or not to add the ring pixel at each transfer with the transfer pixel number set in the setting step;
The number of ring pixels stored in the storage means in which the number of ring pixels to be added to the Bayer data stored in the storage means when it is determined in the determination step to add ring pixels, and the setting Based on the transfer pixel number set in the step, a variable setting step for variably setting the number of ring pixels added at the time of the transfer,
A transfer control method comprising:

Images