JP4904620B2 - Oscillator with controllable frequency and duty ratio - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an oscillator configured by connecting inverting or non-inverting gates in a plurality of stages, and more particularly to an oscillator capable of freely controlling a frequency and a duty ratio.
[0002]
[Prior art]
A ring oscillator configured by connecting a plurality of logic gates in a ring form is configured, for example, by connecting an odd number of inverters (inverted gates) and oscillates at a period depending on the propagation time of the ring-shaped logic gate.
[0003]
FIG. 1 is a circuit diagram of a conventional frequency-controllable oscillator. 1 includes a ring oscillator OSC # 1 having n stages of gates G1 to Gn, a ring oscillator OSC # 2 having 2n stages of gates G1 to G2n, 3n stages, 4n stages,. . . A ring oscillator OSC # K having Kn stages of gates is provided, and an output of each ring oscillator is selected by a selection circuit SEL according to a selection signal C and output to an output terminal OUT. That is, based on the oscillation frequency f0 of the ring oscillator OSC # 1, the ring oscillators OSC # 2 to OSC # K generate oscillation signals of frequencies f0 to f0 / K (K is an integer), respectively, and these oscillation signals are selected. And output. Each ring oscillator has an odd number of inversion gates (inverters) and an arbitrary number of non-inversion gates, and the total number of stages is n, 2n, 3n. . . . It is Kn.
[0004]
This oscillator can control the oscillation frequency output by the selection signal C. However, the duty ratio of the oscillation signal cannot be controlled at each frequency. Further, the oscillator shown in FIG. 1 needs to be provided with a plurality of ring oscillators, which increases the circuit scale and the number of elements, and is disadvantageous in terms of semiconductor chip area, cost, and power consumption.
[0005]
FIG. 2 is a circuit diagram of another conventional oscillator. The oscillator shown in FIG. 2 includes a ring oscillation circuit OSC to which gates G1 to G8 are connected, three exclusive ORs XNOR1, 2, 3 and a selection circuit SEL. The output N1 of the gate G8 is an oscillation output of the basic oscillation frequency f0, and the output N3 of the exclusive OR gate XNOR1 having the inputs N1 and N2 of the gates G8 and G6 having a phase difference of 90 ° as input is shown in FIG. As shown in (B), the oscillation output has a frequency 2f0 multiplied by two. The output N7 of the exclusive OR gate XNOR3 having the inputs N4 and N5 of the outputs N4 and N5 of the gates G5 and G7 having a phase difference of 90 ° and the signal N3 as shown in FIG. As shown, the oscillation output has a frequency 4f0 multiplied by 4.
[0006]
Further, although not shown, the exclusive OR of the output N1 of the gate G8 and the output N4 of the gate G5 has a frequency of 2f0 and an oscillation output whose duty ratio is increased by 25% from the signal N3.
[0007]
[Problems to be solved by the invention]
The oscillator shown in FIG. 2 can reduce the circuit scale as compared with the oscillator shown in FIG. 1, but the frequency that can be generated is a power of 2 of the fundamental frequency f0 (2 ⁿ ) And a ring oscillator consisting of at least eight stages of gates is required to extract from the fundamental frequency to the quadruple frequency, and there is a limit to increase the oscillation frequency by reducing the number of stages. Further, the oscillator of FIG. 2 needs to increase the number of stages in order to increase the resolution of duty ratio control of the output waveform.
[0008]
Accordingly, an object of the present invention is to provide an oscillator that has a small circuit scale, can be controlled to a high oscillation frequency, and can also control a duty ratio.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to one aspect of the present invention, in an oscillator that generates a clock signal having a predetermined frequency, a plurality of gates including at least one inversion gate are connected in a cascade and circularly connected. And an oscillation circuit in which an exclusive OR gate having an oscillation control input is appropriately inserted. Then, by inputting the oscillation control input to the exclusive OR gate at a desired position at a desired timing, the exclusive OR gate is converted into an inverting gate or a non-inverting gate, and a propagation signal wave is generated in the oscillation circuit. Generate. The oscillation frequency is controlled by the number of generated propagation signal waves, and the duty ratio is controlled by the position of the exclusive OR gate to be converted.
[0010]
A second aspect of the present invention relates to an oscillator that generates a clock signal having a predetermined frequency.
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit for generating a plurality of oscillation control signals in a predetermined combination according to the oscillation selection signal;
In response to a change in any one of the gate outputs, the plurality of oscillation control signals are fetched, and the plurality of oscillation control signals are delayed in accordance with the oscillation selection signal, respectively, to the oscillation control input of the exclusive OR gate. A plurality of delay circuits to supply,
After the delay time of the delay circuit, according to the plurality of oscillation control signals, any one or more of the plurality of exclusive OR gates are converted into inversion or non-inversion gates to perform an oscillation operation. Features.
[0011]
In the above second aspect, in the oscillator of a more preferred embodiment,
When the oscillation circuit is oscillating at the first frequency, the exclusive OR gate is converted into the inverting or non-inverting gate, and the oscillation state is shifted to the oscillating state at the second frequency higher than the first frequency. It is characterized by that.
[0012]
In the above embodiment, the oscillator of the more preferred embodiment is
When shifting from the first frequency to the second frequency, according to the plurality of oscillation control signals, the position of the exclusive OR gate to be converted into the inversion or non-inversion gate is selected, thereby selecting the selected duty A clock signal having a ratio is generated.
[0013]
A third aspect of the present invention for achieving the above object is an oscillator that generates a clock signal having a predetermined frequency.
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit that generates a plurality of oscillation control signals in a predetermined combination in accordance with the oscillation selection signal and supplies the oscillation control signals to the oscillation control inputs of the plurality of exclusive OR gates,
When the oscillation circuit is in a non-oscillation state, any one or more of the exclusive OR gates are inverted or non-inverted by the plurality of oscillation control signals to start an oscillation operation. Features.
[0014]
According to the above invention, an exclusive OR gate having a high frequency response characteristic, at least one inversion gate, and a plurality of inversion or non-inversion gates are connected in cascade to form an oscillation circuit. An oscillation control signal having a desired frequency or duty ratio can be realized by supplying an oscillation control signal to the inverting or non-inverting gate.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, this embodiment does not limit the technical scope of the present invention.
[0016]
FIG. 3 is a circuit diagram of a basic configuration of the oscillator in the present embodiment. In the example of FIG. 3, seven stages of inverters (inversion gates) I <b> 1 to I <b> 7 and an exclusive logic NOR gate X <b> 1 are connected in a ring shape to constitute the oscillation circuit 100. The output of the exclusive logic NOR gate X1 becomes the output terminal OUT, the oscillation control signal C is supplied to one input of the exclusive logic NOR gate X1, and the output node n1 of the inverter I7 is supplied to the other input. Is done. The oscillation control signal C is controlled to “1 (H level)” or “0 (L level)” at a timing delayed by a predetermined delay time from the output OUT timing. The timing is generated by the oscillation control signal generator 10. The oscillation control signal generator 10 is supplied with the oscillation selection C0 and the oscillation output OUT, and the oscillation control signal C is generated at a timing according to the timing of the oscillation output OUT.
[0017]
The exclusive logic NOR gate X1 has the function of an inverter that inverts the logic of the node n1 when the oscillation control signal C is “0 (L level)”, and the oscillation control signal C is “1 (H level)”. In some cases, it has a function of a buffer gate (non-inverting gate) that propagates the logic of the node n1 as it is. If an exclusive logic OR gate is used, the above function is only reversed, and therefore the logic value of the oscillation control signal C may be reversed.
[0018]
FIG. 4 is an example of a transistor circuit constituting the inverters I1 to I7. This inverter has a sufficiently high gain frequency characteristic, and can invert the output / OUT with a high gain against a change in the input Vin. The inverter circuit is an SCFL type logic circuit, and the sources of field effect transistors Q1 and Q2 having high frequency characteristics such as HEMT are commonly connected, and the common source is connected to the ground Vss through a current source. The drains of the transistors Q1 and Q2 are connected to the power source Vcc via the resistors R1 and R2, and the drain terminals are connected to the outputs / OUT and OUT. The ENOR gate X1 is similarly configured by the SCFL type logic circuit of FIG.
[0019]
By using the inverters I1 to I7 and the ENOR gate X1 configured using transistor elements having such high-frequency characteristics, the oscillator of FIG. 3 has an oscillation operation at the fundamental frequency f0 and its double frequency of 2 · f0. The oscillation operation can be freely controlled.
[0020]
FIG. 5 is an operation timing chart of the oscillator of FIG. In the initial state before time T1, since the oscillation control signal C is at the L level, the ENOR gate X1 functions as an inverter, and the ring oscillator is connected to an even number of inverters and does not oscillate.
[0021]
Therefore, when the oscillation control signal C changes from L level to H level at time T1, the ENOR gate X changes from an inverter to a buffer gate, and the output OUT of the ENOR gate X1 is changed to L level corresponding to the internal node n1 = L. Lower. As the ENOR gate becomes a buffer gate, it becomes an odd-numbered inverter circuit and starts oscillating.
[0022]
This falling waveform propagates one after another through the inverters I1 to I7, the internal node n1 rises to H level, and the output OUT rises to H level via the gate X1 functioning as a buffer gate. The ring oscillator of FIG. 3 is a circuit composed of seven stages of inverters. The time T0 from when the output OUT falls to the next rise is the time required for the signal wave to propagate through the ring oscillator. Accordingly, the period from the time T1 to the time T2 is a state in which the ring oscillator is transmitting at the reference frequency f0, and the period is the time required for the signal wave to propagate through the ring oscillator twice.
[0023]
That is, f0 = 1/2 (τX1 + 7τI) (τX1 is an ENOR gate delay time, and τI is an inverter gate delay time).
[0024]
At time T2, when the oscillation control signal C is returned from the H level to the L level while the internal node n1 is at the L level, the ENOR gate X1 becomes an inverter. Broken line As shown in (5), the internal node n1 = L is inverted and the output OUT is raised to the H level. This rising waveform is added to the propagation signal wave indicated by a solid line in FIG. 5, and the ring oscillator oscillates at 2 · f0 which is doubled. In addition to the propagating signal wave circulated in the period T1-T2 (indicated by the solid line), in the period T2 and later, Broken line The propagating signal wave shown by circulates.
[0025]
FIG. 6 is a diagram for explaining the operating principle of the oscillator of FIG. 6 (1) and 6 (2) show a circulation path showing a ring-shaped propagation path of the oscillator. Assume that the highest position of the circular circuit is the phase 0 of the ENOR gate output, and the lowest position is the same phase π (180 °). Since the oscillation control signal C = 1 at time T1, the propagation signal wave circulates at the frequency f0. Then, by setting the oscillation control signal to C = 0 at the timing of the phase π of the propagation signal wave due to C = 1, the propagation signal wave due to C = 0 is newly generated and circulated, and the frequency is doubled. 2 · f0.
[0026]
Therefore, the timing T2 in FIG. 5 is preferably the timing at which the propagation signal wave becomes phase π. This timing is good when the falling signal wave of the output OUT passes through the inverter I5. For this purpose, the oscillation control signal generator 10 oscillates after a delay time corresponding to four stages of gates from the falling of the output OUT. It is sufficient if the control signal C can be lowered to the L level.
[0027]
When each gate of the ring oscillator of FIG. 3 has an ideal high gain / frequency characteristic, the internal node n1 is switched to L level when switching the oscillation control signal C from H level to L level or from L level to H level. By performing during the period, the oscillation frequency is further multiplied by 3 and 4. . . It can be multiplied by n.
[0028]
FIG. 7 is a circuit diagram of the oscillator according to the first embodiment. 7 is the same as the ring oscillator of FIG. ^n-1 It has a configuration in which stages are connected. The first stage segment is composed of segment A1 of ENOR gate X1 and segment B1 composed of gates I1 to Ik such as an inverter (inverted gate), buffer (non-inverted gate), and logic gate, and the next stage segment is ENOR gate X2. Segment A2 and segment B2 consisting of gates Ik + 1 to I2k, and the last two ^n-1 The second segment is the ENOR gate X (2 ^n-2 -1) k + 1 segment A2 ^n-1 And gate I (2 ^n-2 -1) k + 1 to I2 ^n-1 Segment B2 consisting of k ^n-1 Consists of. The oscillation circuit 200 is configured by connecting the plurality of segments.
[0029]
This oscillator is provided with an oscillation frequency selection circuit SEL. The oscillation frequency selection circuit SEL decodes an input oscillation frequency selection signal C to generate oscillation control signals X1 to X2. ^n-1 These oscillation control signals are supplied to the ENOR gate of each stage via the delay circuit DELAY. In response to the switch signal SW = H, the AND gate AND1 becomes conductive, and the ring oscillation can be started. And oscillation control signals X1 to X2 ^n-1 Is supplied to the ENOR gate of each stage at a desired timing, and the oscillation circuit generates a circulation propagation signal according to the principle described in FIG. ^n-1 Oscillates at any frequency up to the frequency of multiplication. Furthermore, the oscillator receives the oscillation control signals X1 to X2 that are input. ^n-1 By selecting, an oscillation signal with a desired duty ratio can be generated.
[0030]
FIG. 8 is a simplified circuit diagram of the oscillator according to the first embodiment shown in FIG. The oscillator shown in FIG. 8 is an example of an oscillation circuit 200 having a four-stage configuration as a whole, where the segment A is composed of the ENOR gate X and the segment B is composed of one inverter. The last segment B4 is composed of a NAND gate and receives an oscillation switch signal SW.
[0031]
The 2-bit oscillation frequency selection signal C is supplied to the oscillation frequency selection circuit SEL, and the decoded oscillation control signals X1 to X4 are supplied to the delay circuit DELAY. Further, the delay circuit latches the oscillation control signals X1 to X4 at the rising timing of the output OUT, and supplies the oscillation control signal to the ENOR gate X of each segment A after a delay time corresponding to the oscillation frequency selection signal C. . Another gate output change can be used for the latch timing.
[0032]
FIG. 9 is a circuit diagram of the oscillation frequency selection circuit SEL. In this example, 2-bit oscillation frequency selection signals C1 and C2 are converted into inverted and non-inverted signals by buffer inverters 12 and 13, and oscillation frequency selection is performed by AND / NAND gates 14, 15, 16, 17, and 18. Oscillation control signals X1 to X4 according to a predetermined logic combination of signals C1 and C2 are output. The gates 16, 17 and 18 output the other input in response to the rising edge of the oscillation switch signal SW.
[0033]
FIG. 10 is a circuit diagram of the delay circuit DELAY. The delay circuit includes a latch circuit D1 that latches the oscillation control signals X1 to X4 at the rising edge of the output OUT, four-stage buffer gates 19 to 22, and a circuit SEL2 that selects the output of each buffer by the oscillation frequency selection signal C. Have Whereas the ring oscillator of FIG. 8 has a total of 8 gates, this delay circuit DELAY is provided with half of the four stages of buffer gates.
[0034]
Therefore, the operation of the delay circuit DELAY is performed when the oscillation control signal is output immediately regardless of the timing of the output OUT and when the oscillation control signal is latched at the timing of the output OUT and then output after a delay of one gate stage. In some cases, the signal is output after a delay of two stages of gates, and the signal is output after three stages of gates.
[0035]
FIG. 11 is a diagram showing a logical value table of the frequency selection circuit in the frequency selection operation in the oscillator of FIG. FIG. 12 is a diagram for explaining the frequency selection operation of the oscillator. In the initial state of FIG. 12 (1), since all outputs of the delay circuit DELAY are at L level, the ENOR gates X1 to X4 all function as inverters. Therefore, the oscillator of FIG. 8 is composed of eight inverters and is in a non-oscillating state.
[0036]
Next, when the oscillation frequency selection signals C1 and C2 are set to “0, 0” and the oscillation switch signal SW is set to the H level, the outputs X1 to X4 of the oscillation frequency selection circuit SEL are “ 1000 ". Accordingly, one input of the ENOR gate X1 becomes H level “logic 1”, the ENOR gate X1 becomes a buffer gate, and oscillation is started at the reference frequency f0 as described with reference to FIG. The period at this time is the time required for the propagation waveform to propagate twice through the ring oscillator, and its reciprocal is the reference frequency f0. This oscillation state is as shown in FIG.
[0037]
In FIG. 12, “×” represents a newly generated propagation signal wave, and “◯” represents a propagation signal wave that has already occurred. The same applies to other drawings to be described later.
[0038]
Next, when the oscillation frequency selection signals C1 and C2 are set to “1, 0”, the oscillation frequency selection circuit SEL decodes them and outputs the outputs X1 to X4 of the selection circuit SEL as “ 0000 ". That is, only the output X1 changes from the H level to the L level. This change of the output X1 to the L level is latched in response to the rising edge of the output OUT in the delay circuit DELAY1, and is input to the ENOR gate X1 with a delay of the propagation delay time of the four-stage gates 19-22.
[0039]
In other words, the output X1 of the selection circuit SEL falls from the H level to the L level at the timing when the propagation signal wave that raised the output OUT propagates as the rising waveform of the output of the inverter I2. This timing is the timing when the first propagated signal wave is in phase π. In other words, when there are 2M stages of oscillators, the number of gates of the delay circuit DELAY1 needs to be M stages in order to take the timing of phase π. As a result, ENOR gate X1 becomes an inverter, and its output falls from H level to L level. This operation is the same as the operation at time T2 in FIG. As a result, as shown in FIG. 12 (3), a new propagation signal wave for oscillation is generated by the output X1 = 0 of the selection circuit, and the oscillation frequency is doubled to 2f0.
[0040]
Next, when the oscillation frequency selection signals C1 and C2 are set to “0, 1”, the oscillation frequency selection circuit SEL decodes them and outputs the outputs X1 to X4 of the selection circuit SEL as “ 1010 ". That is, the outputs X1 and X3 change from the L level to the H level. The change of the outputs X1 and X3 to the H level is latched in response to the rising edge of the output OUT in the delay circuits DELAY1 and 3, and delayed by the propagation delay time of the two-stage gates 19 and 20, ENOR gates X1 and X3. Respectively.
[0041]
This input timing is the timing after one of the two propagation signal waves shown in FIG. 12 (3) has passed through the output OUT and two gates have elapsed, and is shown in FIG. 12 (4). As can be seen, the two propagation signal waves have a 90 ° phase difference timing.
[0042]
At this timing, ENOR gates X1 and X3 are both converted to inverters, and two new propagation signal waves are generated accordingly. As a result, in addition to the previous two propagation signal waves, a total of four propagation signal waves propagate through the ring oscillator circuit at the same time, and the frequency becomes 4 · f0 multiplied by 4.
[0043]
Further, when the oscillation frequency selection signals C1 and C2 are set to “1, 1”, the oscillation frequency selection circuit SEL decodes them and outputs the outputs X1 to X4 of the selection circuit SEL to “0101” as shown in FIG. " That is, the outputs X1 and X3 change from H level to L level (logic “1” to “0”), and the outputs X2 and X4 change from L level to H level (logic “0” to “1”). The changes of the outputs X1 and X3 to the L level and the outputs X2 and X4 to the H level are latched in response to the rising edge of the output OUT in the delay circuits DELAY1 to DELAY1-4. The signals are input to ENOR gates X1 to X4 with a delay of the propagation delay time.
[0044]
In response to these inputs, the ENOR gates X1 and X3 are switched to buffers and the ENOR gates X2 and X4 are switched to inverters, and the respective outputs are inverted. As shown in FIG. Newly occurs. As a result, the oscillation frequency is multiplied by 8 to 8 · f0.
[0045]
As shown in the table of FIG. 11, by changing the frequency selection signals C1 and C2 in order, the oscillation frequencies are f0, 2f0, 4f0, 8f0 and 2 ⁿ It is possible to shift higher by multiples. In any oscillation state at any oscillation frequency, the oscillation operation of the oscillator can be stopped and the oscillation operation can be newly controlled by dropping the oscillation switch signal SW to the L level.
[0046]
FIG. 13 is a diagram showing a logical value table and oscillation waveforms of the selection circuit SEL in the duty ratio control operation in the oscillator of FIG. In this operation, the oscillation clock signal can be controlled to an arbitrary duty ratio when the oscillation state at the reference frequency f0 is changed to the oscillation at the double frequency 2f0. FIG. 14 is a diagram for explaining the duty ratio control operation. As a premise, the delay circuits DELAY1 to DELAY1 to 4 have the number of delay gates shown in the logic value table of FIG. 13 unlike FIG. 10, and when the selection signals C1 and C2 are “1, 1”, the number of delay stages is set to 0. ing. Further, unlike FIG. 9, the selection circuit SEL is also decoded as shown in the logic value table of FIG.
[0047]
As described with reference to FIG. 11, in the initial state, the ring oscillator is composed of eight stages of inverters and does not oscillate. Therefore, when the selection signals C1 and C2 are set to “0, 0” and the oscillation switch signal SW is set to the H level, the selector output signals X1 to X4 are set to “1000”, and each delay circuit DELAY1 to 4 has no delay. Supply the output to the ENOR gate. Thereby, the oscillation at the reference frequency f0 is started.
[0048]
In this state, when the selection signals C1 and C2 are set to “1, 0”, the output signals X1 to X4 of the selection circuit become “1100”, and after the delay time of four stages of gates from the rise of the output OUT, these output signals Is supplied to the ENOR gate. Thereby, as shown in FIG. 14 (2), the ENOR gate X ₂ Is switched to a buffer gate, and its output is lowered from H level to L level to generate a new propagation signal wave. As a result, as shown in FIG. 13B, an oscillation operation with a frequency of 2 · f0 and a duty ratio of 1/4 is performed.
[0049]
Next, after switching from the initial state to the oscillation operation state at the reference frequency f0, when the selection signals C1 and C2 are set to “0, 1”, the output signals X1 to X4 of the selection circuit become “1001”. , They are supplied to the ENOR gate after a delay time of two stages from the rising edge of the output OUT. As a result, as shown in FIG. _Four Is switched to a buffer gate, and its output is lowered from H level to L level to generate a new propagation signal wave. As a result, as shown in FIG. 13B, an oscillation operation with a frequency of 2 · f0 and a duty ratio of 2/4 is performed.
[0050]
Further, when the selection signals C1 and C2 are set to “1, 1” from the state of the reference frequency f0, the output signals X1 to X4 of the selection circuit become “1100”, and they are ENOR gates at the rising timing of the output OUT. To be supplied. Thereby, as shown in FIG. 14 (4), the ENOR gate X ₂ Is switched to a buffer gate, and its output is raised from L level to H level to generate a new propagation signal wave. As a result, as shown in FIG. 13B, an oscillation operation with a frequency of 2 · f0 and a duty ratio of 3/4 is performed.
[0051]
As will be apparent to those skilled in the art, when switching from the reference frequency f0 to the higher frequency of multiplication 2f0, the position of the propagation signal wave to be newly inserted among the four ENOR gates is controlled by the selection circuit SEL, thereby 1/4. The duty ratio can be controlled in units. Of course, if the number of oscillator stages is increased, the resolution of the controllable duty ratio can be increased. In addition, since the duty ratio can be controlled by selecting the output of the selection circuit according to the delay amount of the delay circuit, the delay amount and the selector output signal may be in other combinations.
[0052]
FIG. 15 is a circuit diagram of an oscillator according to the second embodiment. This oscillator can generate an oscillation output from the fundamental frequency f0 to its N multiplied frequency. In the oscillator 300 of FIG. 15, the circuits of the respective stages including the segments A and B shown in the oscillator of FIG. 7 are connected in an M-stage ring shape. In FIG. 15, for simplification, ENOR gate X is provided as segment A, and inverter I is provided as segment B, and a total of k gates are provided at each stage. A selection circuit SEL that generates output signals X1 to XM according to the oscillation frequency selection signal C is provided, and the output signals X1 to XM are directly input to the ENOR gates of the respective stages. A NAND gate NAND to which the oscillation switch signal SW is input instead of the inverter is provided in the Mth stage circuit.
[0053]
FIG. 16 is a simplified circuit diagram of the oscillator of FIG. In the example of FIG. 16, each stage of the oscillation circuit 300 is composed of one ENOR gate X and one inverter I, and is connected in 12 stages as a whole. In the final stage (12th stage), a NAND gate to which the oscillation switch signal SW is input is provided instead of the inverter.
[0054]
FIG. 17 is a circuit diagram of the selection circuit SEL of FIG. FIG. 18 is a diagram showing a logical value table of the selection circuit. 4-bit frequency selection signals C1 to C4 are input to the selection circuit SEL, their inverted and non-inverted signals are generated by the buffer inverters 30 to 33, and a decoding circuit comprising AND and OR gate groups 34 to 43 is provided. , Output signals X1 to X12 according to the logical value table are generated. The output signals X1 to X12 are preferably the same timing, and the corresponding ENOR gates X ₁ ~ X ₁₂ Is input. Therefore, the gates at the final stage may output all at once in response to the rising edge of the output OUT.
[0055]
Next, the operation of the oscillator of FIG. 16 will be described. FIG. 19 is a diagram for explaining the operation of the oscillator. First, in the initial state, the oscillation switch signal SW is at L level, and the oscillator is in a non-oscillation state. When the selection signals C1 to C4 are set to “0000” and the oscillation switch signal SW becomes H level, the NAND gate becomes an inverter and all the ENOR gates become inverters. However, since the total number of inverters is an even number of 24 stages, oscillation does not occur.
[0056]
Next, when the frequency selection signals C1 to C4 become “1000”, the output X1 = 1 is input to the ENOR gate X1 in the first stage. Thereby, as shown in FIG. 19 (1), oscillation at the reference frequency f0 is started.
[0057]
In the case of starting oscillation at the doubled frequency 2 · f0, the oscillation switch signal SW is set to L level to stop the oscillation operation of the oscillator, and then the frequency selection signals C1 to C41 are set to “0100”. In response to this, the selection circuit SEL sets the outputs X1 and X7 to the H level (logic “1”) and inputs them to the ENOR gates in the first and seventh stages. Thereby, as shown in FIG. 19 (2), two propagation signal waves are generated, and oscillation is started at a frequency of 2 × f0 multiplied by two.
[0058]
Even when oscillation is started at the tripled frequency 3 · f0, the frequency selection signals C1 to C41 are set to “1100” after the oscillation operation of the oscillator is stopped again. In response to this, the outputs X1, 5, and 9 of the selection circuit become H level, three propagation signal waves are generated, and oscillation is started at a frequency of 3 times.
[0059]
Similarly, in the case of oscillating operation at a frequency of 4, 6, or 12 times, the frequency selection signal is controlled as shown in FIG. A number of propagation signals are generated, and an oscillation operation is started at frequencies of 4, 6, and 12 times.
[0060]
As described above, it is possible to oscillate at a frequency that is approximately 1, 2, 3, 4, 6, 12 times the total number of stages of the oscillator. Each of the above examples is an example in which the duty ratio is set to 50%. By appropriately changing the output position of the selection circuit controlled to the H level, it is possible to control the oscillation at an arbitrary duty ratio. However, the duty ratio can be controlled only with a resolution of 1 / total number of stages. That is, the oscillation frequency can be controlled by the number of conversions of the ENOR gate to the inverting gate or the non-inverting gate, and the duty ratio can be controlled by the position.
[0061]
FIG. 20 is a diagram showing an operation logic value table of the selection circuit when the duty ratio is controlled by the oscillator of FIG. FIG. 21 is a diagram for explaining the duty ratio control operation. From the initial state, when the oscillation switch signal SW is set to the H level and the selection signals C1 to C4 are “0000”, the oscillator is composed of 24 inverters and therefore is in a non-oscillation state. Therefore, when the selection signals C1 to C4 are set to “1000”, as shown in FIG. 20, the selection circuit (not shown) sets the output signals X1 and X2 to the H level, and the ENOR gate X ₁ , X ₂ To enter. In response to this, as shown in FIG. 21 (1), two propagation signal waves are generated with a phase difference of two stages of the inverter, and the oscillation operation is performed at a double frequency and a duty ratio of 1/12. Be started.
[0062]
Similarly, when the selection signals C1 to C4 are set to “0100” from the non-oscillation state where the selection signals C1 to C4 are “0000”, the output signals X1 and X3 become H level, and the ENOR gate X ₁ , X _Three It will be entered. In response to this, as shown in FIG. 21 (2), two propagation signal waves are generated with a phase difference of four stages of the inverter, and the oscillation operation with a frequency of double and a duty ratio of 2/12 is performed. Be started.
[0063]
Similarly, as shown in the logical value table of FIG. 20, by appropriately selecting the selection signal from the non-oscillation state where the selection signals C1 to C4 are “0000”, two propagation signal waves are generated from the ENOR gate. Occurs at an arbitrary position and starts oscillating at an arbitrary duty ratio. As described above, when oscillating at a doubled frequency, the position of the ENOR gate that converts to the inverting gate or the non-inverting gate is selected, and the position where the propagation signal wave is generated is selected appropriately. Oscillation operation with the duty ratio can be performed. However, the resolution of the duty ratio depends on the number of stages of the gate of the oscillator, and the resolution can be increased as the number of stages increases.
[0064]
The frequency control operation described above is also possible when the oscillation state at the reference frequency f0 is changed to a higher k-multiplied frequency. Similarly, the above-described duty ratio control operation is also possible when changing from the oscillation state at the reference frequency f0 to the oscillation state at the doubled frequency 2f0.
[0065]
For example, in the frequency control operation, the selection circuit SEL in FIG. 16 responds to the change in the output OUT after the selection circuit output signals X1 to X12 in the second row in FIG. When the output signals X1 to X12 in the third and subsequent rows are output, the propagation signal waves are one, two, and three, respectively. . . And transition to an oscillation state at a higher frequency.
[0066]
Similarly, in the duty ratio control operation, the selection circuit SEL in FIG. 16 responds to the change in the output OUT after the selection circuit output signals X1 to X12 in the second row in FIG. When the output signals X1 to X12 in the second and subsequent rows in FIG. 20 are output, another propagation signal wave is added to the position of a different ENOR gate, and a clock signal having a desired duty ratio is generated by multiplication by two.
[0067]
FIG. 22 is a circuit diagram of an oscillator according to the third embodiment. The oscillation circuit 400 of this oscillator has one NAND gate and one ENOR gate X. ₁ And 10 inverter gates I ₁ ~ I _Ten Are connected in a ring shape, and oscillation at the fundamental frequency is started by the oscillation switch signal SW. The oscillation operation is detected by the oscillation detection circuit 51. After the oscillation is detected, the oscillation frequency is doubled by the oscillation frequency control signal C. The oscillation at the fundamental frequency can be switched. The latch circuit 50 latches the oscillation frequency control signal C at the falling edge of the node N14, the oscillation detection circuit 51 monitors the node N14 to detect the oscillation operation, and the delay circuit 53 further detects the oscillation switch signal SW. Is delayed for a predetermined time. The selection circuit 52 selects the output of the delay circuit 53 while the output N12 of the oscillation detection circuit 51 is in the L level in the non-oscillation state, and the latch circuit 50 outputs the output N12 while the output N12 is in the H level in the oscillation state. Select an output.
[0068]
FIG. 23 is a timing chart for explaining the operation of the oscillator of FIG. The operation of the oscillator will be described with reference to this figure. When the oscillation frequency control signal C is set to H level and the oscillation switch signal SW is set to H level from the initial state of non-oscillation state, as shown in (a), one input N11 of the NAND gate becomes H level, After the delay time of the delay circuit 53, the output N13 of the selection circuit 52 rises to the H level. In response to this, the ENOR gate X1 is switched to the buffer gate, the output OUT rises to the H level, and the oscillation operation at the fundamental frequency is started. The basic oscillation frequency f0 at that time is 1 / (2 if one gate delay time is about 10 ps. ^* 10ps ^* 11).
[0069]
Next, as shown in (b), the oscillation operation is detected by the detection circuit 51, and its output N12 rises to the H level. Thereby, the selection circuit 52 selects the output of the latch circuit 50. As shown in (c), when the oscillation frequency control signal C is set to L level, the latch circuit 50 takes in the signal C in synchronization with the falling edge of the output N14 of the inverter I2, and the selection circuit 52 outputs the output N13. Set to L level. In response to this, the ENOR gate X1 is switched to an inverter, a new propagation signal wave is generated, and oscillation starts at the doubled frequency.
[0070]
Next, as shown in (d), when the oscillation frequency control signal C is set to H level again, the signal C is latched at the falling edge of the node N14 as in the case of (c), and the output of the selection circuit 52 is output. N13 stands up. In response to this, a new propagation signal is generated, and the oscillation operation by triple is started. However, the response characteristics of each inverter cannot cope with such a high frequency, and oscillation is temporarily stopped. After that, oscillation at the fundamental frequency resumes due to external noise or the like.
[0071]
Finally, as shown in (e), when the oscillation switch signal SW is lowered to the L level, the NAND gate is closed and the oscillation is eventually stopped.
[0072]
As described above, in the oscillator shown in FIG. 22, a plurality of stages of gates and ENOR gates are connected in a ring shape, and the oscillation frequency control signal C is switched to switch between oscillation at the fundamental frequency and oscillation at the double frequency. Can be switched.
[0073]
In the above embodiments, the ENOR gate may be an EOR gate. In that case, it is necessary to reverse the logic of the signal applied to the oscillation control input. In addition, the ring-shaped oscillation circuit only needs to include at least one inversion gate, and the rest can be configured with a non-inversion gate.
[0074]
The above embodiment is summarized as follows.
[0075]
(Appendix 1) In an oscillator that generates a clock signal having a predetermined frequency,
An oscillation circuit in which at least one exclusive OR gate having an oscillation control input, at least one inversion gate, and a plurality of inversion or non-inversion gates are connected in cascade, and
An oscillation control signal generation circuit for inputting an oscillation control signal to the oscillation control input after a predetermined delay time from the change of any one of the gate outputs,
By inputting the oscillation control signal, a propagation signal wave is generated in the oscillation circuit, and the oscillation circuit oscillates at a frequency corresponding to the number of the propagation signal waves.
[0076]
(Appendix 2) In an oscillator that generates a clock signal having a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit for generating a plurality of oscillation control signals in a predetermined combination according to the oscillation selection signal;
In response to a change in any one of the gate outputs, the plurality of oscillation control signals are fetched, and the plurality of oscillation control signals are delayed in accordance with the oscillation selection signal, respectively, to the oscillation control input of the exclusive OR gate. A plurality of delay circuits to supply,
After the delay time of the delay circuit, according to the plurality of oscillation control signals, any one or more of the plurality of exclusive OR gates are converted into inversion or non-inversion gates to perform an oscillation operation. Features an oscillator.
[0077]
(Appendix 3) In Appendix 2,
When the oscillation circuit is oscillating at the first frequency, the exclusive OR gate is converted into the inverting or non-inverting gate, and the oscillation state is shifted to the oscillating state at the second frequency higher than the first frequency. An oscillator characterized by that.
[0078]
(Appendix 4) In Appendix 3,
When shifting from the first frequency to the second frequency, according to the plurality of oscillation control signals, the position of the exclusive OR gate to be converted into the inversion or non-inversion gate is selected, thereby selecting the selected duty A clock signal having a ratio is generated.
[0079]
(Supplementary Note 5) In an oscillator that generates a clock signal having a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit that generates a plurality of oscillation control signals in a predetermined combination in accordance with the oscillation selection signal and supplies the oscillation control signals to the oscillation control inputs of the plurality of exclusive OR gates,
When the oscillation circuit is in a non-oscillation state, any one or more of the exclusive OR gates are inverted or non-inverted by the plurality of oscillation control signals to start an oscillation operation. Features an oscillator.
[0080]
(Appendix 6) In Appendix 5,
The oscillation selection signal is a signal for selecting an oscillation frequency,
In accordance with the plurality of oscillation control signals, by selecting the number of exclusive OR gates to be converted into the inversion or non-inversion gate, the oscillation operation is started at one of the basic frequency and the N frequency multiplied by the basic frequency. An oscillator characterized by that.
[0081]
(Appendix 7) In Appendix 5,
The oscillation selection signal is a signal for selecting a duty ratio,
An oscillator, wherein a clock signal having a selected duty ratio is generated by selecting a position of an exclusive OR gate to be converted into the inversion or non-inversion gate according to the plurality of oscillation control signals. .
[0082]
(Supplementary Note 8) In an oscillator that generates a clock signal having a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
A plurality of oscillation control signals in a predetermined combination are generated in accordance with the oscillation selection signal, and the plurality of oscillation control signals are input to the oscillation control inputs of the plurality of exclusive OR gates in response to a change in any one of the gate outputs. And an oscillation selection circuit for supplying to each of
When the oscillation circuit is oscillating at a first frequency, one or more of the exclusive OR gates are converted into inversion or non-inversion gates by the plurality of oscillation control signals, and the first An oscillator characterized by transitioning to an oscillation state at a second frequency higher than the first frequency.
[0083]
(Appendix 9) In Appendix 8,
When shifting from the first frequency to the second frequency, according to the plurality of oscillation control signals, the position of the exclusive OR gate to be converted into the inversion or non-inversion gate is selected, thereby selecting the selected duty A clock signal having a ratio is generated.
[0084]
【Effect of the invention】
As described above, according to the present invention, it is possible to oscillate by selecting a plurality of oscillation frequencies or selecting a plurality of duty ratios with a small circuit scale.
[0085]
As described above, the protection scope of the present invention is not limited to the above-described embodiment, but extends to the invention described in the claims and equivalents thereof.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a conventional frequency-controllable oscillator.
FIG. 2 is a circuit diagram of another conventional oscillator.
FIG. 3 is a circuit diagram of a basic configuration of an oscillator according to the present embodiment.
FIG. 4 is a transistor circuit constituting inverters I1 to I7.
5 is an operation timing chart of the oscillator of FIG. 3. FIG.
6 is a diagram for explaining the operating principle of the oscillator of FIG. 3; FIG.
FIG. 7 is a circuit diagram of an oscillator according to the first embodiment.
FIG. 8 is a simplified circuit diagram of the oscillator according to the first embodiment.
FIG. 9 is a circuit diagram of an oscillation frequency selection circuit SEL.
FIG. 10 is a circuit diagram of a delay circuit DELAY.
11 is a diagram showing a logical value table of a frequency selection circuit in the frequency selection operation in the oscillator of FIG. 8. FIG.
12 is a diagram for explaining a frequency selection operation of the oscillator of FIG. 8. FIG.
13 is a diagram illustrating a logical value table of a selection circuit SEL in a duty ratio control operation in the oscillator of FIG. 8;
14 is a diagram for explaining a duty ratio control operation of the oscillator of FIG. 8; FIG.
FIG. 15 is a circuit diagram of an oscillator according to a second embodiment.
FIG. 16 is a simplified circuit diagram of an oscillator according to a second embodiment.
17 is a circuit diagram of the selection circuit SEL in FIG. 16;
18 is a diagram illustrating a logical value table of the selection circuit in FIG. 16;
19 is a diagram for explaining a frequency selection operation of the oscillator of FIG. 16;
20 is a diagram showing an operation logic value table of a selection circuit when duty ratio control is performed in the oscillator of FIG. 16. FIG.
FIG. 21 is a diagram for explaining a duty ratio control operation in the oscillator of FIG. 16;
FIG. 22 is a circuit diagram of an oscillator in the third embodiment.
FIG. 23 is a timing chart for explaining the operation of the oscillator of FIG. 22;
[Explanation of symbols]
X ₁ ~ Xn Exclusive OR gate, ENOR gate
I ₁ ~ In Inversion gate, inverter
SEL oscillation selection circuit, oscillation frequency (duty ratio) selection circuit
OUT output
DELAY delay circuit
100 Oscillator circuit
200 Oscillator circuit
300 Oscillator circuit
400 Oscillator circuit

Claims (5)

In an oscillator that generates a clock signal of a predetermined frequency,
An oscillation circuit in which at least one exclusive OR gate having an oscillation control input, at least one inversion gate, and a plurality of inversion or non-inversion gates are connected in cascade, and
A first oscillation control signal is input to the oscillation control input to cause a first change in the output of the exclusive OR gate, and a first propagation signal wave is propagated in the oscillation circuit to a first frequency. yielding a first oscillation by the delayed time to reach the first propagation signal wave according to the first change position in the desired phase in the oscillation circuit of said annular, the said oscillation control input first An oscillation control signal generating circuit for inputting a second oscillation control signal for causing a second change opposite to the change in the output of the exclusive OR gate to occur.
Wherein by the second inputting an oscillation control signal, said exclusive OR said second change in the output of the gate occurs first propagation signal wave is different from the second propagation signal wave the oscillation circuit propagated to the first and second propagation signal waves a second oscillator, wherein the oscillation is caused by the second frequency different from the first frequency according to the number of. In an oscillator that generates a clock signal of a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit for generating a plurality of oscillation control signals in a predetermined combination according to the oscillation selection signal;
Wherein either captures the plurality of oscillation control signal in response to changes in the gate output, in accordance with the oscillation selection signal, supplying the plurality of oscillation control signal to the oscillation control input of the exclusive OR gates respectively delayed A plurality of delay circuits,
A first oscillation control signal is input to the oscillation control input of any one of the plurality of exclusive OR gates, and the first exclusive OR gate is output to the first exclusive OR gate. To cause the first propagation signal wave to propagate in the oscillation circuit to cause the first oscillation with the first frequency,
The delay circuit inputs the second oscillation control signal to the oscillation control input of one of the exclusive OR gates at the timing when the first propagation signal wave reaches the position of the desired phase in the oscillation circuit. Then, a second change opposite to the first change is caused in the output of the exclusive OR gate to propagate the second propagation signal wave in the oscillation circuit, and the first and second Generating a second oscillation with a second frequency higher than the first frequency in accordance with the number of propagating signal waves;
Further, the delay circuit sends a third oscillation control signal to one of the exclusive OR gates at a timing when the first and second propagation signal waves reach a desired phase position in the oscillation circuit. An input to the oscillation control input causes a third change opposite to the second change to occur in the output of the exclusive OR gate, and a third propagation signal wave is propagated in the oscillation circuit. An oscillator characterized by causing a third oscillation with a third frequency higher than the second frequency according to the number of first, second and third propagation signal waves . In an oscillator that generates a clock signal of a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
An oscillation selection circuit that generates one or a plurality of oscillation control signals in a predetermined combination in accordance with the oscillation selection signal and simultaneously supplies them to the oscillation control inputs of the one or more exclusive OR gates. ,
When the oscillation circuit is in a non-oscillation state, one or more of the exclusive OR gates are converted into inversion or non-inversion gates by the one or more oscillation control signals, and the conversion is performed. One or more new propagation signal waves are generated in the annular oscillation circuit by inversion change of the output state of the exclusive OR gate, and oscillate at a frequency corresponding to the number of the propagation signal waves generated. An oscillator characterized by starting operation. In claim 3,
The oscillation selection signal is a signal for selecting an oscillation frequency,
In accordance with the plurality of oscillation control signals, by selecting the number of exclusive OR gates to be converted into the inversion or non-inversion gate, the oscillation operation is started at one of the basic frequency and the N frequency multiplied by the basic frequency. An oscillator characterized by that. In an oscillator that generates a clock signal of a predetermined frequency,
An oscillation circuit in which N pieces of segments in which at least one inversion gate and a plurality of inversion or non-inversion gates are connected in cascade are connected in a ring, and an exclusive OR gate having an oscillation control input;
In accordance with the oscillation selection signal, a plurality of oscillation control signals in a predetermined combination are generated, and in response to a change in any one of the gate outputs, a first change generated by an inversion change in the output state of the exclusive OR gate in timing is reached to the position of the desired phase propagation signal wave in the oscillation circuit of said annular, and each supplying an oscillation selection circuit to the oscillation control inputs of the plurality of oscillation control signal of the plurality of exclusive OR gates Have
When the oscillation circuit is oscillating at a first frequency by propagation of the first propagation signal wave, the oscillation selection circuit sends the plurality of oscillation control signals to the oscillation control input of the exclusive OR gate at the timing. the annular by inputting, to convert the inverting or non-inverting gate of the one or more one of the exclusive oR gates, the inversion change in state of the output of the converted XOR gates An oscillator characterized by generating one or a plurality of new second propagation signal waves in the oscillation circuit and shifting to an oscillation state at a second frequency higher than the first frequency.

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