JP4892970B2 - Method of using electronic circuit and programmable logic device - Google Patents

Description

  The present invention relates to a method of using an electronic circuit and a programmable logic device, and more particularly, a plurality of logic circuit cells and an electrical connection between the individual logic circuit cells provided between the individual logic circuit cells can be reconfigured. The present invention relates to an electronic circuit provided with a programmable logic device provided with various wirings, capable of configuring an arbitrary circuit and capable of changing the circuit once configured, and a method of using the programmable logic device applicable to the electronic circuit.

  In recent years, programmable logic devices (PLDs), which are programmable logic ICs, have become widespread against the background of an increase in development costs of ASICs (Application Specific Integrated Circuits). PLD has many logic elements such as AND circuit, OR circuit, NOT circuit, LUT (LookUp Table) circuit, D flip-flop and so on, and connection between individual logic elements can be set from outside. It is possible to configure a desired circuit by giving configuration information that defines connections between individual logic elements, etc., and change the circuit configuration by changing the configuration information given to the PLD (reconfiguration) It is also possible to do. PLDs include SPLD (Simple PLD), CPLD (Complex PLD), FPGA (Field Programmable Gate Array), and the like. Recently, DAP / DNA capable of reloading configuration information in one clock cycle is also available.

  In addition, a technique for appropriately switching the circuit configured on the PLD using the fact that the circuit configured on the PLD can be reconfigured has been proposed. For example, Patent Documents 1 and 2 rewrite the circuit configuration. There has been disclosed a technique for improving the usage efficiency of a CPU and reducing power consumption by changing the number of CPUs configured on a possible programmable device and the bit width of a bus connected to the CPU.

Patent Document 3 stores a plurality of pieces of circuit information having different numbers of stages of pipeline processing. When the FPGA temperature is high, a circuit having a lower number of stages of pipeline processing is reduced on the FPGA while lowering the operating frequency. When the temperature of the FPGA is low, a technique for increasing the operating frequency and configuring a circuit with a large number of pipeline processing stages on the FPGA is disclosed.
JP 2003-186680 A JP 2005-50363 A Japanese Patent Laid-Open No. 2004-22724

  As described in Patent Documents 1 to 3, a technique for switching whether to configure a high-speed circuit on a PLD or a low-power consumption circuit on a PLD according to various conditions is a general-purpose that can be used for various purposes. It is expected to develop as a highly functional technology.

  However, the techniques described in Patent Documents 1 and 2 switch the operation speed / power consumption of a circuit by switching the number of CPUs and the bit width of a bus connected to the CPU. There is a possibility that it is necessary to switch the I / F (bit width, data transfer rate, etc.) of data transmission / reception between the circuit configured on the PLD and the external circuit. Therefore, the techniques described in Patent Documents 1 and 2 do not want to change the I / F of data transmission / reception between the circuit configured on the PLD and the outside even if the configuration of the circuit formed on the PLD is switched. In this case, there is a problem that it is difficult to apply.

  In addition, since the technique described in Patent Document 3 switches the operation speed / power consumption by changing the number of stages of pipeline processing, the circuit configured on the PLD is a circuit that performs processing suitable for pipeline processing. However, there is a problem that it is difficult to apply to a circuit that performs processing that is not suitable for pipelining, such as a sequencer.

  The present invention has been made in view of the above facts, and an object of the present invention is to obtain a method of using an electronic circuit and a programmable logic device capable of switching the operation speed / power consumption of the circuit while ensuring versatility.

請 electronic circuit according to the invention Motomeko 1 described, a plurality of logic circuit cells, electrically connected reconfigurable wiring between the individual logic cells is provided between the individual said logic circuit cells A programmable logic device capable of configuring any circuit and reconfiguring the circuit configuration, and a first circuit that is a state transition circuit capable of high-speed operation on the programmable logic device. Storage means for storing configuration information and second configuration information for configuring a second circuit, which is a state transition circuit operable with low power consumption, on the programmable logic device, and a configuration on the programmable logic device state transition circuit, to switch to the first circuit or the second circuit in accordance with the configuration in which the program logic device is connected to the board mounted, the Reconfiguration means for configuring the first circuit or the second circuit on the programmable logic device by reconfiguring at least the wiring in accordance with the first configuration information or the second configuration information stored in the storage unit And.

The invention according to claim 2 is the invention according to claim 1, wherein the program logic device mounted on the board is connected to an electronic component, transmits information to and from the electronic component, and the reconfiguration means Is characterized in that the frequency of the information transmission between the programmable logic device and the electronic component is changed according to the configuration connected to the board on which the program logic device is mounted.

According to a third aspect of the present invention, in the first aspect of the invention, the state transition circuit includes a holding circuit that holds a 1-bit value and a specific internal state among m types of internal states. 1-bit value indicating whether or not the data is held in the holding circuit, and held in the holding circuit every time a predetermined event related to the transition to or from the specific internal state occurs And a change circuit for changing the value of 1 bit, which is the same as the number m of types of internal states, is provided, and each of the change circuits is provided in each of the m types of internal states in each holding circuit. One bit value corresponding to different internal states is held.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the state transition circuit is provided with n number of logarithmic values equal to or greater than the logarithmic value of the number m of the internal states with 2 as the base, and each holds a value of 1 bit. And holding the n-bit value representing the current internal state in the n holding circuits, and each time a predetermined event occurs, the n-bit value held in the n holding circuits And a single change circuit that changes the value to an n-bit value that represents an internal state corresponding to the type of event that has occurred.

According to a fifth aspect of the invention, in the fourth aspect of the invention, the m types of n-bit values respectively corresponding to any of the m types of internal states are changed by the change circuit. The n-bit value after the change is determined so that only one of the n bits changes with respect to the n-bit value before the change.

According to a sixth aspect of the present invention, there is provided a method of using a programmable logic device, wherein a plurality of logic circuit cells and an electrical connection between the individual logic circuit cells provided between the individual logic circuit cells can be reconfigured. A first circuit, which is a state transition circuit capable of high-speed operation, is configured on the programmable logic device when using a programmable logic device in which arbitrary wiring is provided and an arbitrary circuit can be configured and the circuit configuration can be reconfigured First configuration information for causing the storage device to store second configuration information for configuring a second circuit, which is a state transition circuit operable with low power consumption, on the programmable logic device, A state transition circuit configured on the programmable logic device is stored in the storage unit so as to switch to the first circuit or the second circuit according to a configuration connected to a substrate on which the program logic device is mounted. The first circuit or the second circuit is configured on the programmable logic device by reconfiguring at least the wiring according to the first configuration information or the second configuration information.

The invention makes it possible to switch the operating speed / power consumption of the circuit while ensuring the versatility, has a gutter Cormorant effect.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a computer 10 equipped with a printer I / F (interface) card 30 corresponding to an electronic circuit according to the present invention and capable of functioning as a print server.

  The computer 10 includes a CPU 12 that executes various programs under the control of an OS (Operating System), and the CPU 12 is connected to an FSB (Front Side Bus) 14 that is a processor direct connection bus. The computer 10 is provided with a PCI (Peripheral Component Interconnect Bus) 16, and the FSB 14 is connected to the PCI bus 16 via a CPU bridge (host-PCI bridge) 18. The CPU bridge 18 includes a memory controller function for controlling an access operation to the memory 20 and a data buffer for absorbing a difference in data transfer speed between the FSB 18 and the PCI bus 20.

  The memory 20 is connected to the CPU bridge 18 and reads various programs (OS, various device drivers, BIOS (Basic Input / Output System), various application programs, etc.) executed by the CPU 12, and is processed by the programs. Used as a work area for writing data. A display is connected to the CPU bridge 18 via a video subsystem (not shown). The video subsystem includes a video controller that actually processes a drawing command from the CPU 12, writes the processed drawing information into a video memory (VRAM), and reads out the drawing information from the VRAM and outputs it to the display as drawing data. It is configured.

  An I / O bridge 22 is connected to the PCI bus 16, and an HDD (Hard Disk Drive) 24 is connected to the I / O bridge 22. The I / O bridge 22 includes a bridge function between the PCI bus 16 and an ISA bus (not shown), a DMA controller function, a programmable interrupt controller (PIC) function, a programmable interval timer (PIT) function, and an IDE (Integrated Drive Electronics). It has an interface function, a USB (Universal Serial Bus) function, and an SMB (System Management Bus) interface function. The DMA controller function is a function for executing data transfer between a peripheral device (for example, the HDD 24) and the memory 20 without intervention of the CPU 12. The PIC function is a function for executing a predetermined program (interrupt handler) in response to an interrupt request (IRQ) from a peripheral device, and the PIT function is a function for generating a timer signal at a predetermined cycle.

  A printer I / F card 30 is connected to the PCI bus 16. The printer I / F card 30 is an I / F card for connecting a maximum of two printers 26A and 26B having a unique I / F to a computer and causing the printer 26 to perform printing processing in accordance with an instruction from the computer. The PC 10 is connected to the PCI bus 16 by being inserted into a PCI slot (not shown) provided in the computer 10. The printer I / F card 30 is executed by the CPU 34, a PCI I / F unit 32 that controls transmission and reception of control signals and data via the PCI bus 16, a CPU 34 that controls each unit of the printer I / F card 30, and the CPU 34. To connect a flash ROM 36 in which programs and various types of information are written, a memory 38 including a DRAM, an FPGA (Field Programmable Gate Array) 40 as a programmable logic device according to the present invention, and a connection cable 44 of the printer 26. These two connectors 42 are provided. The circuit mounted on the printer I / F card 30 corresponds to the electronic circuit according to the present invention.

  The FPGA 40 is a type of PLD that can be configured with an arbitrary circuit according to the configuration information by giving configuration information to the chip. As shown in FIG. 2 as an example, there are many FPGAs on the FPGA 40 chip. A number of logic circuit cells 46 are arranged on a matrix.

  The individual logic circuit cells 46 have the same configuration, and as shown in FIG. 3, a 4-input 2-output LUT (look-up table) 60, a D-FF (flip-flop) 62, and six programmable multiplexers. 64 (hereinafter simply referred to as “MUX”) 64, 66, 68, 70, 72, 74, and a buffer 76. The three input signal lines A to C of the logic circuit cell 46 are respectively connected to the input terminals of the LUT 60, and the input signal line D is connected to one of the two input terminals of the MUX 64 and one of the two input terminals of the MUX 66, respectively. It is connected. The other input terminal of the MUX 64 is connected to the Q terminal of the D-FF 62, the output terminal of the MUX 64 is connected to the remaining input terminal of the LUT 60, the other input terminal of the MUX 66 is connected to the output terminal G of the LUT 60, The output terminal of the MUX 66 is connected to the R terminal of the D-FF 62.

  The input signal line A is connected to one of the two input terminals of the MUX 68. The other input terminal of the MUX 68 is connected to the output terminal F of the LUT 60, and the output terminal of the MUX 68 is connected to the S terminal of the D-FF 62. ing. The three input terminals of the MUX 70 are connected to the output terminal G of the LUT 60, the output terminal of the MUX 64, and the clock signal input line K, respectively. The output terminal of the MUX 70 is connected to the input terminal of the buffer 76. The output terminal of the buffer 76 is connected to the power supply line via the resistor 78 and is also connected to the synchronization signal input terminal of the D-FF 62. The D terminal of the D-FF 62 is connected to the output terminal F of the LUT 60, and the three input terminals of the MUXs 72 and 74 are connected to the output terminal F of the LUT 60, the output terminal G of the LUT 60, and the Q terminal of the D-FF 62, respectively. The output terminal of the MUX 72 is connected to the output signal line X, and the output terminal of the MUX 74 is connected to the output signal line Y.

  The configuration information given to the FPGA 40 includes cell configuration information given to each logic circuit cell 46 on the FPGA 40, and wiring configuration information given to each switch matrix 50 and each I / O block 54 (both described later) on the FPGA 40. The individual MUXs 64, 66, 68, 70, 72, 74 provided in the logic circuit cell 46 are given to the corresponding logic circuit cell 46 among the configuration information given to the FPGA 40. According to the cell configuration information, any one of a plurality of signals input via a plurality of input terminals is selectively output. Therefore, by switching the contents of the cell configuration information given to the logic circuit cell 46, the logic circuit realized by the logic circuit cell 46 is also switched as shown in FIGS. The LUT 60 can realize various functions (conversions) by switching conversion data used for conversion. However, the conversion data set in the LUT 60 can also be switched by switching cell configuration information given to the logic circuit cell 46. Thus, by switching the conversion data set in the LUT 60 in the logic circuits shown in FIGS. 4A to 4C, various logic circuits can be realized by the single logic circuit cell 46.

The buffer 76 provided in the logic circuit cell 46 receives a signal (usually a clock signal) input from the MUX 70 via the input terminal according to the cell configuration information given to the logic circuit cell 46. The first state is output as it is to the synchronization signal input terminal, and the second state is set to make the output terminal high impedance regardless of the input signal. While the buffer 76 is in the second state, the potential of the synchronous signal input terminal of D-FF 62, depending via a resistor 78 connected feed line Ru is maintained at a constant level.

  Further, as shown in FIG. 2, on the FPGA 40 chip, between the individual logic circuit cells 46 arranged on the matrix, a wiring group 48 made up of a plurality of wirings is provided along the X direction and the Y direction. A switch matrix 50 is provided at each intersection of the wiring group 48 extending in the X direction and the wiring group 48 extending in the Y direction. It has been. The switch matrix 50 switches connection of individual wirings according to the corresponding wiring configuration information among the configuration information given to the FPGA 40. Further, the FPGA 40 is provided with a PLL circuit 52 that generates and outputs a clock signal having a predetermined frequency by PLL control based on a reference clock signal input from the outside. The output terminal of the PLL circuit 52 is connected to any one of the wiring groups 48, and the wiring connected to the PLL circuit 52 functions as a clock signal transmission line.

  In addition, a large number of I / O blocks 54 are arranged on the peripheral portion of the FPGA 40 on the chip, and each I / O block 54 is provided in a plurality of wirings of a wiring group 48 and a package of the FPGA 40. Any one of the many pins is connected to each other. Although not shown, the I / O block 54 is also configured to include a MUX (programmable multiplexer), and the MUX is switched according to the corresponding wiring configuration information among the configuration information given to the FPGA 40, so that the connected pins Is used as an input terminal to output a signal input through the pin to a connected specific wiring, or a signal input through a connected specific wiring using the connected pin as an output terminal It is configured to switch to a plurality of states such as outputting to a pin or outputting a signal input via a connected first wiring to a connected second wiring.

  The individual logic circuit cells 46 provided on the chip of the FPGA 40 are connected to the individual wirings of the wiring group 48, although not shown. Accordingly, by providing configuration information (cell configuration information, wiring configuration information, etc.) to the FPGA 40, a predetermined number of logic circuit cells 46 among the logic circuit cells 46 provided on the FPGA 40 are used, and each logic used Each of the circuit cells 46 can function as a logic circuit having a predetermined configuration, and these logic circuits can be connected in a predetermined order, so that a circuit having a predetermined configuration can be configured on the FPGA 40. Further, by switching the configuration information given to the FPGA 40, at least one of the number of the logic circuit cells 46 to be used, the configuration of the logic circuits realized by the individual logic circuit cells 46, and the connection order of the individual logic circuits is switched. A circuit having an arbitrary configuration can be reconfigured on the FPGA 40.

  In the present embodiment, configuration information to be given to the FPGA 40 is stored in the flash ROM 36, and the CPU 34 of the printer I / F card 30 is turned on when the computer 10 is turned on to supply power to the printer I / F card 30. Then, the configuration information is read from the flash ROM 36, and the read configuration information is written into a memory cell (not shown) for holding configuration information provided on the chip of the FPGA 40, thereby giving the configuration information to the FPGA 40. As a result, the circuit corresponding to the configuration information is reconfigured on the FPGA 40 by switching the MUX, the switch matrix 50, etc. provided in the FPGA 40 according to the configuration information written in the memory cell for storing the configuration information. It will be. The flash ROM 36 according to the present embodiment stores a plurality of types of configuration information as configuration information to be given to the FPGA 40, and the CPU 34 needs to switch circuits configured on the FPGA 40 when the power is turned on. In addition, any one of the plurality of types of configuration information is selectively read from the flash ROM 36, and the read configuration information is given to the FPGA 40.

  Next, as an operation of the present embodiment, first, a circuit configured in the FPGA 40 will be described. In this embodiment, the printer I / F card 30 is made to function as an I / F card that connects a maximum of two printers 26A and 26B to a computer and causes the printer 26 to perform print processing in accordance with an instruction from the computer. The plurality of types of configuration information stored in the flash ROM 36 are set so that the I / F circuit 80 shown in FIG.

  The I / F circuit 80 is connected to the PCI I / F unit 32 and processes input data from the PCI I / F unit 32, and is connected to the connector 42 for output to the printer 26. A plurality of output I / F units 84 that process data read from the memory 38, and a CPU I / F unit that is connected to the CPU 34, processes an address input from the CPU 34, and transmits / receives data to / from the CPU 34. 86, a memory I that is connected to the memory 38 and each of the I / F units 82 to 86, writes data to and reads data from the memory 38 in accordance with instructions from the I / F units 82 to 86, and controls refresh of the memory 38 / F unit 88 and the frequency required by each I / F unit 82 to 88 from the clock signal connected to the PLL circuit 52 and supplied from the PLL circuit 52 Is configured to include a clock generation circuit 90 is supplied to the I / F unit 82 to 88 to generate a clock signal.

  As shown in FIG. 6A, the input I / F unit 82 includes an input DMA sequencer 92 and an input DMA buffer 94 having a small amount (for example, about 512 bytes) of buffer memory. The sequencer 92 requests the PCI I / F unit 32 to input data while monitoring the buffer memory state (full or empty) of the input DMA buffer 94, and is input from the PCI I / F unit 32 by DMA transfer. The data (printing data) is temporarily stored in the buffer memory of the input DMA buffer 94, and the memory I / F unit 88 is requested to write the data temporarily stored in the buffer memory of the input DMA buffer 94 to the memory 38. When writing to the memory 38 becomes possible, the memory I / F unit 88 is notified of the write address (internal address) and entered. The data was temporarily stored in a buffer memory of the DMA buffer 94 performs processing to output to the memory I / F section 88 by the DMA transfer.

  As shown in FIG. 6B, the output I / F unit 84 includes an output DMA sequencer 96 and an output DMA buffer 98 having a small amount (for example, about 512 bytes) of buffer memory. The DMA sequencer 96 requests the memory I / F unit 88 to read data from the memory 38 while monitoring the state (full or empty) of the buffer memory of the output DMA buffer 98. When it becomes possible, the memory I / F unit 88 is notified of the read address (internal address) to read data from the memory 38, and the data (printing data) input from the memory I / F unit 88 by DMA transfer. ) Is temporarily stored in the buffer memory of the output DMA buffer 98, and the data temporarily stored in the buffer memory of the output DMA buffer 98 is also stored. Connector 42 data, performs a process of transferring to the printer 26 via the connection cable 44.

  As shown in FIG. 6C, the CPU I / F unit 86 includes a CPU access control sequencer 100 and a data bus control unit 102. The CPU access control sequencer 100 reads or writes data from the CPU 34. Each time the CPU 34 instructs to read data from the memory 38 or write data to the memory 38, the memory I / F unit 88 is requested to read or write data according to the instruction. The notified address is converted into an internal address and notified to the memory I / F unit 88. The CPU access control sequencer 100 transfers the read data input from the memory I / F unit 88 to the data bus control unit 102 to the CPU 34 when reading data, and from the CPU 34 to the data bus control unit 102 when writing data. The input write data is transferred to the memory I / F unit 88.

  Further, as shown in FIG. 6D, the memory I / F unit 88 includes a memory control sequencer 104, a data bus control unit 106, and a refresh counter 108. When the data writing to the memory 38 is instructed from the / F unit 82 or the CPU I / F unit 86 and the instructed writing is in an executable state, a control signal instructing the reading is output to the memory 38. At the same time, the internal address notified from the write request source (input I / F unit 82 or CPU I / F unit 86) is notified to the memory 38 as a write address, and input from the write request source to the data bus control unit 106 The written data is output to the memory 38. Further, the memory control sequencer 104 is instructed to read data from the memory 38 from the output I / F unit 84 or the CPU I / F unit 86, and when the instructed reading is possible, the memory control sequencer 104 performs the reading. A control signal to be instructed is output to the memory 38, and the internal address notified from the read request source (the output I / F unit 84 or the CPU I / F unit 86) is notified to the memory 38 as a read address. The read data input to the bus control unit 106 is transferred to the read request source.

  The refresh counter 108 manages the refresh execution cycle for the memory 38, and the memory control sequencer 104 receives a signal from the refresh counter 108 indicating that the time for executing refresh has arrived. Is instructed to execute refresh, and returns a busy response to the read / write request input during the execution of refresh. When the completion of the refresh is notified from the memory 38, the refresh counter 108 A signal for resetting the count value is output to the refresh counter 108.

  As described above, the input I / F unit 82, the output I / F unit 84, the CPU I / F unit 86, and the memory I / F unit 88 included in the I / F circuit 80 each include a sequencer. The sequencer is a circuit that holds the current internal state and changes the held internal state each time a predetermined event occurs, and performs processing according to the internal state after the transition. 7 (A), when the internal state is “state A”, “state A” is maintained until an event satisfying condition 1 occurs, and when an event satisfying condition 1 occurs, “state B When the internal state is “state B”, “state B” is maintained until an event satisfying condition 2 occurs, and when an event satisfying condition 2 occurs, the state transitions to “state C”. When the internal state is “state C”, “state C” is maintained until an event satisfying condition 3 occurs, and when an event satisfying condition 3 occurs, the state transitions to “state D”. In the case of “D”, “state D” is not changed until an event satisfying condition 4 occurs. Lifting, and transitions when events occur satisfying the condition 4 to the "state A".

  In order to perform the state transition as described above, the sequencer is configured to include a state transition circuit that holds and updates the internal state, but there are a plurality of types of state transition circuits, and one of them is, for example, As shown in FIG. 7B, when m is the number of types of internal states of the sequencer, a holding circuit (shown as a flip-flop in the figure) 112 that holds a 1-bit value, and the current internal state is m The holding circuit 112 holds a 1-bit value indicating whether or not a specific internal state of the types of internal states, and a predetermined event related to a transition to or from a specific internal state ( For example, in the state transition shown in FIG. 7A, if the specific internal state is “state A”, an event that satisfies condition 1 or an event that satisfies condition 4) occurs. Bit value There is a state transition circuit 110 having a configuration (one-hot type) in which the number of state transition management units 114 that change the number of internal states is the same as the number m of types of internal states. FIG. 7 is based on the assumption that the number of types of internal states of the sequencer is m = 4, and the state transition circuit 110 is provided with four holding circuits 112.

  In addition, as another configuration of the state transition circuit, for example, as shown in FIG. 7C, n number more than logarithmic values of the number m of internal states with 2 are provided and each holds a 1-bit value. A holding circuit (shown as a flip-flop in the figure) 118 and an n-bit value representing the current internal state are held in n holding circuits 118, and each time a predetermined event for changing the internal state occurs, a single state transition management unit 120 that changes an n-bit value held in n holding circuits 118 to an n-bit value representing an internal state corresponding to the type of event that has occurred. There is also a state transition circuit 116 of (binary type or gray type). If the number m of internal state types = 4, the logarithmic value of the number m of internal state types with base 2 is = 2, and therefore the same number (n = 2) of logarithmic values are included in the state transition circuit 116. The holding circuit 118 is provided.

  In the one-hot type state transition circuit 110 shown in FIG. 7B, the value of 1 bit held in each of the four holding circuits 112 is changed to different internal states among the four types of internal states. The 4-bit value representing the current internal state is held in the four holding circuits 112 (see also the chart shown in FIG. 7B). Accordingly, the same number of state transition management units 114 that are provided in the same number as the holding circuits 112 and change the values held in the holding circuits 112 are held in the corresponding holding circuits 112 each time the predetermined event occurs. Since the process of changing the value of 1 bit can be performed independently of the other state transition management unit 114, high-speed operation is possible (the frequency band of the operable clock signal is high). However, in the one-hot type state transition circuit 110, since the value of 1 bit held by the two holding circuits 112 always changes when the internal state is changed, the switching frequency is relatively large and the power consumption is high. There are drawbacks.

  On the other hand, in the binary type or gray type state transition circuit 116 shown in FIG. 7C, the current internal state of the four types of internal states is encoded into a 2-bit value and held in the two holding circuits 118. Therefore, as shown in FIG. 7C, the state transition management unit 120 recognizes the 2-bit value held in the two holding circuits 118 when recognizing the current internal state. It is necessary to perform a process of decoding into a 4-bit value representing the value, and when the internal state is changed, the 4-bit value representing the changed internal state is encoded into a 2-bit value and then stored in the two holding circuits 118 Since it is necessary to carry out the holding process, it is disadvantageous in terms of operation speed (the frequency band of the operable clock signal is low). However, when an event that should change the internal state occurs, the average value of the number of holding circuits 118 whose 1-bit value held is changed is smaller than 2, and the one-hot type state transition circuit 110 is changed. Lower power consumption.

  In the state transition circuit 116, as an allocation method of n-bit values to individual internal states of the sequencer, n bits arranged in ascending order of n-bit binary numbers with respect to individual internal states arranged in the state transition order. Number of bits whose value changes at the time of state transition for each internal state arranged in the order of state transitions (binary type: see also the chart shown as binary type in FIG. 7C) There is a method of assigning n-bit values arranged so that the values are always 1 (gray type: see also the chart shown as gray type in FIG. 7C). The gray type is adopted rather than the binary type because the number of holding circuits 118 that change the value of 1 bit held is always 1 when an event whose internal state should be changed occurs. However, the power consumption of the state transition circuit 116 is lower.

  Based on the above, in the present embodiment, as configuration information for configuring the I / F circuit 80 on the FPGA 40, one-hot type state transition occupying the sequencers of the I / F units 82 to 88 configuring the I / F circuit 80. Two types of configuration information for configuring either one of two types of I / F circuits 80 having different ratios of the sequencer provided with the circuit 110 and the gray type state transition circuit 116 on the FPGA 40 are prepared. First configuration information for configuring on the FPGA 40 a high-speed operation version I / F circuit 80 having a high ratio of the sequencer having the one-hot type state transition circuit 110 occupying the sequencer of ~ 88, and each I / F unit A second configuration in which an I / F circuit 80 of a low power consumption version with a high proportion of the sequencer provided with the gray type state transition circuit 116 occupying the 82 to 88 sequencers is configured on the FPGA 40. Information is stored in the flash ROM 36 in advance. The high-speed operation version I / F circuit 80 corresponds to the first circuit according to the present invention, and the low power consumption version I / F circuit 80 corresponds to the second circuit according to the present invention. The flash ROM 36 for storing configuration information corresponds to the storage means according to the present invention.

  In the high-speed operation version I / F circuit 80 and the low power consumption version I / F circuit 80, a sequencer and a gray type having a one-hot type state transition circuit 110 occupying the sequencers of the respective I / F units 82 to 88 The ratio of the state transition circuit 116 can be determined according to the required performance for the high-speed operation version I / F circuit 80 and the low power consumption version I / F circuit 80.

  The printer I / F card 30 according to the present embodiment is an I / F card that can connect a maximum of two printers 26 </ b> A and 26 </ b> B to the computer 10, and the printer connected to the computer 10 via the printer I / F card 30. The number of 26 may be one or two. Therefore, in the following, when two printers 26 are connected to the computer 10, the high-speed operation version I / F circuit 80 is configured on the FPGA 40 using the first configuration information. In the case where only one printer 26 is connected, the high-speed operation version I / F circuit is exemplified by an example in which the low power consumption I / F circuit 80 is configured on the FPGA 40 using the second configuration information. An example of the configuration of the I / F circuit 80 of 80 and the low power consumption version will be described with specific numerical values. Note that the present invention is not limited to the numerical values described below.

  As an example, as shown in FIG. 8A, information transmission between the input I / F unit 82 and the PCI I / F unit 32 is performed in synchronization with a clock signal of 32 MHz and a 32-bit width (transmission rate ( (Bit rate) = 1056 Mbps), information transmission between the output I / F unit 84 and the printer 26A is performed in synchronization with a clock signal of 55 MHz having a 32-bit width (transmission speed (bit rate) = 1980 Mbps), and output I Information transmission between the CPU / F unit 84 and the printer 26B is performed in synchronization with a clock signal of 66 MHz having a 32-bit width (transmission speed (bit rate) = 2376 Mbps), between the CPU I / F unit 86 and the CPU 34. Is transmitted in synchronization with a clock signal of 32 MHz and 66 MHz (transmission speed (bit rate) = 2112 Mbps).

  When two printers 26A and 26B are connected to the printer I / F card 30, the I / F units 82 to 86 access the memory 38 via the memory I / F unit 88. In order to avoid that the F unit 88 becomes a bottleneck of the processing speed of the I / F circuit 80, the processing speed (bit rate) of the memory I / F unit 88 is set to the above-described I / F units 82 to 86. The total bit rate must be larger than 7524 Mbps. Here, if information transmission between the memory I / F unit 88 and the memory 38 is performed in synchronization with a clock signal of 64 MHz and 120 MHz, the transmission speed (bit rate) is 7680 Mbps, and the above required value is Therefore, it can be avoided that the memory I / F unit 88 becomes a bottleneck of the processing speed of the I / F circuit 80.

However, the upper limit of the operable frequency band of the gray type state transition circuit 116 is currently about 100 MHz, and a sequencer including the gray type state transition circuit 116 is applied as the memory control sequencer 104 of the memory I / F unit 88. It is difficult. For this reason, in the high-speed operation version I / F circuit 80, a sequencer including the gray type state transition circuit 116 is applied as the sequencer of the I / F units 82 to 86, while the memory control of the memory I / F unit 88 is performed. The first configuration information is set so that the sequencer provided with the one-hot type state transition circuit 110 is applied as the sequencer 104. In the first configuration information, the clock generation circuit 90 of the high-speed operation version I / F circuit 80 supplies a 33 MHz clock signal to the input I / F unit 82 to transmit information to the printer 26A. A 55 MHz clock signal is supplied to the output I / F unit 84 to be performed, and a 66 MHz clock signal is supplied to the output I / F unit 84 and the CPU I / F unit 86 for transmitting information to and from the printer 26A. also includes the set information so that the structure for supplying a clock signal of 120MHz to section 88.

  On the other hand, when only the printer 26A is connected to the printer I / F card 30, the output I / F unit connected to the printer 26B out of the two output I / F units 84, as shown in FIG. 8B. 84 (the output I / F unit 84 indicated as “output BI / F unit” in FIG. 8B) and the printer 26B, no information is transmitted between the I / F units 82 to 86. Of these, the total value of the bit rates in the I / F part excluding the output I / F part 84 is 5148 Mbps. Therefore, if information transmission between the memory I / F unit 88 and the memory 38 is performed in synchronization with a clock signal of 64 MHz and 81 MHz, the transmission speed (bit rate) becomes 5184 Mbps, and the above required value Therefore, it can be avoided that the memory I / F unit 88 becomes a bottleneck of the processing speed of the I / F circuit 80. The frequency 81 MHz is lower than the upper limit of the operable frequency band of the gray type state transition circuit 116.

For this reason, in the low power consumption I / F circuit 80, a sequencer including a gray type state transition circuit 116 is applied as a sequencer of all the I / F units 82 to 88 including the memory I / F unit 88. Second configuration information is set so as to be a configuration. Further, in the second configuration information, the clock generation circuit 90 of the low power consumption I / F circuit 80 supplies a 33 MHz clock signal to the input I / F unit 82 to transmit information to the printer 26A. A 55 MHz clock signal is supplied to the output I / F unit 84 that performs the operation, a 66 MHz clock signal is supplied to the CPU I / F unit 86, and an 81 MHz clock signal is supplied to the memory I / F unit 88. also it includes the set information to.

Since the power consumption of the circuit is approximately proportional to the operating frequency, the operating frequency of the memory I / F unit 88 in the I / F circuit 80 of the low power consumption version is changed from 120 MHz to 81 MHz as compared with the high speed operation version of the I / F circuit 80. If the power consumption of the memory I / F unit 88 in the high-speed operation version I / F circuit 80 is 100%, the power consumption of the memory I / F unit 88 in the low power consumption version I / F circuit 80 is reduced. Is
100 x (81 ÷ 120) = 67.5%
To drop.

Further, in the high-speed operation version I / F circuit 80, a sequencer provided with a one-hot type state transition circuit 110 is applied as the memory control sequencer 104 of the memory I / F unit 88, whereas low power consumption is achieved. In the version I / F circuit 80, a sequencer including a gray type state transition circuit 116 is applied as the memory control sequencer 104 of the memory I / F unit 88. In the one-hot type state transition circuit 110, an internal when an event to change the condition occurs, against to the number of the holding circuit 112 the value of 1 bit held is changed is always 2, the gray type of state transition circuit 116, an internal state When an event to be changed occurs, the number of holding circuits 112 to which the value of 1 bit held is changed is always 1, and the number of times of switching is halved. F The power consumption of the memory I / F unit 88 in the circuit 80 is obtained by changing the memory control sequencer 104 to a sequencer including a gray type state transition circuit 116 in addition to lowering the operating frequency as described above. It will be further reduced.

  In addition, the first and second configuration information according to the present embodiment includes individual logic circuits that constitute a part of the I / F circuit 80 configured on the FPGA 40 among the logic circuit cells 46 provided on the FPGA 40. The cell 46 is in the first state in which the clock signal input to the buffer 76 in the logic circuit cell 46 is output to the synchronization signal input terminal of the D-FF 62 as it is, and when the I / F circuit 80 is configured on the FPGA 40. For other logic circuit cells 46 that are not used, the buffer 76 in the logic circuit cell 46 is set to be in the second state in which the output terminal is set to high impedance regardless of the input signal. As a result, the supply of the clock signal to the D-FF 62 in the unused logic circuit cell 46 is cut off regardless of whether the high-speed operation version or the low power consumption version I / F circuit 80 is configured on the FPGA 40. Therefore, the power consumption of the I / F circuit 80 of the high-speed operation version and the low power consumption version is further reduced.

  Incidentally, as described above, whether the high-speed operation version I / F circuit 80 or the low power consumption version I / F circuit 80 is configured on the FPGA 40 is determined via the printer I / F card 30 via the computer 10. When switching according to the number of printers 26 connected to the CPU, the CPU 34 of the printer I / F card 30 is first connected to the printer I / F card 30 when the computer 10 is powered on and supplied with power. If the number of detected printers 26 is two, and the detected number is two, the first configuration information is read from the flash ROM 36, and the read first configuration information is given to the FPGA 40. If the I / F circuit 80 is configured and the number of detected units is one, the second configuration information is read from the flash ROM 36 and the read second configuration information is read. By providing the configuration information to the FPGA 40, thereby constituting the I / F circuit 80 of the low-power version on FPGA 40. Thus, the CPU 34 corresponds to the reconstruction unit according to the present invention. Thus, the configuration of the I / F circuit 80 configured on the FPGA 40 is switched according to the required performance for the I / F circuit 80 that changes according to the number of printers 26 connected to the printer I / F card 30. be able to.

  Further, when the interface with the printer 26 is an interface that allows the connection cable 44 to be inserted and removed (so-called hot plug) while the computer 10 is operating, the printer 26 connected to the printer I / F card 30. Is detected periodically and compared with the previously detected number of units. If the number of detected units is different from the previously detected number, the configuration information corresponding to the latest detected number of units is read from the flash ROM 36 and read. By providing the configuration information to the FPGA 40, the CPU 34 executes so that the I / F circuit 80 corresponding to the number of the printers 26 currently connected to the printer I / F card 30 is configured on the FPGA 40. What is necessary is just to comprise a program.

  In the above, whether to configure the high-speed operation version I / F circuit 80 or the low power consumption version I / F circuit 80 on the FPGA 40 is connected to the computer 10 via the printer I / F card 30. Although the mode of switching according to the number of printers 26 has been described, the present invention is not limited to this. For example, the transmission speed (bit rate) between the printer I / F card 30 and the printer 26 can be switched according to the magnitude of the load applied to the printer 26, or the printer via the PCI bus 16. Requests to the printer I / F card 30 (I / F circuit 80) such that the substantial transfer rate of data input to the I / F card 30 varies depending on the load applied to the computer 10. Since the performance may change from moment to moment, the required performance for the printer I / F card 30 (I / F circuit 80) is detected, and the I / F circuit 80 configured on the FPGA 40 is configured according to the detected required performance. You may make it switch.

  In addition, in a programmable logic device such as an FPGA, characteristics relating to capacitance and signal delay are provided for each wiring provided between each logic circuit cell 46 on the chip and each wiring in each logic circuit cell 46. It is different. Therefore, for example, as shown in FIG. 9, when a wiring A having a large capacity and a small signal delay and a wiring B having a small capacity and a large signal delay are present on the programmable logic device, the wiring is configured on the programmable logic device. Among the circuits, the operation speed is further increased by using the wiring A for the high-speed operation version circuit that emphasizes the operation speed, and the wiring B is used for the low-power consumption version circuit that emphasizes the power consumption. The configuration information of each circuit may be set so that the circuit is configured by using wiring having characteristics suitable for items emphasized in each circuit, such as further suppressing power consumption. Thereby, even if the circuit configuration itself is the same, the performance (operation speed or power consumption) of each circuit can be further improved.

  In the above, the flash ROM 36 includes first configuration information for configuring the high-speed operation version I / F circuit 80 on the FPGA 40 and second configuration information for configuring the low power consumption version I / F circuit 80. However, the number of types of circuits (number of types of configuration information) configured on the FPGA 40 is not limited to the above, and more types of configuration information are prepared, and each configuration information A circuit configured on the FPGA 40 may be selected / switched from a larger number of types of circuits corresponding to the above.

In the above description, the case where the I / F circuit 80 is configured on the FPGA 40 mounted on the printer I / F card 30 has been described as an example. However, the programmable logic device to which the present invention is applicable is not limited to the FPGA. For example, PLD (specifically, for example, MAXII manufactured by Altera Corporation) equipped with a flash memory capable of storing and rewriting configuration information, or programmable such that DAP / DNA can reconfigure the circuit configuration. The present invention can be applied to any logical device. Further, the circuit configured on the programmable logic device is not limited to the I / F circuit 80, and the electronic circuit according to the present invention including the programmable logic device is limited to the circuit mounted on the printer I / F card 30. Rather, the present invention is applicable to an electronic circuit having an arbitrary configuration including a programmable logic device, and is a first state transition circuit that can operate at high speed according to the configuration of the electronic circuit and the required performance for the electronic circuit. Needless to say, the present invention can be applied to a case where a circuit and a second circuit, which is a state transition circuit operable with lower power consumption than the first circuit, are selectively configured on a programmable logic device.

1 is a block diagram illustrating a schematic configuration of a computer and a printer I / F card according to an embodiment. It is a top view which shows schematic structure on the chip | tip of FPGA. It is a circuit diagram which shows an example of a structure of the logic circuit cell of FPGA. (A)-(C) are block diagrams which show an example of the logic circuit realizable by the logic circuit cell of FIG. FIG. 2 is a block diagram illustrating an example of a circuit configured on an FPGA of a printer I / F card. (A)-(D) are block diagrams which show schematic structure of each I / F part in the circuit of FIG. (A) is a conceptual diagram showing an example of state transition of a sequencer, (B) is a one-hot type, (C) is a schematic configuration diagram of a gray type sequencer, and values and internal states held in each flip-flop. It is a chart which shows the relationship. (A) is an explanatory diagram for explaining an example of required performance when two printers are connected to the printer I / F card, and (B) is an example of required performance when only one printer is connected. It is a conceptual diagram for demonstrating the performance improvement of the circuit by selecting the wiring from which a characteristic differs.

Explanation of symbols

30 Printer I / F Card 34 CPU
36 Flash ROM
38 memory 40 FPGA
46 logic circuit cell 48 wiring group 62 D-FF
76 Buffer 110 State Transition Circuit 116 State Transition Circuit

Claims (6)

Arranged between a plurality of logic circuit cells and the individual logic circuit cells, and wiring capable of reconfiguring electrical connection between the individual logic circuit cells is provided, and an arbitrary circuit can be configured and the circuit A programmable logic device capable of reconfiguration, and
First configuration information for configuring a first circuit, which is a state transition circuit capable of high-speed operation, on the programmable logic device, and a second circuit, which is a state transition circuit operable at low power consumption, on the programmable logic device Storage means for storing each of the second configuration information for configuring
A state transition circuit configured on the programmable logic device is stored in the storage unit so as to switch to the first circuit or the second circuit according to a configuration connected to a substrate on which the program logic device is mounted. Reconfiguration means for configuring the first circuit or the second circuit on the programmable logic device by reconfiguring at least the wiring according to the first configuration information or the second configuration information.
Including electronic circuit.   The program logic device mounted on the substrate is connected to an electronic component and transmits information to and from the electronic component.
The reconfiguration unit changes a frequency of the information transmission between the programmable logic device and the electronic component according to a configuration connected to a board on which the program logic device is mounted. Item 2. The electronic circuit according to Item 1. The state transition circuit causes the holding circuit to hold a 1-bit value and a holding circuit to hold a 1-bit value indicating whether the current internal state is a specific internal state among m types of internal states. And a change circuit that changes a value of 1 bit held in the holding circuit each time a predetermined event related to the transition to or from the specific internal state occurs. The number of internal states is the same as the number of types m, and each of the change circuits causes each of the holding circuits to hold 1-bit values corresponding to different internal states of the m types of internal states. The electronic circuit according to claim 1. The state transition circuit is provided with n holding circuits each having a logarithmic value greater than or equal to the logarithm value of the number m of the internal states with 2 as a base, and holding an n-bit value representing the current internal state. Each of the n holding circuits holds the n-bit value held in the n holding circuits every time a predetermined event occurs, and represents an internal state corresponding to the type of the generated event n The electronic circuit according to claim 1, comprising a single change circuit for changing to a bit value. The m types of n-bit values respectively corresponding to any of the m types of internal states are the n-bit values after the change when the values are changed by the change circuit. 5. The electronic circuit according to claim 4, wherein only one of n bits is changed with respect to the value of. A plurality of logic circuit cells and wiring provided between the individual logic circuit cells and capable of reconfiguring electrical connection between the individual logic circuit cells are provided, and an arbitrary circuit can be configured and a circuit configuration. When using programmable logic devices that can be reconfigured
First configuration information for configuring a first circuit, which is a state transition circuit capable of high-speed operation, on the programmable logic device, and a second circuit, which is a state transition circuit operable at low power consumption, on the programmable logic device Second configuration information for configuring each is stored in the storage means,
A state transition circuit configured on the programmable logic device is stored in the storage unit so as to switch to the first circuit or the second circuit according to a configuration connected to a substrate on which the program logic device is mounted. The first circuit or the second circuit is configured on the programmable logic device by reconfiguring at least the wiring according to the first configuration information or the second configuration information.
A method for using a programmable logic device.

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