JP4890563B2 - Plasma display apparatus and driving method thereof - Google Patents

Description

  The present invention relates to a plasma display device and a driving method thereof.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of partition walls formed in parallel to the data electrodes on each of the dielectric layers. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method for driving the panel, a subfield method, that is, a method in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields that emit light is generally used. In this subfield method, Patent Document 1 discloses a novel driving method in which light emission not related to gradation display is reduced as much as possible to suppress an increase in black luminance and to improve a contrast ratio. The driving method will be briefly described below.

  Each subfield has an initialization period, an address period, and a sustain period. Also, during the initialization period, all cell initialization operations for performing initialization discharge for all discharge cells that perform image display, or selectively for discharge cells that have undergone sustain discharge in the immediately preceding subfield, are performed. One of the selective initialization operations for performing the initialization discharge is performed.

  First, in the all-cell initializing period, initializing discharge is simultaneously performed in all the discharge cells, the history of wall charges for the individual individual discharge cells is erased, and the wall charges necessary for the subsequent address operation are removed. Form. In the subsequent address period, a scan pulse is sequentially applied to the scan electrodes, and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes, so that an address discharge is selectively generated between the scan electrodes and the data electrodes. Then, selective wall charge formation is performed. In the sustain period, a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.

  However, in a state where no sustain discharge is caused, that is, in a discharge cell in which a black state continues for several fields, priming is insufficient and the discharge delay becomes large. Therefore, the initialization discharge becomes unstable during the all-cell initialization period, and excessive positive wall charges may accumulate on the scan electrodes. In a discharge cell in which excessive positive wall charges are accumulated on the scan electrode, a sustain discharge is caused even though no write discharge is caused. This sustain discharge was visually recognized as a bright spot, deteriorating the black display quality.

  Patent Document 2 describes a driving method that solves the problem that a bright spot is visually recognized in a discharge cell in which excessive positive wall charges are accumulated on a scan electrode.

  The driving method will be briefly described below. An abnormal wall charge erasing unit is provided that applies a positive rectangular waveform voltage to the scan electrode during the all-cell initialization period or the selective initialization period, and then applies a negative rectangular waveform voltage to the scan electrode. In a discharge cell in which excessive positive wall charges are accumulated on the scan electrode, a strong discharge is generated at the abnormal wall charge erasing portion with a positive rectangular waveform voltage applied to the scan electrode. This strong discharge inverts the wall charges, and then an erasing discharge is generated by the negative rectangular waveform voltage applied to the scan electrodes, and the wall charges are erased.

  As described above, even in the discharge cell in which excessive positive wall charges are accumulated on the scan electrodes, the wall charges are erased in the abnormal wall charge erasing portion in the initialization period, and thus no bright spot is generated.

JP 2000-242224 A JP 2005-326612 A

  However, a discharge cell whose discharge start voltage has greatly decreased due to secular change or the like causes discharge due to a positive rectangular waveform voltage applied to the scan electrode in the abnormal wall charge erasing portion, and a negative polarity applied to the subsequent scan electrode. The rectangular waveform voltage causes an erasing discharge and the wall charges are erased. As described above, in the cell in which the discharge start voltage is greatly reduced, the wall charge is erased in the abnormal wall charge erasing portion even though excessive positive wall charge is not accumulated on the scan electrode. Write operation is not possible.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display device and a driving method thereof that can perform a normal writing operation and display an image with good quality even in a discharge cell having a greatly reduced discharge start voltage. .

  (1) A plasma display device according to one aspect of the present invention includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes, and one field period includes a plurality of subfields. A plasma display device driven by a subfield method, comprising: a scan electrode drive circuit for driving a scan electrode; a sustain electrode drive circuit for driving a sustain electrode; and a data electrode drive circuit for driving a data electrode; At least one of the subfields includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible, and the scan electrode driving circuit is configured to operate in the first period within the initialization period. A first ramp waveform voltage is applied to the scan electrode, the scan electrode serves as an anode, and the sustain electrode and the data electrode serve as a cathode. A second discharge is generated by generating an initializing discharge and applying a downward ramp waveform voltage to the scanning electrode in the second period after the first period in the initializing period, using the scanning electrode as a cathode and the sustain electrode and the data electrode as an anode. In the third period after the second period in the initialization period, a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrode, and the data electrode driving circuit A positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the third period.

  In the plasma display device, at least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state where address discharge is possible.

  In the first period within the initialization period, the scan electrode driving circuit applies an upward ramp waveform voltage to the scan electrode, and a first initialization discharge is generated with the scan electrode as the anode and the sustain electrode and the data electrode as the cathode. The As a result, negative wall charges are stored on the scan electrodes and positive wall charges are stored on the sustain electrodes and the data electrodes.

  In a second period after the first period in the initialization period, a second ramp waveform voltage is applied to the scan electrode by the scan electrode driving circuit, and the scan electrode serves as a cathode and the sustain electrode and the data electrode serve as an anode. Initializing discharge is generated. Thereby, the wall charges on the scan electrodes and the wall charges on the sustain electrodes are reduced, and the wall charges on the data electrodes are also adjusted to values suitable for the write operation.

  Here, when the discharge delay is large, in the first period of the initialization period, when the discharge occurs, the voltage of the discharge cell greatly exceeds the discharge start voltage, and thus a strong discharge is generated instead of a weak discharge. Alternatively, a strong discharge using the data electrode as a cathode occurs in advance. Then, excessive negative wall charges are accumulated on the scan electrodes. Thereby, in the second period of the initialization period, the discharge cell again generates a strong discharge. As a result, excessive positive wall charges are accumulated on the scan electrodes.

  In a third period after the second period in the initialization period, the scan electrode driving circuit applies a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrodes. Further, in the third period, a positive rectangular waveform voltage is applied to the data electrode by the data electrode driving circuit between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.

  During this time, in a discharge cell in which positive excess wall charges are accumulated on the scan electrode and a discharge cell in which the discharge start voltage is lowered, when a positive rectangular waveform voltage is applied to the scan electrode, the discharge cell Since the voltage exceeds the discharge start voltage, a strong discharge occurs and the wall charges on the scan electrodes are inverted. In a discharge cell having a reduced discharge start voltage, discharge occurs when a positive rectangular waveform voltage is applied to the data electrode. This discharge is in a state where the erasing discharge is forcibly terminated halfway. By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. A discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scan electrode. A discharge cell in which excessive wall charges are accumulated discharges with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scan electrode. When the discharge cell discharges with a positive rectangular waveform voltage applied to the data electrode, the discharge is in a state where the erasing discharge is forcibly terminated halfway, but excessive wall charges are accumulated. The state of being is canceled. In the discharge cell in which the erasing discharge is generated by the negative rectangular waveform voltage applied to the scan electrode, the wall charge inside the discharge cell is erased.

  As described above, in the discharge cell in which the discharge start voltage is lowered, the wall charge is not erased in the third period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.

  (2) The data electrode driving circuit may continuously apply two or more positive rectangular waveform voltages to the data electrode in the third period.

  In this case, even when the discharge delay of the discharge cell in which the discharge start voltage is reduced is large, the wall charge is prevented from being erased in the third period of the initialization period. Therefore, a normal write operation is performed.

  (3) The data electrode drive circuit continuously applies two or more positive rectangular waveform voltages to the data electrode in the third period, and the voltage application time of the first rectangular waveform voltage applied to the data electrode is The voltage application period of a plurality of rectangular waveform voltages applied to the data electrode may be the shortest.

  In this case, a discharge cell with a small discharge delay among the discharge cells having a reduced discharge start voltage can be discharged with a rectangular waveform voltage applied first. This prevents the wall charges from being erased in the third period of the initialization period even when the discharge delays of the discharge cells having a reduced discharge start voltage are different. Therefore, a normal write operation is performed.

  (4) A plasma display device according to another aspect of the present invention includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes, wherein one field period includes a plurality of subfields. A plasma display device that is driven by a subfield method, includes a scan electrode drive circuit that drives a scan electrode, a sustain electrode drive circuit that drives a sustain electrode, and a data electrode drive circuit that drives a data electrode. At least one of the subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible, and the scan electrode driving circuit is configured to operate in the first period of the initialization period. Initial application of a downward ramp waveform voltage to the scan electrode, with the scan electrode as the cathode and the sustain and data electrodes as the anode In the second period after the first period of the initializing period, a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrodes in the second period. The positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage applied to the scan electrode and the negative rectangular waveform voltage.

  In the plasma display device, at least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state where address discharge is possible.

  In a first period within the initialization period, a downward ramp waveform voltage is applied to the scan electrode by the scan electrode driving circuit, and an initialization discharge is generated with the scan electrode as the cathode and the sustain electrode and the data electrode as the anode. As a result, the sustain discharge is performed in the sustain period of the previous subfield, and in the discharge cell, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is also a value suitable for the write operation. Adjusted to

  Here, when the discharge delay is large, in the first period of the initialization period, when the discharge occurs, the voltage of the discharge cell greatly exceeds the discharge start voltage, and thus a strong discharge is generated instead of a weak discharge. Alternatively, a strong discharge using the data electrode as a cathode occurs in advance. As a result, excessive positive wall charges are accumulated on the scan electrodes.

  In the second period within the initialization period, the scan electrode driving circuit applies a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrodes. Further, in the second period, a positive rectangular waveform voltage is applied to the data electrode by the data electrode driving circuit between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.

  During this time, in a discharge cell in which positive excess wall charges are accumulated on the scan electrode and a discharge cell in which the discharge start voltage is lowered, when a positive rectangular waveform voltage is applied to the scan electrode, the discharge cell Since the voltage exceeds the discharge start voltage, a strong discharge occurs and the wall charges on the scan electrodes are inverted. In a discharge cell having a reduced discharge start voltage, discharge occurs when a positive rectangular waveform voltage is applied to the data electrode. This discharge is in a state where the erasing discharge is forcibly terminated halfway. By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. A discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scan electrode. A discharge cell in which excessive wall charges are accumulated discharges with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scan electrode. When the discharge cell discharges with a positive rectangular waveform voltage applied to the data electrode, the discharge is in a state where the erasing discharge is forcibly terminated halfway, but excessive wall charges are accumulated. The state of being is canceled. In the discharge cell in which the erasing discharge is generated by the negative rectangular waveform voltage applied to the scan electrode, the wall charge inside the discharge cell is erased.

  As described above, in the discharge cell in which the discharge start voltage is lowered, the wall charge is not erased in the second period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.

  (5) A driving method of a plasma display device according to still another aspect of the present invention includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes. A method of driving a plasma display device that is driven by a subfield method including a plurality of subfields, comprising: driving a scan electrode; driving a sustain electrode; and driving a data electrode; At least one subfield of the field includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible, and the step of driving the scan electrode includes a first period in the initialization period. In this case, an upward ramp waveform voltage is applied to the scan electrode, the scan electrode is the anode, and the sustain electrode and the data electrode are And generating a first initializing discharge, and applying a downward ramp waveform voltage to the scan electrode in the second period after the first period in the initializing period, using the scan electrode as the cathode, the sustain electrode and the data A step of generating a second initializing discharge with the electrode as an anode, and a positive rectangular waveform voltage and a negative rectangular waveform voltage on the scan electrode in a third period after the second period in the initializing period; The step of driving the data electrode includes the step of driving the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the third period. It includes a step of applying a waveform voltage.

  In the driving method of the plasma display device, at least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.

  In a first period within the initialization period, a rising ramp waveform voltage is applied to the scan electrode, and a first initialization discharge is generated with the scan electrode as the anode and the sustain electrode and the data electrode as the cathode. As a result, negative wall charges are stored on the scan electrodes and positive wall charges are stored on the sustain electrodes and the data electrodes.

  In a second period after the first period in the initialization period, a downward ramp waveform voltage is applied to the scan electrode, and a second initialization discharge is generated with the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. Is done. Thereby, the wall charges on the scan electrodes and the wall charges on the sustain electrodes are reduced, and the wall charges on the data electrodes are also adjusted to values suitable for the write operation.

  Here, when the discharge delay is large, in the first period of the initialization period, when the discharge occurs, the voltage of the discharge cell greatly exceeds the discharge start voltage, and thus a strong discharge is generated instead of a weak discharge. Alternatively, a strong discharge using the data electrode as a cathode occurs in advance. Then, excessive negative wall charges are accumulated on the scan electrodes. Thereby, in the second period of the initialization period, the discharge cell again generates a strong discharge. As a result, excessive positive wall charges are accumulated on the scan electrodes.

  In a third period after the second period in the initialization period, a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrodes. Further, in the third period, the positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.

  During this time, in a discharge cell in which positive excess wall charges are accumulated on the scan electrode and a discharge cell in which the discharge start voltage is lowered, when a positive rectangular waveform voltage is applied to the scan electrode, the discharge cell Since the voltage exceeds the discharge start voltage, a strong discharge occurs and the wall charges on the scan electrodes are inverted. In a discharge cell having a reduced discharge start voltage, discharge occurs when a positive rectangular waveform voltage is applied to the data electrode. This discharge is in a state where the erasing discharge is forcibly terminated halfway. By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. A discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scan electrode. A discharge cell in which excessive wall charges are accumulated discharges with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scan electrode. When the discharge cell discharges with a positive rectangular waveform voltage applied to the data electrode, the discharge is in a state where the erasing discharge is forcibly terminated halfway, but excessive wall charges are accumulated. The state of being is canceled. In the discharge cell in which the erasing discharge is generated by the negative rectangular waveform voltage applied to the scan electrode, the wall charge inside the discharge cell is erased.

  As described above, in the discharge cell in which the discharge start voltage is lowered, the wall charge is not erased in the third period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.

  (6) The step of driving the data electrode may include a step of continuously applying two or more positive rectangular waveform voltages to the data electrode in the third period.

  In this case, even when the discharge delay of the discharge cell in which the discharge start voltage is reduced is large, the wall charge is prevented from being erased in the third period of the initialization period. Therefore, a normal write operation is performed.

  (7) The step of driving the data electrode includes a step of continuously applying two or more positive rectangular waveform voltages to the data electrode in the third period, and the rectangular waveform voltage applied first to the data electrode The voltage application time may be the shortest of the voltage application periods of the plurality of rectangular waveform voltages applied to the data electrodes.

  In this case, a discharge cell with a small discharge delay among the discharge cells having a reduced discharge start voltage can be discharged with a rectangular waveform voltage applied first. This prevents the wall charges from being erased in the third period of the initialization period even when the discharge delays of the discharge cells having a reduced discharge start voltage are different. Therefore, a normal write operation is performed.

  (8) A driving method of a plasma display device according to still another aspect of the present invention includes a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes, and a plurality of data electrodes. A method of driving a plasma display device that is driven by a subfield method including a plurality of subfields, comprising: driving a scan electrode; driving a sustain electrode; and driving a data electrode; At least one sub-field of the field includes an initialization period in which wall charges of the plurality of discharge cells are adjusted to enable address discharge, and the step of driving the scan electrode is performed in the first period of the initialization period. A downward ramp waveform voltage is applied to the scan electrode, the scan electrode is the cathode, and the sustain electrode and data electrode are the anode Generating an initializing discharge, and applying a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrode in a second period after the first period of the initializing period, The step of driving the electrode includes a step of applying a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the second period. It is a waste.

  In the driving method of the plasma display device, at least one subfield of the plurality of subfields includes an initialization period in which the wall charges of the plurality of discharge cells are adjusted to a state in which address discharge is possible.

  In a first period within the initialization period, a downward ramp waveform voltage is applied to the scan electrode, and an initialization discharge is generated with the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. As a result, the sustain discharge is performed in the sustain period of the previous subfield, and in the discharge cell, the wall charge on the scan electrode and the wall charge on the sustain electrode are reduced, and the wall charge on the data electrode is also a value suitable for the write operation. Adjusted to

  Here, when the discharge delay is large, in the first period of the initialization period, when the discharge occurs, the voltage of the discharge cell greatly exceeds the discharge start voltage, and thus a strong discharge is generated instead of a weak discharge. Alternatively, a strong discharge using the data electrode as a cathode occurs in advance. As a result, excessive positive wall charges are accumulated on the scan electrodes.

  In the second period within the initialization period, a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrodes. In the second period, the positive rectangular waveform voltage is applied to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode.

  During this time, in a discharge cell in which positive excess wall charges are accumulated on the scan electrode and a discharge cell in which the discharge start voltage is lowered, when a positive rectangular waveform voltage is applied to the scan electrode, the discharge cell Since the voltage exceeds the discharge start voltage, a strong discharge occurs and the wall charges on the scan electrodes are inverted. In a discharge cell having a reduced discharge start voltage, discharge occurs when a positive rectangular waveform voltage is applied to the data electrode. This discharge is in a state where the erasing discharge is forcibly terminated halfway. By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. A discharge cell discharged with a positive rectangular waveform voltage applied to the data electrode does not discharge with a negative rectangular waveform voltage applied to the scan electrode. A discharge cell in which excessive wall charges are accumulated discharges with a positive rectangular waveform voltage applied to the data electrode or a negative rectangular waveform voltage applied to the scan electrode. When the discharge cell discharges with a positive rectangular waveform voltage applied to the data electrode, the discharge is in a state where the erasing discharge is forcibly terminated halfway, but excessive wall charges are accumulated. The state of being is canceled. In the discharge cell in which the erasing discharge is generated by the negative rectangular waveform voltage applied to the scan electrode, the wall charge inside the discharge cell is erased.

  As described above, in the discharge cell in which the discharge start voltage is lowered, the wall charge is not erased in the second period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.

  According to the present invention, in the discharge cell having a reduced discharge start voltage, the wall charge is not erased in the final period of the initialization period, so that a normal write operation is performed in the next write period. Therefore, it is possible to display an image with good quality.

FIG. 1 is a perspective view showing a main part of a panel used in the first embodiment of the present invention. FIG. 2 is an electrode array diagram of the panel according to the first embodiment of the present invention. FIG. 3 is a block diagram of a plasma display device using the panel driving method. Figure 4 shows the drive waveform applied to each electrode of the panel. FIG. 5 is a circuit diagram of the data electrode driving circuit according to the first embodiment of the present invention. FIG. 6 is a circuit diagram of the scan electrode driving circuit according to the first embodiment of the present invention. FIG. 7 is a circuit diagram of the sustain electrode drive circuit according to the first embodiment of the present invention. FIG. 8 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the first embodiment of the invention. FIG. 9 is a drive waveform diagram applied to each electrode of the panel according to the second embodiment of the present invention. FIG. 10 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the second embodiment of the present invention. FIG. 11 is a drive waveform diagram applied to each electrode of the panel according to the third embodiment of the present invention. FIG. 12 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the third embodiment of the present invention. FIG. 13 is a drive waveform diagram applied to each electrode of the panel in the fourth embodiment of the present invention. FIG. 14 is a timing chart for explaining an example of the operation of the scan electrode driving circuit in the all-cell initializing period in the fourth embodiment of the invention.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(1) 1st Embodiment FIG. 1: is a disassembled perspective view which shows the structure of the panel 10 in the 1st Embodiment of this invention. On the glass front plate 21, a plurality of display electrode pairs 28 made up of the scan electrodes 22 and the sustain electrodes 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 cross each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 28 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of the panel according to the embodiment of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged along the row direction, and m along the column direction. The data electrodes D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of the plasma display device 1 according to the first embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit that supplies necessary power to each circuit block. (Not shown). The image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. Scan electrode driving circuit 53 has sustain pulse generating circuit 100 for generating sustain pulses to be applied to scan electrodes SCN1 to SCNn in the sustain period, and drives each of scan electrodes SCN1 to SCNn based on the timing signal. Sustain electrode drive circuit 54 includes a circuit that applies voltage Ve1 to sustain electrodes SUS1 to SUSn during the initialization period, and a sustain pulse generation circuit 200 that generates sustain pulses to be applied to sustain electrodes SUS1 to SUSn during the sustain period. And sustain electrodes SUS1 to SUSn are driven based on the timing signal.

  Next, a driving waveform for driving the panel and its operation will be described. In the embodiment, one field is divided into 10 subfields (first SF, second SF,..., And 10th SF), and each subfield is (1, 2, 3, 6, 11, 18, 30, 44, 60 and 80). In this way, the field is configured such that the luminance weight becomes larger in the rear subfield.

  FIG. 4 is a drive waveform diagram applied to each electrode of the panel according to the first embodiment of the present invention, and shows a subfield having an initialization period for performing the all-cell initialization operation (hereinafter referred to as “all-cell initialization subfield”). ) And a drive waveform of a subfield having an initialization period for performing a selective initialization operation (hereinafter, abbreviated as “selective initialization subfield”). FIG. 4 shows a drive waveform diagram in which the first SF is used as an all-cell initializing subfield and the second SF is used as a selective initializing subfield.

  First, the drive waveform and operation of the all-cell initialization subfield will be described. The all-cell initialization period will be described by dividing it into three periods: a first half (first period), a second half (second period), and an abnormal charge erasing part (third period) as follows.

  In the first half of the initialization period, sustain electrodes SUS1 to SUSn are held at 0 (V), data electrodes D1 to Dm are held at positive voltage Vd (V), and a discharge start voltage is applied to scan electrodes SCN1 to SCNn. An upward ramp waveform voltage that gradually rises from the following voltage Vp (V) toward voltage Vr (V) exceeding the discharge start voltage is applied. Then, a weak initializing discharge is generated with scan electrodes SCN1 to SCNn as anodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as cathodes. Thus, the first weak setup discharge is generated in all the discharge cells, negative wall voltages are stored on scan electrodes SCN1 to SCNn, and positive on sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm. Wall voltage is stored. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  In the second half of the initialization period, sustain electrodes SUS1 to SUSn are kept at positive voltage Ve1 (V), data electrodes D1 to Dm are kept at 0 (V), and scan electrodes SCN1 to SCNn are supplied with voltage from voltage Vg (V). (Va + Vset2) A downward ramp waveform voltage that gently falls toward (V) is applied. Then, in all the discharge cells, a second weak initializing discharge is generated with scan electrodes SCN1 to SCNn as cathodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as anodes. Then, the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened, and the wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the write operation. As described above, the initializing operation in the all-cell initializing subfield is an all-cell initializing operation for generating an initializing discharge in all the discharge cells.

  However, if the discharge delay increases due to insufficient priming or the like, excessive positive wall charges are accumulated on scan electrodes SCN1 to SCNn in the first half and second half of the all-cell initialization period. The reason will be described.

  When the discharge delay increases, in the first half of the initialization period, the discharge cell is discharged by the gradually increasing upward ramp waveform voltage applied to the scan electrodes SCN1 to SCNn, but when the discharge occurs, the voltage of the discharge cell becomes the discharge start voltage. Therefore, a strong discharge is generated instead of a weak discharge. Or the strong discharge which uses the data electrodes D1-Dm as a cathode will generate | occur | produce in advance. Then, excessive negative wall charges are accumulated on scan electrodes SCN1 to SCNn. Then, in the latter half of the setup period, the discharge cell again generates a strong discharge while applying a downward ramp waveform voltage to scan electrodes SCN1 to SCNn, and excessive positive wall charges accumulate on scan electrodes SCN1 to SCNn. Will be.

  In the abnormal charge erasing unit in the initialization period, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, after applying positive voltage Vs (V) less than the discharge start voltage to scan electrodes SCN1 to SCNn for 5 to 20 μs, positive voltage Vd (V for 100 ns to 1 μs) is applied to data electrodes D1 to Dm. ) And then a negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn for a short time of 5 μs or less. During this time, discharge does not occur in the discharge cells in which the discharge start voltage has not decreased among the discharge cells that have performed stable initialization discharge, and the wall voltage maintains the state in the latter half of the initialization period. However, in a discharge cell in which positive abnormal wall charges are accumulated on scan electrodes SCN1 to SCNn and a discharge cell in which the discharge start voltage is lowered, when voltage Vs (V) is applied to scan electrodes SCN1 to SCNn, Since the voltage of the discharge cell exceeds the discharge start voltage, a strong discharge occurs and the wall voltage on scan electrodes SCN1 to SCNn is inverted. Among the discharge cells in which abnormal wall charges are accumulated and the discharge cells in which the discharge start voltage is reduced, the positive voltage Vd (V) is applied to the data electrodes D1 to Dm in the discharge cell in which the discharge start voltage is reduced. When is applied, discharge occurs. In this discharge, the positive voltage Vd (V) applied to the data electrodes D1 to Dm is applied for a very short time, so that the erasing discharge is forcibly terminated halfway.

  By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. The discharge cells discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm are not discharged with the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. A discharge cell in which abnormal wall charges are accumulated discharges with a positive voltage Vd (V) applied to the data electrodes D1 to Dm or a negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. When the discharge cell is discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm, the discharge is in a state where the erasing discharge is forcibly terminated midway, but the wall charge is abnormally high. The state where is accumulated is canceled. In a discharge cell in which an erasing discharge is generated with a negative pulse voltage Va (V) applied to scan electrodes SCN1 to SCNn, the wall voltage inside the discharge cell is erased.

  For a discharge cell in which abnormal wall charges are accumulated, the probability that the discharge voltage is discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm increases as the wall charge accumulation amount increases and the discharge delay decreases. Become. The discharge cells that have not been discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm are discharged with the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. As described above, the discharge cell in which abnormal wall charges are accumulated has a positive voltage Vd (V) applied to the data electrodes D1 to Dm or a negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. It is possible to eliminate the state in which the wall charges are abnormally accumulated by causing discharge at either voltage.

  In the subsequent address period, voltage Ve2 is applied to sustain electrodes SUS1 to SUSn when scan electrodes SCN1 to SCNn are at voltage 0 (V). Next, negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn, and scan electrodes SCN1 to SCNn are held at voltage Vc (V).

  The reason why the scan electrodes SCN1 to SCNn are held at the voltage Vc (V) after the negative voltage Va (V) is applied to the scan electrodes SCN1 to SCNn is that the voltage Vc (V) is raised from the voltage Va (V). This is because a necessary circuit configuration is general, and the present invention is not limited to this. For example, the negative voltage Va (V) may not be applied to the scan electrodes SCN <b> 1 to SCNn using a circuit configuration that can increase the voltage from 0 (V) to the voltage Vc (V).

  In addition, when scan electrodes SCN1 to SCNn are at voltage 0 (V), voltage Ve2 (V) is applied to sustain electrodes SUS1 to SUSn, but scan electrodes SCN1 to SCNn are at voltage Vc (V). Sometimes, the voltage Ve2 (V) may be applied to the sustain electrodes SUS1 to SUSn. Further, when voltage Ve2 (V) is applied to sustain electrodes SUS1 to SUSn when scan electrodes SCN1 to SCNn are at voltage Vc (V), negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn. May not be applied.

  Next, a positive address pulse voltage Vd (V) is applied to the data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the first row. Scan pulse voltage Va (V) is applied to scan electrode SCN1. At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SCN1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vd−Va) (V). Which exceeds the discharge start voltage. An address discharge occurs between data electrode Dk and scan electrode SCN1 and between sustain electrode SUS1 and scan electrode SCN1, positive wall charges are accumulated on scan electrode SCN1 of this discharge cell, and on sustain electrode SUS1. Negative wall charges are accumulated in the data electrode Dk, and negative wall charges are also accumulated on the data electrode Dk. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall charges are accumulated on the respective electrodes. On the other hand, since the voltage at the intersection of the data electrode to which the positive address pulse voltage Vd (V) is not applied and the scan electrode SCN1 does not exceed the discharge start voltage, the address discharge does not occur. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vs (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCNi and sustain electrode SUSi is equal to sustain pulse voltage Vs (V) and the magnitude of the wall voltage on scan electrode SCNi and sustain electrode SUSi. Becomes the added value and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCNi and sustain electrode SUSi, negative wall charges are accumulated on scan electrode SCNi, and positive wall charges are accumulated on sustain electrode SUSi. At this time, positive wall charges are also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall charge state at the end of the initialization period is maintained. Subsequently, scan electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vs (V) is applied to sustain electrodes SUS1 to SUSn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between sustain electrode SUSi and scan electrode SCNi exceeds the discharge start voltage, so that a sustain discharge occurs again between sustain electrode SUSi and scan electrode SCNi. Negative wall charges are accumulated on SUSi, and positive wall charges are accumulated on scan electrode SCNi. Thereafter, similarly, by applying sustain pulse voltage alternately to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn, sustain discharge is continuously performed in the discharge cells in which the address discharge is generated in the address period. At the end of the sustain period, a so-called narrow pulse is applied between scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn to leave positive wall charges on data electrode Dk, and scan electrode SCN1. ˜SCNn and the wall charges on the sustain electrodes SUS1 to SUSn are erased. Thus, the maintenance operation in the maintenance period is completed.

  Next, the drive waveform and operation of the selective initialization subfield will be described.

  In the initialization period, sustain electrodes SUS1 to SUSn are held at Ve1 (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are moved from Vq (V) to Va (V). Apply a descending ramp waveform voltage that gradually falls. Then, in the discharge cell in which the sustain discharge is performed in the sustain period of the previous subfield, a weak initializing discharge is generated, the wall voltage on scan electrode SCNi and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk is reduced. Is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells in which the address discharge and the sustain discharge were not performed in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  The address period and the sustain period are the same as the address period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted.

  Here, in the abnormal charge erasing portion in the initialization period, a period between the time when the positive voltage Vs (V) is applied to the scan electrodes SCN1 to SCNn and the time when the negative voltage Va (V) is applied. The reason for applying the positive voltage Vd (V) to the data electrodes D1 to Dm will be described. The discharge cell in which the discharge start voltage is greatly reduced causes discharge by the positive voltage Vs (V) applied to the scan electrodes SCN1 to SCNn in the abnormal wall charge erasing portion. When the positive voltage Vd (V) is not applied to the data electrodes D1 to Dm, an erasing discharge is caused by the negative rectangular waveform voltage applied to the subsequent scanning electrodes, and the wall charges are erased. As described above, in the cell in which the discharge start voltage is greatly reduced, the wall charge is erased in the abnormal wall charge erasing portion even though excessive positive wall charge is not accumulated on the scan electrode. Write operation is not possible.

  Therefore, in the abnormal charge erasing part in the all-cell initialization period, in a period between the time when the positive voltage Vs (V) is applied to the scan electrodes SCN1 to SCNn and the time when the negative voltage Va (V) is applied A positive voltage Vd (V) is applied to the data electrodes D1 to Dm. As a result, the wall charge of the discharge cell whose discharge start voltage is greatly reduced is adjusted, the wall charge is prevented from being erased by the abnormal wall charge erasing unit, and the normal writing operation can be performed.

  In the present embodiment, an example is shown in which the subfield for performing the all-cell initialization operation is one subfield, but the present invention is not limited to this. For example, the all-cell initializing operation may be performed in a plurality of subfields, and one or more all-cell initializing periods may be provided in one or more all-cell initializing periods.

  Next, an example of the control of the data electrode drive circuit, the scan electrode drive circuit, and the sustain electrode drive circuit in the all-cell initialization period in the first embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a circuit diagram of the data electrode driving circuit 52 according to the first embodiment of the present invention. Data electrode drive circuit 52 includes power supply VD for generating voltage Vd, switching elements Q1D1 to Q1Dm, and switching elements Q2D1 to Q2Dm. The data electrodes 32 (D1 to Dm) are independently connected to the power supply VD via the switching elements Q1D1 to Q1Dm and clamped to the voltage Vd. The data electrodes 32 (D1 to Dm) are independently grounded via the switching elements Q2D1 to Q2Dm and clamped to 0 (V). In this way, the data electrode driving circuit 52 drives the data electrodes 32 independently and applies a positive address pulse voltage Vd to the data electrodes 32.

  The control signals SD1 to SDm of the data electrode driving circuit 52 are given to the data electrode driving circuit 52 by the timing generation circuit 55 and the image signal processing circuit 51 as timing signals.

  Next, FIG. 6 is a circuit diagram of the scan electrode driving circuit 53 in the first embodiment of the present invention. Scan electrode driving circuit 53 has sustain pulse generation circuit 100 for generating a sustain pulse, initialization waveform generation circuit 300 for generating an initialization waveform, scan pulse generation circuit 400 for generating a scan pulse, and scan electrode 22 at voltage Va. A switching element Q15 for clamping is provided.

  Sustain pulse generation circuit 100 includes a power recovery unit 110 and a clamp unit 120. The power recovery unit 110 includes a power recovery capacitor C10, switching elements Q11 and Q12, backflow prevention diodes D11 and D12, and resonance inductors L11 and L12. The clamp unit 120 has switching elements Q13 and Q14. The power recovery unit 110 and the clamp unit 120 are connected to the scan electrode 22 via the scan pulse generation circuit 400.

  The power recovery unit 110 causes LC resonance between the panel capacitance (not shown) of the plasma display panel and the inductor L11 or the inductor L12 to form rising and falling of the sustain pulse voltage. When the sustain pulse voltage rises, the charge stored in the power recovery capacitor C10 is moved to the interelectrode capacitance Cp via the switching element Q11, the diode D11, and the inductor L11. When the sustain pulse falls, the electric charge stored in the panel capacitance is returned to the power recovery capacitor C10 via the inductor L12, the diode D12, and the switching element Q12. In this way, the sustain pulse is applied to the scan electrode 22. Thus, since the power recovery unit 110 drives the scan electrode 22 by LC resonance without supplying power from the power supply, the power consumption is ideally zero. The power recovery capacitor C10 has a sufficiently large capacity compared to the interelectrode capacitance Cp, and is charged to about Vs / 2, which is half the voltage Vs of the power supply VS so as to serve as a power supply for the power recovery unit 110. Yes.

  In the voltage clamp unit 120, the scan electrode 22 is connected to the power source VS via the switching element Q13, and the scan electrode 22 is clamped to the voltage Vs. Further, the scanning electrode 22 is grounded via the switching element Q14 and clamped to 0 (V). In this way, the voltage clamp unit 120 drives the scan electrode 22. Therefore, the impedance at the time of voltage application by the voltage clamp unit 120 is small, and a large discharge current due to strong sustain discharge can be stably passed.

  Thus, sustain pulse generation circuit 100 applies sustain pulse to scan electrode 22 using power recovery unit 110 and voltage clamp unit 120 by controlling switching element Q11, switching element Q12, switching element Q13, and switching element Q14. . In addition, these switching elements can be comprised using generally known elements, such as MOSFET (metal oxide semiconductor field effect transistor) or IGBT (insulated gate bipolar transistor).

  The initialization waveform generation circuit 300 includes Miller integration circuits 310 and 320, generates the above-described initialization waveform, and controls the initialization voltage in the all-cell initialization operation. Miller integrating circuit 310 includes field effect transistor FET1, capacitor C1, and resistor R1, and generates an up-ramp waveform voltage that gradually rises in a ramp shape up to voltage Vr in which voltage Vz is superimposed on voltage Vs. Miller integrating circuit 320 includes field effect transistor FET2, capacitor C2, and resistor R2, and generates a down-ramp waveform voltage that gradually decreases in a ramp shape to a predetermined initialization voltage Va. In FIG. 6, the input terminals of Miller integrating circuit 310 and Miller integrating circuit 320 are shown as terminal IN1 and terminal IN2, respectively.

  In this embodiment, a Miller integration circuit using a FET that is practical and has a relatively simple configuration is employed as the initialization waveform generation circuit 300. However, the present invention is not limited to this configuration. Any circuit may be used as long as it can generate an up-ramp waveform voltage and a down-ramp waveform voltage.

  Scan pulse generation circuit 400 includes switching element S31, switching element S32, and scan IC (integrated circuit) 401. Main energization line (sustain pulse generation circuit 100, initialization waveform generation circuit 300, and scan pulse generation circuit 400 is common). Then, one of the voltage applied to the energization line (shown by a broken line in the drawings connected) and the voltage obtained by superimposing the voltage Vscn on the voltage of the main energization line is selected and applied to the scan electrode. For example, in the address period, the voltage of the main energization line is maintained at the negative voltage Va, and the negative voltage Va input to the scan IC 401 and the voltage Vc obtained by superimposing the voltage Vscn on the negative voltage Va are switched and output. As a result, the negative scanning pulse voltage described above is generated.

  The scan electrode driving circuit 53 includes an AND gate AG that performs a logical product operation, and a comparator CP that compares the magnitudes of input signals input to two input terminals. The comparator CP compares the voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the voltage Va and the voltage of the main conduction line, and outputs “0” when the voltage of the main conduction line is higher, otherwise Then, “1” is output. Two input signals, that is, an output signal SL1 (CEL1) of the comparator CP and a switching signal SL2 are input to the AND gate AG. As the switching signal CEL2, for example, a timing signal output from the timing generation circuit 55 can be used. The AND gate AG outputs “1” when any of the input signals is “1”, and outputs “0” otherwise. The output of the AND gate AG is input to the scan pulse generation circuit 400. Scan pulse generation circuit 400 outputs the voltage of the main conducting line if the output of AND gate AG is “0”, and superimposes voltage Vscn on the voltage of the main conducting line if the output of AND gate AG is “1”. Output the output voltage.

  Next, FIG. 7 is a circuit diagram of the sustain electrode driving circuit 54 in the first embodiment of the present invention. Sustain electrode drive circuit 54 includes sustain pulse generating circuit 200 that generates a sustain pulse, and switching elements Q26 and Q27 for clamping sustain electrode 23 to voltage Ve.

  Sustain pulse generation circuit 200 includes a power recovery unit 210 and a clamp unit 220. The power recovery unit 210 includes a power recovery capacitor C20, switching elements Q21 and Q22, backflow prevention diodes D21 and D22, and resonance inductors L21 and L22. The clamp unit 120 has switching elements Q23 and Q24. The power recovery unit 210 and the clamp unit 220 are connected to the sustain electrode 23. These switching elements can be configured using generally known elements such as MOSFETs or IGBTs.

  FIG. 8 is a timing chart for explaining an example of operations of the data electrode driving circuit 52, the scan electrode driving circuit 53, and the sustain electrode driving circuit 54 in the all-cell initializing period in the present embodiment. The all-cell initialization period will be described by dividing it into three periods: a first half (first period), a second half (second period), and an abnormal charge erasing part (third period).

(First half)
When switching element Q11 of scan electrode drive circuit 53 is turned on at time t1, a current starts to flow from power recovery capacitor C10 to switching electrode 22 through switching element Q11, diode D11 and inductor L11, and the voltage of scan electrode 22 begins to rise. . At time t2, switching element Q13 of scan electrode driving circuit 53 is turned on. Then, since the scan electrode 22 is connected to the power source VS through the switching element Q13, the scan electrode 22 is clamped to the voltage Vs.

  At time t3, the control signals SD1 to SDm of the switching elements Q1D1 to Q1Dm and the switching elements Q2D1 to Q2Dm of the data electrode driving circuit 52 are set to Lo (low level). Switching elements Q1D1 to Q1Dm are turned on, switching elements Q2D1 to Q2Dm are turned off, and the voltage of data electrode 32 is clamped to voltage Vd. Switching elements Q1D1 to Q1Dm are composed of elements that are turned on when the control signal is Lo.

  At time t4, the potential of the input terminal IN1 of Miller integrating circuit 310 is set to “high level”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal IN1. Then, a constant current flows from the resistor R1 toward the capacitor C1, the source voltage of the transistor FET1 rises in a ramp shape, and is superimposed on the voltage Vs via the capacitor 31. The output voltage of the scan electrode drive circuit 53 also starts to rise in a ramp shape. This voltage increase continues until the output voltage increases to Vr. When the output voltage rises to Vr, the output voltage is fixed at Vr while the potential of the input terminal IN1 is “high level”. In this way, an up-ramp waveform voltage that gradually rises from the voltage Vs toward the voltage Vr exceeding the discharge start voltage is applied to the scan electrode 22.

(Second half)
When the potential of the input terminal IN1 is set to “low level” at time t5, the voltage of the scan electrode 22 decreases to the voltage Vs. At time t6, the control signals SD1 to SDm of the switching elements Q1D1 to Q1Dm and the switching elements Q2D1 to Q2Dm of the data electrode driving circuit 52 are set to Hi (high level). Switching elements Q1D1 to Q1Dm are turned off, switching elements Q2D1 to Q2Dm are turned on, and the voltage of data electrode 32 is clamped to voltage 0 (V).

  When switching elements Q25 and Q26 of sustain electrode drive circuit 54 are turned on at time t7, the voltage of sustain electrode 22 rises to Ve1. Switching element Q21 and switching element Q23 are turned off immediately before time t7.

  At time t8, the potential of the input terminal IN2 of the Miller integrating circuit 320 is set to “high level”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal IN2. Then, a constant current flows from the resistor R2 toward the capacitor C2, the drain voltage of the transistor FET2 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 53 starts to decrease in a ramp shape. Switching Q11 and Q13 are turned off immediately before time t8.

  At this time, the comparator CP compares the down-ramp waveform voltage (voltage of the main energization line) with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va, and the output signal SL1 from the comparator CP. Is switched from “0” to “1” at time t9 when the down-ramp waveform voltage becomes equal to or lower than the voltage (Va + Vset2). At this time, since the switching signal SL2 is “1”, both inputs of the AND gate AG are “1”, and “1” is output from the AND gate AG. As a result, the scan pulse generation circuit 400 outputs a voltage Vc in which the voltage Vscn is superimposed on the downward ramp waveform voltage.

  Thus, the minimum voltage in the down-ramp waveform voltage can be (Va + Vset2).

(Abnormal charge eraser)
When the switching element 14 is turned on at time t10, the voltage of the scan electrode 22 is reduced to 0 (V).

  At time t11, switching element Q22 of sustain electrode drive circuit 54 is turned on. Then, a current starts to flow from the sustain electrode 23 to the capacitor C20 through the inductor L22, the diode D22, and the switching element Q22, and the voltage of the sustain electrode 23 starts to decrease.

  Switching element Q24 is turned on at time t12. Then, since sustain electrode 23 is grounded through switching element Q24, the voltage of sustain electrode 23 is clamped to 0 (V). Further, the switching element Q11 of the scan electrode driving circuit 53 is turned on at the same timing as the switching element Q24 is turned on at time t12. Then, current starts to flow from the power recovery capacitor C10 to the scan electrode 22 through the switching element Q11, the diode D11, and the inductor L11, and the voltage of the scan electrode 22 starts to rise.

  At time t13, switching element Q13 of scan electrode drive circuit 53 is turned on. Then, since the scan electrode 22 is connected to the power source VS through the switching element Q13, the scan electrode 22 is clamped to the voltage Vs.

  At time t14, switching element Q12 of scan electrode drive circuit 53 is turned on. Then, current starts to flow from the scan electrode 22 to the capacitor C10 through the inductor L12, the diode D12, and the switching element Q12, and the voltage of the scan electrode 22 starts to decrease.

  Switching element Q14 is turned on at time t15. Then, since the scan electrode 22 is grounded through the switching element Q14, the voltage of the scan electrode 22 is clamped to 0 (V).

  At time t16, the control signals SD1 to SDm of the switching elements Q1D1 to Q1Dm and the switching elements Q2D1 to Q2Dm of the data electrode driving circuit 52 are set to Lo. Switching elements Q1D1 to Q1Dm are turned on, switching elements Q2D1 to Q2Dm are turned off, and the voltage of data electrode 32 is clamped to voltage Vd.

  At time 17, control signals SD1 to SDm of switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm of data electrode driving circuit 52 are set to Hi. Switching elements Q1D1 to Q1Dm are turned off, switching elements Q2D1 to Q2Dm are turned on, and the voltage of data electrode 32 is clamped to voltage 0 (V).

  At time t18, the potential of the input terminal IN2 of the Miller integrating circuit 320 of the scan electrode driving circuit 53 is set to “high level”, and the switching element Q15 is turned on. Then, the voltage of the scan electrode 22 is clamped to the voltage Va. Switching elements Q12 and Q14 are turned off immediately before time t8.

  At time t19, the switching signal SL2 of the AND gate AG of the scan electrode driving circuit 53 is set to “1”. In the comparator CP, the voltage of the main energization line is compared with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va. The voltage of the main energization line is the voltage Va, which is equal to or lower than the voltage (Va + Vset2). Therefore, the output signal SL1 from the comparator CP is “1”. As a result, the scan pulse generation circuit 400 outputs a voltage Vc in which the voltage Vscn is superimposed on the voltage of the main energization line, and the voltage of the scan electrode driver 22 becomes Vc.

  At time t20, switching element Q14 of scan electrode drive circuit 53 is turned on. Then, the scan electrode 22 is clamped to a voltage of 0 (V). Just before time t20, the switching element Q15 is turned off, the switching signal SL2 of the AND gate AG is set to “0”, and the potential of the input terminal IN2 of the Miller integrating circuit 320 is set to “low level”.

  Thus, in the present embodiment, the data electrode driving circuit has the circuit configuration shown in FIG. 5, the scan electrode driving circuit 53 has the circuit configuration shown in FIG. 6, and the sustain electrode driving circuit is shown in FIG. The data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 are driven at the timing shown in the timing chart of FIG. Thereby, it is possible to realize the drive waveforms applied to the data D1 to Dm electrodes, the scan electrodes 22, and the sustain electrodes 23 in the all-cell initialization period of the present embodiment. In particular, in the abnormal charge erasing unit in the all-cell initialization period, a positive pulse voltage is applied to the data electrode between the positive pulse voltage and the negative pulse voltage applied to the scan electrode. As a result, normal write discharge can be performed in the subsequent write period, and a high-quality image can be displayed.

(2) Second Embodiment Next, a plasma display device according to a second embodiment of the present invention will be described. The configuration diagram of the plasma display apparatus of the present embodiment is the same as that of the first embodiment. The present embodiment is different from the first embodiment in the drive waveform applied to the abnormal charge erasing unit in the initialization period. FIG. 9 is a drive waveform diagram applied to each electrode of the panel in the present embodiment, and shows drive waveforms of the all-cell initialization subfield and the selective initialization subfield. FIG. 9 shows a drive waveform including the first SF as an all-cell initialization subfield and the second SF as a selective initialization subfield.

  First, the drive waveform and operation of the all-cell initialization subfield will be described. The all-cell initialization period will be described as follows, divided into the first half (first period), the second half (second period), and the abnormal charge erasing part (third period). Since the first half and the second half of the initialization period are the same as those in the first embodiment, detailed description thereof is omitted. When the discharge delay becomes large, such as when priming is insufficient, excessive positive wall charges are accumulated on scan electrodes SCN1 to SCNn in the first half and second half of the all-cell initialization period.

  In the abnormal charge erasing unit in the initialization period, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, after applying positive voltage Vs (V) less than the discharge start voltage to scan electrodes SCN <b> 1 to SCNn for 5 to 20 μs, first positive voltage of 100 ns to 1 μs is applied to data electrodes D <b> 1 to Dm. Vd (V) is applied, and a second positive voltage Vd (V) of 100 ns to 1 μs is applied to the data electrodes D1 to Dm with an interval of 100 ns to 1 μs. At this time, the application time of the first positive voltage Vd (V) applied to the data electrodes D1 to Dm is shorter than the application time of the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. To do.

  Thereafter, negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn for a short time of 5 μs or less. During this time, discharge does not occur in the discharge cells in which the discharge start voltage has not decreased among the discharge cells that have performed stable initialization discharge, and the wall voltage maintains the state in the latter half of the initialization period. However, in a discharge cell in which positive abnormal wall charges are accumulated on scan electrode SCNi and a discharge cell in which the discharge start voltage is lowered, when voltage Vs (V) is applied to scan electrodes SCN1 to SCNn, discharge start voltage Therefore, a strong discharge is generated and the wall voltage on the scan electrode SCNi is inverted.

  A first positive voltage Vd (V) is applied to the data electrodes D1 to Dm in a discharge cell in which the discharge start voltage is greatly reduced. If the discharge delays of the red, green, and blue discharge cells are not significantly different, the red, green, and blue discharge cells are discharged at the first positive voltage Vd (V) applied to the data electrodes D1 to Dm. The wall charge can be adjusted so that the writing operation can be normally performed in the writing period. However, when the discharge delays of the red, green, and blue discharge cells are greatly different, the discharge cells having a large discharge delay do not discharge with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm. There is a case. For example, when the discharge delay of the green discharge cell is small and the discharge delay of the red and blue discharge cells is large, the application time of the first positive voltage Vd (V) applied to the data electrodes D1 to Dm is set to the discharge delay. It is determined according to the characteristics of the green discharge cell having a small size.

  In order to match the characteristics of the green discharge cell having a small discharge delay, the application time of the first positive voltage Vd (V) is set to be as short as about 150 ns. The necessity of matching the first positive voltage Vd (V) applied to the data electrodes D1 to Dm with the characteristics of the green discharge cell having a small discharge delay will be described. If the application time of the first positive voltage Vd (V) is too long, for example, about 400 ns, in the green discharge cell with a small discharge delay, the erase discharge cannot be terminated halfway, and the wall charge It will be erased. Therefore, for the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, the application time is set very short in accordance with the characteristics of the green discharge cell having a small discharge delay.

  Blue and red discharge cells having a large discharge delay may not be discharged at the first positive voltage Vd (V) having a short application time. Therefore, the second positive voltage Vd (V) is then applied to the data electrodes D1 to Dm. The application time of the second positive voltage Vd (V) is determined in accordance with the characteristics of the red and blue discharge cells having a large discharge delay. Since the discharge delay is large, the blue and red discharge cells that were not discharged with the first positive voltage Vd (V) having a short application time applied to the data electrodes D1 to Dm are applied to the data electrodes D1 to Dm. Discharge occurs at the second positive voltage Vd (V). The application time of the second positive voltage Vd (V) applied to the data electrodes D1 to Dm is about 400 ns.

  Since the green discharge cell having a small discharge delay is discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, the second positive voltage Vd ( V) does not discharge. In this way, the green cell with a small discharge delay is discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, and the red and blue discharge cells with the large discharge delay are among the data. The discharge cells that have not been discharged with the first positive voltage Vd (V) applied to the electrodes D1 to Dm are discharged with the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. By these discharges, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. A discharge cell having a reduced discharge start voltage is either the first positive voltage Vd (V) applied to the data electrodes D1 to Dm or the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. Is discharged at a negative voltage Va (V) applied to scan electrodes SCN1 to SCNn. Since the discharge cells having a reduced discharge start voltage are not discharged by the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn, the wall charges are prevented from being erased.

  The discharge cells in which abnormal wall charges are accumulated include a first positive voltage Vd (V) applied to the data electrodes D1 to Dm and a second positive voltage Vd (applied to the data electrodes D1 to Dm. V) and a negative voltage Va (V) applied to scan electrodes SCN1 to SCNn. When a discharge occurs at the positive voltage Vd (V) applied to the data electrodes D1 to Dm or the second positive voltage Vd (V) applied to the data electrodes D1 to Dm, the discharge is in the middle of the erasing discharge. However, the abnormally accumulated wall charge is eliminated. In the discharge cells in which the erasing discharge is generated with the negative pulse voltage Va (V) applied to scan electrodes SCN1 to SCNn, the wall charges inside the discharge cells are erased. For discharge cells in which abnormal wall charges are accumulated, the discharge is performed with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm as the amount of accumulated wall charges increases and the discharge delay decreases. Probability increases.

  The discharge cells that have not been discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm are the second positive voltage Vd (V) or scan electrode applied to the data electrodes D1 to Dm. It discharges with the negative voltage Va (V) applied to SCN1-SCNn. As described above, the discharge cells in which abnormal wall charges are accumulated have the first positive voltage Vd (V) applied to the data electrodes D1 to Dm and the second positive voltage applied to the data electrodes D1 to Dm. It is possible to eliminate the state in which wall charges are abnormally accumulated by causing discharge at any one of voltage Vd (V) and negative voltage Va (V) applied to scan electrodes SCN1 to SCNn.

  The subsequent writing period, sustain period, and selective initialization subfield are the same as those in the first embodiment, and are therefore omitted.

  As described above, in the abnormal charge erasing portion in the all-cell initializing period, between the time when the positive voltage Vs (V) is applied to the scan electrodes SCN1 to SCNn and the time when the negative voltage Va (V) is applied. In the period, the first positive voltage Vd (V) and the second positive voltage Vd (V) are applied to the data electrodes D1 to Dm. As a result, even when the discharge delay characteristics of the red, green, and blue discharge cells are different, the wall charge of the discharge cell in which the discharge start voltage is greatly reduced is adjusted, and the wall charge is reduced at the abnormal wall charge erasing unit. Erasing can be prevented and normal writing operation can be performed.

  In the present embodiment, an example is shown in which the subfield for performing the all-cell initialization operation is one subfield, but the present invention is not limited to this. For example, the all-cell initializing operation may be performed in a plurality of subfields, and one or more all-cell initializing periods may be provided in one or more all-cell initializing periods.

  Next, an example of control of the data electrode drive circuit, the scan electrode drive circuit, and the sustain electrode drive circuit in the all-cell initialization period in this embodiment will be described with reference to the drawings. The data electrode drive circuit, scan electrode drive circuit, and sustain electrode drive circuit used in this embodiment are the same as those in the first embodiment, and FIG. 10 shows the data electrodes in the all-cell initialization period in the first embodiment. 5 is a timing chart for explaining an example of operations of drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54. Further, since time t1 to time t17 is the same as that of the first embodiment, description thereof is omitted.

  At time t100 next to time t7, the control signals SD1 to SDm of the switching elements Q1D1 to Q1Dm and the switching elements Q2D1 to Q2Dm of the data electrode driving circuit 52 are set to Lo. Switching elements Q1D1 to Q1Dm are turned on, switching elements Q2D1 to Q2Dm are turned off, and the voltage of data electrode 32 is clamped to voltage Vd.

  At time 200, control signals SD1 to SDm of switching elements Q1D1 to Q1Dm and switching elements Q2D1 to Q2Dm of data electrode driving circuit 52 are set to Hi. Switching elements Q1D1 to Q1Dm are turned off, switching elements Q2D1 to Q2Dm are turned on, and the voltage of data electrode 32 is clamped to voltage 0 (V).

  Since time t18 to time t20 is the same as that of the first embodiment of the present invention, description thereof will be omitted.

  Thus, in the present embodiment, the data electrode driving circuit has the circuit configuration shown in FIG. 5, the scan electrode driving circuit 53 has the circuit configuration shown in FIG. 6, and the sustain electrode driving circuit is shown in FIG. The data electrode driving circuit 52, the scan electrode driving circuit 53, and the sustain electrode driving circuit 54 are driven at the timing shown in the timing chart of FIG. Thereby, it is possible to realize the drive waveforms applied to the data D1 to Dm electrodes, the scan electrodes 22, and the sustain electrodes 23 in the all-cell initialization period of the present embodiment.

  In particular, in the abnormal charge erasing portion in the all-cell initialization period, the positive pulse voltage is applied twice to the data electrode between the positive pulse voltage and the negative pulse voltage applied to the scan electrode. As a result, even when there are discharge cells having different discharge delays, it is possible to perform normal address discharge in the subsequent address period and display a high-quality image.

(3) Third Embodiment A third embodiment of the present invention will be described. The configuration diagram of the plasma display device in the present embodiment is the same as that in the first embodiment. This embodiment is different from the first embodiment in that the abnormal charge erasing unit is provided in the selective initialization period instead of the all-cell initialization period. FIG. 11 is a drive waveform diagram applied to each electrode of the panel in the present embodiment, and shows drive waveform diagrams of the all-cell initializing subfield and the selective initializing subfield. FIG. 11 shows a driving waveform including the first SF as an all-cell initializing subfield and the second SF as a selective initializing subfield.

  First, the drive waveform and operation of the all-cell initialization subfield will be described. Since the first half and the second half of the all-cell initialization period are the same as those in the first embodiment, detailed description thereof is omitted. When the discharge delay becomes large, such as when priming is insufficient, excessive positive wall charges are accumulated on scan electrodes SCN1 to SCNn in the first half and second half of the all-cell initialization period. Further, the writing period and the sustaining period are the same as those in the first embodiment, and thus description thereof is omitted here.

  Next, the drive waveform and operation of the selective initialization subfield will be described. The selective initialization period will be described as divided into two periods, a first half (first period) and an abnormal charge erasing part (second period) as follows.

  First, in the first half of the initialization period, sustain electrodes SUS1 to SUSn are held at Ve1 (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are supplied with voltage from voltage Vq (V). A downward ramp waveform voltage that gently falls toward Va (V) is applied. Then, in the discharge cell in which the sustain discharge is performed in the sustain period of the previous subfield, a weak initializing discharge is generated, the wall voltage on scan electrode SCNi and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk is reduced. Is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells in which the address discharge and the sustain discharge were not performed in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  In the abnormal charge erasing unit in the initialization period, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, after applying positive voltage Vs (V) less than the discharge start voltage to scan electrodes SCN1 to SCNn for 5 to 20 μs, positive voltage Vd (V for 100 ns to 1 μs) is applied to data electrodes D1 to Dm. ) And then a negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn for a short time of 5 μs or less. During this time, discharge does not occur in the discharge cells in which the discharge start voltage has not decreased among the discharge cells that have performed stable initialization discharge, and the wall voltage maintains the state in the latter half of the initialization period. However, in a discharge cell in which positive abnormal wall charges are accumulated on scan electrode SCNi and a discharge cell in which the discharge start voltage is lowered, when voltage Vs (V) is applied to scan electrodes SCN1 to SCNn, discharge start voltage Therefore, a strong discharge is generated and the wall voltage on the scan electrode SCNi is inverted.

  Among the discharge cells in which abnormal wall charges are accumulated and the discharge cells in which the discharge start voltage is reduced, the positive voltage Vd (V) is applied to the data electrodes D1 to Dm in the discharge cell in which the discharge start voltage is reduced. When is applied, discharge occurs. In this discharge, the positive voltage Vd (V) applied to the data electrodes D1 to Dm is applied for a very short time, so that the erasing discharge is forcibly terminated halfway. By this discharge, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period. The discharge cells discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm are not discharged with the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn.

  A discharge cell in which abnormal wall charges are accumulated discharges with a positive voltage Vd (V) applied to the data electrodes D1 to Dm or a negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. When a discharge is generated at the positive voltage Vd (V) applied to the data electrodes D1 to Dm, the discharge is in a state where the erasing discharge is forcibly terminated in the middle, but the wall charge is abnormally increased. The accumulated state is canceled. In the discharge cell in which the erasing discharge is generated with the negative pulse voltage Va (V) applied to the scan electrodes SCN1 to SCNn, the wall charges inside the discharge cell are erased. For a discharge cell in which abnormal wall charges are accumulated, the probability that the discharge voltage is discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm increases as the wall charge accumulation amount increases and the discharge delay decreases. Become.

  The discharge cells that have not been discharged with the positive voltage Vd (V) applied to the data electrodes D1 to Dm are discharged with the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. As described above, the discharge cell in which abnormal wall charges are accumulated has a positive voltage Vd (V) applied to the data electrodes D1 to Dm or a negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn. It is possible to eliminate the state in which the wall charges are abnormally accumulated by causing discharge at either voltage.

  The address period and the sustain period are the same as the address period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted.

  As described above, in the abnormal charge erasing portion in the selective initialization period, the period between the time when the positive voltage Vs (V) is applied to the scan electrodes SCN1 to SCNn and the time when the negative voltage Va (V) is applied. In addition, a positive voltage Vd (V) is applied to the data electrodes D1 to Dm. Thereby, the wall charge of the discharge cell in which the discharge start voltage is greatly reduced is adjusted, the wall charge is prevented from being erased by the abnormal wall charge erasing unit, and the normal writing operation can be performed.

  In this embodiment, an example in which the subfield for performing the selective initialization operation is two subfields is shown, but the present invention is not limited to this. For example, the selective initialization operation may be performed in a plurality of subfields, and the abnormal charge erasing unit may be provided in one or more selective initialization periods among the plurality of selective initialization periods.

  Next, an example of control of the data electrode driving circuit, the scan electrode driving circuit, and the sustain electrode driving circuit in the selective initialization period in this embodiment will be described with reference to the drawings. The data electrode drive circuit, scan electrode drive circuit, and sustain electrode drive circuit used in the third embodiment of the present invention are the same as those in the first embodiment.

  FIG. 12 is a timing chart for explaining an example of operations of the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 in the selective initialization period according to the third embodiment of the present invention. Since time t8 to t20 is the same as that of the first embodiment of the present invention, detailed description is omitted.

  That is, the data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit from time t8 to time t20 in the drive timing chart in the all-cell initialization period shown in FIG. 8 in the first embodiment of the present invention. The operation at 54 is the same as the operation at the data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54 in the selective initialization period in the present embodiment.

  Thus, in the present embodiment, the data electrode driving circuit has the circuit configuration shown in FIG. 5, the scan electrode driving circuit 53 has the circuit configuration shown in FIG. 6, and the sustain electrode driving circuit is shown in FIG. The data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 are driven at the timing shown in the timing chart of FIG. Thereby, it is possible to realize the drive waveforms applied to the data D1 to Dm electrodes, the scan electrodes 22 and the sustain electrodes 23 in the selective initialization period of the present embodiment. In particular, in the abnormal charge erasing portion in the selective initialization period, a positive pulse voltage is applied to the data electrode between a positive pulse voltage and a negative pulse voltage applied to the scan electrode. As a result, normal write discharge can be performed in the subsequent write period, and a high-quality image can be displayed.

(4) Fourth Embodiment A fourth embodiment of the present invention will be described. The configuration diagram of the plasma display device of the present embodiment is the same as that of the second embodiment. This embodiment is different from the second embodiment in that the abnormal charge erasing unit is provided in the selective initialization period instead of the all-cell initialization period. FIG. 6 is a drive waveform diagram applied to each electrode of the panel according to the third embodiment of the present invention, and shows drive waveforms in the all-cell initializing subfield and the selective initializing subfield. FIG. 6 shows, as an example, a drive waveform diagram including the first SF as an all-cell initialization subfield and the second SF as a selective initialization subfield.

  First, the drive waveform and operation of the all-cell initialization subfield will be described.

  Since the first half and the second half of the all-cell initialization period are the same as those in the first embodiment, detailed description thereof is omitted. When the discharge delay becomes large, such as when priming is insufficient, excessive positive wall charges are accumulated on scan electrodes SCN1 to SCNn in the first half and second half of the all-cell initialization period. Further, the writing period and the sustain period are the same as those in the first embodiment, and thus description thereof is omitted.

  Next, the drive waveform and operation of the selective initialization subfield will be described. The selective initialization period will be described as follows by dividing it into two periods, the first half (first period) and the abnormal charge erasing part (second period).

  In the first half of the initialization period, sustain electrodes SUS1 to SUSn are held at Ve1 (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are transferred from Vq (V) to Va (V ) Applying a downward ramp waveform voltage that gradually falls toward). Then, in the discharge cell in which the sustain discharge is performed in the sustain period of the previous subfield, a weak initializing discharge is generated, the wall voltage on scan electrode SCNi and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk is reduced. Is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells in which the address discharge and the sustain discharge were not performed in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  In the abnormal charge erasing unit in the initialization period, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, after applying positive voltage Vs (V) less than the discharge start voltage to scan electrodes SCN <b> 1 to SCNn for 5 to 20 μs, first positive voltage of 100 ns to 1 μs is applied to data electrodes D <b> 1 to Dm. Vd (V) is applied, and a second positive voltage Vd (V) of 100 ns to 1 μs is applied to the data electrodes D1 to Dm with an interval of 100 ns to 1 μs. At this time, the application time of the first positive voltage Vd (V) applied to the data electrodes D1 to Dm is shorter than the application time of the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. To do. Thereafter, negative voltage Va (V) is applied to scan electrodes SCN1 to SCNn for a short time of 5 μs or less. During this time, discharge does not occur in the discharge cells in which the discharge start voltage has not decreased among the discharge cells that have performed stable initialization discharge, and the wall voltage maintains the state in the latter half of the initialization period. However, in a discharge cell in which positive abnormal wall charges are accumulated on scan electrode SCNi and a discharge cell in which the discharge start voltage is lowered, when voltage Vs (V) is applied to scan electrodes SCN1 to SCNn, the discharge cell Since this voltage exceeds the discharge start voltage, a strong discharge occurs and the wall voltage on the scan electrode SCNi is inverted.

  A first positive voltage Vd (V) is applied to the data electrodes D1 to Dm in the discharge cell in which the discharge start voltage is greatly reduced. If the discharge delays of the red, green, and blue discharge cells are not significantly different, the red, green, and blue discharge cells are discharged at the first positive voltage Vd (V) applied to the data electrodes D1 to Dm. The wall charge can be adjusted so that the writing operation can be normally performed in the writing period. However, when the discharge delays of the red, green, and blue colors of the discharge cells are greatly different, the discharge cells having a large discharge delay do not discharge with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm. There is a case. For example, when the discharge delay of the green discharge cell is small and the discharge delay of the red and blue discharge cells is large, the application time of the first positive voltage Vd (V) applied to the data electrodes D1 to Dm is set to the discharge delay. It is determined according to the characteristics of the green discharge cell having a small size.

  In order to match the characteristics of the green discharge cell with a small discharge delay, the application time of the first positive voltage Vd (V) is set to be as short as about 150 ns. Blue and red discharge cells having a large discharge delay may not be discharged at the first positive voltage Vd (V) having a short application time. Therefore, the second positive voltage Vd (V) is then applied to the data electrodes D1 to Dm. The application time of the second positive voltage Vd (V) is determined in accordance with the characteristics of the red and blue discharge cells having a large discharge delay. Since the discharge delay is large, the blue and red discharge cells that have not been discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm having a short application time are applied to the data electrodes D1 to Dm. Discharge occurs at the second positive voltage Vd (V). The application time of the second positive voltage Vd (V) applied to the data electrodes D1 to Dm is about 400 ns.

  Since the green discharge cell having a small discharge delay is discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, the second positive voltage Vd ( V) does not discharge. In this way, the green discharge cell with a small discharge delay is discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm, and the data among the red and blue discharge cells with the large discharge delay is data. The discharge cells that have not been discharged with the first positive voltage Vd (V) applied to the electrodes D1 to Dm are discharged with the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. By these discharges, the wall charges in the discharge cells are adjusted so that the writing operation can be normally performed in the writing period.

  A discharge cell having a reduced discharge start voltage is either the first positive voltage Vd (V) applied to the data electrodes D1 to Dm or the second positive voltage Vd (V) applied to the data electrodes D1 to Dm. Is discharged at a negative voltage Va (V) applied to scan electrodes SCN1 to SCNn. Since the discharge cells having a reduced discharge start voltage are not discharged by the negative voltage Va (V) applied to the scan electrodes SCN1 to SCNn, the wall charges are prevented from being erased.

  The discharge cells in which abnormal wall charges are accumulated include a first positive voltage Vd (V) applied to the data electrodes D1 to Dm and a second positive voltage Vd (applied to the data electrodes D1 to Dm. V) and a negative voltage Va (V) applied to scan electrodes SCN1 to SCNn. When the discharge cell is discharged at the positive voltage Vd (V) applied to the data electrodes D1 to Dm or the second positive voltage Vd (V) applied to the data electrodes D1 to Dm, the discharge is caused by erasing discharge. Although it is in a state where it is forcibly terminated on the way, the state where the wall charges are abnormally accumulated is eliminated. In the discharge cell in which the erasing discharge is generated with the negative pulse voltage Va (V) applied to the scan electrodes SCN1 to SCNn, the wall charges inside the discharge cell are erased. For discharge cells in which abnormal wall charges are accumulated, discharge is performed at the first positive voltage Vd (V) applied to the data electrodes D1 to Dm as the amount of accumulated wall charges increases and the discharge delay decreases. Probability increases.

  The discharge cells that have not been discharged with the first positive voltage Vd (V) applied to the data electrodes D1 to Dm are the second positive voltage Vd (V) or scan electrode applied to the data electrodes D1 to Dm. It discharges with the negative voltage Va (V) applied to SCN1-SCNn. As described above, the discharge cell in which abnormal wall charges are accumulated has the first positive voltage Vd (V) applied to the data electrodes D1 to Dm and the second positive voltage applied to the data electrodes D1 to Dm. It is possible to eliminate the state in which wall charges are abnormally accumulated by causing discharge at any one of voltage Vd (V) and negative voltage Va (V) applied to scan electrodes SCN1 to SCNn.

  The address period and the sustain period are the same as the address period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted.

  As described above, in the abnormal charge erasing portion in the selective initialization period, the period between the time when the positive voltage Vs (V) is applied to the scan electrodes SCN1 to SCNn and the time when the negative voltage Va (V) is applied. In addition, the first positive voltage Vd (V) and the second positive voltage Vd (V) are applied to the data electrodes D1 to Dm. As a result, even when characteristics such as discharge delay of the red, green, and blue discharge cells are different, the wall charge of the discharge cell in which the discharge start voltage is greatly reduced is adjusted, and the wall charge is reduced at the abnormal wall charge erasing unit. Erasing can be prevented and normal writing operation can be performed.

  In this embodiment, an example in which the subfield for performing the selective initialization operation is two subfields is shown, but the present invention is not limited to this. For example, the selective initialization operation may be performed in a plurality of subfields, and the abnormal charge erasing unit may be provided in one or more selective initialization periods among the plurality of selective initialization periods.

  As described above, according to the panel driving method of the present embodiment, in the abnormal charge erasing portion in the initialization period, the wall charge of the discharge cell in which the discharge start voltage is greatly reduced is adjusted, thereby obtaining an image with good quality. It can be displayed.

  Next, an example of control of the data electrode driving circuit, the scan electrode driving circuit, and the sustain electrode driving circuit in the selective initialization period in this embodiment will be described with reference to the drawings. The data electrode drive circuit, scan electrode drive circuit, and sustain electrode drive circuit used in the present embodiment are the same as those in the first embodiment.

  FIG. 14 is a timing chart for explaining an example of operations of the data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 in the selective initialization period according to the fourth embodiment of the present invention. Further, since time t8 to t20 is the same as that of the second embodiment, detailed description thereof is omitted. That is, operations in data electrode drive circuit 52, scan electrode drive circuit 53, and sustain electrode drive circuit 54 from time t8 to time t20 in the drive timing chart of the all-cell initialization period shown in FIG. 10 in the second embodiment. However, the operations in the data electrode driving circuit 52, the scan electrode driving circuit 53, and the sustain electrode driving circuit 54 in the selective initialization period in the present embodiment are the same.

  Thus, in the present embodiment, the data electrode driving circuit has the circuit configuration shown in FIG. 5, the scan electrode driving circuit 53 has the circuit configuration shown in FIG. 6, and the sustain electrode driving circuit is shown in FIG. The data electrode drive circuit 52, the scan electrode drive circuit 53, and the sustain electrode drive circuit 54 are driven at the timing shown in the timing chart of FIG. Thereby, it is possible to realize the drive waveforms applied to the data D1 to Dm electrodes, the scan electrodes 22 and the sustain electrodes 23 in the selective initialization period of the present embodiment.

  The present invention makes it possible to display an image with a good quality by preventing wall charges from being erased by an abnormal wall charge erasing unit in an initialization period for a discharge cell having a greatly reduced discharge start voltage. It is useful as an image display device using a panel.

Claims (8)

A plasma display apparatus for driving a plasma display panel having a plurality of discharge cells at intersections of scan electrodes and sustain electrodes and a plurality of data electrodes by a subfield method in which one field period includes a plurality of subfields,
A scan electrode driving circuit for driving the scan electrode;
A sustain electrode driving circuit for driving the sustain electrode;
A data electrode driving circuit for driving the data electrode,
At least one subfield of the plurality of subfields includes an initialization period for adjusting wall charges of the plurality of discharge cells to a state in which address discharge is possible,
The scan electrode driving circuit applies an upward ramp waveform voltage to the scan electrode in a first period within the initialization period, and uses the scan electrode as an anode and the sustain electrode and the data electrode as a cathode. An initializing discharge is generated, and a downward ramp waveform voltage is applied to the scan electrode in a second period after the first period within the initialization period, so that the scan electrode serves as a cathode, and the sustain electrode and the data electrode A second initializing discharge with the anode as an anode is generated, and a positive rectangular waveform voltage and a negative rectangular waveform voltage are applied to the scan electrode in a third period after the second period within the initializing period. Applied,
The data electrode driving circuit applies a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the third period. Applying a plasma display device. 2. The plasma display device according to claim 1, wherein the data electrode driving circuit continuously applies two or more of the positive-polarity rectangular waveform voltages to the data electrode in the third period. The data electrode driving circuit continuously applies two or more positive-polarity rectangular waveform voltages to the data electrode in the third period,
2. The plasma display apparatus according to claim 1, wherein a voltage application time of the first rectangular waveform voltage applied to the data electrode is the shortest among a plurality of rectangular waveform voltage application periods applied to the data electrode. A plasma display apparatus for driving a plasma display panel having a plurality of discharge cells at intersections of scan electrodes and sustain electrodes and a plurality of data electrodes by a subfield method in which one field period includes a plurality of subfields,
A scan electrode driving circuit for driving the scan electrode;
A sustain electrode driving circuit for driving the sustain electrode;
A data electrode driving circuit for driving the data electrode,
At least one subfield of the plurality of subfields includes an initialization period for adjusting wall charges of the plurality of discharge cells to a state in which address discharge is possible,
The scan electrode drive circuit applies an initial ramp waveform voltage to the scan electrode in the first period of the initialization period, and performs an initializing discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. Applying a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrode in a second period after the first period of the initialization period,
The data electrode driving circuit applies a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the second period. Applying a plasma display device. A plasma display apparatus driving method for driving a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes and a plurality of data electrodes by a subfield method in which one field period includes a plurality of subfields. And
Driving the scan electrode;
Driving the sustain electrode;
Driving the data electrode,
At least one subfield of the plurality of subfields includes an initialization period for adjusting wall charges of the plurality of discharge cells to a state in which address discharge is possible,
Driving the scan electrode comprises:
Applying a rising ramp waveform voltage to the scan electrode in a first period within the initialization period to generate a first initialization discharge using the scan electrode as an anode and the sustain electrode and the data electrode as a cathode; When,
A second ramp waveform voltage is applied to the scan electrode in a second period after the first period within the initialization period, and the scan electrode serves as a cathode and the sustain electrode and the data electrode serve as an anode. Generating an initializing discharge; and
Applying a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrode in a third period after the second period within the initialization period,
Driving the data electrode comprises:
Applying a positive rectangular waveform voltage to the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the third period; Driving method of display device. 6. The method of driving a plasma display device according to claim 5, wherein the step of driving the data electrode includes a step of continuously applying two or more of the positive-polarity rectangular waveform voltages to the data electrode in the third period. The step of driving the data electrode includes the step of continuously applying two or more of the positive rectangular waveform voltages to the data electrode in the third period,
6. The plasma display apparatus according to claim 5, wherein a voltage application time of the first rectangular waveform voltage applied to the data electrode is the shortest of a plurality of rectangular waveform voltage application periods applied to the data electrode. Driving method. A plasma display apparatus driving method for driving a plasma display panel having a plurality of discharge cells at intersections of scan electrodes, sustain electrodes and a plurality of data electrodes by a subfield method in which one field period includes a plurality of subfields. And
Driving the scan electrode;
Driving the sustain electrode;
Driving the data electrode,
At least one subfield of the plurality of subfields includes an initialization period for adjusting wall charges of the plurality of discharge cells to a state in which address discharge is possible,
Driving the scan electrode comprises:
Applying a downward ramp waveform voltage to the scan electrode in the first period of the initialization period to generate an initialization discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode;
Applying a positive rectangular waveform voltage and a negative rectangular waveform voltage to the scan electrode in a second period after the first period of the initialization period,
The step of driving the data electrode includes a positive rectangular waveform on the data electrode between the positive rectangular waveform voltage and the negative rectangular waveform voltage applied to the scan electrode in the second period. A method for driving a plasma display device, comprising applying a voltage.

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