JP4889889B2 - Static random access memory with nonvolatile data retention function and operation method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a static random access memory (SRAM) with a nonvolatile data holding function, and in particular, an element for making a low-cost memory element non-volatile that operates at high speed and can be integrated on a large scale. The present invention relates to a static random access memory with a nonvolatile data holding function, which is characterized by its structure and operation method.
[0002]
[Prior art]
In recent years, with the widespread use of high-speed data communication, electronic devices and systems for performing data communication at high speed and with low power consumption are required to have lower prices, higher speed, and lower power consumption.
[0003]
One of the electronic devices used for such data communication is SRAM (Static Random Access Memory). Conventional SRAM elements are high-speed, low power consumption with power supply voltage applied as a single element. It can be operated with
[0004]
In particular, a pn-junction one-transistor SRAM capable of forming an SRAM with one transistor and reducing the chip area has been proposed as a low-cost, highly-integrated SRAM. Here, with reference to FIG. A pn junction 1-transistor SRAM will be described.
[0005]
FIG. 7A is a schematic cross-sectional view of one memory cell of a conventional pn junction 1-transistor SRAM, and an element surrounded by an element isolation oxide film 42 provided on a p-type silicon substrate 41. An n ⁺ type channel region 43 and an n ⁺ type source region 44 are provided in the formation region, and a p ⁺ type drain region 47 is provided so as to be in contact with the n ⁺ type channel region 43, and the n ⁺ type channel region 43 and the p ⁺ type are provided. A gate electrode 46 is provided through a gate oxide film 45 so as to cover the pn junction 48 formed in the drain region 47.
[0006]
In addition, after providing the W load resistance layer 50 via the first interlayer insulating film 49, the second interlayer insulating film 51 is provided, and the W load resistance layer is provided via the contact hole provided in the second interlayer insulating film 51. 50, a power supply electrode 52 connected to one end of the transistor 50, a drain electrode 53 connected to the other end of the W load resistance layer 50 and in contact with the p ⁺ type drain region 47, and a source electrode 54 in contact with the n ⁺ type source region 44 are provided. Is.
[0007]
FIG. 7B is an equivalent circuit of one memory cell of the conventional pn junction 1-transistor SRAM shown in FIG. 7A, and the power supply potential V _dd is applied to the power supply electrode 52. A source potential V _s (ground potential in the figure) is applied to the source electrode, and the drain potential V _d output to the drain electrode 53 is controlled by the gate potential V _g applied to the gate electrode 46. is there.
[0008]
Reference to FIG. 7C FIG. 7C is an I _d -V _d characteristic diagram of a pn junction 1-transistor SRAM. The gate potential V _g is applied to control the thickness of the depletion layer of the pn junction 48. Thereby, an N-shaped negative differential resistance characteristic is obtained.
[0009]
In this case, the intersection of the pn junction 48 negative differential resistance indicated by the solid line and the load resistance of the W load resistance layer 50 indicated by the broken line gives two stable states, and the negative differential resistance current is controlled by the gate potential V _g. Thus, the voltage in two states, that is, the high state H (V _H ) and the low state L (V _L ) can be controlled.
[0010]
By maintaining one of these two stable voltage states as long as there is no signal input, SRAM (Static Random Access Memory) characteristics can be obtained with only one pn junction with a gate electrode. It is what
[0011]
[Problems to be solved by the invention]
However, since such a pn junction one-transistor SRAM does not have a function of holding data in a nonvolatile manner, for example, in a system such as a personal computer, it always coexists with a nonvolatile memory, and data is read from the nonvolatile memory. Need to be stored.
[0012]
Therefore, when viewed as a whole system, there is a problem that power consumption due to wiring between memories and a loss of a manufacturing process are large, and it is difficult to reduce power consumption and cost.
[0013]
Accordingly, an object of the present invention is to realize further reduction in power consumption and price by providing a nonvolatile data holding function.
[0014]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
1A is a conceptual configuration diagram of one memory cell, FIG. 1B is an I _d -V _d characteristic diagram, and reference numerals 7 and 10 in the figure denote second gate insulating films, respectively. And an element isolation insulating film.
1A and 1B, in order to achieve the above-mentioned object, the present invention provides a one-conductivity type drain region 4 in one-conductivity type semiconductor substrate 1 in a static random access memory with a nonvolatile data holding function. The reverse conductivity type channel region 2 and the reverse conductivity type source region 3 are provided, and the floating and gate electrodes 8 are formed so as to cover the pn junction formed by the one conductivity type drain region 4 and the reverse conductivity type channel region 2. And a load resistor 9 is provided so as to be in electrical contact with the one conductivity type drain region 4 at one end.
The one-conductivity-type semiconductor substrate in the present invention includes not only a one-conductivity-type semiconductor substrate but also a one-conductivity-type well region provided on the reverse-conductivity-type semiconductor substrate.
[0015]
That is, according to the present invention, by adding the floating gate 6 to the pn junction one-transistor SRAM, a function capable of holding information in a nonvolatile manner is added to the SRAM without increasing the area of the element, and the function of the element is improved. As a result, the number of elements as a whole system for storing data can be reduced, power consumption due to wiring between memory cells and loss of manufacturing process can be reduced, and low power consumption and low price can be realized. .
[0016]
In this case, the power supply voltage V _dd is applied to the other end of the load resistor 9, and the drain electrode potential V _d is in the high state H and the low state L due to the negative differential resistance in a state where there is no reverse conductivity type carrier in the floating gate 6. The pn junction does not exhibit negative differential resistance when the floating gate 6 has a reverse conductivity type carrier, and the drain electrode potential V _d is a stable high state different from the high state H. It is necessary to adjust the thickness of the floating gate 6 and the thickness of the first gate insulating film 5 interposed between the floating gate 6 and the one-conductivity-type semiconductor substrate 1 so as to take H ′.
[0017]
When such a pn junction transistor SRAM is operated, the intersection of the negative differential resistance and the load resistance 9 corresponds to two stable operating points in the state where there is no reverse conductivity type carrier in the floating gate 6. The intermediate high state H is moved to the stable operating point H ′ in the state where the floating gate 6 has the reverse conductivity type carrier after the power supply is cut off, and the reverse conductivity type carrier is transferred to the floating gate 6 after the low state L is turned off. Move to a stable operating point in the absence.
[0018]
Further, when information is held in a nonvolatile manner, before the power supply voltage V _dd is cut off, the external sense amplifier circuit senses whether the state is the high state H or the low state L. In the high state H, the bias is applied between the gate electrode 8 and the reverse conductivity type source region 3 so as to inject a reverse conductivity type carrier into the floating gate 6, and the reverse conductivity type carrier is applied to the floating gate 6. And after moving to the stable operating point H ′, the power source may be cut off.
[0019]
Further, when returning from a state in which information is held in a non-volatile state, the power supply voltage V _dd is applied, the drain voltage V _d is once set to 0 V by an external circuit, then moved to a stable point, and the drain voltage V at the stable point is set. _{When d} is latched, a bias having a polarity that discharges the reverse conductivity type carrier between the gate electrode 8 and the reverse conductivity type source region 3 is applied, and the reverse conductivity type carrier is accumulated in the floating gate 6, After releasing the reverse conductivity type carrier, the latched drain voltage V _d may be applied and moved to a stable point.
[0020]
In this case, when the latched drain voltage V _d is in the low state L, that is, before the power supply voltage is applied, and the floating gate 6 has no reverse conductivity type carrier, the drain voltage V _d is in the low state L, before the power supply voltage is applied, When there is a reverse conductivity type carrier in the floating gate 6, the drain voltage V _d becomes the high state H, and the power supply voltage is turned off once in two states of the SRAM high state H and low state L, and is applied again. At this time, it is possible to return to the respective states and to add a function capable of holding information in a nonvolatile manner in the SRAM chip.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Here, the SRAM with nonvolatile data holding function according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 5. First, the manufacturing process will be described with reference to FIGS. .
2A. First, for example, after an element isolation oxide film 12 is selectively formed on a p-type silicon substrate 11 doped with B (boron) at 1 × 10 ¹⁶ cm ⁻³ , a resist pattern 13 is provided, Using this resist pattern 13 as a mask, As ions 14 are implanted into a region excluding the drain region of the activation region surrounded by the element isolation oxide film 12 so that the concentration becomes, for example, 1 × 10 ¹⁹ cm ⁻³ . An n ⁺ type region 15 to be an n ⁺ type channel region 16 and an n ⁺ type source region 17 is formed.
[0022]
2B, after the resist pattern 13 is removed, a first gate oxide film 18 having a thickness of, for example, 4 nm is formed on the exposed surface by dry oxidation, and then the thickness to become a floating gate is formed. For example, a 10 nm non-doped polycrystalline silicon layer 19 is deposited.
[0023]
Next, after the second gate oxide film 20 having a thickness of, for example, 4 nm is formed on the surface of the non-doped polycrystalline silicon layer 19 by dry oxidation, the non-doped film having a thickness of, for example, 300 nm is formed. A polycrystalline silicon layer 21 is deposited.
[0024]
Next, referring to FIG. 3C, a resist pattern 22 having a width of, for example, 300 nm is provided, and etching is performed using the resist pattern 22 as a mask, whereby gate electrode 24 / second gate oxide film 20 / floating 23 / first. A gate structure made of the gate oxide film 18 is formed.
[0025]
Next, after removing the resist pattern 22, a resist pattern 25 is newly formed to cover the n ⁺ -type source region 17. Using this resist pattern 25 as a mask, the concentration of B ions 26 is, for example, By implanting to 1 × 10 ¹⁹ cm ⁻³ , a p ⁺ type drain region 27 is formed, a pn junction 28 is formed between the n ⁺ type channel region, and the gate electrode 24 is converted to p type. To do.
The floating gate 23 remains undoped.
[0026]
Next, referring to FIG. 4E, after removing the resist pattern 25, a first interlayer insulating film 29 made of an SiO ₂ film is formed by using a thermal CVD method, and then a W film is deposited on the entire surface, and then a predetermined film is formed. The W load resistance layer 30 is formed by patterning so as to obtain a resistance value of.
[0027]
Next, after forming a second interlayer insulating film 31 made of a BPSG film on the entire surface, contact holes are formed at predetermined positions, and then an Al film having a thickness of, for example, 300 nm is formed on the entire surface. , A power supply electrode 32 connected to one end of the W load resistance layer 30, a drain electrode 33 connected to the other end of the W load resistance layer 30 and the p ⁺ type drain region 27, and an n ⁺ type source region 17. By forming the source electrode 34 connected to, the basic configuration of the SRAM with a nonvolatile data holding function is completed.
[0028]
Note that the thickness of the first gate oxide film 18 and the floating gate 23 in this SRAM with a nonvolatile data holding function is such that the pn junction 28 does not exhibit a negative differential resistance when the floating gate 23 has electrons and the drain potential V _It is necessary to adjust so that _d takes the state of a stable point H ′ shown in FIG.
[0029]
Next, the operation of the SRAM with a nonvolatile data holding function will be described with reference to FIG.
Reference to FIG. 5A FIG. 5A is an equivalent circuit diagram of the SRAM with the nonvolatile data holding function according to the first embodiment of the present invention. not been implanted, with the source electrode 34 is the ground potential V _s, the power supply voltage V _dd is applied to the power supply electrode 32, depletion of the pn junction 28 by a positive gate potential V _g applied to the gate electrode 24 The thickness of the layer is controlled so that an N-shaped negative differential resistance appears.
When the gate potential V _g is 0 or negative, an N-shaped negative differential resistance does not appear in the pn junction 28, and the diode characteristics are distorted.
[0030]
See FIG. 5C. In this case, in the same manner as in the conventional pn junction 1-transistor SRAM, the negative differential resistance of (1) due to the pn junction 28 indicated by the solid line and the load resistance due to the W load resistance layer 30 indicated by the broken line The two intersections correspond to two stable operating points L and H, and by making these operating points L and H correspond to “0” and “1”, respectively, SRAM operation becomes possible.
[0031]
Next, a method for holding information in a nonvolatile manner will be described.
First, before cutting the power supply voltage V _dd , the external sense amplifier circuit senses whether the drain potential V _d of each memory cell is in a high (H) or low (L) state, and low In the memory cell in this state, the power is turned off as it is.
[0032]
5B and 5C, on the other hand, in the memory cell in which the drain potential V _d is High, a positive bias is applied between the gate electrode 24 and the source electrode 34, and electrons are supplied to the floating gate 23. Then, after moving to a stable point H ′, which is an intersection point with the diode characteristic indicated by (2) indicated by a thin solid line in FIG. 5C and the load resistance by the W load resistance layer 30 indicated by a broken line, the power is turned off. .
[0033]
Next, a method for restoring stored data when the power is turned off and then turned on again will be described.
First, when the power supply voltage V _dd is applied again, the drain potential V _d is once set to 0 V by an external circuit, then moved to a stable point, the potential V _d (L or H ′) is latched, and the gate electrode 24 and A negative bias is applied between the source electrode 34 and the source electrode 34.
[0034]
At the time when the power supply is cut off, in the memory cell whose drain potential V _d is L, since electrons are not injected into the floating gate 23, a differential negative resistance appears and the drain potential V _d returns to L again.
[0035]
On the other hand, in the memory cell whose drain potential _Vd is H when the power supply is cut off, electrons are accumulated in the floating gate 23. Therefore, the electrons are emitted by the applied negative bias, and the electrons are emitted and then latched. The applied potential H ′ is applied to move to the stable point H due to the negative differential resistance.
[0036]
As described above, in the first embodiment of the present invention, when the power supply voltage is turned off once and the power supply voltage is turned off once again only by providing the floating gate, the state is restored to the respective state. And a function capable of holding information in a nonvolatile manner in the SRAM chip can be added.
[0037]
Therefore, since the memory cell area is exactly the same as that of a conventional pn junction 1-transistor SRAM, the integration degree of the SRAM itself does not decrease, and it is necessary to use a nonvolatile memory in addition to the SRAM in the entire system such as a personal computer. Therefore, it is possible to reduce power consumption and manufacturing process loss due to wiring between memories, thereby reducing power consumption and price.
[0038]
Although it takes about 10 ⁻⁶ seconds to inject or withdraw electrons from the floating gate 23 when the power is turned off and on, the SRAM operation can be performed at the same high speed as other SRAMs.
[0039]
Next, with reference to FIG. 6, the manufacturing process of the SRAM with a nonvolatile data holding function according to the second embodiment of the present invention will be described.
6A First, after forming the gate structure by the steps of FIGS. 2A to 3C exactly as in the first embodiment of the present invention, the gate structure and the drain are formed. A new resist pattern 35 is provided so as to cover the formation region, and then As ions 36 are implanted at a relatively high energy, for example, at a concentration of 1 × 10 ¹⁹ cm ^{−3 using} the resist pattern 35 as a mask. forming a deep n ⁺ -type source region 37 from the n ⁺ type channel region 16 by.
[0040]
Thereafter, the non-volatile data holding function having substantially the same configuration as that of the first embodiment except for the shape of the n ⁺ type source region 37 is performed again through the steps of FIGS. 3D to 4F. The basic structure of the attached SRAM is completed.
[0041]
In the second embodiment, since the n ⁺ type source region 37 is formed deeply, no short circuit due to Al penetration occurs when the source electrode 34 is formed.
In this case, since the drain region is p-type having the same conductivity type as the p-type silicon substrate, it is not necessary to form it deeply.
[0042]
While the embodiments of the present invention have been described above, the present invention is not limited to the numerical values, conditions, and the like described in the embodiments, and various modifications can be made.
For example, in each of the above embodiments, a floating gate is provided in order to hold information when power is turned off in a nonvolatile manner. However, as in other conventional nonvolatile memories, the non-doped polycrystalline silicon layer Instead, an SiN film may be used to trap electrons using the interface state at the SiO ₂ / SiN interface.
[0043]
In each of the above embodiments, the W load resistance layer is used as the load resistance. However, a load resistance using other metal or polycrystalline silicon may be used. Furthermore, the load resistance layer may be formed on the surface of the semiconductor substrate. A diffused resistor may be used as a load resistor.
[0044]
Further, in each of the above embodiments, the carriers traveling in the channel region are electrons, but are not limited to electrons, and may be holes. In that case, the conductivity type of each region And all the polarities of the applied biases may be reversed.
[0045]
【Effect of the invention】
According to the present invention, since the floating gate is provided in the pn junction 1-transistor SRAM, a nonvolatile data holding function can be added without increasing the area, thereby simplifying the entire system such as a personal computer, A major contribution to lower power consumption and cost.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of the manufacturing process up to the middle of the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of the manufacturing process until the middle of FIG. 2 and subsequent steps of the first embodiment of the present invention.
FIG. 4 is an explanatory diagram of the manufacturing process after FIG. 3 according to the first embodiment of the present invention.
FIG. 5 is an explanatory diagram of the operation of the SRAM according to the first embodiment of this invention;
FIG. 6 is an explanatory diagram of a manufacturing process according to the second embodiment of this invention.
FIG. 7 is an explanatory diagram of a conventional pn junction 1-transistor SRAM.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1 conductivity type semiconductor substrate 2 Reverse conductivity type channel region 3 Reverse conductivity type source region 4 1 conductivity type drain region 5 1st gate insulating film 6 Floating gate 7 2nd gate insulating film 8 Gate electrode 9 Load resistance 10 Element isolation insulating film 11 p-type silicon substrate 12 element isolation oxide film 13 resist pattern 14 As ion 15 n ⁺ type region 16 n ⁺ type channel region 17 n ⁺ type source region 18 first gate oxide film 19 non-doped polycrystalline silicon layer 20 second Gate oxide film 21 Non-doped polycrystalline silicon layer 22 Resist pattern 23 Floating gate 24 Gate electrode 25 Resist pattern 26 B ion 27 p ⁺ type drain region 28 pn junction 29 First interlayer insulating film 30 W load resistance layer 31 Second interlayer Insulating film 32 Power supply electrode 33 Drain electrode 34 Source electrode 35 Turn 36 As ion 37 n ⁺ type source region 41 p type silicon substrate 42 element isolation oxide film 43 n ⁺ type channel region 44 n ⁺ type source region 45 gate oxide film 46 gate electrode 47 p ⁺ type drain region 48 pn junction 49 1 interlayer insulating film 50 W load resistance layer 51 second interlayer insulating film 52 power supply electrode 53 drain electrode 54 source electrode

Claims (5)

  A one conductivity type semiconductor substrate is provided with a one conductivity type drain region, a reverse conductivity type channel region, and a reverse conductivity type source region, and covers a pn junction formed by the one conductivity type drain region and the reverse conductivity type channel region. A static random access memory with a nonvolatile data retention function, wherein a floating resistor and a gate electrode are provided, and a load resistor is provided so as to be in electrical contact with the one conductivity type drain region at one end.   A power supply voltage is applied to the other end of the load resistor, and the drain electrode potential takes two states, a high state H and a low state L due to negative differential resistance, in the absence of reverse conductivity type carriers in the floating gate. In the state where the reverse conductivity type carrier exists in the floating gate, the pn junction does not exhibit a negative differential resistance, and the floating gate has a stable high state H ′ different from the high state H. And a film thickness of a first gate insulating film interposed between the floating gate and the one-conductivity-type semiconductor substrate is adjusted. Random access memory. 3. An operation method of a static random access memory with a nonvolatile data holding function according to claim 1 or 2, wherein the negative differential resistance and the load resistance are crossed in a state where there is no reverse conductivity type carrier in the floating gate. there corresponding to two stable operating point moves to the stable operating point H 'in a state where there is opposite conductivity type carriers into the floating gate of the high state H before powering down therein, the low state L A method of operating a static random access memory with a nonvolatile data holding function, characterized in that the power is turned off as it is.   Before the power supply voltage is cut off, an external sense amplifier circuit senses whether the state is a high state H or a low state L. In the low state L, the power is turned off as it is, and in the high state H, it is opposite to the gate electrode. A bias having a polarity for injecting a reverse conductivity type carrier into the floating gate is applied between the conductive type source regions to inject the reverse conductivity type carrier into the floating gate and moved to the stable operating point H ′. 4. The method of operating a static random access memory with a nonvolatile data holding function according to claim 3, wherein the information is held in a nonvolatile manner by cutting the information. Apply a power supply voltage to the static random access memory with nonvolatile data retention function in the state where information is retained, set the drain voltage _Vd to 0V by an external circuit, move it to the stable point, and then drain the drain voltage at the stable point. It latches V _d, a bias of polarity that releases opposite conductivity type carrier between said gate electrode and opposite conductivity type source region, when the opposite conductivity type carriers into the floating gate are accumulated, reverse-conducting 4. The static random access function with a nonvolatile data holding function according to claim 3, wherein after the type carrier is discharged, the latched drain voltage _Vd is applied and moved to a stable point to restore the memory information. How the memory works.

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