JP4882340B2 - Electro-optical device and electronic apparatus including the same - Google Patents

Description

The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

This type of electro-optical device is generally driven based on an image signal that has undergone serial-parallel conversion (also referred to as “serial-parallel expansion” or “phase expansion”). For example, in a liquid crystal device, a plurality of data lines wired to an image display area on a substrate are divided into blocks every predetermined number, and serial-parallel converted image signals are included in the block in block units. The data line is supplied via a sampling switch. Thus, a predetermined number of data lines are simultaneously driven and a plurality of data lines are sequentially driven every predetermined number. In this case, the plurality of image signal lines are generally wired so as to run in parallel on the substrate and avoid the data line driving circuit from the plurality of external circuit connection terminals to the sampling circuit including the sampling switch. It is. For example, as disclosed in Patent Document 1 by the applicant of the present application, the plurality of image signal lines are each composed of the same film as any of the films constituting the data line driving circuit and are viewed in plan on the substrate. The data line driving circuit is wired so as not to overlap with each other.

JP-A-11-95257

However, as described above, when a plurality of image signal lines are wired so as to run in parallel on the substrate and avoid the data line driving circuit, a relatively large difference occurs in the wiring length between the plurality of image signal lines. End up. For this reason, variation in wiring resistance or electric capacity between a plurality of image signal lines becomes large, and vertical band unevenness corresponding to each image signal line in image display, in other words, a block driven simultaneously by parallel image signals. There is a technical problem that unevenness of units occurs.

  The present invention has been made in view of, for example, the above-described problems, and includes an electro-optical device that reduces vertical band-shaped display unevenness caused by wiring resistance or electric capacitance between a plurality of image signal lines, and the electro-optical device. It is an object to provide an electronic device.

Electro-optical device of the present invention, in order to solve the above problems, a substrate, a multiple data lines wired in picture element region, and the terminal is connected to the terminals, an image signal to which image signals are supplied a line, a data line drive circuit for generating a sampling signal, is connected between the image signal lines and the plurality of data lines, provided with a sampling circuit controlled in response to the sampling signal The image signal line connects the first portion disposed between the data line driving circuit and the sampling circuit, the terminal and the first portion, and overlaps the data line driving circuit. Has two parts.

  According to the electro-optical device of the present invention, at the time of driving, the image signal is supplied to the image signal line through, for example, the external circuit connection terminal, and further, for example, a plurality of sampling switches arranged corresponding to the data line Is supplied to a sampling circuit including The image signal is a serial-parallel converted N (where N is a natural number greater than or equal to 2) series image signal, and the image signal line is supplied with N number of N series image signals. It may be an image signal line. For example, for an N-sequence image signal, a serial image signal is converted into 3-phase, 6-phase, 12-phase, 24-phase,... By an external circuit in order to realize high-definition image display while suppressing an increase in drive frequency. , Etc., may be generated by being converted into a plurality of parallel image signals (that is, a plurality of parallel image signals).

  In parallel with the supply of the image signal, the sampling signal is sequentially supplied to the sampling switch corresponding to the data line, for example, by the data line driving circuit. Then, the image signal is sequentially supplied to the plurality of data lines for each data line by the sampling circuit in accordance with the sampling signal. Therefore, the plurality of data lines are sequentially driven. Note that the sampling switch is composed of, for example, a single-channel TFT, and the source is electrically connected to the image signal line, the drain is connected to the data line, and the sampling signal is supplied to the gate to turn it on. It is said.

  When the data line is driven in this manner, in each pixel unit, for example, the data line is connected via a pixel switching element that performs a switching operation in accordance with a scanning signal supplied from the scanning line driving circuit via the scanning line. Thus, an image signal is supplied to the display element. Thus, for example, a liquid crystal element as a display element performs image display in a pixel area or a pixel array area (or also referred to as “image display area”) based on the supplied image signal.

  Here, in particular, the data line driving circuit is typically arranged along one side on the substrate in a peripheral region located around the pixel region. On the other hand, the image signal line typically has a plurality of data from an external circuit connection terminal arranged in a region close to the edge of the substrate (for example, the one side) in the peripheral region for electrical connection with an external circuit. A plurality of sampling switches corresponding to the lines are wired. In other words, the external circuit connection terminal is typically located on the opposite side of the pixel area with respect to the data line driving circuit as viewed in plan on the substrate. Therefore, if no countermeasures are taken, the image signal lines are wired so as to avoid the data line driving circuit in a plan view on the substrate, that is, to bypass the periphery of the data line driving circuit. The wiring length of the image signal lines must be relatively long. Accordingly, the wiring resistance or electric capacity of the image signal line is increased. Alternatively, when the image signal lines are N image signal lines for supplying, for example, N (where N is a natural number greater than or equal to 2) series image signals, the difference between the outer circuit and the inner circuit causes N lines The difference in the wiring length between the image signal lines must be relatively large. Therefore, due to the difference in wiring resistance or capacitance between the N image signal lines, uneven vertical stripes in image display, in other words, uneven block units driven simultaneously by parallel image signals are generated.

  However, in the present invention, in particular, the image signal line has a first portion overlapping with the data line driving circuit. That is, the image signal line is formed of a conductive film located in a different layer via an interlayer insulating film with respect to the conductive film constituting the data line driving circuit, for example, when viewed in plan on the substrate, The data line driving circuit partially overlaps with each other. Therefore, the wiring length of the image signal line can be shortened as compared with the case where the above-described image signal line is wired so as to avoid the data line driving circuit when viewed in plan on the substrate. Alternatively, when the image signal lines are, for example, N image signal lines for supplying N-series image signals, the difference in wiring length between the N image signal lines is almost completely or in a practical sense. Can be eliminated. That is, when viewed in plan on the substrate, the image signal lines are arranged from the edge side of the data line driving circuit on the substrate (ie, the side close to the external circuit connection terminal) to the center side (ie, the side close to the pixel portion). If the data line driving circuit is configured so as to pass over or under the data line driving circuit or in the data line driving circuit, the image signal line of the image signal line is equivalent to the first line overlapping the data line driving circuit when viewed in plan on the substrate. The wiring length can be shortened and the degree of freedom of wiring is high. Alternatively, when the image signal lines are, for example, N image signal lines for supplying N-series image signals, the difference in wiring length between the N image signal lines is almost completely or in a practical sense. Can be eliminated. Therefore, it is possible to eliminate vertical band-like display unevenness caused by a difference in wiring resistance or capacitance between the N image signal lines almost or completely in a practical sense.

  Furthermore, since the first portion overlaps the data line driving circuit when viewed in plan on the substrate, the image signal lines are wired so as to avoid the data line driving circuit when viewed in plan on the substrate. As compared with the case where the image signal lines are provided, the area on the substrate necessary for wiring the image signal lines can be reduced. Therefore, the electro-optical device can be reduced in size by reducing the size of the substrate, or the electro-optical device can be improved in performance by effectively using the area on the substrate and arranging other wirings or circuits, for example. It becomes possible.

In one aspect of the electro-optical device of the present invention, the second portion, the second conductive located in different layers via an interlayer insulating film on the first conductive film that make up the data line driving circuit Formed from a film.

  According to this aspect, the image signal line and the data line driving circuit are connected without electrically connecting the image signal line and the plurality of first conductive films constituting the data line driving circuit, that is, while being insulated from each other. They can be partially overlapped with each other when viewed in plan on the substrate. Therefore, the wiring length of the image signal line can be shortened and the degree of freedom of wiring is high.

In another aspect of the electro-optical device of the present invention, the image signal lines, the plurality of data lines, N (where, N is the natural number of 2 or more) data line group of the book data line and 1 group to drive each of N series serial - includes an image signal line of the N the parallel converted image signal is supplied through the terminal,
The data line driving circuit is disposed along one side of the substrate in a peripheral region located around the pixel region,
Before SL pin, said the peripheral along said one side in the region and the pixel region to the data line driving circuit are arranged on the opposite side, the image signal lines of the N present, the in the peripheral region a first portion that is wired between said sampling circuit extending Mashimashi and the data line driving circuit in the direction of one side have respectively the second portion, from said terminal to said first portion, said side Wired in the intersecting direction.

  According to this aspect, at the time of driving, N-series image signals subjected to serial-parallel conversion are supplied to the N image signal lines via the external circuit connection terminals, and further include, for example, a plurality of sampling switches. Supplied to the sampling circuit. In parallel with the supply of the image signal, the data line driving circuit sequentially supplies the sampling signal for each sampling switch corresponding to the data line group. Then, the N-series image signals are sequentially supplied to the plurality of data lines for each data line group according to the sampling signal by the sampling circuit. Therefore, data lines belonging to the same data line group are driven simultaneously. In other words, the plurality of data lines are divided into blocks every predetermined number, and are driven simultaneously in units of blocks. In this aspect, in particular, the first portion is wired from the external circuit connection terminals arranged along one side of the substrate in a direction intersecting with one side so as to overlap with the data line driving circuit when viewed in plan on the substrate. Then, the wiring is extended to the second portion extending in the direction of one side (in other words, along the data line driving circuit). Therefore, compared with the case where N image signal lines are wired so as to avoid the data line driving circuit when viewed in plan on the substrate, the difference in wiring length between the N image signal lines is reduced. It can be made more effective by forming the first part that it is completely or practically eliminated. The first portion and the second portion may be integrally formed from the same conductive film, or may be formed from different conductive films and electrically connected via, for example, a contact hole opened in the interlayer insulating film. May be connected.

In another aspect of the electro-optical device according to the aspect of the invention, in the pixel region, a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked on the substrate on the upper layer side of the plurality of data lines. The first conductive film is made of the same film as any one of the plurality of data lines or the lower layer electrode, and the second conductive film is made of the same film as the upper electrode.

  According to this aspect, the plurality of wirings constituting the data line driving circuit are made of the same film as at least one of the first and second conductive films constituting the data line and the lower electrode, respectively. The portion is made of the same film as the third conductive film constituting the upper electrode. That is, the first conductive film constituting the data line driving circuit is the same film as at least one of the first and second conductive films, and the second conductive film constituting the first portion is the third conductive film. Is the same film. Here, the “same film” means films formed on the same occasion in the manufacturing process and are the same type of film. Note that the phrase “same film” does not mean that the film is continuous as a single film, but basically a film part of the same film that is separated from each other is sufficient. It is. Therefore, the plurality of wirings constituting the data line driving circuit can be formed at the same opportunity as the formation of at least one of the data line and the lower electrode, and the first portion has the same opportunity as the formation of the upper electrode. Can be formed. That is, without complicating the manufacturing process, the plurality of wirings constituting the data line driving circuit can be formed from at least one of the first and second conductive films, and the first portion can be formed from the third conductive film. Therefore, the first portion can be reliably formed so as to overlap with the data line driving circuit when viewed in plan on the substrate.

  Note that the storage capacitor improves, for example, the potential holding characteristic of the pixel electrode constituting the pixel portion, and the display can have high contrast.

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and a Conduction Electron-Emitter Display), an electrophoretic device, and a device using the electron emission device, DLP (Digital Light Processing) and the like can also be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

(First embodiment)
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  Particularly in the present embodiment, the routing wiring 90 includes an image signal line having a first portion and a second portion described later. That is, the lead wiring 90 includes an image signal line that vertically traverses the data line driving circuit 101 in FIG. 1, which will be described in detail later.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring such as a pixel switching TFT (Thin Film Transistor) as a driving element, a scanning line, and a data line is formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO (Indium Tin Oxide) is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, the overall configuration of the liquid crystal device will be described with reference to FIG. FIG. 3 is a block diagram showing the overall configuration of the liquid crystal device.

  As shown in FIG. 3, the liquid crystal device includes a liquid crystal panel 100 and an image signal supply circuit 720, a timing control circuit 730, and a power supply circuit 710 provided as external circuits.

  The timing control circuit 730 is configured to output various timing signals used in each unit. A timing signal output means that is a part of the timing control circuit 730 generates a dot clock that is a minimum unit clock and scans each pixel. Based on the dot clock, a Y clock signal CLY and an inverted Y clock signal are generated. CLYinv, X clock signal CLX, inverted X clock signal XCLinv, Y start pulse DY and X start pulse DX are generated.

  One line of input image data VID is input to the image signal supply circuit 720 from the outside. The image signal supply circuit 720 performs serial-parallel conversion on one system of input image data VID, and N-phase (where N is a natural number of 2 or more), in this embodiment, 6-phase (N = 6) image signal VID1. ~ VID6 is generated. Further, in the image signal supply circuit 720, the voltages of the image signals VID1 to VID6 are inverted to a positive polarity and a negative polarity with respect to a predetermined reference potential, and the image signals VID1 to VID6 thus inverted in polarity are output. You may be made to do.

  Further, the power supply circuit 710 supplies a common power supply having a predetermined common potential LCC to the counter electrode 21 shown in FIG. In the present embodiment, the counter electrode 21 is formed on the lower side of the counter substrate 20 shown in FIG. 2 so as to face the plurality of pixel electrodes 9a.

  Next, the electrical configuration of the liquid crystal panel will be described with reference to FIG. FIG. 4 is a block diagram showing the electrical configuration of the liquid crystal panel.

  As shown in FIG. 4, the liquid crystal panel 100 is provided with an internal drive circuit including a scanning line drive circuit 104, a data line drive circuit 101, and a sampling circuit 7 in the peripheral region of the TFT array substrate 10.

  The scanning line driving circuit 104 is supplied with a Y clock signal CLY, an inverted Y clock signal CLYinv, and a Y start pulse DY. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially generates and outputs the scanning signals G1,..., Gm at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv.

  The data line driving circuit 101 is supplied with an X clock signal CLX, an inverted X clock signal CLXinv, and an X start pulse DX. When the X start pulse DX is input, the data line driving circuit 101 sequentially generates and outputs sampling signals S1,..., Sn at a timing based on the X clock signal CLX and the inverted X clock signal XCLXinv.

  The sampling circuit 7 includes a plurality of sampling switches 7 s formed of P-channel or N-channel single-channel TFTs or complementary TFTs.

  The liquid crystal panel 100 further includes data lines 6a and scanning lines 11a wired vertically and horizontally in the image display area 10a occupying the center of the TFT array substrate, and each pixel unit 700 corresponding to the intersection is arranged in a matrix. The pixel electrode 9a of the arranged liquid crystal element 118 and the TFT 30 for controlling the switching of the pixel electrode 9a are provided. In the present embodiment, the total number of scanning lines 11a is assumed to be m (where m is a natural number of 2 or more), and the total number of data lines 6a is assumed to be n (where n is a natural number of 2 or more). To do.

  The image signals VID1 to VID6 that are serial-parallel-developed in six phases are supplied to the liquid crystal panel 100 via N image signals 170 in this embodiment. The n data lines 6a are sequentially driven for each data line group including six data lines 6a corresponding to the number of image signal lines 170 as a group, as will be described below.

  A sampling signal Si (i = 1, 2,..., N) is sequentially supplied from the data line driving circuit 101 to each sampling switch 7s corresponding to the data line group, and each sampling switch 7s corresponds to the sampling signal Si. Turns on. As will be described later, each sampling switch 7s is connected to the image signal line 170 via a branch wiring. The detailed configuration of this branch wiring will be described later.

  Therefore, the image signals VID1 to VID6 are supplied from the six image signal lines 170 simultaneously to the data lines 6a belonging to the data line group and sequentially for each data line group through the sampling switch 7s that is turned on. . Therefore, the data lines 6a belonging to the data line group are driven simultaneously. Therefore, in this embodiment, since the n data lines 6a are driven for each data line group, the driving frequency can be suppressed.

  In FIG. 4, when attention is paid to the configuration of one pixel portion 700, the data line 6a to which the image signal VIDk (where k = 1, 2, 3,..., 6) is supplied to the source electrode of the TFT 30. Is electrically connected to the gate electrode of the TFT 30, and a scanning line 11a to which a scanning signal Yj (j = 1, 2, 3,..., M) is supplied is electrically connected. In addition, the pixel electrode 9 a of the liquid crystal element 118 is connected to the drain electrode of the TFT 30. Here, in each pixel portion 700, the liquid crystal element 118 has a liquid crystal sandwiched between the pixel electrode 9 a and the counter electrode 21. Accordingly, each pixel unit 700 is arranged in a matrix corresponding to each intersection of the scanning line 11a and the data line 6a.

  Each scanning line 11a is selected line-sequentially by scanning signals G1,..., Gm output from the scanning line driving circuit 104. In the pixel portion 700 corresponding to the selected scanning line 11a, when the scanning signal Yj is supplied to the TFT 30, the TFT 30 is turned on and the pixel portion 700 is in the selected state. An image signal VIDk is supplied to the pixel electrode 9a of the liquid crystal element 118 at a predetermined timing from the data line 6a by closing the switch of the TFT 30 for a certain period. As a result, an applied voltage defined by the potentials of the pixel electrode 9 a and the counter electrode 21 is applied to the liquid crystal element 118. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signals VID1 to VID6 is emitted from the liquid crystal panel 100 as a whole.

  Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal element 118. One electrode of the storage capacitor 70 is connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is connected to the capacitor wiring 400 with a fixed potential so as to have a constant potential.

  Next, a main configuration relating to driving of the data line will be described with reference to FIG. FIG. 5 is a circuit diagram showing a circuit configuration relating to driving of the data lines.

  In the following, regarding the main configuration related to driving of the data lines 6a, the n data lines 6a are sequentially driven for each data line group in one direction or one of the two directions along the arrangement direction. In this case, the three driving signals are driven based on the three sampling signals Si-1, Si, Si + 1 output from the data line driving circuit 101 to the (i-1) th, ith, and (i + 1) th. Of the data line groups, the description will be given with particular attention to the configuration of the i-th data line group driven based on the i-th sampling signal Si. The configuration relating to the i-th data line group described below is the same for the (i−1) -th data line group and the (i + 1) -th data line group.

  In FIG. 5, six branch lines E1 to E6 of the branch lines 175 are arranged corresponding to the arrangement of the data lines 6ae (that is, the data lines 6ae-1 to 6ae-6) belonging to the i-th data line group. ing. The six image signal lines 170-1 to 170-6 are arranged along a direction intersecting the arrangement direction of the data lines 6ae. One end of each of the six branch wirings E1 to E6 is electrically connected to a corresponding one of the six image signal lines 170-1 to 170-6, and the six branch wirings. The other ends of E1 to E6 are electrically connected to the data line 6ae via the sampling switch 7s. The TFT 7s constituting each sampling switch has a source connected to the branch wiring Ek and a drain electrically connected to the data line 6ae. The gate of each TFT 7s is electrically connected to the data line driving circuit 101 via the control wirings X1 to X6. The i-th sampling signal Si is supplied from the data line driving circuit 101 to the control wirings X1 to X6.

  On the TFT array substrate 10, the six image signal lines 170-1 to 170-6 are formed of the same film as the data line 6 ae or the electrodes constituting the storage capacitor 70, for example, as will be described in detail later. The control wirings X1 to X6 are wired in the direction intersecting with the image signal lines 170-1 to 170-6 and extending in the data line 6ae, and are formed of, for example, a polysilicon film. Each branch wiring E1 to E6 is wired in a direction in which the data line 6ae extends from one end side electrically connected to the corresponding image signal line 170-k. A part of each of the branch lines E1 to E6 forms a source electrode of the sampling switch 7s, and a part of each of the data lines 6ae belonging to the i-th data line group forms a drain electrode of the sampling switch 7s. A part of the wires X1 to X6 forms a gate electrode of the sampling switch 7s.

  Next, a specific configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 6 and 7 are plan views showing a partial configuration related to the pixel portion on the TFT array substrate, which respectively correspond to a lower layer portion (FIG. 6) and an upper layer portion (FIG. 7) in a laminated structure to be described later. To do. FIG. 8 is a cross-sectional view taken along line AA ′ when FIGS. 6 and 7 are overlapped. In FIG. 8, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.

  6 to 8, each circuit element of the pixel unit 700 described above with reference to FIG. 4 is structured on the TFT array substrate 10 as a patterned conductive film. The TFT array substrate 10 includes, for example, a glass substrate, a quartz substrate, an SOI substrate, a semiconductor substrate, and the like, and is disposed to face the counter substrate 20 made of, for example, a glass substrate or a quartz substrate. Each circuit element includes, in order from the bottom, the first layer including the scanning line 11a, the second layer including the TFT 30 and the like, the third layer including the data line 6a and the like, the fourth layer including the storage capacitor 70 and the like, and the pixel electrode It consists of the 5th layer containing 9a etc. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, the second interlayer insulating film 42 is provided between the third layer and the fourth layer, and the fourth layer. A third interlayer insulating film 43 is provided between the layer and the fifth layer, respectively, to prevent a short circuit between the aforementioned elements. Of these, the first to third layers are shown in FIG. 6 as lower layer portions, and the fourth to fifth layers are shown in FIG. 7 as upper layer portions.

(Structure of the first layer-scanning lines, etc.)
The first layer is composed of scanning lines 11a. The scanning line 11a is patterned into a shape including a main line portion extending along the X direction in FIG. 6 and a protruding portion extending in the Y direction in FIG. 6 where the data line 6a extends. Such a scanning line 11a is made of, for example, conductive polysilicon, and among other high melting point metals such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), and molybdenum (Mo). It can be formed of a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate thereof including at least one of the above.

  The scanning line 11a is arranged on the lower layer side of the TFT 30 so as to include a region facing the channel region 1a ′, and is made of a conductive film.

(Second layer configuration-TFT, etc.)
The second layer is composed of the TFT 30. The TFT 30 has an LDD (Lightly Doped Drain) structure, for example, and includes a gate electrode 3a, a semiconductor layer 1a, and an insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a. The gate electrode 3a is made of, for example, conductive polysilicon. The semiconductor layer 1a is made of, for example, polysilicon, and includes a channel region 1a ′, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e. The TFT 30 preferably has an LDD structure. However, the TFT 30 may have an offset structure in which no impurity is implanted into the low concentration source region 1b and the low concentration drain region 1c. It may be a self-aligned type in which a high concentration source region and a high concentration drain region are formed by implanting the film.

  The gate electrode 3a of the TFT 30 is electrically connected to the scanning line 11a through a contact hole 12cv formed in the base insulating film 12 in a part 3b thereof. The base insulating film 12 is made of, for example, a silicon oxide film, and is formed on the entire surface of the TFT array substrate 10 in addition to the interlayer insulating function between the first layer and the second layer. Has a function of preventing changes in the element characteristics of the TFT 30 caused by the above.

  The TFT 30 according to the present embodiment is a top gate type, but may be a bottom gate type.

(3rd layer configuration-data lines, etc.)
The third layer is composed of a data line 6a and a relay layer 600.

  The data line 6a is formed as a three-layer film of aluminum, titanium nitride, and silicon nitride in order from the bottom. The data line 6 a is formed so as to partially cover the channel region 1 a ′ of the TFT 30. For this reason, the channel region 1a ′ of the TFT 30 can be shielded against incident light from the upper layer side by the data line 6a that can be disposed close to the channel region 1a ′. The data line 6 a is electrically connected to the high concentration source region 1 d of the TFT 30 through a contact hole 81 that penetrates the first interlayer insulating film 41.

  Note that a conductive film having a lower reflectance than a conductive film such as an Al film constituting the main body of the data line 6a may be formed on the side of the data line 6a facing the channel region 1a. By doing so, the return light described above is reflected on the surface of the data line 6a facing the channel region 1a, that is, the lower layer side of the data line 6a, and multiple reflected light, stray light, etc. are generated from this. Can be prevented. Therefore, the influence of light on the channel region 1a can be reduced. Such a data line 6a has a reflectance on the surface of the data line 6a opposite to the channel region 1a, that is, on the lower layer side of the data line 6a, than the Al film or the like constituting the main body of the data line 6a. A low material metal or a barrier metal may be formed. Note that chromium (Cr), titanium (Ti), titanium nitride (TiN), tungsten (W), or the like can be used as a metal having a lower reflectance than that of an Al film or the like, or as a barrier metal.

  The relay layer 600 is formed as the same film as the data line 6a. As shown in FIG. 6, the relay layer 600 and the data line 6a are formed so as to be separated from each other. The relay layer 600 is electrically connected to the high-concentration drain region 1 e of the TFT 30 through a contact hole 83 that penetrates the first interlayer insulating film 41.

  The first interlayer insulating film 41 is made of, for example, NSG (non-silicate glass). In addition, for the first interlayer insulating film 41, silicate glass such as PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride, silicon oxide, or the like can be used.

(Fourth layer configuration-storage capacity, etc.)
The fourth layer includes a storage capacitor 70. In the storage capacitor 70, a capacitor electrode 300 as an example of the “upper electrode” according to the present invention and a lower electrode 71 as an example of the “lower electrode” according to the present invention are arranged to face each other via the dielectric film 75. It has a configuration.

  The extending portion of the capacitor electrode 300 is electrically connected to the relay layer 600 through a contact hole 84 that penetrates the second interlayer insulating film 42.

  Capacitance electrode 300 or lower electrode 71 is, for example, a metal simple substance containing at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, an alloy, a metal silicide, a polysilicide, and a laminate thereof. Or preferably, it consists of tungsten silicide.

  As shown in FIG. 7, the dielectric film 75 is formed in the non-opening region located in the gap of the opening region for each pixel when viewed in plan on the TFT array substrate 10, that is, almost formed in the opening region. It has not been. The dielectric film 75 is formed of a silicon nitride film or the like having a high dielectric constant without considering the transmittance. In addition to the silicon nitride film, for example, a single layer film or a multilayer film such as hafnium oxide (HfO 2), alumina (Al 2 O 3), tantalum oxide (Ta 2 O 5) or the like may be used as the dielectric film.

  The second interlayer insulating film 42 is made of, for example, NSG. In addition, for the second interlayer insulating film 42, silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like can be used. The surface of the second interlayer insulating film 42 is subjected to a planarization process such as a chemical polishing process (CMP), a polishing process, a spin coat process, or a recess embedding process. Therefore, the unevenness caused by these elements on the lower layer side is removed, and the surface of the second interlayer insulating layer 42 is flattened. Such planarization may be performed on the surface of another interlayer insulating film.

(Fifth layer configuration-pixel electrode, etc.)
A third interlayer insulating film 43 is formed on the entire surface of the fourth layer, and a pixel electrode 9a is formed thereon as a fifth layer. The third interlayer insulating film 43 is made of, for example, NSG. In addition, the third interlayer insulating film 43 can be made of silicate glass such as PSG, BSG, or BPSG, silicon nitride, silicon oxide, or the like. The surface of the third interlayer insulating film 43 is subjected to a planarization process such as CMP similarly to the second interlayer insulating film 42.

  The pixel electrode 9a (indicated by the broken line 9a 'in FIG. 7) is arranged in each of the pixel areas partitioned vertically and horizontally, and the data lines 6a and the scanning lines 11a are arranged in a grid at the boundaries. (See FIGS. 6 and 7). The pixel electrode 9a is made of a transparent conductive film such as ITO.

  The pixel electrode 9a is electrically connected to the extending portion of the capacitor electrode 300 through a contact hole 85 that penetrates the interlayer insulating film 43 (see FIG. 8). Therefore, the potential of the capacitor electrode 300, which is the conductive film immediately below the pixel electrode 9a, is the pixel potential. Therefore, the pixel potential is not adversely affected by the parasitic capacitance between the pixel electrode 9a and the underlying conductive film during the operation of the liquid crystal device.

  Further, as described above, the extended portion of the capacitor electrode 300 and the relay layer 600 and the relay layer 600 and the high-concentration drain region 1e of the TFT 30 are electrically connected through the contact holes 84 and 83, respectively. ing. That is, the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 are relay-connected through the relay layer 600 and the extended portion of the capacitor electrode 300.

  An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a.

  The above is the configuration of the pixel portion on the TFT array substrate 10 side.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 8). As with the pixel electrode 9a, the counter electrode 21 is made of a transparent conductive film such as an ITO film. A light-shielding film 23 is provided between the counter substrate 20 and the counter electrode 21 so as to cover at least a region facing the TFT 30 in order to prevent generation of light leakage current in the TFT 30.

  A liquid crystal layer 50 is provided between the TFT array substrate 10 thus configured and the counter substrate 20. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the substrates 10 and 20 with a sealing material. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIGS. Such pixel portions are periodically formed in the image display region 10a (see FIG. 1).

  Next, a specific configuration of the data line driving circuit of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 9 is a cross-sectional view including the TFT for the data line driving circuit and the first partial wiring of the image signal line. In FIG. 9, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. Here, a specific configuration of a TFT for a data line driving circuit, which is a driving element constituting the data line driving circuit, will be mainly described.

  As shown in FIG. 9, the data line driving circuit 101 has a stacked structure similar to that of the pixel portion 700. That is, the light shielding film 110a located in the same layer as the scanning line 11a is formed on the TFT array substrate 10 as the first layer. A data line driving circuit TFT 202 located in the same layer as the pixel switching TFT 30 is formed as a second layer via the first interlayer insulating film 41 on the upper layer side. Like the pixel switching TFT 30, the data line driving circuit TFT 202 has, for example, an LDD structure, and includes an insulating film 2 including a gate electrode 202ga, a semiconductor layer 202a, and a gate insulating film that insulates the gate electrode 202ga from the semiconductor layer 202a. I have. The gate electrode 202ga is formed in the same layer as the gate electrode 3a of the pixel switching TFT 30, and the semiconductor layer 202a is formed in the same layer as the semiconductor layer 1a of the pixel switching TFT 30. The semiconductor layer 202a includes a channel region 202a ′, a low concentration source region 202b and a low concentration drain region 202c, and a high concentration source region 202d and a high concentration drain region 202e. The data line driver circuit TFT 202 preferably has an LDD structure, but may have an offset structure in which no impurity is implanted into the low concentration source region 202b and the low concentration drain region 202c, or the gate electrode 202ga is masked. Alternatively, a high-concentration source region and a high-concentration drain region may be formed by implanting impurities at a high concentration.

  The gate electrode 202ga of the data line driving circuit TFT 202 is electrically connected to the light-shielding film 110a through a contact hole 14cv formed in the base insulating film 12 at a part 202gb. The data line driving circuit TFT 202 according to this embodiment is a top gate type, but may be a bottom gate type.

  On the upper layer side of the data line driving circuit TFT 202, a source wiring 204s and a drain wiring 204d are formed as a third layer with a first interlayer insulating film 41 interposed therebetween. The source wiring 204s and the drain wiring 204d are examples of “a plurality of wirings” according to the present invention. The source wiring 204 s is electrically connected to the high concentration source region 202 d of the data line driving circuit TFT 202 via a contact hole 810 opened in the first interlayer insulating film 41. The drain wiring 204 d is electrically connected to the high-concentration drain region 202 e of the data line driving circuit TFT 202 via a contact hole 830 opened in the first interlayer insulating film 41.

  Next, a specific configuration of the image signal lines of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 10 is a plan view showing the layout of the image signal line and data line driving circuit on the TFT array substrate. FIG. 11 is a perspective view showing the configuration of the second partial wiring of the image signal line.

  In FIG. 10, particularly in the present embodiment, each of the six image signal lines 170 includes a first partial wiring 171 and a second partial wiring 172. Hereinafter, the first partial wiring 170-1 and the second partial wiring 170-2 of the image signal line 170-1 will be mainly described, but the other image signal lines 170-2 to 170-6 have the same configuration. ing.

  In FIG. 9 again, the first partial wiring 171-1 is formed of the same film as the capacitor electrode 300 (see FIG. 8) of the storage capacitor 70 described above. That is, the first partial wiring 171-1 is a conductive film located on the upper layer side through the second interlayer insulating film 42 with respect to the conductive film constituting the TFT 202, the source wiring 204s, and the drain wiring 204d of the data line driving circuit 101. Formed from.

  On the other hand, as shown in FIG. 10, the second partial wiring 172-1 is on the same side as the image display area 10a with respect to the data line driving circuit 101, along the data line driving circuit 101 (that is, in the horizontal direction in the figure). Is wired).

  Further, as shown in FIG. 11, the second partial wiring 172-1 has a double wiring structure composed of the sub partial wirings 172-1a and 172-1b. The sub partial wiring 172-1a is made of the same film as the capacitor wiring 300 (see FIG. 8), and is formed integrally with the first partial wiring 171-1. The sub partial wiring 172-1b is made of the same film as the lower electrode 71 (see FIG. 8), and is formed integrally with the branch wiring 175. The sub partial wirings 172-1a and 172-1b are electrically connected through contact holes 61 and 62 opened in the dielectric film 75. Therefore, the second partial wiring 172-1 has a low resistance by having a double wiring structure.

  As shown in FIG. 11, the second partial wiring 172-1 is electrically connected to the other second partial wirings 172-2 to 172-6 in plan view on the TFT array substrate 10. For the portion that intersects the branch wiring 175, the sub partial wiring 172-1b is configured to be partially interrupted. The sub partial wirings 172-1a and 172-1b are electrically connected through contact holes 61 formed for the corresponding branch wirings 175.

  Further, although not shown, for example, a portion of the second partial wiring 172-2 that intersects the first partial wiring 171-1 when viewed in plan on the TFT array substrate 10 is the sub partial wiring 172-2. 2a is configured to be partially interrupted.

  As shown in FIG. 10 again, particularly in the present embodiment, the first partial wirings 171-1 to 171-6 overlap with the data line driving circuit 101 when viewed in plan on the TFT array substrate 10. That is, the first partial wirings 171-1 to 171-6 are arranged on the opposite side to the data line driving circuit 101 from the external circuit connection terminals 102-1 to 102-6 arranged along one side of the TFT array substrate 10. The second partial wirings 172-1 to 172-6 are wired so as to overlap the data line driving circuit 101 in plan view on the TFT array substrate 10. Therefore, the data line driving circuit is configured so that the six image signal lines avoid the data line driving circuit 101 when viewed in plan on the TFT array substrate 10 (that is, so as not to overlap the data line driving circuit 101). Compared to the case of wiring (bypassing around 101), the difference in wiring length between the six image signal lines 170-1 to 170-6 can be eliminated almost or preferably completely. That is, when viewed in plan on the TFT array substrate 10, from the edge side (that is, the lower side in the figure) of the data line driving circuit 101 on the TFT array substrate 10 to the center side (that is, the upper side in the figure), Since the image signal line 170 is configured to pass over the data line driving circuit 101, the image signal line 170 includes a first partial wiring 171 that overlaps the data line driving circuit 101 when viewed in plan on the TFT array substrate 10. As a result, the wiring length of the six image signal lines 170-1 to 170-6 can be shortened and the degree of freedom of wiring is high. Therefore, the distance between the six image signal lines 170-1 to 170-6 is high. The difference in wiring length can be eliminated almost or preferably completely. Accordingly, it is possible to eliminate almost or preferably completely the vertical band-like display unevenness caused by the difference in wiring resistance or electric capacity between the six image signal lines 170-1 to 170-6.

  Further, since the first partial wiring 171-1 overlaps the data line driving circuit 101 in plan view on the TFT array substrate 10, the six image signal lines 170-1 to 170-6 are connected to the TFT array substrate. The TFT array necessary for wiring the six image signal lines 170-1 to 170-6 as compared with the case where the data line driving circuit 101 is wired so as to avoid the data line driving circuit 101 when viewed in plan on 10. The area on the substrate 10 can be reduced. Therefore, by reducing the size of the TFT array substrate 10, the entire liquid crystal device can be downsized, or the area on the TFT array substrate 10 can be effectively used, for example, by arranging other wirings or circuits to increase the liquid crystal device. It is also possible to improve performance.

As shown in FIG. 10, in the second partial wiring 172, a portion 179 (that is, a portion not intersecting with the branch wiring 175) on the left side of the contact hole 62 when viewed in plan on the TFT array substrate 10 is provided. Thus, the wiring resistance or capacitance between the plurality of image signal lines 170 can be further adjusted. In practice, when there is no need for such adjustment, there is no electrical connection point with the branch wiring 175 in the portion 179, so the portion 179 may be omitted.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIG. FIG. 12 is a plan view having the same concept as in FIG. 10 in the second embodiment. In FIG. 12, the same components as those in the first embodiment shown in FIGS. 1 to 11 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  As shown in FIG. 12, the first partial wirings 171-1 to 171-6 may be arranged at intervals of each data line group, that is, every six branch wirings corresponding to the data line group.

  Also in this case, as in the first embodiment, the difference in wiring length between the six image signal lines 170-1 to 170-6 can be eliminated almost or preferably completely. Therefore, it is possible to almost or preferably completely eliminate the vertical band-like display unevenness caused by the difference in wiring resistance or electric capacity between the six image signal lines 170-1 to 170-6.

Further, since the first partial wiring 171-1 overlaps the data line driving circuit 101 in plan view on the TFT array substrate 10, the six image signal lines 170-1 to 170-6 are connected to the TFT array substrate. The TFT array necessary for wiring the six image signal lines 170-1 to 170-6 as compared with the case where the data line driving circuit 101 is wired so as to avoid the data line driving circuit 101 when viewed in plan on 10. The area on the substrate 10 can be reduced. Therefore, by reducing the size of the TFT array substrate 10, the entire liquid crystal device can be downsized, or the area on the TFT array substrate 10 can be effectively used, for example, by arranging other wirings or circuits to increase the liquid crystal device. It is also possible to improve performance.
<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 13 is a plan view showing a configuration example of the projector. As shown in FIG. 13, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  Next, an example in which the liquid crystal device is applied to a mobile personal computer will be described. FIG. 14 is a perspective view showing the configuration of this personal computer. In FIG. 14, the computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal device 1005 described above.

  Further, an example in which the liquid crystal device is applied to a mobile phone will be described. FIG. 15 is a perspective view showing the configuration of this mobile phone. In FIG. 15, a mobile phone 1300 includes a reflective liquid crystal device 1005 together with a plurality of operation buttons 1302. In the reflective liquid crystal device 1005, a front light is provided on the front surface thereof as necessary.

  In addition to the electronic devices described with reference to FIGS. 13 to 15, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Examples include a station, a videophone, a POS terminal, a device equipped with a touch panel, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is sectional drawing of HH 'of FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal device according to a first embodiment. It is a block diagram which shows the electrical structure of a liquid crystal panel. It is a circuit diagram which shows the circuit structure concerning the drive of a data line. It is a top view showing the partial structure which concerns on the pixel part on a TFT array substrate, and is a figure equivalent to a lower layer part among laminated structures. It is a top view showing the partial structure concerning the pixel part on a TFT array substrate, and is a figure corresponded to the upper layer part among laminated structures. FIG. 8 is a cross-sectional view taken along line AA ′ when FIG. 6 and FIG. 7 are overlapped. FIG. 5 is a cross-sectional view including a data line driving circuit TFT and a first partial wiring of an image signal line. It is a top view which shows the layout on the TFT array substrate of an image signal line and a data line drive circuit. It is a perspective view which shows the structure of the 2nd partial wiring of an image signal line. It is a top view of the same meaning as FIG. 10 in 2nd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied. 1 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which an electro-optical device is applied. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 7 ... sampling circuit, 9a ... pixel electrode, 11a ... scanning line, 10 ... TFT array substrate, 10a ... image display area, 41, 42, 43 ... interlayer insulating film, 101 ... data line drive circuit, 102 DESCRIPTION OF SYMBOLS ... External circuit connection terminal, 104 ... Scanning line drive circuit, 170 ... Image signal line, 171 ... 1st partial wiring, 172 ... 2nd partial wiring, 175 ... Branch wiring, 700 ... Pixel part, VID1-VID6 ... Image signal

Claims (5)

A substrate,
A plurality of data lines wired to the pixel region;
A terminal,
An image signal line connected to the terminal and supplied with an image signal;
A data line driving circuit for generating a sampling signal;
A sampling circuit connected between the plurality of data lines and the image signal line and controlled in accordance with the sampling signal;
With
The image signal line is
A first portion disposed between the data line driving circuit and the sampling circuit;
An electro-optical device comprising: a second portion that connects between the terminal and the first portion and overlaps the data line driving circuit.   The second portion is formed of a second conductive film located in a different layer with respect to the first conductive film constituting the data line driving circuit via an interlayer insulating film. 2. The electro-optical device according to 1. The image signal line is an N-series serial-parallel conversion for driving the plurality of data lines for each data line group in which N (where N is a natural number of 2 or more) data lines. Including N image signal lines to which the image signal is supplied through the terminal;
The data line driving circuit is disposed along one side of the substrate in a peripheral region located around the pixel region,
The terminals are arranged along the one side in the peripheral region and on the side opposite to the pixel region with respect to the data line driving circuit,
The N image signal lines each have a first portion extending in the direction of the one side in the peripheral region and wired between the data line driving circuit and the sampling circuit,
The electro-optical device according to claim 1, wherein the second portion is wired in a direction intersecting the one side from the terminal to the first portion. In the pixel region, a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are sequentially stacked on the substrate on the upper layer side than the plurality of data lines,
The first conductive film is made of the same film as any one of the plurality of data lines or the lower layer electrode,
The second conductive film is made of the same film as the upper electrode.
The electro-optical device according to claim 2 .   An electronic apparatus comprising the electro-optical device according to claim 1.

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