JP4869991B2 - Capacitor built-in wafer level package and manufacturing method thereof - Google Patents

Description

  The present invention relates to a wafer level package including a decoupling capacitor in the vicinity of a semiconductor integrated circuit element mounted on a semiconductor device and contributing to stable operation in a high frequency region, for example, a GHz band, and a method for manufacturing the same.

  Currently, in a semiconductor integrated circuit element such as a microprocessor, an operation speed is increased and a power consumption is reduced.

  In order to stably operate the semiconductor integrated circuit element at a low voltage in the high frequency region of the GHz band, the power supply voltage fluctuation caused by a rapid fluctuation of the load impedance is suppressed and the high frequency of the power supply is controlled. It is extremely important to remove noise.

  On a conventional semiconductor package substrate, a multilayer chip capacitor is used as a decoupling capacitor in order to prevent malfunction of the semiconductor integrated circuit element due to power supply voltage fluctuations and high frequency noise in the substrate superimposed on the power supply and ground lines. It is mounted in the vicinity of the element.

  As a capacitor used for this purpose, a capacitor having both a large capacity and a low inductance in a high frequency region of GHz or more is required. In the above-described mounting form, wiring is provided between the chip capacitor and the semiconductor integrated circuit element. Since it has to be routed and a parasitic inductance is generated as a result, the suppression of power supply voltage fluctuation and the function of absorbing high-frequency ripple for a semiconductor integrated circuit device operating at high speed are significantly reduced.

  Therefore, a technology is known that enables inductance to be reduced by arranging a capacitor immediately below the semiconductor integrated circuit element and minimizing the wiring from the power supply and ground line to the capacitor to supply power to the semiconductor integrated circuit element. ing.

  FIG. 12 is a cutaway side view showing a principal part of a semiconductor device in which a capacitor is arranged directly under a semiconductor integrated circuit element. In the figure, 1 is a motherboard, 2 is a package substrate, 3 is a capacitor built-in interposer, 4 is a capacitor, Reference numeral 5 denotes a semiconductor integrated circuit element.

  As is apparent from the figure, since the interposer 3 with a built-in capacitor 4 is disposed immediately below the semiconductor integrated circuit element 5, the semiconductor integrated circuit element 5 and the capacitor 4 are at a short distance, and various There is no wiring routing.

  As another means for disposing the capacitor in the vicinity of the semiconductor integrated circuit element, a capacitor is formed on or embedded in the semiconductor integrated circuit element, and the semiconductor integrated circuit element and the capacitor are integrated to form a module. Techniques have been proposed (see, for example, Patent Document 1 or Patent Document 2).

  However, introducing a process of forming a capacitor on the redistribution layer formed on the semiconductor integrated circuit element by a sputtering method, a CVD (chemical vapor deposition) method, or the like causes a reduction in manufacturing yield, and is a risk. Will lead to increased costs.

  Furthermore, it is also conceivable to arrange a multilayer chip capacitor conventionally used frequently in a rewiring layer formed of a conductor and a resin layer on a semiconductor integrated circuit element in a wafer level package.

  FIG. 13 is a cutaway side view showing a principal part of a semiconductor device in which multilayer chip capacitors are arranged in a redistribution layer of a semiconductor integrated circuit element. In the figure, 5 is a semiconductor integrated circuit element, 6 is a redistribution layer, and 7 is Each of the multilayer chip capacitors is shown.

  Usually, the multilayer chip capacitor 7 has a height of 0.6 to 2 mm, and if it has a large capacity, it surely becomes 1 mm or more. Therefore, the configuration shown in FIG. Needless to say, there are many problems in the realization such as fan-out being restricted, and it is difficult to expect a reduction in cost because it requires a difficult technology in terms of manufacturing.

Furthermore, since it is difficult to carry out the electrode via extraction process to the upper part of the multilayer chip capacitor 7, another active component or a passive component such as a chip capacitor is mounted on the top of the chip size package to form a module. Proposals have also been made.
JP 2005-294451 A JP 2006-059957 A

  The present invention is intended to provide a wafer level package that can be manufactured at low cost, has a high degree of freedom in routing a rewiring layer, and has a built-in large-capacitance capacitor, and a method for manufacturing the same.

  In the wafer level package with a built-in capacitor and the manufacturing method thereof according to the present invention, the anode made of a valve metal material electrically connected to the power supply electrode of the semiconductor integrated circuit element formed on the wafer, and the valve metal material The anodic oxide film between the anodized film which is a dielectric film of the capacitor formed on the surface of the anode and the anode made of the valve metal material and electrically connected to the grounding electrode of the semiconductor integrated circuit element It is basically provided with a sheet-like capacitor configured with a cathode made of a conductive polymer material that sandwiches, and a rewiring layer that is on the wafer and includes the sheet-like capacitor and aggregates each electrical wiring. It has become.

  By adopting the above means, the wafer level package with a built-in capacitor according to the present invention has a structure in which a planar electrolytic capacitor using a dielectric film produced by using an anodizing technique that has been widely used in various industrial fields has been built. Therefore, it is possible to mount a large-capacity capacitor very close to the semiconductor integrated circuit element, and it is inevitable that the distance between the two is the shortest, so it is easy to reduce the inductance of the capacitor. Can be achieved.

  In addition, since the mounting form of the capacitor according to the present invention greatly exceeds the required impedance of the conventional capacitor, it is possible to greatly reduce the capacitor parts conventionally mounted around the semiconductor integrated circuit element. This can contribute to cost reduction of a package that requires a capacitor.

  Furthermore, when compared with a wafer level package with a passive component built-in according to the conventional concept, a built-in planar electrolytic capacitor is built instead of built-in, and the ground terminal and the power terminal are led out to the outside. Since the quality of KGD (Knowed Good Die) and electrolytic capacitor of each part in the wafer can be separately inspected and selected, the manufacturing yield of the package is improved.

  In the wafer level package with a built-in capacitor according to the present invention, a sheet-like conductive polymer capacitor using a conductive polymer film as a cathode and an oxide film formed by anodic oxidation on the surface of an aluminum foil is integrated into a semiconductor. It is mounted by bonding on a silicon wafer on which a semiconductor device composed of circuit elements is formed, and the anode and cathode of the capacitor are drawn out as electrode vias.

  As a mounting form of the capacitor, the power source and ground of the semiconductor integrated circuit element are concentrated on a rewiring layer made of a conductor and a resin film, and connected to the cathode and anode of the capacitor.

  FIG. 1 to FIG. 4 are cutaway side views showing a main part of a package at a process point for explaining a process for manufacturing a wafer level package with a built-in capacitor according to the present invention. Hereinafter, referring to these figures, FIG. explain.

See FIG. 1A (1)
By using the photolithography method, an opening is formed at a required portion of the passivation film 12 made of SiN covering the silicon substrate 11 on which the integrated circuit is formed, and conductively connected to the semiconductor integrated circuit formed in the silicon substrate 11. The electrode pad 13 is formed.

Refer to FIG. 1 (B) (2)
A resin film 14 made of polyimide is formed on the entire surface, and openings 14A corresponding to the electrode pads 13 are formed by using a photolithography method.

See FIG. 1C (3)
A wiring 15 made of Cu that fills the opening 14A and extends on the resin film 14 is formed.

See Fig. 2 (4)
If necessary, a resin film 14 and a wiring 15 made of Cu are further laminated to form a rewiring layer 16.

(5)
An opening is formed in the resin film 14 at a required location of the rewiring layer 16, that is, a location where the sheet-like capacitor is mounted and bonded and bonded, and a silver paste film 17 that contacts the wiring 15 made of Cu is formed. .

See FIG. 3 (6)
The sheet-shaped capacitor will be described in detail later. From an anode 18A made of an aluminum foil having a dielectric film formed thereon, an anode 18A made of a conductive polymer, and a cathode 18B made of a conductive polymer. The sheet-like capacitor 18 is bonded and adhered to the rewiring layer 16 using a silver paste film 17 which is a conductive adhesive material, and is cured. In addition, the thickness S of the sheet-like capacitor 18 illustrated here is 0.1 mm to 0.15 mm. The conductive adhesive material is not limited to a silver paste, and for example, a carbon paste or an anisotropic conductive film (ACF) can be used.

(7)
The sheet capacitor 18 is filled with the resin film 14, and an opening for forming a required electrode is formed in the resin film 14.

Refer to FIG. 4 (8)
External connection terminals such as the power supply electrode 19, the ground electrode 20, and the signal electrode 21 are formed to complete a capacitor built-in wafer level package.

  5A and 5B are explanatory views for explaining a case of manufacturing a sheet-like capacitor. FIG. 5A is a cutaway side view of a main part showing a wafer level package with a built-in capacitor, and FIG. It is a partial cutaway side view, and parts indicated by the same symbols as those used in FIGS. 1 to 4 represent the same or equivalent parts.

  When an aluminum foil is used for the anode 18A of the sheet-like capacitor 18, it is preferable that the surface of the anode 18A made of the aluminum foil is etched to have a porous structure as shown in FIG. Accordingly, the effective surface area of the anodic oxide film 18C is increased, and the capacitor capacity is remarkably increased.

  In order to form the anodic oxide film 18C on the anode 18A made of aluminum foil, an anodic oxide film 18C (capacitor dielectric film) is formed by performing anodizing treatment in an aqueous solution of ammonium adipate or ammonium pentaborate.

  Next, in order to form the cathode 18B made of a conductive polymer, a capacitor cathode 18B is realized by forming a conductive polymer layer such as polypyrrole or polyethylenedioxythiophene on the surface of the anodized film 18C.

  In the wafer level package with a built-in capacitor according to the present invention, there are many arrangements and number of stacked sheets of capacitors 18 or various electrodes, that is, how to take out the power supply electrode 19, the ground electrode 20, and the signal electrode 21. Is possible, and is not limited to the above description. Next, some examples will be described.

  FIG. 6 is a cutaway side view showing a main part of a wafer level package with a built-in capacitor for explaining an embodiment of the present invention. The parts indicated by the same symbols as those used in FIGS. 1 to 5 are the same. Or it shall represent the part of the same effect.

  In this example, the anode 18A made of an aluminum foil is exposed at both ends thereof, bonded with a silver paste film 17, and applied with a voltage via a power supply electrode 19. The cathode 18B made of a conductive polymer on the substrate 11 side is connected to the electrode pad 13 on the silicon substrate 11 at a plurality of locations, and the cathode 18B made of a conductive polymer on the surface side has a signal at a plurality of locations. The electrode 20 is connected. In addition, the thickness S of the sheet-like capacitor 18 used here is 0.1 mm to 0.15 mm.

  FIG. 7 is a cutaway side view of a principal part showing a capacitor built-in wafer level package for explaining an embodiment of the invention. The parts indicated by the same symbols as those used in FIGS. It shall represent the part with the same effect.

  This example is different from the embodiment described with reference to FIG. 6 in that the anode 18A made of aluminum foil is divided into a plurality of parts on both the silicon substrate 11 side and the surface side.

  FIG. 8 is a cut-away side view of the main part showing a wafer level package with a built-in capacitor for explaining an embodiment of the present invention, and the parts designated by the same symbols as those used in FIGS. 1 to 7 are the same. Or it shall represent the part of the same effect.

  In this example, a configuration is adopted in which a plurality of sheet-like capacitors 18 described with reference to FIGS. The sheet capacitor 18 is not limited to two layers, and the number of layers can be further increased.

  FIG. 9 is a top view of an essential part overlooking the capacitor built-in wafer level package described with reference to FIG. 4, and the parts indicated by the same symbols as those used in FIGS. 1 to 8 represent the same or equivalent parts. Shall.

  According to FIG. 9, the arrangement of the power source electrode 19, the ground electrode 20, and the signal electrode 21 can be clearly seen.

  FIG. 10 is a top view of an essential part of the sheet-like capacitor in the wafer level package with a built-in capacitor described with reference to FIG. 4, and is indicated by the same symbols as those used in FIGS. The parts shall represent the same or equivalent parts.

  According to FIG. 10, the anode 18A located on one side edge of the sheet-like capacitor 18 is connected to the power supply electrode 19, and in the vicinity of the side edge opposite to the one side edge of the cathode 18B. It can be seen that the ground electrode 20 is connected.

  From the above, in the wafer level package with a built-in capacitor according to the present invention, the power supply electrode 19, the ground electrode 20, and the signal electrode 21 in the semiconductor device are integrated in the rewiring layer 16, and the anode of the sheet-like capacitor 18. It will be understood that the structure is connected to 18A and cathode 18B.

  A capacitor built-in wafer level package manufactured through the steps described with reference to FIGS. 1 to 4 will be specifically described as a first embodiment.

  The surface of an aluminum foil having a thickness of 0.1 mm is subjected to electrolytic etching treatment to have a porous structure, washed with hydrofluoric acid and distilled water, and then anodes in an aqueous solution in which 150 g of ammonium adipate is dissolved in 1000 ml of pure water. Chemical conversion is performed to form an aluminum oxide film. The liquid temperature during the formation was 85 ° C., the formation voltage was 100 V, the current was 0.3 A, and the voltage application time was 20 minutes.

  Next, a solution containing polyethylene dioxythiophene and styrene sulfonic acid was applied to the surface of the anodized film and dried, and this was repeated three times to obtain a film thickness of 20 μm. At this time, a protective mask was formed in advance on the portion serving as the anode of the capacitor.

  Separately from the above steps, an electrode pad for connecting to the capacitor is formed on a silicon wafer on which a passivation film made of silicon nitride and an aluminum electrode pad are formed on a semiconductor device.

  First, using a spin coating method, a photosensitive polyimide resin varnish is applied at 2500 rpm for 30 seconds to form a film with a thickness of 6 μm.

  After pre-baking at a temperature of 120 ° C., through exposure and development processes, a main baking at a temperature of 350 ° C. is performed to form a polyimide resin film having a thickness of 3 μm and having openings corresponding to the electrode pads of the semiconductor device.

  A Cr film and a Cu film are formed using a sputtering method, a resist protective film is formed at a required location, and then Cu plating is performed to electrically connect the anode made of aluminum and the cathode made of a conductive polymer of the capacitor. Conductor vias are extracted, and this process is repeated to collect the power and ground layers of the rewiring layer. Further, the signal electrode is pulled out as it is.

  Using a printing method, silver paste, which is a conductive adhesive material layer, is applied and patterned at positions corresponding to the anode and cathode of the capacitor, and the sheet-like capacitor is adhered and cured thereon. The curing conditions in this case are 200 ° C. and 20 minutes in the atmosphere.

  A photosensitive polyimide resin is used as an insulating protective film on the upper part of the sheet capacitor. As above, a polyimide resin film having a thickness of 3 μm is formed, a Cr film and a Cu film are formed by a sputtering method, a resist protective film is formed at a required location, and then Cu plating is performed. Conductor vias for electrical connection to a cathode made of a conductive polymer were drawn out to complete a capacitor built-in wafer level package.

  The aluminum foil that is the capacitor anode material in Example 1 is replaced with niobium foil. In that case, the niobium foil was washed with acid and distilled water, a protective mask was formed on the anode side conductive lead portion of the capacitor, and then anodized in a phosphoric acid solution to form a niobium oxide film on the niobium foil. In this case, the liquid temperature during the formation is 90 ° C., the formation voltage is 150 V, the current is 0.6 A, and the voltage application time is 10 minutes.

  Thereafter, the wafer level package with a built-in capacitor was completed through the same process as in Example 1. The relative dielectric constant of the niobium oxide film is about 42, which is much larger than the relative dielectric constant of about 8 that is the aluminum oxide film, and the capacity of the capacitor can be increased.

  When producing a dielectric film of a capacitor, an aluminum foil having a porous surface formed by electrolytic etching is washed with fluorinated nitric acid and distilled water, and then ammonium adipate is added to 1000 ml of pure water. Anodization was performed in an aqueous solution in which 150 g was dissolved to form an aluminum oxide film. In this case, the liquid temperature during formation was 85 ° C., the formation voltage was 100 V, the current was 0.3 A, and the voltage application time was 20 minutes.

  Next, a solution containing polypyrrole is applied to the anodized film surface and dried. This was repeated 5 times, and the film thickness was 50 μm.

  Through the same process as in the first embodiment, an electrode pad for connecting to the capacitor is formed on the silicon wafer on which the semiconductor device is formed.

ACF was applied to the electrode pads at positions corresponding to the anode and cathode of the capacitor, and the sheet capacitor was adhered while heating at 170 ° C. for 20 seconds and applying pressure of 1 MPa / cm ^2. The wafer level package with a built-in capacitor was completed through the same process.

  A 0.1 mm thick aluminum foil having a porous structure formed on the surface by electrolytic etching was washed with hydrofluoric acid and distilled water, and then anodized in an aqueous solution in which 150 g of ammonium adipate was dissolved in 1000 ml of pure water. In line, an aluminum oxide film is formed on the surface. At this time, the liquid temperature during the formation was 85 ° C., the formation voltage was 100 V, the current was 0.3 A, and the voltage application time was 20 minutes.

  Next, a solution containing polyethylene dioxythiophene and styrene sulfonic acid is applied to the surface of the aluminum oxide film and dried. This was repeated three times to make the film thickness 20 μm. At this time, a protective mask was formed on the anode side conductive lead portion of the capacitor.

  Two sheet-like capacitors produced as described above are stacked as described with reference to FIG. 8, and the same method as in Example 1, that is, bonding using a silver paste film, is performed to provide a large-capacity sheet-like capacitor. Completed wafer level package with built-in capacitor.

  FIG. 11 is a diagram showing the impedance characteristics of a sheet-like capacitor according to the present invention in comparison with those of other types of capacitors. The vertical axis represents impedance (Ω), and the horizontal axis represents frequency (Hz). ) Respectively.

  From the figure, it can be seen that the impedance characteristics in the high frequency range of the capacitor according to the present invention are superior to those of various conventional capacitors.

  Normally, in the impedance characteristics of a capacitor, the point where the impedance is lowest is the resonance frequency. With this point as the boundary, it is often capacitive (capacitive) below the resonance point, and inductive (inductive) beyond the resonance point. Are known.

  Therefore, in order to realize a low-impedance capacitor that can fully perform the decoupling function of the capacitor, it is essential to have a high capacity and a low inductance. Therefore, conventionally, an impedance curve using various capacitors is required. The components have been selected in the direction of reducing the impedance as much as possible.

  In general, it is often caused by the internal structure of the capacitor. However, in a large-capacity capacitor, the resonance point is low and it has inductivity in a high-frequency region, so that the impedance increases. The resonance point is high, but the capacitance is small, so the overall impedance is large.

  As is apparent from the figure, the capacitor according to the present invention is far superior to the impedance curve of the conventional capacitor. Therefore, the resonance point can be controlled by modifying the mounting method and internal structure. In this case, since the impedance curve can be controlled in a good direction, the impedance can be further reduced.

It is a principal part cutting side view showing the package in the process important point for demonstrating the process of manufacturing the capacitor built-in wafer level package of this invention. It is a principal part cutting side view showing the package in the process important point for demonstrating the process of manufacturing the capacitor built-in wafer level package of this invention. It is a principal part cutting side view showing the package in the process important point for demonstrating the process of manufacturing the capacitor built-in wafer level package of this invention. It is a principal part cutting side view showing the package in the process important point for demonstrating the process of manufacturing the capacitor built-in wafer level package of this invention. It is principal part explanatory drawing of the wafer level package with a built-in capacitor for demonstrating the case where a sheet-like capacitor is produced. It is a principal part cutting side view showing the capacitor built-in wafer level package for demonstrating one embodiment of this invention. It is a principal part cutting side view showing the capacitor built-in wafer level package for demonstrating one embodiment of this invention. It is a principal part cut side view showing a capacitor built-in wafer level package for explaining an embodiment of the present invention, FIG. 7 is a top view of an essential part of an overhead view of the capacitor built-in wafer level package described with reference to FIG. 6. FIG. 7 is a top view of the main part of the sheet-like capacitor in the wafer level package with a capacitor described with reference to FIG. FIG. 6 is a diagram illustrating impedance characteristics of a sheet capacitor according to the present invention in comparison with those of other types of capacitors. It is a principal part cutting side view showing the semiconductor device which has arrange | positioned the capacitor directly under the semiconductor integrated circuit element. It is a principal part cutting side view showing the semiconductor device which has arrange | positioned the multilayer chip capacitor in the rewiring layer of a semiconductor integrated circuit element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Passivation film 13 Electrode pad 14 Resin film 14A Opening 15 Wiring 16 Redistribution layer 17 Silver paste film 18 Sheet-like capacitor 18A Anode 18B Cathode 18C Anodized film 19 Power supply electrode 20 Ground electrode 21 Signal electrode

Claims (4)

An anode made of a valve metal material electrically connected to a power supply electrode of a semiconductor integrated circuit element formed on a wafer, and an anodized film that is a dielectric film of a capacitor formed on the surface of the anode made of the valve metal material And a sheet-like capacitor comprising a cathode made of a conductive polymer material electrically connected to a grounding electrode of the semiconductor integrated circuit element and sandwiching the anodized film between the anode made of the valve metal material; ,
A rewiring layer that is on the wafer and includes the sheet-like capacitor and aggregates each electrical wiring ;
The conductive adhesive material for connecting the anode made of the valve metal material to the power electrode and the cathode made of the conductive polymer material to the ground electrode is a paste of silver or carbon, or a paste in which both are mixed Be
The capacitor built WLP to feature. An anode made of a valve metal material electrically connected to a power supply electrode of a semiconductor integrated circuit element formed on a wafer, and an anodized film that is a dielectric film of a capacitor formed on the surface of the anode made of the valve metal material And a sheet-like capacitor comprising a cathode made of a conductive polymer material electrically connected to a grounding electrode of the semiconductor integrated circuit element and sandwiching the anodized film between the anode made of the valve metal material; ,
A redistribution layer on the wafer that includes the sheet-like capacitor and aggregates electrical wirings;
With
The anode power supply electrodes made of the valve metal material, and, you, wherein the conductive adhesive material for connecting each of the cathode made of the conductive polymer material to the grounding electrode is anisotropic conductive film key Yapashita built-in wafer level package. Forming an electrical wiring layer on a wafer incorporating a semiconductor integrated circuit element;
Forming a conductive adhesive material layer in place of the electrical wiring layer;
Adhering an anode made of a valve metal material and a cathode made of a conductive polymer material in the sheet-like capacitor to the conductive adhesive material layer;
Forming a wiring separately electrically connected to the anode and the cathode of the sheet capacitor;
Deriving an external connection terminal above the sheet capacitor;
Contains
It said conductive adhesive material silver or carbon paste, or features and to Ruki the <br/> be a paste obtained by mixing both Yapashita built WLP fabrication method. Forming an electrical wiring layer on a wafer incorporating a semiconductor integrated circuit element;
Forming a conductive adhesive material layer in place of the electrical wiring layer;
Adhering an anode made of a valve metal material and a cathode made of a conductive polymer material in the sheet-like capacitor to the conductive adhesive material layer;
Forming a wiring separately electrically connected to the anode and the cathode of the sheet capacitor;
Deriving an external connection terminal above the sheet capacitor;
Contains
The conductive adhesive material is an anisotropic conductive film
A method for manufacturing a wafer level package with a built-in capacitor.

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